281dfda8d66f6d05da7f4b5dd10e6c17685de939
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.10 / 0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
1 From eaec375aa840b776641f2619dbc974fa6ec44d80 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 20 May 2012 00:42:39 +0200
4 Subject: [PATCH 31/34] I2C: MIPS: lantiq: add FALC-ON i2c bus master
5
6 This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs.
7
8 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 ---
11 drivers/i2c/busses/Kconfig | 10 +
12 drivers/i2c/busses/Makefile | 1 +
13 drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++
14 drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++
15 4 files changed, 992 insertions(+)
16 create mode 100644 drivers/i2c/busses/i2c-lantiq.c
17 create mode 100644 drivers/i2c/busses/i2c-lantiq.h
18
19 --- a/drivers/i2c/busses/Kconfig
20 +++ b/drivers/i2c/busses/Kconfig
21 @@ -495,6 +495,16 @@ config I2C_IOP3XX
22 This driver can also be built as a module. If so, the module
23 will be called i2c-iop3xx.
24
25 +config I2C_LANTIQ
26 + tristate "Lantiq I2C interface"
27 + depends on LANTIQ && SOC_FALCON
28 + help
29 + If you say yes to this option, support will be included for the
30 + Lantiq I2C core.
31 +
32 + This driver can also be built as a module. If so, the module
33 + will be called i2c-lantiq.
34 +
35 config I2C_MPC
36 tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
37 depends on PPC
38 --- a/drivers/i2c/busses/Makefile
39 +++ b/drivers/i2c/busses/Makefile
40 @@ -48,6 +48,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic
41 obj-$(CONFIG_I2C_IMX) += i2c-imx.o
42 obj-$(CONFIG_I2C_INTEL_MID) += i2c-intel-mid.o
43 obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
44 +obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o
45 obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
46 obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
47 obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
48 --- /dev/null
49 +++ b/drivers/i2c/busses/i2c-lantiq.c
50 @@ -0,0 +1,747 @@
51 +
52 +/*
53 + * Lantiq I2C bus adapter
54 + *
55 + * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33
56 + *
57 + * This program is free software; you can redistribute it and/or modify
58 + * it under the terms of the GNU General Public License as published by
59 + * the Free Software Foundation; either version 2 of the License, or
60 + * (at your option) any later version.
61 + *
62 + * This program is distributed in the hope that it will be useful,
63 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
64 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
65 + * GNU General Public License for more details.
66 + *
67 + * You should have received a copy of the GNU General Public License
68 + * along with this program; if not, write to the Free Software
69 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
70 + *
71 + * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
72 + */
73 +
74 +#include <linux/kernel.h>
75 +#include <linux/module.h>
76 +#include <linux/delay.h>
77 +#include <linux/slab.h> /* for kzalloc, kfree */
78 +#include <linux/i2c.h>
79 +#include <linux/errno.h>
80 +#include <linux/completion.h>
81 +#include <linux/interrupt.h>
82 +#include <linux/platform_device.h>
83 +#include <linux/io.h>
84 +#include <linux/of_irq.h>
85 +#include <linux/of_i2c.h>
86 +
87 +#include <lantiq_soc.h>
88 +#include "i2c-lantiq.h"
89 +
90 +/*
91 + * CURRENT ISSUES:
92 + * - no high speed support
93 + * - ten bit mode is not tested (no slave devices)
94 + */
95 +
96 +/* access macros */
97 +#define i2c_r32(reg) \
98 + __raw_readl(&(priv->membase)->reg)
99 +#define i2c_w32(val, reg) \
100 + __raw_writel(val, &(priv->membase)->reg)
101 +#define i2c_w32_mask(clear, set, reg) \
102 + i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg)
103 +
104 +#define DRV_NAME "i2c-lantiq"
105 +#define DRV_VERSION "1.00"
106 +
107 +#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */
108 +
109 +#ifdef DEBUG
110 +#define LTQ_I2C_XFER_TIMEOUT (25*HZ)
111 +#else
112 +#define LTQ_I2C_XFER_TIMEOUT HZ
113 +#endif
114 +
115 +#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \
116 + I2C_IMSC_I2C_ERR_INT_EN)
117 +
118 +#define LTQ_I2C_ARB_LOST (1 << 0)
119 +#define LTQ_I2C_NACK (1 << 1)
120 +#define LTQ_I2C_RX_UFL (1 << 2)
121 +#define LTQ_I2C_RX_OFL (1 << 3)
122 +#define LTQ_I2C_TX_UFL (1 << 4)
123 +#define LTQ_I2C_TX_OFL (1 << 5)
124 +
125 +struct ltq_i2c {
126 + struct mutex mutex;
127 +
128 +
129 + /* active clock settings */
130 + unsigned int input_clock; /* clock input for i2c hardware block */
131 + unsigned int i2c_clock; /* approximated bus clock in kHz */
132 +
133 + struct clk *clk_gate;
134 + struct clk *clk_input;
135 +
136 +
137 + /* resources (memory and interrupts) */
138 + int irq_lb; /* last burst irq */
139 +
140 + struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */
141 +
142 + struct i2c_adapter adap;
143 + struct device *dev;
144 +
145 + struct completion cmd_complete;
146 +
147 +
148 + /* message transfer data */
149 + struct i2c_msg *current_msg; /* current message */
150 + int msgs_num; /* number of messages to handle */
151 + u8 *msg_buf; /* current buffer */
152 + u32 msg_buf_len; /* remaining length of current buffer */
153 + int msg_err; /* error status of the current transfer */
154 +
155 +
156 + /* master status codes */
157 + enum {
158 + STATUS_IDLE,
159 + STATUS_ADDR, /* address phase */
160 + STATUS_WRITE,
161 + STATUS_READ,
162 + STATUS_READ_END,
163 + STATUS_STOP
164 + } status;
165 +};
166 +
167 +static irqreturn_t ltq_i2c_isr(int irq, void *dev_id);
168 +
169 +static inline void enable_burst_irq(struct ltq_i2c *priv)
170 +{
171 + i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
172 +}
173 +static inline void disable_burst_irq(struct ltq_i2c *priv)
174 +{
175 + i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
176 +}
177 +
178 +static void prepare_msg_send_addr(struct ltq_i2c *priv)
179 +{
180 + struct i2c_msg *msg = priv->current_msg;
181 + int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */
182 + u16 addr = msg->addr;
183 +
184 + /* new i2c_msg */
185 + priv->msg_buf = msg->buf;
186 + priv->msg_buf_len = msg->len;
187 + if (rd)
188 + priv->status = STATUS_READ;
189 + else
190 + priv->status = STATUS_WRITE;
191 +
192 + /* send slave address */
193 + if (msg->flags & I2C_M_TEN) {
194 + i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);
195 + i2c_w32(addr & 0xff, txd);
196 + } else {
197 + i2c_w32((addr & 0x7f) << 1 | rd, txd);
198 + }
199 +}
200 +
201 +static void ltq_i2c_set_tx_len(struct ltq_i2c *priv)
202 +{
203 + struct i2c_msg *msg = priv->current_msg;
204 + int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
205 +
206 + pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T');
207 +
208 + priv->status = STATUS_ADDR;
209 +
210 + if (!(msg->flags & I2C_M_RD))
211 + len += msg->len;
212 + else
213 + /* set maximum received packet size (before rx int!) */
214 + i2c_w32(msg->len, mrps_ctrl);
215 + i2c_w32(len, tps_ctrl);
216 + enable_burst_irq(priv);
217 +}
218 +
219 +static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap)
220 +{
221 + struct ltq_i2c *priv = i2c_get_adapdata(adap);
222 + unsigned int input_clock = clk_get_rate(priv->clk_input);
223 + u32 dec, inc = 1;
224 +
225 + /* clock changed? */
226 + if (priv->input_clock == input_clock)
227 + return 0;
228 +
229 + /*
230 + * this formula is only an approximation, found by the recommended
231 + * values in the "I2C Architecture Specification 1.7.1"
232 + */
233 + dec = input_clock / (priv->i2c_clock * 2);
234 + if (dec <= 6)
235 + return -ENXIO;
236 +
237 + i2c_w32(0, fdiv_high_cfg);
238 + i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) |
239 + (dec << I2C_FDIV_CFG_DEC_OFFSET),
240 + fdiv_cfg);
241 +
242 + dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n",
243 + input_clock, priv->i2c_clock, dec);
244 +
245 + priv->input_clock = input_clock;
246 + return 0;
247 +}
248 +
249 +static int ltq_i2c_hw_init(struct i2c_adapter *adap)
250 +{
251 + int ret = 0;
252 + struct ltq_i2c *priv = i2c_get_adapdata(adap);
253 +
254 + /* disable bus */
255 + i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
256 +
257 +#ifndef DEBUG
258 + /* set normal operation clock divider */
259 + i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
260 +#else
261 + /* for debugging a higher divider value! */
262 + i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);
263 +#endif
264 +
265 + /* setup clock */
266 + ret = ltq_i2c_hw_set_clock(adap);
267 + if (ret != 0) {
268 + dev_warn(priv->dev, "invalid clock settings\n");
269 + return ret;
270 + }
271 +
272 + /* configure fifo */
273 + i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */
274 + I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */
275 + I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */
276 + I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */
277 + I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */
278 + I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */
279 + fifo_cfg);
280 +
281 + /* configure address */
282 + i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in
283 + the fifo */
284 + I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */
285 + I2C_ADDR_CFG_MnS_EN | /* we are master device */
286 + 0, /* our slave address (not used!) */
287 + addr_cfg);
288 +
289 + /* enable bus */
290 + i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
291 +
292 + return 0;
293 +}
294 +
295 +static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv)
296 +{
297 + unsigned long timeout;
298 +
299 + timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT);
300 +
301 + do {
302 + u32 stat = i2c_r32(bus_stat);
303 +
304 + if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE)
305 + return 0;
306 +
307 + cond_resched();
308 + } while (!time_after_eq(jiffies, timeout));
309 +
310 + dev_err(priv->dev, "timeout waiting for bus ready\n");
311 + return -ETIMEDOUT;
312 +}
313 +
314 +static void ltq_i2c_tx(struct ltq_i2c *priv, int last)
315 +{
316 + if (priv->msg_buf_len && priv->msg_buf) {
317 + i2c_w32(*priv->msg_buf, txd);
318 +
319 + if (--priv->msg_buf_len)
320 + priv->msg_buf++;
321 + else
322 + priv->msg_buf = NULL;
323 + } else {
324 + last = 1;
325 + }
326 +
327 + if (last)
328 + disable_burst_irq(priv);
329 +}
330 +
331 +static void ltq_i2c_rx(struct ltq_i2c *priv, int last)
332 +{
333 + u32 fifo_stat, timeout;
334 + if (priv->msg_buf_len && priv->msg_buf) {
335 + timeout = 5000000;
336 + do {
337 + fifo_stat = i2c_r32(ffs_stat);
338 + } while (!fifo_stat && --timeout);
339 + if (!timeout) {
340 + last = 1;
341 + pr_debug("\nrx timeout\n");
342 + goto err;
343 + }
344 + while (fifo_stat) {
345 + *priv->msg_buf = i2c_r32(rxd);
346 + if (--priv->msg_buf_len) {
347 + priv->msg_buf++;
348 + } else {
349 + priv->msg_buf = NULL;
350 + last = 1;
351 + break;
352 + }
353 + /*
354 + * do not read more than burst size, otherwise no "last
355 + * burst" is generated and the transaction is blocked!
356 + */
357 + fifo_stat = 0;
358 + }
359 + } else {
360 + last = 1;
361 + }
362 +err:
363 + if (last) {
364 + disable_burst_irq(priv);
365 +
366 + if (priv->status == STATUS_READ_END) {
367 + /*
368 + * do the STATUS_STOP and complete() here, as sometimes
369 + * the tx_end is already seen before this is finished
370 + */
371 + priv->status = STATUS_STOP;
372 + complete(&priv->cmd_complete);
373 + } else {
374 + i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
375 + priv->status = STATUS_READ_END;
376 + }
377 + }
378 +}
379 +
380 +static void ltq_i2c_xfer_init(struct ltq_i2c *priv)
381 +{
382 + /* enable interrupts */
383 + i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc);
384 +
385 + /* trigger transfer of first msg */
386 + ltq_i2c_set_tx_len(priv);
387 +}
388 +
389 +static void dump_msgs(struct i2c_msg msgs[], int num, int rx)
390 +{
391 +#if defined(DEBUG)
392 + int i, j;
393 + pr_debug("Messages %d %s\n", num, rx ? "out" : "in");
394 + for (i = 0; i < num; i++) {
395 + pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i,
396 + (msgs[i].flags & I2C_M_RD) ? 'R' : 'T',
397 + msgs[i].len, msgs[i].addr);
398 + if (!(msgs[i].flags & I2C_M_RD) || rx) {
399 + for (j = 0; j < msgs[i].len; j++)
400 + pr_debug("%02X ", msgs[i].buf[j]);
401 + }
402 + pr_debug("\n");
403 + }
404 +#endif
405 +}
406 +
407 +static void ltq_i2c_release_bus(struct ltq_i2c *priv)
408 +{
409 + if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)
410 + i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
411 +}
412 +
413 +static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
414 + int num)
415 +{
416 + struct ltq_i2c *priv = i2c_get_adapdata(adap);
417 + int ret;
418 +
419 + dev_dbg(priv->dev, "xfer %u messages\n", num);
420 + dump_msgs(msgs, num, 0);
421 +
422 + mutex_lock(&priv->mutex);
423 +
424 + INIT_COMPLETION(priv->cmd_complete);
425 + priv->current_msg = msgs;
426 + priv->msgs_num = num;
427 + priv->msg_err = 0;
428 + priv->status = STATUS_IDLE;
429 +
430 + /* wait for the bus to become ready */
431 + ret = ltq_i2c_wait_bus_not_busy(priv);
432 + if (ret)
433 + goto done;
434 +
435 + while (priv->msgs_num) {
436 + /* start the transfers */
437 + ltq_i2c_xfer_init(priv);
438 +
439 + /* wait for transfers to complete */
440 + ret = wait_for_completion_interruptible_timeout(
441 + &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT);
442 + if (ret == 0) {
443 + dev_err(priv->dev, "controller timed out\n");
444 + ltq_i2c_hw_init(adap);
445 + ret = -ETIMEDOUT;
446 + goto done;
447 + } else if (ret < 0)
448 + goto done;
449 +
450 + if (priv->msg_err) {
451 + if (priv->msg_err & LTQ_I2C_NACK)
452 + ret = -ENXIO;
453 + else
454 + ret = -EREMOTEIO;
455 + goto done;
456 + }
457 + if (--priv->msgs_num)
458 + priv->current_msg++;
459 + }
460 + /* no error? */
461 + ret = num;
462 +
463 +done:
464 + ltq_i2c_release_bus(priv);
465 +
466 + mutex_unlock(&priv->mutex);
467 +
468 + if (ret >= 0)
469 + dump_msgs(msgs, num, 1);
470 +
471 + pr_debug("XFER ret %d\n", ret);
472 + return ret;
473 +}
474 +
475 +static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id)
476 +{
477 + struct ltq_i2c *priv = dev_id;
478 + struct i2c_msg *msg = priv->current_msg;
479 + int last = (irq == priv->irq_lb);
480 +
481 + if (last)
482 + pr_debug("LB ");
483 + else
484 + pr_debug("B ");
485 +
486 + if (msg->flags & I2C_M_RD) {
487 + switch (priv->status) {
488 + case STATUS_ADDR:
489 + pr_debug("X");
490 + prepare_msg_send_addr(priv);
491 + disable_burst_irq(priv);
492 + break;
493 + case STATUS_READ:
494 + case STATUS_READ_END:
495 + pr_debug("R");
496 + ltq_i2c_rx(priv, last);
497 + break;
498 + default:
499 + disable_burst_irq(priv);
500 + pr_warn("Status R %d\n", priv->status);
501 + break;
502 + }
503 + } else {
504 + switch (priv->status) {
505 + case STATUS_ADDR:
506 + pr_debug("x");
507 + prepare_msg_send_addr(priv);
508 + break;
509 + case STATUS_WRITE:
510 + pr_debug("w");
511 + ltq_i2c_tx(priv, last);
512 + break;
513 + default:
514 + disable_burst_irq(priv);
515 + pr_warn("Status W %d\n", priv->status);
516 + break;
517 + }
518 + }
519 +
520 + i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);
521 + return IRQ_HANDLED;
522 +}
523 +
524 +static void ltq_i2c_isr_prot(struct ltq_i2c *priv)
525 +{
526 + u32 i_pro = i2c_r32(p_irqss);
527 +
528 + pr_debug("i2c-p");
529 +
530 + /* not acknowledge */
531 + if (i_pro & I2C_P_IRQSS_NACK) {
532 + priv->msg_err |= LTQ_I2C_NACK;
533 + pr_debug(" nack");
534 + }
535 +
536 + /* arbitration lost */
537 + if (i_pro & I2C_P_IRQSS_AL) {
538 + priv->msg_err |= LTQ_I2C_ARB_LOST;
539 + pr_debug(" arb-lost");
540 + }
541 + /* tx -> rx switch */
542 + if (i_pro & I2C_P_IRQSS_RX)
543 + pr_debug(" rx");
544 +
545 + /* tx end */
546 + if (i_pro & I2C_P_IRQSS_TX_END)
547 + pr_debug(" txend");
548 + pr_debug("\n");
549 +
550 + if (!priv->msg_err) {
551 + /* tx -> rx switch */
552 + if (i_pro & I2C_P_IRQSS_RX) {
553 + priv->status = STATUS_READ;
554 + enable_burst_irq(priv);
555 + }
556 + if (i_pro & I2C_P_IRQSS_TX_END) {
557 + if (priv->status == STATUS_READ)
558 + priv->status = STATUS_READ_END;
559 + else {
560 + disable_burst_irq(priv);
561 + priv->status = STATUS_STOP;
562 + }
563 + }
564 + }
565 +
566 + i2c_w32(i_pro, p_irqsc);
567 +}
568 +
569 +static irqreturn_t ltq_i2c_isr(int irq, void *dev_id)
570 +{
571 + u32 i_raw, i_err = 0;
572 + struct ltq_i2c *priv = dev_id;
573 +
574 + i_raw = i2c_r32(mis);
575 + pr_debug("i_raw 0x%08X\n", i_raw);
576 +
577 + /* error interrupt */
578 + if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
579 + i_err = i2c_r32(err_irqss);
580 + pr_debug("i_err 0x%08X bus_stat 0x%04X\n",
581 + i_err, i2c_r32(bus_stat));
582 +
583 + /* tx fifo overflow (8) */
584 + if (i_err & I2C_ERR_IRQSS_TXF_OFL)
585 + priv->msg_err |= LTQ_I2C_TX_OFL;
586 +
587 + /* tx fifo underflow (4) */
588 + if (i_err & I2C_ERR_IRQSS_TXF_UFL)
589 + priv->msg_err |= LTQ_I2C_TX_UFL;
590 +
591 + /* rx fifo overflow (2) */
592 + if (i_err & I2C_ERR_IRQSS_RXF_OFL)
593 + priv->msg_err |= LTQ_I2C_RX_OFL;
594 +
595 + /* rx fifo underflow (1) */
596 + if (i_err & I2C_ERR_IRQSS_RXF_UFL)
597 + priv->msg_err |= LTQ_I2C_RX_UFL;
598 +
599 + i2c_w32(i_err, err_irqsc);
600 + }
601 +
602 + /* protocol interrupt */
603 + if (i_raw & I2C_RIS_I2C_P_INT_INTOCC)
604 + ltq_i2c_isr_prot(priv);
605 +
606 + if ((priv->msg_err) || (priv->status == STATUS_STOP))
607 + complete(&priv->cmd_complete);
608 +
609 + return IRQ_HANDLED;
610 +}
611 +
612 +static u32 ltq_i2c_functionality(struct i2c_adapter *adap)
613 +{
614 + return I2C_FUNC_I2C |
615 + I2C_FUNC_10BIT_ADDR |
616 + I2C_FUNC_SMBUS_EMUL;
617 +}
618 +
619 +static struct i2c_algorithm ltq_i2c_algorithm = {
620 + .master_xfer = ltq_i2c_xfer,
621 + .functionality = ltq_i2c_functionality,
622 +};
623 +
624 +static int __devinit ltq_i2c_probe(struct platform_device *pdev)
625 +{
626 + struct device_node *node = pdev->dev.of_node;
627 + struct ltq_i2c *priv;
628 + struct i2c_adapter *adap;
629 + struct resource *mmres, irqres[4];
630 + int ret = 0;
631 +
632 + dev_dbg(&pdev->dev, "probing\n");
633 +
634 + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
635 + ret = of_irq_to_resource_table(node, irqres, 4);
636 + if (!mmres || (ret != 4)) {
637 + dev_err(&pdev->dev, "no resources\n");
638 + return -ENODEV;
639 + }
640 +
641 + /* allocate private data */
642 + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
643 + if (!priv) {
644 + dev_err(&pdev->dev, "can't allocate private data\n");
645 + return -ENOMEM;
646 + }
647 +
648 + adap = &priv->adap;
649 + i2c_set_adapdata(adap, priv);
650 + adap->owner = THIS_MODULE;
651 + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
652 + strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
653 + adap->algo = &ltq_i2c_algorithm;
654 +
655 + if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) {
656 + dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n");
657 + priv->i2c_clock = 100000;
658 + }
659 +
660 + init_completion(&priv->cmd_complete);
661 + mutex_init(&priv->mutex);
662 +
663 + priv->membase = devm_request_and_ioremap(&pdev->dev, mmres);
664 + if (priv->membase == NULL)
665 + return -ENOMEM;
666 +
667 + priv->dev = &pdev->dev;
668 + priv->irq_lb = irqres[0].start;
669 +
670 + ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst,
671 + IRQF_DISABLED, "i2c lb", priv);
672 + if (ret) {
673 + dev_err(&pdev->dev, "can't get last burst IRQ %d\n",
674 + irqres[0].start);
675 + return -ENODEV;
676 + }
677 +
678 + ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst,
679 + IRQF_DISABLED, "i2c b", priv);
680 + if (ret) {
681 + dev_err(&pdev->dev, "can't get burst IRQ %d\n",
682 + irqres[1].start);
683 + return -ENODEV;
684 + }
685 +
686 + ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr,
687 + IRQF_DISABLED, "i2c err", priv);
688 + if (ret) {
689 + dev_err(&pdev->dev, "can't get error IRQ %d\n",
690 + irqres[2].start);
691 + return -ENODEV;
692 + }
693 +
694 + ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr,
695 + IRQF_DISABLED, "i2c p", priv);
696 + if (ret) {
697 + dev_err(&pdev->dev, "can't get protocol IRQ %d\n",
698 + irqres[3].start);
699 + return -ENODEV;
700 + }
701 +
702 + dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
703 + dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start,
704 + irqres[1].start, irqres[2].start, irqres[3].start);
705 +
706 + priv->clk_gate = devm_clk_get(&pdev->dev, NULL);
707 + if (IS_ERR(priv->clk_gate)) {
708 + dev_err(&pdev->dev, "failed to get i2c clk\n");
709 + return -ENOENT;
710 + }
711 +
712 + /* this is a static clock, which has no refcounting */
713 + priv->clk_input = clk_get_fpi();
714 + if (IS_ERR(priv->clk_input)) {
715 + dev_err(&pdev->dev, "failed to get fpi clk\n");
716 + return -ENOENT;
717 + }
718 +
719 + clk_activate(priv->clk_gate);
720 +
721 + /* add our adapter to the i2c stack */
722 + ret = i2c_add_numbered_adapter(adap);
723 + if (ret) {
724 + dev_err(&pdev->dev, "can't register I2C adapter\n");
725 + goto out;
726 + }
727 +
728 + platform_set_drvdata(pdev, priv);
729 + i2c_set_adapdata(adap, priv);
730 +
731 + /* print module version information */
732 + dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
733 + (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
734 + (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
735 +
736 + /* initialize HW */
737 + ret = ltq_i2c_hw_init(adap);
738 + if (ret) {
739 + dev_err(&pdev->dev, "can't configure adapter\n");
740 + i2c_del_adapter(adap);
741 + platform_set_drvdata(pdev, NULL);
742 + } else {
743 + dev_info(&pdev->dev, "version %s\n", DRV_VERSION);
744 + }
745 +
746 + of_i2c_register_devices(adap);
747 +
748 +out:
749 + /* if init failed, we need to deactivate the clock gate */
750 + if (ret)
751 + clk_deactivate(priv->clk_gate);
752 +
753 + return ret;
754 +}
755 +
756 +static int __devexit ltq_i2c_remove(struct platform_device *pdev)
757 +{
758 + struct ltq_i2c *priv = platform_get_drvdata(pdev);
759 +
760 + /* disable bus */
761 + i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
762 +
763 + /* power down the core */
764 + clk_deactivate(priv->clk_gate);
765 +
766 + /* remove driver */
767 + i2c_del_adapter(&priv->adap);
768 + kfree(priv);
769 +
770 + dev_dbg(&pdev->dev, "removed\n");
771 + platform_set_drvdata(pdev, NULL);
772 +
773 + return 0;
774 +}
775 +static const struct of_device_id ltq_i2c_match[] = {
776 + { .compatible = "lantiq,lantiq-i2c" },
777 + {},
778 +};
779 +MODULE_DEVICE_TABLE(of, ltq_i2c_match);
780 +
781 +static struct platform_driver ltq_i2c_driver = {
782 + .probe = ltq_i2c_probe,
783 + .remove = __devexit_p(ltq_i2c_remove),
784 + .driver = {
785 + .name = DRV_NAME,
786 + .owner = THIS_MODULE,
787 + .of_match_table = ltq_i2c_match,
788 + },
789 +};
790 +
791 +module_platform_driver(ltq_i2c_driver);
792 +
793 +MODULE_DESCRIPTION("Lantiq I2C bus adapter");
794 +MODULE_AUTHOR("Thomas Langer <thomas.langer@lantiq.com>");
795 +MODULE_ALIAS("platform:" DRV_NAME);
796 +MODULE_LICENSE("GPL");
797 +MODULE_VERSION(DRV_VERSION);
798 --- /dev/null
799 +++ b/drivers/i2c/busses/i2c-lantiq.h
800 @@ -0,0 +1,234 @@
801 +#ifndef I2C_LANTIQ_H
802 +#define I2C_LANTIQ_H
803 +
804 +/* I2C register structure */
805 +struct lantiq_reg_i2c {
806 + /* I2C Kernel Clock Control Register */
807 + unsigned int clc; /* 0x00000000 */
808 + /* Reserved */
809 + unsigned int res_0; /* 0x00000004 */
810 + /* I2C Identification Register */
811 + unsigned int id; /* 0x00000008 */
812 + /* Reserved */
813 + unsigned int res_1; /* 0x0000000C */
814 + /*
815 + * I2C RUN Control Register
816 + * This register enables and disables the I2C peripheral. Before
817 + * enabling, the I2C has to be configured properly. After enabling
818 + * no configuration is possible
819 + */
820 + unsigned int run_ctrl; /* 0x00000010 */
821 + /*
822 + * I2C End Data Control Register
823 + * This register is used to either turn around the data transmission
824 + * direction or to address another slave without sending a stop
825 + * condition. Also the software can stop the slave-transmitter by
826 + * sending a not-accolade when working as master-receiver or even
827 + * stop data transmission immediately when operating as
828 + * master-transmitter. The writing to the bits of this control
829 + * register is only effective when in MASTER RECEIVES BYTES, MASTER
830 + * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state
831 + */
832 + unsigned int endd_ctrl; /* 0x00000014 */
833 + /*
834 + * I2C Fractional Divider Configuration Register
835 + * These register is used to program the fractional divider of the I2C
836 + * bus. Before the peripheral is switched on by setting the RUN-bit the
837 + * two (fixed) values for the two operating frequencies are programmed
838 + * into these (configuration) registers. The Register FDIV_HIGH_CFG has
839 + * the same layout as I2C_FDIV_CFG.
840 + */
841 + unsigned int fdiv_cfg; /* 0x00000018 */
842 + /*
843 + * I2C Fractional Divider (highspeed mode) Configuration Register
844 + * These register is used to program the fractional divider of the I2C
845 + * bus. Before the peripheral is switched on by setting the RUN-bit the
846 + * two (fixed) values for the two operating frequencies are programmed
847 + * into these (configuration) registers. The Register FDIV_CFG has the
848 + * same layout as I2C_FDIV_CFG.
849 + */
850 + unsigned int fdiv_high_cfg; /* 0x0000001C */
851 + /* I2C Address Configuration Register */
852 + unsigned int addr_cfg; /* 0x00000020 */
853 + /* I2C Bus Status Register
854 + * This register gives a status information of the I2C. This additional
855 + * information can be used by the software to start proper actions.
856 + */
857 + unsigned int bus_stat; /* 0x00000024 */
858 + /* I2C FIFO Configuration Register */
859 + unsigned int fifo_cfg; /* 0x00000028 */
860 + /* I2C Maximum Received Packet Size Register */
861 + unsigned int mrps_ctrl; /* 0x0000002C */
862 + /* I2C Received Packet Size Status Register */
863 + unsigned int rps_stat; /* 0x00000030 */
864 + /* I2C Transmit Packet Size Register */
865 + unsigned int tps_ctrl; /* 0x00000034 */
866 + /* I2C Filled FIFO Stages Status Register */
867 + unsigned int ffs_stat; /* 0x00000038 */
868 + /* Reserved */
869 + unsigned int res_2; /* 0x0000003C */
870 + /* I2C Timing Configuration Register */
871 + unsigned int tim_cfg; /* 0x00000040 */
872 + /* Reserved */
873 + unsigned int res_3[7]; /* 0x00000044 */
874 + /* I2C Error Interrupt Request Source Mask Register */
875 + unsigned int err_irqsm; /* 0x00000060 */
876 + /* I2C Error Interrupt Request Source Status Register */
877 + unsigned int err_irqss; /* 0x00000064 */
878 + /* I2C Error Interrupt Request Source Clear Register */
879 + unsigned int err_irqsc; /* 0x00000068 */
880 + /* Reserved */
881 + unsigned int res_4; /* 0x0000006C */
882 + /* I2C Protocol Interrupt Request Source Mask Register */
883 + unsigned int p_irqsm; /* 0x00000070 */
884 + /* I2C Protocol Interrupt Request Source Status Register */
885 + unsigned int p_irqss; /* 0x00000074 */
886 + /* I2C Protocol Interrupt Request Source Clear Register */
887 + unsigned int p_irqsc; /* 0x00000078 */
888 + /* Reserved */
889 + unsigned int res_5; /* 0x0000007C */
890 + /* I2C Raw Interrupt Status Register */
891 + unsigned int ris; /* 0x00000080 */
892 + /* I2C Interrupt Mask Control Register */
893 + unsigned int imsc; /* 0x00000084 */
894 + /* I2C Masked Interrupt Status Register */
895 + unsigned int mis; /* 0x00000088 */
896 + /* I2C Interrupt Clear Register */
897 + unsigned int icr; /* 0x0000008C */
898 + /* I2C Interrupt Set Register */
899 + unsigned int isr; /* 0x00000090 */
900 + /* I2C DMA Enable Register */
901 + unsigned int dmae; /* 0x00000094 */
902 + /* Reserved */
903 + unsigned int res_6[8154]; /* 0x00000098 */
904 + /* I2C Transmit Data Register */
905 + unsigned int txd; /* 0x00008000 */
906 + /* Reserved */
907 + unsigned int res_7[4095]; /* 0x00008004 */
908 + /* I2C Receive Data Register */
909 + unsigned int rxd; /* 0x0000C000 */
910 + /* Reserved */
911 + unsigned int res_8[4095]; /* 0x0000C004 */
912 +};
913 +
914 +/*
915 + * Clock Divider for Normal Run Mode
916 + * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long
917 + * as the new divider value RMC is not valid, the register returns 0x0000 00xx
918 + * on reading.
919 + */
920 +#define I2C_CLC_RMC_MASK 0x0000FF00
921 +/* field offset */
922 +#define I2C_CLC_RMC_OFFSET 8
923 +
924 +/* Fields of "I2C Identification Register" */
925 +/* Module ID */
926 +#define I2C_ID_ID_MASK 0x0000FF00
927 +/* field offset */
928 +#define I2C_ID_ID_OFFSET 8
929 +/* Revision */
930 +#define I2C_ID_REV_MASK 0x000000FF
931 +/* field offset */
932 +#define I2C_ID_REV_OFFSET 0
933 +
934 +/* Fields of "I2C Interrupt Mask Control Register" */
935 +/* Enable */
936 +#define I2C_IMSC_BREQ_INT_EN 0x00000008
937 +/* Enable */
938 +#define I2C_IMSC_LBREQ_INT_EN 0x00000004
939 +
940 +/* Fields of "I2C Fractional Divider Configuration Register" */
941 +/* field offset */
942 +#define I2C_FDIV_CFG_INC_OFFSET 16
943 +
944 +/* Fields of "I2C Interrupt Mask Control Register" */
945 +/* Enable */
946 +#define I2C_IMSC_I2C_P_INT_EN 0x00000020
947 +/* Enable */
948 +#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
949 +
950 +/* Fields of "I2C Error Interrupt Request Source Status Register" */
951 +/* TXF_OFL */
952 +#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
953 +/* TXF_UFL */
954 +#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
955 +/* RXF_OFL */
956 +#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
957 +/* RXF_UFL */
958 +#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
959 +
960 +/* Fields of "I2C Raw Interrupt Status Register" */
961 +/* Read: Interrupt occurred. */
962 +#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
963 +/* Read: Interrupt occurred. */
964 +#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
965 +
966 +/* Fields of "I2C FIFO Configuration Register" */
967 +/* TX FIFO Flow Control */
968 +#define I2C_FIFO_CFG_TXFC 0x00020000
969 +/* RX FIFO Flow Control */
970 +#define I2C_FIFO_CFG_RXFC 0x00010000
971 +/* Word aligned (character alignment of four characters) */
972 +#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
973 +/* Word aligned (character alignment of four characters) */
974 +#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
975 +/* 1 word */
976 +#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
977 +
978 +/* Fields of "I2C FIFO Configuration Register" */
979 +/* 1 word */
980 +#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
981 +/* Stop on Packet End Enable */
982 +#define I2C_ADDR_CFG_SOPE_EN 0x00200000
983 +/* Stop on Not Acknowledge Enable */
984 +#define I2C_ADDR_CFG_SONA_EN 0x00100000
985 +/* Enable */
986 +#define I2C_ADDR_CFG_MnS_EN 0x00080000
987 +
988 +/* Fields of "I2C Interrupt Clear Register" */
989 +/* Clear */
990 +#define I2C_ICR_BREQ_INT_CLR 0x00000008
991 +/* Clear */
992 +#define I2C_ICR_LBREQ_INT_CLR 0x00000004
993 +
994 +/* Fields of "I2C Fractional Divider Configuration Register" */
995 +/* field offset */
996 +#define I2C_FDIV_CFG_DEC_OFFSET 0
997 +
998 +/* Fields of "I2C Bus Status Register" */
999 +/* Bus Status */
1000 +#define I2C_BUS_STAT_BS_MASK 0x00000003
1001 +/* Read from I2C Bus. */
1002 +#define I2C_BUS_STAT_RNW_READ 0x00000004
1003 +/* I2C Bus is free. */
1004 +#define I2C_BUS_STAT_BS_FREE 0x00000000
1005 +/*
1006 + * The device is working as master and has claimed the control on the
1007 + * I2C-bus (busy master).
1008 + */
1009 +#define I2C_BUS_STAT_BS_BM 0x00000002
1010 +
1011 +/* Fields of "I2C RUN Control Register" */
1012 +/* Enable */
1013 +#define I2C_RUN_CTRL_RUN_EN 0x00000001
1014 +
1015 +/* Fields of "I2C End Data Control Register" */
1016 +/*
1017 + * Set End of Transmission
1018 + * Note:Do not write '1' to this bit when bus is free. This will cause an
1019 + * abort after the first byte when a new transfer is started.
1020 + */
1021 +#define I2C_ENDD_CTRL_SETEND 0x00000002
1022 +
1023 +/* Fields of "I2C Protocol Interrupt Request Source Status Register" */
1024 +/* NACK */
1025 +#define I2C_P_IRQSS_NACK 0x00000010
1026 +/* AL */
1027 +#define I2C_P_IRQSS_AL 0x00000008
1028 +/* RX */
1029 +#define I2C_P_IRQSS_RX 0x00000040
1030 +/* TX_END */
1031 +#define I2C_P_IRQSS_TX_END 0x00000020
1032 +
1033 +
1034 +#endif /* I2C_LANTIQ_H */