705430ea725e2f2a271acba27e3e78b659d06271
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.14 / 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
1 From fb0c9601f4414c39ff68e26b88681bef0bb04954 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Oct 2012 12:22:23 +0200
4 Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
5
6 ---
7 drivers/net/ethernet/Kconfig | 8 +-
8 drivers/net/ethernet/Makefile | 1 +
9 drivers/net/ethernet/lantiq_pce.h | 163 +++
10 drivers/net/ethernet/lantiq_xrx200.c | 1798 +++++++++++++++++++++++++++++++
11 drivers/net/ethernet/lantiq_xrx200_sw.h | 1328 +++++++++++++++++++++++
12 5 files changed, 3297 insertions(+), 1 deletion(-)
13 create mode 100644 drivers/net/ethernet/lantiq_pce.h
14 create mode 100644 drivers/net/ethernet/lantiq_xrx200.c
15 create mode 100644 drivers/net/ethernet/lantiq_xrx200_sw.h
16
17 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
18 index 506b024..0a0dbe6 100644
19 --- a/drivers/net/ethernet/Kconfig
20 +++ b/drivers/net/ethernet/Kconfig
21 @@ -84,7 +84,13 @@ config LANTIQ_ETOP
22 tristate "Lantiq SoC ETOP driver"
23 depends on SOC_TYPE_XWAY
24 ---help---
25 - Support for the MII0 inside the Lantiq SoC
26 + Support for the MII0 inside the Lantiq ADSL SoC
27 +
28 +config LANTIQ_XRX200
29 + tristate "Lantiq SoC XRX200 driver"
30 + depends on SOC_TYPE_XWAY
31 + ---help---
32 + Support for the MII0 inside the Lantiq VDSL SoC
33
34 source "drivers/net/ethernet/marvell/Kconfig"
35 source "drivers/net/ethernet/mellanox/Kconfig"
36 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
37 index c0b8789..459cce8 100644
38 --- a/drivers/net/ethernet/Makefile
39 +++ b/drivers/net/ethernet/Makefile
40 @@ -38,6 +38,7 @@ obj-$(CONFIG_IP1000) += icplus/
41 obj-$(CONFIG_JME) += jme.o
42 obj-$(CONFIG_KORINA) += korina.o
43 obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
44 +obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o
45 obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
46 obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
47 obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
48 diff --git a/drivers/net/ethernet/lantiq_pce.h b/drivers/net/ethernet/lantiq_pce.h
49 new file mode 100644
50 index 0000000..0c38efe
51 --- /dev/null
52 +++ b/drivers/net/ethernet/lantiq_pce.h
53 @@ -0,0 +1,163 @@
54 +/*
55 + * This program is free software; you can redistribute it and/or modify it
56 + * under the terms of the GNU General Public License version 2 as published
57 + * by the Free Software Foundation.
58 + *
59 + * This program is distributed in the hope that it will be useful,
60 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
61 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
62 + * GNU General Public License for more details.
63 + *
64 + * You should have received a copy of the GNU General Public License
65 + * along with this program; if not, write to the Free Software
66 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
67 + *
68 + * Copyright (C) 2010 Lantiq Deutschland GmbH
69 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
70 + *
71 + * PCE microcode extracted from UGW5.2 switch api
72 + */
73 +
74 +/* Switch API Micro Code V0.3 */
75 +enum {
76 + OUT_MAC0 = 0,
77 + OUT_MAC1,
78 + OUT_MAC2,
79 + OUT_MAC3,
80 + OUT_MAC4,
81 + OUT_MAC5,
82 + OUT_ETHTYP,
83 + OUT_VTAG0,
84 + OUT_VTAG1,
85 + OUT_ITAG0,
86 + OUT_ITAG1, /*10 */
87 + OUT_ITAG2,
88 + OUT_ITAG3,
89 + OUT_IP0,
90 + OUT_IP1,
91 + OUT_IP2,
92 + OUT_IP3,
93 + OUT_SIP0,
94 + OUT_SIP1,
95 + OUT_SIP2,
96 + OUT_SIP3, /*20*/
97 + OUT_SIP4,
98 + OUT_SIP5,
99 + OUT_SIP6,
100 + OUT_SIP7,
101 + OUT_DIP0,
102 + OUT_DIP1,
103 + OUT_DIP2,
104 + OUT_DIP3,
105 + OUT_DIP4,
106 + OUT_DIP5, /*30*/
107 + OUT_DIP6,
108 + OUT_DIP7,
109 + OUT_SESID,
110 + OUT_PROT,
111 + OUT_APP0,
112 + OUT_APP1,
113 + OUT_IGMP0,
114 + OUT_IGMP1,
115 + OUT_IPOFF, /*39*/
116 + OUT_NONE = 63
117 +};
118 +
119 +/* parser's microcode length type */
120 +#define INSTR 0
121 +#define IPV6 1
122 +#define LENACCU 2
123 +
124 +/* parser's microcode flag type */
125 +enum {
126 + FLAG_ITAG = 0,
127 + FLAG_VLAN,
128 + FLAG_SNAP,
129 + FLAG_PPPOE,
130 + FLAG_IPV6,
131 + FLAG_IPV6FL,
132 + FLAG_IPV4,
133 + FLAG_IGMP,
134 + FLAG_TU,
135 + FLAG_HOP,
136 + FLAG_NN1, /*10 */
137 + FLAG_NN2,
138 + FLAG_END,
139 + FLAG_NO, /*13*/
140 +};
141 +
142 +/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */
143 +#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \
144 + { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }}
145 +struct pce_microcode {
146 + unsigned short val[4];
147 +/* unsigned short val_2;
148 + unsigned short val_1;
149 + unsigned short val_0;*/
150 +} pce_microcode[] = {
151 + /* value mask ns fields L type flags ipv4_len */
152 + MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
153 + MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
154 + MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
155 + MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
156 + MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
157 + MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
158 + MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
159 + MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
160 + MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0),
161 + MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
162 + MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
163 + MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0),
164 + MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0),
165 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
166 + MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0),
167 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
168 + MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0),
169 + MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0),
170 + MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0),
171 + MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0),
172 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
173 + MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1),
174 + MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0),
175 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
176 + MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0),
177 + MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0),
178 + MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0),
179 + MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
180 + MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
181 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0),
182 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0),
183 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0),
184 + MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
185 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0),
186 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0),
187 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0),
188 + MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0),
189 + MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0),
190 + MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0),
191 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
192 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
193 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
194 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
195 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
196 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
197 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
198 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
199 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
200 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
201 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
202 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
203 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
204 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
205 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
206 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
207 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
208 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
209 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
210 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
211 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
212 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
213 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
214 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
215 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
216 +};
217 diff --git a/drivers/net/ethernet/lantiq_xrx200.c b/drivers/net/ethernet/lantiq_xrx200.c
218 new file mode 100644
219 index 0000000..2da9d47
220 --- /dev/null
221 +++ b/drivers/net/ethernet/lantiq_xrx200.c
222 @@ -0,0 +1,1798 @@
223 +/*
224 + * This program is free software; you can redistribute it and/or modify it
225 + * under the terms of the GNU General Public License version 2 as published
226 + * by the Free Software Foundation.
227 + *
228 + * This program is distributed in the hope that it will be useful,
229 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
230 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
231 + * GNU General Public License for more details.
232 + *
233 + * You should have received a copy of the GNU General Public License
234 + * along with this program; if not, write to the Free Software
235 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
236 + *
237 + * Copyright (C) 2010 Lantiq Deutschland
238 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
239 + */
240 +
241 +#include <linux/switch.h>
242 +#include <linux/etherdevice.h>
243 +#include <linux/module.h>
244 +#include <linux/platform_device.h>
245 +#include <linux/interrupt.h>
246 +#include <linux/clk.h>
247 +#include <asm/delay.h>
248 +
249 +#include <linux/of_net.h>
250 +#include <linux/of_mdio.h>
251 +#include <linux/of_gpio.h>
252 +
253 +#include <xway_dma.h>
254 +#include <lantiq_soc.h>
255 +
256 +#include "lantiq_pce.h"
257 +#include "lantiq_xrx200_sw.h"
258 +
259 +#define SW_POLLING
260 +#define SW_ROUTING
261 +#define SW_PORTMAP
262 +
263 +#ifdef SW_ROUTING
264 + #ifdef SW_PORTMAP
265 +#define XRX200_MAX_DEV 2
266 + #else
267 +#define XRX200_MAX_DEV 2
268 + #endif
269 +#else
270 +#define XRX200_MAX_DEV 1
271 +#endif
272 +
273 +#define XRX200_MAX_VLAN 64
274 +#define XRX200_PCE_ACTVLAN_IDX 0x01
275 +#define XRX200_PCE_VLANMAP_IDX 0x02
276 +
277 +#define XRX200_MAX_PORT 7
278 +#define XRX200_MAX_DMA 8
279 +
280 +#define XRX200_HEADROOM 4
281 +
282 +#define XRX200_TX_TIMEOUT (10 * HZ)
283 +
284 +/* port type */
285 +#define XRX200_PORT_TYPE_PHY 1
286 +#define XRX200_PORT_TYPE_MAC 2
287 +
288 +/* DMA */
289 +#define XRX200_DMA_DATA_LEN 0x600
290 +#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0
291 +#define XRX200_DMA_RX 0
292 +#define XRX200_DMA_TX 1
293 +#define XRX200_DMA_IS_TX(x) (x%2)
294 +#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x))
295 +
296 +/* fetch / store dma */
297 +#define FDMA_PCTRL0 0x2A00
298 +#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18))
299 +#define SDMA_PCTRL0 0x2F00
300 +#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18))
301 +
302 +/* buffer management */
303 +#define BM_PCFG0 0x200
304 +#define BM_PCFGx(x) (BM_PCFG0 + (x * 8))
305 +
306 +/* MDIO */
307 +#define MDIO_GLOB 0x0000
308 +#define MDIO_CTRL 0x0020
309 +#define MDIO_READ 0x0024
310 +#define MDIO_WRITE 0x0028
311 +#define MDIO_PHY0 0x0054
312 +#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned)))
313 +#define MDIO_CLK_CFG0 0x002C
314 +#define MDIO_CLK_CFG1 0x0030
315 +
316 +#define MDIO_GLOB_ENABLE 0x8000
317 +#define MDIO_BUSY BIT(12)
318 +#define MDIO_RD BIT(11)
319 +#define MDIO_WR BIT(10)
320 +#define MDIO_MASK 0x1f
321 +#define MDIO_ADDRSHIFT 5
322 +#define MDIO1_25MHZ 9
323 +
324 +#define MDIO_PHY_LINK_DOWN 0x4000
325 +#define MDIO_PHY_LINK_UP 0x2000
326 +
327 +#define MDIO_PHY_SPEED_M10 0x0000
328 +#define MDIO_PHY_SPEED_M100 0x0800
329 +#define MDIO_PHY_SPEED_G1 0x1000
330 +
331 +#define MDIO_PHY_FDUP_EN 0x0200
332 +#define MDIO_PHY_FDUP_DIS 0x0600
333 +
334 +#define MDIO_PHY_LINK_MASK 0x6000
335 +#define MDIO_PHY_SPEED_MASK 0x1800
336 +#define MDIO_PHY_FDUP_MASK 0x0600
337 +#define MDIO_PHY_ADDR_MASK 0x001f
338 +#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \
339 + MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK
340 +
341 +/* MII */
342 +#define MII_CFG(p) (p * 8)
343 +
344 +#define MII_CFG_EN BIT(14)
345 +
346 +#define MII_CFG_MODE_MIIP 0x0
347 +#define MII_CFG_MODE_MIIM 0x1
348 +#define MII_CFG_MODE_RMIIP 0x2
349 +#define MII_CFG_MODE_RMIIM 0x3
350 +#define MII_CFG_MODE_RGMII 0x4
351 +#define MII_CFG_MODE_MASK 0xf
352 +
353 +#define MII_CFG_RATE_M2P5 0x00
354 +#define MII_CFG_RATE_M25 0x10
355 +#define MII_CFG_RATE_M125 0x20
356 +#define MII_CFG_RATE_M50 0x30
357 +#define MII_CFG_RATE_AUTO 0x40
358 +#define MII_CFG_RATE_MASK 0x70
359 +
360 +/* cpu port mac */
361 +#define PMAC_HD_CTL 0x0000
362 +#define PMAC_RX_IPG 0x0024
363 +#define PMAC_EWAN 0x002c
364 +
365 +#define PMAC_IPG_MASK 0xf
366 +#define PMAC_HD_CTL_AS 0x0008
367 +#define PMAC_HD_CTL_AC 0x0004
368 +#define PMAC_HD_CTL_RXSH 0x0040
369 +#define PMAC_HD_CTL_AST 0x0080
370 +#define PMAC_HD_CTL_RST 0x0100
371 +
372 +/* PCE */
373 +#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4))
374 +#define PCE_TBL_MASK 0x1120
375 +#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4))
376 +#define PCE_TBL_ADDR 0x1138
377 +#define PCE_TBL_CTRL 0x113c
378 +#define PCE_PMAP1 0x114c
379 +#define PCE_PMAP2 0x1150
380 +#define PCE_PMAP3 0x1154
381 +#define PCE_GCTRL_REG(x) (0x1158 + (x * 4))
382 +#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4))
383 +
384 +#define PCE_TBL_BUSY BIT(15)
385 +#define PCE_TBL_CFG_ADDR_MASK 0x1f
386 +#define PCE_TBL_CFG_ADWR 0x20
387 +#define PCE_TBL_CFG_ADWR_MASK 0x60
388 +#define PCE_INGRESS BIT(11)
389 +
390 +/* MAC */
391 +#define MAC_FLEN_REG (0x2314)
392 +#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4))
393 +
394 +/* buffer management */
395 +#define BM_PCFG(p) (0x200 + (p * 8))
396 +
397 +/* special tag in TX path header */
398 +#define SPID_SHIFT 24
399 +#define DPID_SHIFT 16
400 +#define DPID_ENABLE 1
401 +#define SPID_CPU_PORT 2
402 +#define PORT_MAP_SEL BIT(15)
403 +#define PORT_MAP_EN BIT(14)
404 +#define PORT_MAP_SHIFT 1
405 +#define PORT_MAP_MASK 0x3f
406 +
407 +#define SPPID_MASK 0x7
408 +#define SPPID_SHIFT 4
409 +
410 +/* MII regs not yet in linux */
411 +#define MDIO_DEVAD_NONE (-1)
412 +#define ADVERTIZE_MPD (1 << 10)
413 +
414 +struct xrx200_port {
415 + u8 num;
416 + u8 phy_addr;
417 + u16 flags;
418 + phy_interface_t phy_if;
419 +
420 + int link;
421 + int gpio;
422 + enum of_gpio_flags gpio_flags;
423 +
424 + struct phy_device *phydev;
425 + struct device_node *phy_node;
426 +};
427 +
428 +struct xrx200_chan {
429 + int idx;
430 + int refcount;
431 + int tx_free;
432 +
433 + struct net_device dummy_dev;
434 + struct net_device *devs[XRX200_MAX_DEV];
435 +
436 + struct tasklet_struct tasklet;
437 + struct napi_struct napi;
438 + struct ltq_dma_channel dma;
439 + struct sk_buff *skb[LTQ_DESC_NUM];
440 +};
441 +
442 +struct xrx200_hw {
443 + struct clk *clk;
444 + struct mii_bus *mii_bus;
445 +
446 + struct xrx200_chan chan[XRX200_MAX_DMA];
447 +
448 + struct net_device *devs[XRX200_MAX_DEV];
449 + int num_devs;
450 +
451 + int port_map[XRX200_MAX_PORT];
452 + unsigned short wan_map;
453 +
454 + spinlock_t lock;
455 +
456 + struct switch_dev swdev;
457 +};
458 +
459 +struct xrx200_priv {
460 + struct net_device_stats stats;
461 + int id;
462 +
463 + struct xrx200_port port[XRX200_MAX_PORT];
464 + int num_port;
465 + bool wan;
466 + bool sw;
467 + unsigned short port_map;
468 + unsigned char mac[6];
469 +
470 + struct xrx200_hw *hw;
471 +};
472 +
473 +static __iomem void *xrx200_switch_membase;
474 +static __iomem void *xrx200_mii_membase;
475 +static __iomem void *xrx200_mdio_membase;
476 +static __iomem void *xrx200_pmac_membase;
477 +
478 +#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x))
479 +#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y))
480 +#define ltq_switch_w32_mask(x, y, z) \
481 + ltq_w32_mask(x, y, xrx200_switch_membase + (z))
482 +
483 +#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x))
484 +#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y))
485 +#define ltq_mdio_w32_mask(x, y, z) \
486 + ltq_w32_mask(x, y, xrx200_mdio_membase + (z))
487 +
488 +#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x))
489 +#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y))
490 +#define ltq_mii_w32_mask(x, y, z) \
491 + ltq_w32_mask(x, y, xrx200_mii_membase + (z))
492 +
493 +#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x))
494 +#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y))
495 +#define ltq_pmac_w32_mask(x, y, z) \
496 + ltq_w32_mask(x, y, xrx200_pmac_membase + (z))
497 +
498 +#define XRX200_GLOBAL_REGATTR(reg) \
499 + .id = reg, \
500 + .type = SWITCH_TYPE_INT, \
501 + .set = xrx200_set_global_attr, \
502 + .get = xrx200_get_global_attr
503 +
504 +#define XRX200_PORT_REGATTR(reg) \
505 + .id = reg, \
506 + .type = SWITCH_TYPE_INT, \
507 + .set = xrx200_set_port_attr, \
508 + .get = xrx200_get_port_attr
509 +
510 +static int xrx200sw_read_x(int reg, int x)
511 +{
512 + int value, mask, addr;
513 +
514 + addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x);
515 + value = ltq_switch_r32(addr);
516 + mask = (1 << xrx200sw_reg[reg].size) - 1;
517 + value = (value >> xrx200sw_reg[reg].shift);
518 +
519 + return (value & mask);
520 +}
521 +
522 +static int xrx200sw_read(int reg)
523 +{
524 + return xrx200sw_read_x(reg, 0);
525 +}
526 +
527 +static void xrx200sw_write_x(int value, int reg, int x)
528 +{
529 + int mask, addr;
530 +
531 + addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x);
532 + mask = (1 << xrx200sw_reg[reg].size) - 1;
533 + mask = (mask << xrx200sw_reg[reg].shift);
534 + value = (value << xrx200sw_reg[reg].shift) & mask;
535 +
536 + ltq_switch_w32_mask(mask, value, addr);
537 +}
538 +
539 +static void xrx200sw_write(int value, int reg)
540 +{
541 + xrx200sw_write_x(value, reg, 0);
542 +}
543 +
544 +struct xrx200_pce_table_entry {
545 + int index; // PCE_TBL_ADDR.ADDR = pData->table_index
546 + int table; // PCE_TBL_CTRL.ADDR = pData->table
547 + unsigned short key[8];
548 + unsigned short val[5];
549 + unsigned short mask;
550 + unsigned short type;
551 + unsigned short valid;
552 + unsigned short gmap;
553 +};
554 +
555 +static int xrx200_pce_table_entry_read(struct xrx200_pce_table_entry *tbl)
556 +{
557 + // wait until hardware is ready
558 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
559 +
560 + // prepare the table access:
561 + // PCE_TBL_ADDR.ADDR = pData->table_index
562 + xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR);
563 + // PCE_TBL_CTRL.ADDR = pData->table
564 + xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR);
565 +
566 + //(address-based read)
567 + xrx200sw_write(0, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD
568 +
569 + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access
570 +
571 + // wait until hardware is ready
572 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
573 +
574 + // read the keys
575 + tbl->key[7] = xrx200sw_read(XRX200_PCE_TBL_KEY_7);
576 + tbl->key[6] = xrx200sw_read(XRX200_PCE_TBL_KEY_6);
577 + tbl->key[5] = xrx200sw_read(XRX200_PCE_TBL_KEY_5);
578 + tbl->key[4] = xrx200sw_read(XRX200_PCE_TBL_KEY_4);
579 + tbl->key[3] = xrx200sw_read(XRX200_PCE_TBL_KEY_3);
580 + tbl->key[2] = xrx200sw_read(XRX200_PCE_TBL_KEY_2);
581 + tbl->key[1] = xrx200sw_read(XRX200_PCE_TBL_KEY_1);
582 + tbl->key[0] = xrx200sw_read(XRX200_PCE_TBL_KEY_0);
583 +
584 + // read the values
585 + tbl->val[4] = xrx200sw_read(XRX200_PCE_TBL_VAL_4);
586 + tbl->val[3] = xrx200sw_read(XRX200_PCE_TBL_VAL_3);
587 + tbl->val[2] = xrx200sw_read(XRX200_PCE_TBL_VAL_2);
588 + tbl->val[1] = xrx200sw_read(XRX200_PCE_TBL_VAL_1);
589 + tbl->val[0] = xrx200sw_read(XRX200_PCE_TBL_VAL_0);
590 +
591 + // read the mask
592 + tbl->mask = xrx200sw_read(XRX200_PCE_TBL_MASK_0);
593 + // read the type
594 + tbl->type = xrx200sw_read(XRX200_PCE_TBL_CTRL_TYPE);
595 + // read the valid flag
596 + tbl->valid = xrx200sw_read(XRX200_PCE_TBL_CTRL_VLD);
597 + // read the group map
598 + tbl->gmap = xrx200sw_read(XRX200_PCE_TBL_CTRL_GMAP);
599 +
600 + return 0;
601 +}
602 +
603 +static int xrx200_pce_table_entry_write(struct xrx200_pce_table_entry *tbl)
604 +{
605 + // wait until hardware is ready
606 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
607 +
608 + // prepare the table access:
609 + // PCE_TBL_ADDR.ADDR = pData->table_index
610 + xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR);
611 + // PCE_TBL_CTRL.ADDR = pData->table
612 + xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR);
613 +
614 + //(address-based write)
615 + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD
616 +
617 + // read the keys
618 + xrx200sw_write(tbl->key[7], XRX200_PCE_TBL_KEY_7);
619 + xrx200sw_write(tbl->key[6], XRX200_PCE_TBL_KEY_6);
620 + xrx200sw_write(tbl->key[5], XRX200_PCE_TBL_KEY_5);
621 + xrx200sw_write(tbl->key[4], XRX200_PCE_TBL_KEY_4);
622 + xrx200sw_write(tbl->key[3], XRX200_PCE_TBL_KEY_3);
623 + xrx200sw_write(tbl->key[2], XRX200_PCE_TBL_KEY_2);
624 + xrx200sw_write(tbl->key[1], XRX200_PCE_TBL_KEY_1);
625 + xrx200sw_write(tbl->key[0], XRX200_PCE_TBL_KEY_0);
626 +
627 + // read the values
628 + xrx200sw_write(tbl->val[4], XRX200_PCE_TBL_VAL_4);
629 + xrx200sw_write(tbl->val[3], XRX200_PCE_TBL_VAL_3);
630 + xrx200sw_write(tbl->val[2], XRX200_PCE_TBL_VAL_2);
631 + xrx200sw_write(tbl->val[1], XRX200_PCE_TBL_VAL_1);
632 + xrx200sw_write(tbl->val[0], XRX200_PCE_TBL_VAL_0);
633 +
634 + // read the mask
635 + xrx200sw_write(tbl->mask, XRX200_PCE_TBL_MASK_0);
636 + // read the type
637 + xrx200sw_write(tbl->type, XRX200_PCE_TBL_CTRL_TYPE);
638 + // read the valid flag
639 + xrx200sw_write(tbl->valid, XRX200_PCE_TBL_CTRL_VLD);
640 + // read the group map
641 + xrx200sw_write(tbl->gmap, XRX200_PCE_TBL_CTRL_GMAP);
642 +
643 + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access
644 +
645 + // wait until hardware is ready
646 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
647 +
648 + return 0;
649 +}
650 +
651 +static void xrx200sw_fixup_pvids(void)
652 +{
653 + int index, p, portmap, untagged;
654 + struct xrx200_pce_table_entry tem;
655 + struct xrx200_pce_table_entry tev;
656 +
657 + portmap = 0;
658 + for (p = 0; p < XRX200_MAX_PORT; p++)
659 + portmap |= BIT(p);
660 +
661 + tem.table = XRX200_PCE_VLANMAP_IDX;
662 + tev.table = XRX200_PCE_ACTVLAN_IDX;
663 +
664 + for (index = XRX200_MAX_VLAN; index-- > 0;)
665 + {
666 + tev.index = index;
667 + xrx200_pce_table_entry_read(&tev);
668 +
669 + if (tev.valid == 0)
670 + continue;
671 +
672 + tem.index = index;
673 + xrx200_pce_table_entry_read(&tem);
674 +
675 + if (tem.val[0] == 0)
676 + continue;
677 +
678 + untagged = portmap & (tem.val[1] ^ tem.val[2]);
679 +
680 + for (p = 0; p < XRX200_MAX_PORT; p++)
681 + if (untagged & BIT(p))
682 + {
683 + portmap &= ~BIT(p);
684 + xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p);
685 + }
686 +
687 + for (p = 0; p < XRX200_MAX_PORT; p++)
688 + if (portmap & BIT(p))
689 + xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p);
690 + }
691 +}
692 +
693 +// swconfig interface
694 +static void xrx200_hw_init(struct xrx200_hw *hw);
695 +
696 +// global
697 +static int xrx200sw_reset_switch(struct switch_dev *dev)
698 +{
699 + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
700 +
701 + xrx200_hw_init(hw);
702 +
703 + return 0;
704 +}
705 +
706 +static int xrx200_set_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
707 +{
708 + int p;
709 +
710 + if ((attr->max > 0) && (val->value.i > attr->max))
711 + return -EINVAL;
712 +
713 + for (p = 0; p < XRX200_MAX_PORT; p++) {
714 + xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VEMR, p);
715 + xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VIMR, p);
716 + }
717 +
718 + xrx200sw_write(val->value.i, XRX200_PCE_GCTRL_0_VLAN);
719 + return 0;
720 +}
721 +
722 +static int xrx200_get_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
723 +{
724 + val->value.i = xrx200sw_read(attr->id);
725 + return 0;
726 +}
727 +
728 +static int xrx200_set_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
729 +{
730 + if ((attr->max > 0) && (val->value.i > attr->max))
731 + return -EINVAL;
732 +
733 + xrx200sw_write(val->value.i, attr->id);
734 + return 0;
735 +}
736 +
737 +static int xrx200_get_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
738 +{
739 + val->value.i = xrx200sw_read(attr->id);
740 + return 0;
741 +}
742 +
743 +// vlan
744 +static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr,
745 + struct switch_val *val)
746 +{
747 + int i;
748 + struct xrx200_pce_table_entry tev;
749 + struct xrx200_pce_table_entry tem;
750 +
751 + tev.table = XRX200_PCE_ACTVLAN_IDX;
752 +
753 + for (i = 0; i < XRX200_MAX_VLAN; i++)
754 + {
755 + tev.index = i;
756 + xrx200_pce_table_entry_read(&tev);
757 + if (tev.key[0] == val->value.i && i != val->port_vlan)
758 + return -EINVAL;
759 + }
760 +
761 + tev.index = val->port_vlan;
762 + xrx200_pce_table_entry_read(&tev);
763 + tev.key[0] = val->value.i;
764 + tev.valid = val->value.i > 0;
765 + xrx200_pce_table_entry_write(&tev);
766 +
767 + tem.table = XRX200_PCE_VLANMAP_IDX;
768 + tem.index = val->port_vlan;
769 + xrx200_pce_table_entry_read(&tem);
770 + tem.val[0] = val->value.i;
771 + xrx200_pce_table_entry_write(&tem);
772 +
773 + xrx200sw_fixup_pvids();
774 + return 0;
775 +}
776 +
777 +static int xrx200sw_get_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr,
778 + struct switch_val *val)
779 +{
780 + struct xrx200_pce_table_entry te;
781 +
782 + te.table = XRX200_PCE_ACTVLAN_IDX;
783 + te.index = val->port_vlan;
784 + xrx200_pce_table_entry_read(&te);
785 + val->value.i = te.key[0];
786 +
787 + return 0;
788 +}
789 +
790 +static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
791 +{
792 + int i, portmap, tagmap, untagged;
793 + struct xrx200_pce_table_entry tem;
794 +
795 + portmap = 0;
796 + tagmap = 0;
797 + for (i = 0; i < val->len; i++)
798 + {
799 + struct switch_port *p = &val->value.ports[i];
800 +
801 + portmap |= (1 << p->id);
802 + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
803 + tagmap |= (1 << p->id);
804 + }
805 +
806 + tem.table = XRX200_PCE_VLANMAP_IDX;
807 +
808 + untagged = portmap ^ tagmap;
809 + for (i = 0; i < XRX200_MAX_VLAN; i++)
810 + {
811 + tem.index = i;
812 + xrx200_pce_table_entry_read(&tem);
813 +
814 + if (tem.val[0] == 0)
815 + continue;
816 +
817 + if ((untagged & (tem.val[1] ^ tem.val[2])) && (val->port_vlan != i))
818 + return -EINVAL;
819 + }
820 +
821 + tem.index = val->port_vlan;
822 + xrx200_pce_table_entry_read(&tem);
823 +
824 + // auto-enable this vlan if not enabled already
825 + if (tem.val[0] == 0)
826 + {
827 + struct switch_val v;
828 + v.port_vlan = val->port_vlan;
829 + v.value.i = val->port_vlan;
830 + if(xrx200sw_set_vlan_vid(dev, NULL, &v))
831 + return -EINVAL;
832 +
833 + //read updated tem
834 + tem.index = val->port_vlan;
835 + xrx200_pce_table_entry_read(&tem);
836 + }
837 +
838 + tem.val[1] = portmap;
839 + tem.val[2] = tagmap;
840 + xrx200_pce_table_entry_write(&tem);
841 +
842 + xrx200sw_fixup_pvids();
843 +
844 + return 0;
845 +}
846 +
847 +static int xrx200sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
848 +{
849 + int i;
850 + unsigned short ports, tags;
851 + struct xrx200_pce_table_entry tem;
852 +
853 + tem.table = XRX200_PCE_VLANMAP_IDX;
854 + tem.index = val->port_vlan;
855 + xrx200_pce_table_entry_read(&tem);
856 +
857 + ports = tem.val[1];
858 + tags = tem.val[2];
859 +
860 + for (i = 0; i < XRX200_MAX_PORT; i++) {
861 + struct switch_port *p;
862 +
863 + if (!(ports & (1 << i)))
864 + continue;
865 +
866 + p = &val->value.ports[val->len++];
867 + p->id = i;
868 + if (tags & (1 << i))
869 + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
870 + else
871 + p->flags = 0;
872 + }
873 +
874 + return 0;
875 +}
876 +
877 +static int xrx200sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr,
878 + struct switch_val *val)
879 +{
880 + struct xrx200_pce_table_entry tev;
881 +
882 + tev.table = XRX200_PCE_ACTVLAN_IDX;
883 + tev.index = val->port_vlan;
884 + xrx200_pce_table_entry_read(&tev);
885 +
886 + if (tev.key[0] == 0)
887 + return -EINVAL;
888 +
889 + tev.valid = val->value.i;
890 + xrx200_pce_table_entry_write(&tev);
891 +
892 + xrx200sw_fixup_pvids();
893 + return 0;
894 +}
895 +
896 +static int xrx200sw_get_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr,
897 + struct switch_val *val)
898 +{
899 + struct xrx200_pce_table_entry tev;
900 +
901 + tev.table = XRX200_PCE_ACTVLAN_IDX;
902 + tev.index = val->port_vlan;
903 + xrx200_pce_table_entry_read(&tev);
904 + val->value.i = tev.valid;
905 +
906 + return 0;
907 +}
908 +
909 +// port
910 +static int xrx200sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
911 +{
912 + struct xrx200_pce_table_entry tev;
913 +
914 + if (port >= XRX200_MAX_PORT)
915 + return -EINVAL;
916 +
917 + tev.table = XRX200_PCE_ACTVLAN_IDX;
918 + tev.index = xrx200sw_read_x(XRX200_PCE_DEFPVID_PVID, port);
919 + xrx200_pce_table_entry_read(&tev);
920 +
921 + *val = tev.key[0];
922 + return 0;
923 +}
924 +
925 +static int xrx200sw_get_port_link(struct switch_dev *dev,
926 + int port,
927 + struct switch_port_link *link)
928 +{
929 + if (port >= XRX200_MAX_PORT)
930 + return -EINVAL;
931 +
932 + link->link = xrx200sw_read_x(XRX200_MAC_PSTAT_LSTAT, port);
933 + if (!link->link)
934 + return 0;
935 +
936 + link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port);
937 +
938 + link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010);
939 + link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020);
940 + link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port));
941 +
942 + link->speed = SWITCH_PORT_SPEED_10;
943 + if (xrx200sw_read_x(XRX200_MAC_PSTAT_MBIT, port))
944 + link->speed = SWITCH_PORT_SPEED_100;
945 + if (xrx200sw_read_x(XRX200_MAC_PSTAT_GBIT, port))
946 + link->speed = SWITCH_PORT_SPEED_1000;
947 +
948 + return 0;
949 +}
950 +
951 +static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
952 +{
953 + printk("%s %s(%d)\n", __FILE__, __func__, __LINE__);
954 + if (val->port_vlan >= XRX200_MAX_PORT)
955 + return -EINVAL;
956 +
957 + if ((attr->max > 0) && (val->value.i > attr->max))
958 + return -EINVAL;
959 +
960 + xrx200sw_write_x(val->value.i, attr->id, val->port_vlan);
961 + return 0;
962 +}
963 +
964 +static int xrx200_get_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
965 +{
966 + if (val->port_vlan >= XRX200_MAX_PORT)
967 + return -EINVAL;
968 +
969 + val->value.i = xrx200sw_read_x(attr->id, val->port_vlan);
970 + return 0;
971 +}
972 +
973 +// attributes
974 +static struct switch_attr xrx200sw_globals[] = {
975 + {
976 + .type = SWITCH_TYPE_INT,
977 + .set = xrx200_set_vlan_mode_enable,
978 + .get = xrx200_get_vlan_mode_enable,
979 + .name = "enable_vlan",
980 + .description = "Enable VLAN mode",
981 + .max = 1},
982 +};
983 +
984 +static struct switch_attr xrx200sw_port[] = {
985 + {
986 + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_UVR),
987 + .name = "uvr",
988 + .description = "Unknown VLAN Rule",
989 + .max = 1,
990 + },
991 + {
992 + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VSR),
993 + .name = "vsr",
994 + .description = "VLAN Security Rule",
995 + .max = 1,
996 + },
997 + {
998 + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VINR),
999 + .name = "vinr",
1000 + .description = "VLAN Ingress Tag Rule",
1001 + .max = 2,
1002 + },
1003 + {
1004 + XRX200_PORT_REGATTR(XRX200_PCE_PCTRL_0_TVM),
1005 + .name = "tvm",
1006 + .description = "Transparent VLAN Mode",
1007 + .max = 1,
1008 + },
1009 +};
1010 +
1011 +static struct switch_attr xrx200sw_vlan[] = {
1012 + {
1013 + .type = SWITCH_TYPE_INT,
1014 + .name = "vid",
1015 + .description = "VLAN ID (0-4094)",
1016 + .set = xrx200sw_set_vlan_vid,
1017 + .get = xrx200sw_get_vlan_vid,
1018 + .max = 4094,
1019 + },
1020 + {
1021 + .type = SWITCH_TYPE_INT,
1022 + .name = "enable",
1023 + .description = "Enable VLAN",
1024 + .set = xrx200sw_set_vlan_enable,
1025 + .get = xrx200sw_get_vlan_enable,
1026 + .max = 1,
1027 + },
1028 +};
1029 +
1030 +static const struct switch_dev_ops xrx200sw_ops = {
1031 + .attr_global = {
1032 + .attr = xrx200sw_globals,
1033 + .n_attr = ARRAY_SIZE(xrx200sw_globals),
1034 + },
1035 + .attr_port = {
1036 + .attr = xrx200sw_port,
1037 + .n_attr = ARRAY_SIZE(xrx200sw_port),
1038 + },
1039 + .attr_vlan = {
1040 + .attr = xrx200sw_vlan,
1041 + .n_attr = ARRAY_SIZE(xrx200sw_vlan),
1042 + },
1043 + .get_vlan_ports = xrx200sw_get_vlan_ports,
1044 + .set_vlan_ports = xrx200sw_set_vlan_ports,
1045 + .get_port_pvid = xrx200sw_get_port_pvid,
1046 + .reset_switch = xrx200sw_reset_switch,
1047 + .get_port_link = xrx200sw_get_port_link,
1048 +// .get_port_stats = xrx200sw_get_port_stats, //TODO
1049 +};
1050 +
1051 +static int xrx200sw_init(struct xrx200_hw *hw)
1052 +{
1053 + int netdev_num;
1054 +
1055 + for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++)
1056 + {
1057 + struct switch_dev *swdev;
1058 + struct net_device *dev = hw->devs[netdev_num];
1059 + struct xrx200_priv *priv = netdev_priv(dev);
1060 + if (!priv->sw)
1061 + continue;
1062 +
1063 + swdev = &hw->swdev;
1064 +
1065 + swdev->name = "Lantiq XRX200 Switch";
1066 + swdev->vlans = XRX200_MAX_VLAN;
1067 + swdev->ports = XRX200_MAX_PORT;
1068 + swdev->cpu_port = 6;
1069 + swdev->ops = &xrx200sw_ops;
1070 +
1071 + register_switch(swdev, dev);
1072 + return 0; // enough switches
1073 + }
1074 + return 0;
1075 +}
1076 +
1077 +static int xrx200_open(struct net_device *dev)
1078 +{
1079 + struct xrx200_priv *priv = netdev_priv(dev);
1080 + unsigned long flags;
1081 + int i;
1082 +
1083 + for (i = 0; i < XRX200_MAX_DMA; i++) {
1084 + if (!priv->hw->chan[i].dma.irq)
1085 + continue;
1086 + spin_lock_irqsave(&priv->hw->lock, flags);
1087 + if (!priv->hw->chan[i].refcount) {
1088 + if (XRX200_DMA_IS_RX(i))
1089 + napi_enable(&priv->hw->chan[i].napi);
1090 + ltq_dma_open(&priv->hw->chan[i].dma);
1091 + }
1092 + priv->hw->chan[i].refcount++;
1093 + spin_unlock_irqrestore(&priv->hw->lock, flags);
1094 + }
1095 + for (i = 0; i < priv->num_port; i++)
1096 + if (priv->port[i].phydev)
1097 + phy_start(priv->port[i].phydev);
1098 + netif_start_queue(dev);
1099 +
1100 + return 0;
1101 +}
1102 +
1103 +static int xrx200_close(struct net_device *dev)
1104 +{
1105 + struct xrx200_priv *priv = netdev_priv(dev);
1106 + unsigned long flags;
1107 + int i;
1108 +
1109 + netif_stop_queue(dev);
1110 +
1111 + for (i = 0; i < priv->num_port; i++)
1112 + if (priv->port[i].phydev)
1113 + phy_stop(priv->port[i].phydev);
1114 +
1115 + for (i = 0; i < XRX200_MAX_DMA; i++) {
1116 + if (!priv->hw->chan[i].dma.irq)
1117 + continue;
1118 + spin_lock_irqsave(&priv->hw->lock, flags);
1119 + priv->hw->chan[i].refcount--;
1120 + if (!priv->hw->chan[i].refcount) {
1121 + if (XRX200_DMA_IS_RX(i))
1122 + napi_disable(&priv->hw->chan[i].napi);
1123 + ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma);
1124 + }
1125 + spin_unlock_irqrestore(&priv->hw->lock, flags);
1126 + }
1127 +
1128 + return 0;
1129 +}
1130 +
1131 +static int xrx200_alloc_skb(struct xrx200_chan *ch)
1132 +{
1133 +#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD)
1134 + ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD);
1135 + if (!ch->skb[ch->dma.desc])
1136 + return -ENOMEM;
1137 +
1138 + skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD);
1139 + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
1140 + ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
1141 + DMA_FROM_DEVICE);
1142 + ch->dma.desc_base[ch->dma.desc].addr =
1143 + CPHYSADDR(ch->skb[ch->dma.desc]->data);
1144 + ch->dma.desc_base[ch->dma.desc].ctl =
1145 + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
1146 + XRX200_DMA_DATA_LEN;
1147 + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
1148 +
1149 + return 0;
1150 +}
1151 +
1152 +static void xrx200_hw_receive(struct xrx200_chan *ch, int id)
1153 +{
1154 + struct net_device *dev = ch->devs[id];
1155 + struct xrx200_priv *priv = netdev_priv(dev);
1156 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
1157 + struct sk_buff *skb = ch->skb[ch->dma.desc];
1158 + int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - ETH_FCS_LEN;
1159 + unsigned long flags;
1160 +
1161 + spin_lock_irqsave(&priv->hw->lock, flags);
1162 + if (xrx200_alloc_skb(ch)) {
1163 + netdev_err(dev,
1164 + "failed to allocate new rx buffer, stopping DMA\n");
1165 + ltq_dma_close(&ch->dma);
1166 + }
1167 +
1168 + ch->dma.desc++;
1169 + ch->dma.desc %= LTQ_DESC_NUM;
1170 + spin_unlock_irqrestore(&priv->hw->lock, flags);
1171 +
1172 + skb_put(skb, len);
1173 +#ifdef SW_ROUTING
1174 + skb_pull(skb, 8);
1175 +#endif
1176 + skb->dev = dev;
1177 + skb->protocol = eth_type_trans(skb, dev);
1178 + netif_receive_skb(skb);
1179 + priv->stats.rx_packets++;
1180 + priv->stats.rx_bytes+=len;
1181 +}
1182 +
1183 +static int xrx200_poll_rx(struct napi_struct *napi, int budget)
1184 +{
1185 + struct xrx200_chan *ch = container_of(napi,
1186 + struct xrx200_chan, napi);
1187 + struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
1188 + int rx = 0;
1189 + int complete = 0;
1190 + unsigned long flags;
1191 +
1192 + while ((rx < budget) && !complete) {
1193 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
1194 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
1195 +#ifdef SW_ROUTING
1196 + struct sk_buff *skb = ch->skb[ch->dma.desc];
1197 + u32 *special_tag = (u32*)skb->data;
1198 + int port = (special_tag[1] >> SPPID_SHIFT) & SPPID_MASK;
1199 + xrx200_hw_receive(ch, priv->hw->port_map[port]);
1200 +#else
1201 + xrx200_hw_receive(ch, 0);
1202 +#endif
1203 + rx++;
1204 + } else {
1205 + complete = 1;
1206 + }
1207 + }
1208 + if (complete || !rx) {
1209 + napi_complete(&ch->napi);
1210 + spin_lock_irqsave(&priv->hw->lock, flags);
1211 + ltq_dma_ack_irq(&ch->dma);
1212 + spin_unlock_irqrestore(&priv->hw->lock, flags);
1213 + }
1214 + return rx;
1215 +}
1216 +
1217 +static void xrx200_tx_housekeeping(unsigned long ptr)
1218 +{
1219 + struct xrx200_hw *hw = (struct xrx200_hw *) ptr;
1220 + struct xrx200_chan *ch = &hw->chan[XRX200_DMA_TX];
1221 + unsigned long flags;
1222 + int i;
1223 +
1224 + spin_lock_irqsave(&hw->lock, flags);
1225 + while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
1226 + dev_kfree_skb_any(ch->skb[ch->tx_free]);
1227 + ch->skb[ch->tx_free] = NULL;
1228 + memset(&ch->dma.desc_base[ch->tx_free], 0,
1229 + sizeof(struct ltq_dma_desc));
1230 + ch->tx_free++;
1231 + ch->tx_free %= LTQ_DESC_NUM;
1232 + }
1233 + spin_unlock_irqrestore(&hw->lock, flags);
1234 +
1235 + for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) {
1236 + struct netdev_queue *txq =
1237 + netdev_get_tx_queue(ch->devs[i], 0);
1238 + if (netif_tx_queue_stopped(txq))
1239 + netif_tx_start_queue(txq);
1240 + }
1241 +
1242 + spin_lock_irqsave(&hw->lock, flags);
1243 + ltq_dma_ack_irq(&ch->dma);
1244 + spin_unlock_irqrestore(&hw->lock, flags);
1245 +}
1246 +
1247 +static struct net_device_stats *xrx200_get_stats (struct net_device *dev)
1248 +{
1249 + struct xrx200_priv *priv = netdev_priv(dev);
1250 +
1251 + return &priv->stats;
1252 +}
1253 +
1254 +static void xrx200_tx_timeout(struct net_device *dev)
1255 +{
1256 + struct xrx200_priv *priv = netdev_priv(dev);
1257 +
1258 + printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name);
1259 +
1260 + priv->stats.tx_errors++;
1261 + netif_wake_queue(dev);
1262 +}
1263 +
1264 +static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev)
1265 +{
1266 + int queue = skb_get_queue_mapping(skb);
1267 + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
1268 + struct xrx200_priv *priv = netdev_priv(dev);
1269 + struct xrx200_chan *ch = &priv->hw->chan[XRX200_DMA_TX];
1270 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
1271 + unsigned long flags;
1272 + u32 byte_offset;
1273 + int len;
1274 +#ifdef SW_ROUTING
1275 + #ifdef SW_PORTMAP
1276 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | PORT_MAP_SEL | PORT_MAP_EN | DPID_ENABLE;
1277 + #else
1278 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE;
1279 + #endif
1280 +#endif
1281 +
1282 + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
1283 +
1284 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
1285 + netdev_err(dev, "tx ring full\n");
1286 + netif_tx_stop_queue(txq);
1287 + return NETDEV_TX_BUSY;
1288 + }
1289 +#ifdef SW_ROUTING
1290 + #ifdef SW_PORTMAP
1291 + special_tag |= priv->port_map << PORT_MAP_SHIFT;
1292 + #else
1293 + if(priv->id)
1294 + special_tag |= (1 << DPID_SHIFT);
1295 + #endif
1296 + if(skb_headroom(skb) < 4) {
1297 + struct sk_buff *tmp = skb_realloc_headroom(skb, 4);
1298 + dev_kfree_skb_any(skb);
1299 + skb = tmp;
1300 + }
1301 + skb_push(skb, 4);
1302 + memcpy(skb->data, &special_tag, sizeof(u32));
1303 + len += 4;
1304 +#endif
1305 +
1306 + /* dma needs to start on a 16 byte aligned address */
1307 + byte_offset = CPHYSADDR(skb->data) % 16;
1308 + ch->skb[ch->dma.desc] = skb;
1309 +
1310 + dev->trans_start = jiffies;
1311 +
1312 + spin_lock_irqsave(&priv->hw->lock, flags);
1313 + desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
1314 + DMA_TO_DEVICE)) - byte_offset;
1315 + wmb();
1316 + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
1317 + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
1318 + ch->dma.desc++;
1319 + ch->dma.desc %= LTQ_DESC_NUM;
1320 + spin_unlock_irqrestore(&priv->hw->lock, flags);
1321 +
1322 + if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
1323 + netif_tx_stop_queue(txq);
1324 +
1325 + priv->stats.tx_packets++;
1326 + priv->stats.tx_bytes+=len;
1327 +
1328 + return NETDEV_TX_OK;
1329 +}
1330 +
1331 +static irqreturn_t xrx200_dma_irq(int irq, void *priv)
1332 +{
1333 + struct xrx200_hw *hw = priv;
1334 + int ch = irq - XRX200_DMA_IRQ;
1335 +
1336 + if (ch % 2)
1337 + tasklet_schedule(&hw->chan[ch].tasklet);
1338 + else
1339 + napi_schedule(&hw->chan[ch].napi);
1340 +
1341 + return IRQ_HANDLED;
1342 +}
1343 +
1344 +static int xrx200_dma_init(struct xrx200_hw *hw)
1345 +{
1346 + int i, err = 0;
1347 +
1348 + ltq_dma_init_port(DMA_PORT_ETOP);
1349 +
1350 + for (i = 0; i < 8 && !err; i++) {
1351 + int irq = XRX200_DMA_IRQ + i;
1352 + struct xrx200_chan *ch = &hw->chan[i];
1353 +
1354 + ch->idx = ch->dma.nr = i;
1355 +
1356 + if (i == XRX200_DMA_TX) {
1357 + ltq_dma_alloc_tx(&ch->dma);
1358 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw);
1359 + } else if (i == XRX200_DMA_RX) {
1360 + ltq_dma_alloc_rx(&ch->dma);
1361 + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
1362 + ch->dma.desc++)
1363 + if (xrx200_alloc_skb(ch))
1364 + err = -ENOMEM;
1365 + ch->dma.desc = 0;
1366 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw);
1367 + } else
1368 + continue;
1369 +
1370 + if (!err)
1371 + ch->dma.irq = irq;
1372 + }
1373 +
1374 + return err;
1375 +}
1376 +
1377 +#ifdef SW_POLLING
1378 +static void xrx200_gmac_update(struct xrx200_port *port)
1379 +{
1380 + u16 phyaddr = port->phydev->addr & MDIO_PHY_ADDR_MASK;
1381 + u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK;
1382 + u16 miirate = 0;
1383 +
1384 + switch (port->phydev->speed) {
1385 + case SPEED_1000:
1386 + phyaddr |= MDIO_PHY_SPEED_G1;
1387 + miirate = MII_CFG_RATE_M125;
1388 + break;
1389 +
1390 + case SPEED_100:
1391 + phyaddr |= MDIO_PHY_SPEED_M100;
1392 + switch (miimode) {
1393 + case MII_CFG_MODE_RMIIM:
1394 + case MII_CFG_MODE_RMIIP:
1395 + miirate = MII_CFG_RATE_M50;
1396 + break;
1397 + default:
1398 + miirate = MII_CFG_RATE_M25;
1399 + break;
1400 + }
1401 + break;
1402 +
1403 + default:
1404 + phyaddr |= MDIO_PHY_SPEED_M10;
1405 + miirate = MII_CFG_RATE_M2P5;
1406 + break;
1407 + }
1408 +
1409 + if (port->phydev->link)
1410 + phyaddr |= MDIO_PHY_LINK_UP;
1411 + else
1412 + phyaddr |= MDIO_PHY_LINK_DOWN;
1413 +
1414 + if (port->phydev->duplex == DUPLEX_FULL)
1415 + phyaddr |= MDIO_PHY_FDUP_EN;
1416 + else
1417 + phyaddr |= MDIO_PHY_FDUP_DIS;
1418 +
1419 + ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num));
1420 + ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num));
1421 + udelay(1);
1422 +}
1423 +#else
1424 +static void xrx200_gmac_update(struct xrx200_port *port)
1425 +{
1426 +
1427 +}
1428 +#endif
1429 +
1430 +static void xrx200_mdio_link(struct net_device *dev)
1431 +{
1432 + struct xrx200_priv *priv = netdev_priv(dev);
1433 + int i;
1434 +
1435 + for (i = 0; i < priv->num_port; i++) {
1436 + if (!priv->port[i].phydev)
1437 + continue;
1438 +
1439 + if (priv->port[i].link != priv->port[i].phydev->link) {
1440 + xrx200_gmac_update(&priv->port[i]);
1441 + priv->port[i].link = priv->port[i].phydev->link;
1442 + netdev_info(dev, "port %d %s link\n",
1443 + priv->port[i].num,
1444 + (priv->port[i].link)?("got"):("lost"));
1445 + }
1446 + }
1447 +}
1448 +
1449 +static inline int xrx200_mdio_poll(struct mii_bus *bus)
1450 +{
1451 + unsigned cnt = 10000;
1452 +
1453 + while (likely(cnt--)) {
1454 + unsigned ctrl = ltq_mdio_r32(MDIO_CTRL);
1455 + if ((ctrl & MDIO_BUSY) == 0)
1456 + return 0;
1457 + }
1458 +
1459 + return 1;
1460 +}
1461 +
1462 +static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
1463 +{
1464 + if (xrx200_mdio_poll(bus))
1465 + return 1;
1466 +
1467 + ltq_mdio_w32(val, MDIO_WRITE);
1468 + ltq_mdio_w32(MDIO_BUSY | MDIO_WR |
1469 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
1470 + (reg & MDIO_MASK),
1471 + MDIO_CTRL);
1472 +
1473 + return 0;
1474 +}
1475 +
1476 +static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg)
1477 +{
1478 + if (xrx200_mdio_poll(bus))
1479 + return -1;
1480 +
1481 + ltq_mdio_w32(MDIO_BUSY | MDIO_RD |
1482 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
1483 + (reg & MDIO_MASK),
1484 + MDIO_CTRL);
1485 +
1486 + if (xrx200_mdio_poll(bus))
1487 + return -1;
1488 +
1489 + return ltq_mdio_r32(MDIO_READ);
1490 +}
1491 +
1492 +static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port)
1493 +{
1494 + struct xrx200_priv *priv = netdev_priv(dev);
1495 + struct phy_device *phydev = NULL;
1496 + unsigned val;
1497 +
1498 + phydev = priv->hw->mii_bus->phy_map[port->phy_addr];
1499 +
1500 + if (!phydev) {
1501 + netdev_err(dev, "no PHY found\n");
1502 + return -ENODEV;
1503 + }
1504 +
1505 + phydev = phy_connect(dev, dev_name(&phydev->dev), &xrx200_mdio_link,
1506 + port->phy_if);
1507 +
1508 + if (IS_ERR(phydev)) {
1509 + netdev_err(dev, "Could not attach to PHY\n");
1510 + return PTR_ERR(phydev);
1511 + }
1512 +
1513 + phydev->supported &= (SUPPORTED_10baseT_Half
1514 + | SUPPORTED_10baseT_Full
1515 + | SUPPORTED_100baseT_Half
1516 + | SUPPORTED_100baseT_Full
1517 + | SUPPORTED_1000baseT_Half
1518 + | SUPPORTED_1000baseT_Full
1519 + | SUPPORTED_Autoneg
1520 + | SUPPORTED_MII
1521 + | SUPPORTED_TP);
1522 + phydev->advertising = phydev->supported;
1523 + port->phydev = phydev;
1524 +
1525 + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
1526 + dev->name, phydev->drv->name,
1527 + dev_name(&phydev->dev), phydev->irq);
1528 +
1529 +#ifdef SW_POLLING
1530 + phy_read_status(phydev);
1531 +
1532 + val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
1533 + val |= ADVERTIZE_MPD;
1534 + xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
1535 + xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040);
1536 +
1537 + phy_start_aneg(phydev);
1538 +#endif
1539 + return 0;
1540 +}
1541 +
1542 +static void xrx200_port_config(struct xrx200_priv *priv,
1543 + const struct xrx200_port *port)
1544 +{
1545 + u16 miimode = 0;
1546 +
1547 + switch (port->num) {
1548 + case 0: /* xMII0 */
1549 + case 1: /* xMII1 */
1550 + switch (port->phy_if) {
1551 + case PHY_INTERFACE_MODE_MII:
1552 + if (port->flags & XRX200_PORT_TYPE_PHY)
1553 + /* MII MAC mode, connected to external PHY */
1554 + miimode = MII_CFG_MODE_MIIM;
1555 + else
1556 + /* MII PHY mode, connected to external MAC */
1557 + miimode = MII_CFG_MODE_MIIP;
1558 + break;
1559 + case PHY_INTERFACE_MODE_RMII:
1560 + if (port->flags & XRX200_PORT_TYPE_PHY)
1561 + /* RMII MAC mode, connected to external PHY */
1562 + miimode = MII_CFG_MODE_RMIIM;
1563 + else
1564 + /* RMII PHY mode, connected to external MAC */
1565 + miimode = MII_CFG_MODE_RMIIP;
1566 + break;
1567 + case PHY_INTERFACE_MODE_RGMII:
1568 + /* RGMII MAC mode, connected to external PHY */
1569 + miimode = MII_CFG_MODE_RGMII;
1570 + break;
1571 + default:
1572 + break;
1573 + }
1574 + break;
1575 + case 2: /* internal GPHY0 */
1576 + case 3: /* internal GPHY0 */
1577 + case 4: /* internal GPHY1 */
1578 + switch (port->phy_if) {
1579 + case PHY_INTERFACE_MODE_MII:
1580 + case PHY_INTERFACE_MODE_GMII:
1581 + /* MII MAC mode, connected to internal GPHY */
1582 + miimode = MII_CFG_MODE_MIIM;
1583 + break;
1584 + default:
1585 + break;
1586 + }
1587 + break;
1588 + case 5: /* internal GPHY1 or xMII2 */
1589 + switch (port->phy_if) {
1590 + case PHY_INTERFACE_MODE_MII:
1591 + /* MII MAC mode, connected to internal GPHY */
1592 + miimode = MII_CFG_MODE_MIIM;
1593 + break;
1594 + case PHY_INTERFACE_MODE_RGMII:
1595 + /* RGMII MAC mode, connected to external PHY */
1596 + miimode = MII_CFG_MODE_RGMII;
1597 + break;
1598 + default:
1599 + break;
1600 + }
1601 + break;
1602 + default:
1603 + break;
1604 + }
1605 +
1606 + ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN,
1607 + MII_CFG(port->num));
1608 +}
1609 +
1610 +static int xrx200_init(struct net_device *dev)
1611 +{
1612 + struct xrx200_priv *priv = netdev_priv(dev);
1613 + struct sockaddr mac;
1614 + int err, i;
1615 +
1616 +#ifndef SW_POLLING
1617 + unsigned int reg = 0;
1618 +
1619 + /* enable auto polling */
1620 + for (i = 0; i < priv->num_port; i++)
1621 + reg |= BIT(priv->port[i].num);
1622 + ltq_mdio_w32(reg, MDIO_CLK_CFG0);
1623 + ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1);
1624 +#endif
1625 +
1626 + /* setup each port */
1627 + for (i = 0; i < priv->num_port; i++)
1628 + xrx200_port_config(priv, &priv->port[i]);
1629 +
1630 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
1631 + if (!is_valid_ether_addr(mac.sa_data)) {
1632 + pr_warn("net-xrx200: invalid MAC, using random\n");
1633 + eth_random_addr(mac.sa_data);
1634 + dev->addr_assign_type |= NET_ADDR_RANDOM;
1635 + }
1636 +
1637 + err = eth_mac_addr(dev, &mac);
1638 + if (err)
1639 + goto err_netdev;
1640 +
1641 + for (i = 0; i < priv->num_port; i++)
1642 + if (xrx200_mdio_probe(dev, &priv->port[i]))
1643 + pr_warn("xrx200-mdio: probing phy of port %d failed\n",
1644 + priv->port[i].num);
1645 +
1646 + return 0;
1647 +
1648 +err_netdev:
1649 + unregister_netdev(dev);
1650 + free_netdev(dev);
1651 + return err;
1652 +}
1653 +
1654 +static void xrx200_pci_microcode(void)
1655 +{
1656 + int i;
1657 +
1658 + ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK,
1659 + PCE_TBL_CFG_ADWR, PCE_TBL_CTRL);
1660 + ltq_switch_w32(0, PCE_TBL_MASK);
1661 +
1662 + for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) {
1663 + ltq_switch_w32(i, PCE_TBL_ADDR);
1664 + ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0));
1665 + ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1));
1666 + ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2));
1667 + ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3));
1668 +
1669 + // start the table access:
1670 + ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL);
1671 + while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY);
1672 + }
1673 +
1674 + /* tell the switch that the microcode is loaded */
1675 + ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0));
1676 +}
1677 +
1678 +static void xrx200_hw_init(struct xrx200_hw *hw)
1679 +{
1680 + int i;
1681 +
1682 + /* enable clock gate */
1683 + clk_enable(hw->clk);
1684 +
1685 + ltq_switch_w32(1, 0);
1686 + mdelay(100);
1687 + ltq_switch_w32(0, 0);
1688 + /*
1689 + * TODO: we should really disbale all phys/miis here and explicitly
1690 + * enable them in the device secific init function
1691 + */
1692 +
1693 + /* disable port fetch/store dma */
1694 + for (i = 0; i < 7; i++ ) {
1695 + ltq_switch_w32(0, FDMA_PCTRLx(i));
1696 + ltq_switch_w32(0, SDMA_PCTRLx(i));
1697 + }
1698 +
1699 + /* enable Switch */
1700 + ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB);
1701 +
1702 + /* load the pce microcode */
1703 + xrx200_pci_microcode();
1704 +
1705 + /* Default unknown Broadcat/Multicast/Unicast port maps */
1706 + ltq_switch_w32(0x7f, PCE_PMAP1);
1707 + ltq_switch_w32(0x7f, PCE_PMAP2);
1708 + ltq_switch_w32(0x7f, PCE_PMAP3);
1709 +
1710 + /* RMON Counter Enable for all physical ports */
1711 + for (i = 0; i < 7; i++)
1712 + ltq_switch_w32(0x1, BM_PCFG(i));
1713 +
1714 + /* disable auto polling */
1715 + ltq_mdio_w32(0x0, MDIO_CLK_CFG0);
1716 +
1717 + /* enable port statistic counters */
1718 + for (i = 0; i < 7; i++)
1719 + ltq_switch_w32(0x1, BM_PCFGx(i));
1720 +
1721 + /* set IPG to 12 */
1722 + ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG);
1723 +
1724 +#ifdef SW_ROUTING
1725 + /* enable status header, enable CRC */
1726 + ltq_pmac_w32_mask(0,
1727 + PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC,
1728 + PMAC_HD_CTL);
1729 +#else
1730 + /* disable status header, enable CRC */
1731 + ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS,
1732 + PMAC_HD_CTL_AC,
1733 + PMAC_HD_CTL);
1734 +#endif
1735 +
1736 + /* enable port fetch/store dma & VLAN Modification */
1737 + for (i = 0; i < 7; i++ ) {
1738 + ltq_switch_w32_mask(0, 0x19, FDMA_PCTRLx(i));
1739 + ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i));
1740 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0));
1741 + }
1742 +
1743 + /* enable special tag insertion on cpu port */
1744 + ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6));
1745 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0));
1746 + ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2));
1747 + ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG);
1748 +}
1749 +
1750 +static void xrx200_hw_cleanup(struct xrx200_hw *hw)
1751 +{
1752 + int i;
1753 +
1754 + /* disable the switch */
1755 + ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB);
1756 +
1757 + /* free the channels and IRQs */
1758 + for (i = 0; i < 2; i++) {
1759 + ltq_dma_free(&hw->chan[i].dma);
1760 + if (hw->chan[i].dma.irq)
1761 + free_irq(hw->chan[i].dma.irq, hw);
1762 + }
1763 +
1764 + /* free the allocated RX ring */
1765 + for (i = 0; i < LTQ_DESC_NUM; i++)
1766 + dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]);
1767 +
1768 + /* clear the mdio bus */
1769 + mdiobus_unregister(hw->mii_bus);
1770 + mdiobus_free(hw->mii_bus);
1771 +
1772 + /* release the clock */
1773 + clk_disable(hw->clk);
1774 + clk_put(hw->clk);
1775 +}
1776 +
1777 +static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np)
1778 +{
1779 + hw->mii_bus = mdiobus_alloc();
1780 + if (!hw->mii_bus)
1781 + return -ENOMEM;
1782 +
1783 + hw->mii_bus->read = xrx200_mdio_rd;
1784 + hw->mii_bus->write = xrx200_mdio_wr;
1785 + hw->mii_bus->name = "lantiq,xrx200-mdio";
1786 + snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
1787 +
1788 + if (of_mdiobus_register(hw->mii_bus, np)) {
1789 + mdiobus_free(hw->mii_bus);
1790 + return -ENXIO;
1791 + }
1792 +
1793 + return 0;
1794 +}
1795 +
1796 +static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port)
1797 +{
1798 + const __be32 *addr, *id = of_get_property(port, "reg", NULL);
1799 + struct xrx200_port *p = &priv->port[priv->num_port];
1800 +
1801 + if (!id)
1802 + return;
1803 +
1804 + memset(p, 0, sizeof(struct xrx200_port));
1805 + p->phy_node = of_parse_phandle(port, "phy-handle", 0);
1806 + addr = of_get_property(p->phy_node, "reg", NULL);
1807 + if (!addr)
1808 + return;
1809 +
1810 + p->num = *id;
1811 + p->phy_addr = *addr;
1812 + p->phy_if = of_get_phy_mode(port);
1813 + if (p->phy_addr > 0x10)
1814 + p->flags = XRX200_PORT_TYPE_MAC;
1815 + else
1816 + p->flags = XRX200_PORT_TYPE_PHY;
1817 + priv->num_port++;
1818 +
1819 + p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags);
1820 + if (gpio_is_valid(p->gpio))
1821 + if (!gpio_request(p->gpio, "phy-reset")) {
1822 + gpio_direction_output(p->gpio,
1823 + (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0));
1824 + udelay(100);
1825 + gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
1826 + }
1827 + /* is this port a wan port ? */
1828 + if (priv->wan)
1829 + priv->hw->wan_map |= BIT(p->num);
1830 +
1831 + priv->port_map |= BIT(p->num);
1832 +
1833 + /* store the port id in the hw struct so we can map ports -> devices */
1834 + priv->hw->port_map[p->num] = priv->hw->num_devs;
1835 +}
1836 +
1837 +static const struct net_device_ops xrx200_netdev_ops = {
1838 + .ndo_init = xrx200_init,
1839 + .ndo_open = xrx200_open,
1840 + .ndo_stop = xrx200_close,
1841 + .ndo_start_xmit = xrx200_start_xmit,
1842 + .ndo_set_mac_address = eth_mac_addr,
1843 + .ndo_validate_addr = eth_validate_addr,
1844 + .ndo_change_mtu = eth_change_mtu,
1845 + .ndo_get_stats = xrx200_get_stats,
1846 + .ndo_tx_timeout = xrx200_tx_timeout,
1847 +};
1848 +
1849 +static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface)
1850 +{
1851 + struct xrx200_priv *priv;
1852 + struct device_node *port;
1853 + const __be32 *wan;
1854 + const __be32 *sw;
1855 +
1856 + /* alloc the network device */
1857 + hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv));
1858 + if (!hw->devs[hw->num_devs])
1859 + return;
1860 +
1861 + /* setup the network device */
1862 + strcpy(hw->devs[hw->num_devs]->name, "eth%d");
1863 + hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops;
1864 + hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT;
1865 + hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM;
1866 +
1867 + /* setup our private data */
1868 + priv = netdev_priv(hw->devs[hw->num_devs]);
1869 + priv->hw = hw;
1870 + of_get_mac_address_mtd(iface, priv->mac);
1871 + priv->id = hw->num_devs;
1872 +
1873 + /* is this the wan interface ? */
1874 + wan = of_get_property(iface, "lantiq,wan", NULL);
1875 + if (wan && (*wan == 1))
1876 + priv->wan = 1;
1877 +
1878 + /* should the switch be enabled on this interface ? */
1879 + sw = of_get_property(iface, "lantiq,switch", NULL);
1880 + if (sw && (*sw == 1))
1881 + priv->sw = 1;
1882 +
1883 + /* load the ports that are part of the interface */
1884 + for_each_child_of_node(iface, port)
1885 + if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port"))
1886 + xrx200_of_port(priv, port);
1887 +
1888 + /* register the actual device */
1889 + if (!register_netdev(hw->devs[hw->num_devs]))
1890 + hw->num_devs++;
1891 +}
1892 +
1893 +static struct xrx200_hw xrx200_hw;
1894 +
1895 +static int xrx200_probe(struct platform_device *pdev)
1896 +{
1897 + struct resource *res[4];
1898 + struct device_node *mdio_np, *iface_np;
1899 + int i;
1900 +
1901 + /* load the memory ranges */
1902 + for (i = 0; i < 4; i++) {
1903 + res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
1904 + if (!res[i]) {
1905 + dev_err(&pdev->dev, "failed to get resources\n");
1906 + return -ENOENT;
1907 + }
1908 + }
1909 + xrx200_switch_membase = devm_request_and_ioremap(&pdev->dev, res[0]);
1910 + xrx200_mdio_membase = devm_request_and_ioremap(&pdev->dev, res[1]);
1911 + xrx200_mii_membase = devm_request_and_ioremap(&pdev->dev, res[2]);
1912 + xrx200_pmac_membase = devm_request_and_ioremap(&pdev->dev, res[3]);
1913 + if (!xrx200_switch_membase || !xrx200_mdio_membase ||
1914 + !xrx200_mii_membase || !xrx200_pmac_membase) {
1915 + dev_err(&pdev->dev, "failed to request and remap io ranges \n");
1916 + return -ENOMEM;
1917 + }
1918 +
1919 + /* get the clock */
1920 + xrx200_hw.clk = clk_get(&pdev->dev, NULL);
1921 + if (IS_ERR(xrx200_hw.clk)) {
1922 + dev_err(&pdev->dev, "failed to get clock\n");
1923 + return PTR_ERR(xrx200_hw.clk);
1924 + }
1925 +
1926 + /* bring up the dma engine and IP core */
1927 + spin_lock_init(&xrx200_hw.lock);
1928 + xrx200_dma_init(&xrx200_hw);
1929 + xrx200_hw_init(&xrx200_hw);
1930 + tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw);
1931 +
1932 + /* bring up the mdio bus */
1933 + mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL,
1934 + "lantiq,xrx200-mdio");
1935 + if (mdio_np)
1936 + if (xrx200_of_mdio(&xrx200_hw, mdio_np))
1937 + dev_err(&pdev->dev, "mdio probe failed\n");
1938 +
1939 + /* load the interfaces */
1940 + for_each_child_of_node(pdev->dev.of_node, iface_np)
1941 + if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) {
1942 + if (xrx200_hw.num_devs < XRX200_MAX_DEV)
1943 + xrx200_of_iface(&xrx200_hw, iface_np);
1944 + else
1945 + dev_err(&pdev->dev,
1946 + "only %d interfaces allowed\n",
1947 + XRX200_MAX_DEV);
1948 + }
1949 +
1950 + if (!xrx200_hw.num_devs) {
1951 + xrx200_hw_cleanup(&xrx200_hw);
1952 + dev_err(&pdev->dev, "failed to load interfaces\n");
1953 + return -ENOENT;
1954 + }
1955 +
1956 + xrx200sw_init(&xrx200_hw);
1957 +
1958 + /* set wan port mask */
1959 + ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN);
1960 +
1961 + for (i = 0; i < xrx200_hw.num_devs; i++) {
1962 + xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i];
1963 + xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i];
1964 + }
1965 +
1966 + /* setup NAPI */
1967 + init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev);
1968 + netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev,
1969 + &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32);
1970 +
1971 + platform_set_drvdata(pdev, &xrx200_hw);
1972 +
1973 + return 0;
1974 +}
1975 +
1976 +static int xrx200_remove(struct platform_device *pdev)
1977 +{
1978 + struct net_device *dev = platform_get_drvdata(pdev);
1979 + struct xrx200_priv *priv;
1980 +
1981 + if (!dev)
1982 + return 0;
1983 +
1984 + priv = netdev_priv(dev);
1985 +
1986 + /* free stack related instances */
1987 + netif_stop_queue(dev);
1988 + netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi);
1989 +
1990 + /* shut down hardware */
1991 + xrx200_hw_cleanup(&xrx200_hw);
1992 +
1993 + /* remove the actual device */
1994 + unregister_netdev(dev);
1995 + free_netdev(dev);
1996 +
1997 + return 0;
1998 +}
1999 +
2000 +static const struct of_device_id xrx200_match[] = {
2001 + { .compatible = "lantiq,xrx200-net" },
2002 + {},
2003 +};
2004 +MODULE_DEVICE_TABLE(of, xrx200_match);
2005 +
2006 +static struct platform_driver xrx200_driver = {
2007 + .probe = xrx200_probe,
2008 + .remove = xrx200_remove,
2009 + .driver = {
2010 + .name = "lantiq,xrx200-net",
2011 + .of_match_table = xrx200_match,
2012 + .owner = THIS_MODULE,
2013 + },
2014 +};
2015 +
2016 +module_platform_driver(xrx200_driver);
2017 +
2018 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2019 +MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
2020 +MODULE_LICENSE("GPL");
2021 diff --git a/drivers/net/ethernet/lantiq_xrx200_sw.h b/drivers/net/ethernet/lantiq_xrx200_sw.h
2022 new file mode 100644
2023 index 0000000..e7188a2
2024 --- /dev/null
2025 +++ b/drivers/net/ethernet/lantiq_xrx200_sw.h
2026 @@ -0,0 +1,1328 @@
2027 +/*
2028 + * This program is free software; you can redistribute it and/or modify it
2029 + * under the terms of the GNU General Public License version 2 as published
2030 + * by the Free Software Foundation.
2031 + *
2032 + * This program is distributed in the hope that it will be useful,
2033 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2034 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2035 + * GNU General Public License for more details.
2036 + *
2037 + * You should have received a copy of the GNU General Public License
2038 + * along with this program; if not, write to the Free Software
2039 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2040 + *
2041 + * Copyright (C) 2010 Lantiq Deutschland GmbH
2042 + * Copyright (C) 2013 Antonios Vamporakis <vamporakis@yahoo.com>
2043 + *
2044 + * VR9 switch registers extracted from 310TUJ0 switch api
2045 + * WARNING mult values of 0x00 may not be correct
2046 + *
2047 + */
2048 +
2049 +enum {
2050 +// XRX200_ETHSW_SWRES, /* Ethernet Switch ResetControl Register */
2051 +// XRX200_ETHSW_SWRES_R1, /* Hardware Reset */
2052 +// XRX200_ETHSW_SWRES_R0, /* Register Configuration */
2053 +// XRX200_ETHSW_CLK_MAC_GAT, /* Ethernet Switch Clock ControlRegister */
2054 +// XRX200_ETHSW_CLK_EXP_SLEEP, /* Exponent to put system into sleep */
2055 +// XRX200_ETHSW_CLK_EXP_WAKE, /* Exponent to wake up system */
2056 +// XRX200_ETHSW_CLK_CLK2_EN, /* CLK2 Input for MAC */
2057 +// XRX200_ETHSW_CLK_EXT_DIV_EN, /* External Clock Divider Enable */
2058 +// XRX200_ETHSW_CLK_RAM_DBG_EN, /* Clock Gating Enable */
2059 +// XRX200_ETHSW_CLK_REG_GAT_EN, /* Clock Gating Enable */
2060 +// XRX200_ETHSW_CLK_GAT_EN, /* Clock Gating Enable */
2061 +// XRX200_ETHSW_CLK_MAC_GAT_EN, /* Clock Gating Enable */
2062 +// XRX200_ETHSW_DBG_STEP, /* Ethernet Switch Debug ControlRegister */
2063 +// XRX200_ETHSW_DBG_CLK_SEL, /* Trigger Enable */
2064 +// XRX200_ETHSW_DBG_MON_EN, /* Monitoring Enable */
2065 +// XRX200_ETHSW_DBG_TRIG_EN, /* Trigger Enable */
2066 +// XRX200_ETHSW_DBG_MODE, /* Debug Mode */
2067 +// XRX200_ETHSW_DBG_STEP_TIME, /* Clock Step Size */
2068 +// XRX200_ETHSW_SSB_MODE, /* Ethernet Switch SharedSegment Buffer Mode Register */
2069 +// XRX200_ETHSW_SSB_MODE_ADDE, /* Memory Address */
2070 +// XRX200_ETHSW_SSB_MODE_MODE, /* Memory Access Mode */
2071 +// XRX200_ETHSW_SSB_ADDR, /* Ethernet Switch SharedSegment Buffer Address Register */
2072 +// XRX200_ETHSW_SSB_ADDR_ADDE, /* Memory Address */
2073 +// XRX200_ETHSW_SSB_DATA, /* Ethernet Switch SharedSegment Buffer Data Register */
2074 +// XRX200_ETHSW_SSB_DATA_DATA, /* Data Value */
2075 +// XRX200_ETHSW_CAP_0, /* Ethernet Switch CapabilityRegister 0 */
2076 +// XRX200_ETHSW_CAP_0_SPEED, /* Clock frequency */
2077 +// XRX200_ETHSW_CAP_1, /* Ethernet Switch CapabilityRegister 1 */
2078 +// XRX200_ETHSW_CAP_1_GMAC, /* MAC operation mode */
2079 +// XRX200_ETHSW_CAP_1_QUEUE, /* Number of queues */
2080 +// XRX200_ETHSW_CAP_1_VPORTS, /* Number of virtual ports */
2081 +// XRX200_ETHSW_CAP_1_PPORTS, /* Number of physical ports */
2082 +// XRX200_ETHSW_CAP_2, /* Ethernet Switch CapabilityRegister 2 */
2083 +// XRX200_ETHSW_CAP_2_PACKETS, /* Number of packets */
2084 +// XRX200_ETHSW_CAP_3, /* Ethernet Switch CapabilityRegister 3 */
2085 +// XRX200_ETHSW_CAP_3_METERS, /* Number of traffic meters */
2086 +// XRX200_ETHSW_CAP_3_SHAPERS, /* Number of traffic shapers */
2087 +// XRX200_ETHSW_CAP_4, /* Ethernet Switch CapabilityRegister 4 */
2088 +// XRX200_ETHSW_CAP_4_PPPOE, /* PPPoE table size */
2089 +// XRX200_ETHSW_CAP_4_VLAN, /* Active VLAN table size */
2090 +// XRX200_ETHSW_CAP_5, /* Ethernet Switch CapabilityRegister 5 */
2091 +// XRX200_ETHSW_CAP_5_IPPLEN, /* IP packet length table size */
2092 +// XRX200_ETHSW_CAP_5_PROT, /* Protocol table size */
2093 +// XRX200_ETHSW_CAP_6, /* Ethernet Switch CapabilityRegister 6 */
2094 +// XRX200_ETHSW_CAP_6_MACDASA, /* MAC DA/SA table size */
2095 +// XRX200_ETHSW_CAP_6_APPL, /* Application table size */
2096 +// XRX200_ETHSW_CAP_7, /* Ethernet Switch CapabilityRegister 7 */
2097 +// XRX200_ETHSW_CAP_7_IPDASAM, /* IP DA/SA MSB table size */
2098 +// XRX200_ETHSW_CAP_7_IPDASAL, /* IP DA/SA LSB table size */
2099 +// XRX200_ETHSW_CAP_8, /* Ethernet Switch CapabilityRegister 8 */
2100 +// XRX200_ETHSW_CAP_8_MCAST, /* Multicast table size */
2101 +// XRX200_ETHSW_CAP_9, /* Ethernet Switch CapabilityRegister 9 */
2102 +// XRX200_ETHSW_CAP_9_FLAGG, /* Flow Aggregation table size */
2103 +// XRX200_ETHSW_CAP_10, /* Ethernet Switch CapabilityRegister 10 */
2104 +// XRX200_ETHSW_CAP_10_MACBT, /* MAC bridging table size */
2105 +// XRX200_ETHSW_CAP_11, /* Ethernet Switch CapabilityRegister 11 */
2106 +// XRX200_ETHSW_CAP_11_BSIZEL, /* Packet buffer size (lower part, in byte) */
2107 +// XRX200_ETHSW_CAP_12, /* Ethernet Switch CapabilityRegister 12 */
2108 +// XRX200_ETHSW_CAP_12_BSIZEH, /* Packet buffer size (higher part, in byte) */
2109 +// XRX200_ETHSW_VERSION_REV, /* Ethernet Switch VersionRegister */
2110 +// XRX200_ETHSW_VERSION_MOD_ID, /* Module Identification */
2111 +// XRX200_ETHSW_VERSION_REV_ID, /* Hardware Revision Identification */
2112 +// XRX200_ETHSW_IER, /* Interrupt Enable Register */
2113 +// XRX200_ETHSW_IER_FDMAIE, /* Fetch DMA Interrupt Enable */
2114 +// XRX200_ETHSW_IER_SDMAIE, /* Store DMA Interrupt Enable */
2115 +// XRX200_ETHSW_IER_MACIE, /* Ethernet MAC Interrupt Enable */
2116 +// XRX200_ETHSW_IER_PCEIE, /* Parser and Classification Engine Interrupt Enable */
2117 +// XRX200_ETHSW_IER_BMIE, /* Buffer Manager Interrupt Enable */
2118 +// XRX200_ETHSW_ISR, /* Interrupt Status Register */
2119 +// XRX200_ETHSW_ISR_FDMAINT, /* Fetch DMA Interrupt */
2120 +// XRX200_ETHSW_ISR_SDMAINT, /* Store DMA Interrupt */
2121 +// XRX200_ETHSW_ISR_MACINT, /* Ethernet MAC Interrupt */
2122 +// XRX200_ETHSW_ISR_PCEINT, /* Parser and Classification Engine Interrupt */
2123 +// XRX200_ETHSW_ISR_BMINT, /* Buffer Manager Interrupt */
2124 +// XRX200_ETHSW_SPARE_0, /* Ethernet Switch SpareCells 0 */
2125 +// XRX200_ETHSW_SPARE_0_SPARE, /* SPARE0 */
2126 +// XRX200_ETHSW_SPARE_1, /* Ethernet Switch SpareCells 1 */
2127 +// XRX200_ETHSW_SPARE_1_SPARE, /* SPARE1 */
2128 +// XRX200_ETHSW_SPARE_2, /* Ethernet Switch SpareCells 2 */
2129 +// XRX200_ETHSW_SPARE_2_SPARE, /* SPARE2 */
2130 +// XRX200_ETHSW_SPARE_3, /* Ethernet Switch SpareCells 3 */
2131 +// XRX200_ETHSW_SPARE_3_SPARE, /* SPARE3 */
2132 +// XRX200_ETHSW_SPARE_4, /* Ethernet Switch SpareCells 4 */
2133 +// XRX200_ETHSW_SPARE_4_SPARE, /* SPARE4 */
2134 +// XRX200_ETHSW_SPARE_5, /* Ethernet Switch SpareCells 5 */
2135 +// XRX200_ETHSW_SPARE_5_SPARE, /* SPARE5 */
2136 +// XRX200_ETHSW_SPARE_6, /* Ethernet Switch SpareCells 6 */
2137 +// XRX200_ETHSW_SPARE_6_SPARE, /* SPARE6 */
2138 +// XRX200_ETHSW_SPARE_7, /* Ethernet Switch SpareCells 7 */
2139 +// XRX200_ETHSW_SPARE_7_SPARE, /* SPARE7 */
2140 +// XRX200_ETHSW_SPARE_8, /* Ethernet Switch SpareCells 8 */
2141 +// XRX200_ETHSW_SPARE_8_SPARE, /* SPARE8 */
2142 +// XRX200_ETHSW_SPARE_9, /* Ethernet Switch SpareCells 9 */
2143 +// XRX200_ETHSW_SPARE_9_SPARE, /* SPARE9 */
2144 +// XRX200_ETHSW_SPARE_10, /* Ethernet Switch SpareCells 10 */
2145 +// XRX200_ETHSW_SPARE_10_SPARE, /* SPARE10 */
2146 +// XRX200_ETHSW_SPARE_11, /* Ethernet Switch SpareCells 11 */
2147 +// XRX200_ETHSW_SPARE_11_SPARE, /* SPARE11 */
2148 +// XRX200_ETHSW_SPARE_12, /* Ethernet Switch SpareCells 12 */
2149 +// XRX200_ETHSW_SPARE_12_SPARE, /* SPARE12 */
2150 +// XRX200_ETHSW_SPARE_13, /* Ethernet Switch SpareCells 13 */
2151 +// XRX200_ETHSW_SPARE_13_SPARE, /* SPARE13 */
2152 +// XRX200_ETHSW_SPARE_14, /* Ethernet Switch SpareCells 14 */
2153 +// XRX200_ETHSW_SPARE_14_SPARE, /* SPARE14 */
2154 +// XRX200_ETHSW_SPARE_15, /* Ethernet Switch SpareCells 15 */
2155 +// XRX200_ETHSW_SPARE_15_SPARE, /* SPARE15 */
2156 +// XRX200_BM_RAM_VAL_3, /* RAM Value Register 3 */
2157 +// XRX200_BM_RAM_VAL_3_VAL3, /* Data value [15:0] */
2158 +// XRX200_BM_RAM_VAL_2, /* RAM Value Register 2 */
2159 +// XRX200_BM_RAM_VAL_2_VAL2, /* Data value [15:0] */
2160 +// XRX200_BM_RAM_VAL_1, /* RAM Value Register 1 */
2161 +// XRX200_BM_RAM_VAL_1_VAL1, /* Data value [15:0] */
2162 +// XRX200_BM_RAM_VAL_0, /* RAM Value Register 0 */
2163 +// XRX200_BM_RAM_VAL_0_VAL0, /* Data value [15:0] */
2164 +// XRX200_BM_RAM_ADDR, /* RAM Address Register */
2165 +// XRX200_BM_RAM_ADDR_ADDR, /* RAM Address */
2166 +// XRX200_BM_RAM_CTRL, /* RAM Access Control Register */
2167 +// XRX200_BM_RAM_CTRL_BAS, /* Access Busy/Access Start */
2168 +// XRX200_BM_RAM_CTRL_OPMOD, /* Lookup Table Access Operation Mode */
2169 +// XRX200_BM_RAM_CTRL_ADDR, /* Address for RAM selection */
2170 +// XRX200_BM_FSQM_GCTRL, /* Free Segment Queue ManagerGlobal Control Register */
2171 +// XRX200_BM_FSQM_GCTRL_SEGNUM, /* Maximum Segment Number */
2172 +// XRX200_BM_CONS_SEG, /* Number of Consumed SegmentsRegister */
2173 +// XRX200_BM_CONS_SEG_FSEG, /* Number of Consumed Segments */
2174 +// XRX200_BM_CONS_PKT, /* Number of Consumed PacketPointers Register */
2175 +// XRX200_BM_CONS_PKT_FQP, /* Number of Consumed Packet Pointers */
2176 +// XRX200_BM_GCTRL_F, /* Buffer Manager Global ControlRegister 0 */
2177 +// XRX200_BM_GCTRL_BM_STA, /* Buffer Manager Initialization Status Bit */
2178 +// XRX200_BM_GCTRL_SAT, /* RMON Counter Update Mode */
2179 +// XRX200_BM_GCTRL_FR_RBC, /* Freeze RMON RX Bad Byte 64 Bit Counter */
2180 +// XRX200_BM_GCTRL_FR_RGC, /* Freeze RMON RX Good Byte 64 Bit Counter */
2181 +// XRX200_BM_GCTRL_FR_TGC, /* Freeze RMON TX Good Byte 64 Bit Counter */
2182 +// XRX200_BM_GCTRL_I_FIN, /* RAM initialization finished */
2183 +// XRX200_BM_GCTRL_CX_INI, /* PQM Context RAM initialization */
2184 +// XRX200_BM_GCTRL_FP_INI, /* FPQM RAM initialization */
2185 +// XRX200_BM_GCTRL_FS_INI, /* FSQM RAM initialization */
2186 +// XRX200_BM_GCTRL_R_SRES, /* Software Reset for RMON */
2187 +// XRX200_BM_GCTRL_S_SRES, /* Software Reset for Scheduler */
2188 +// XRX200_BM_GCTRL_A_SRES, /* Software Reset for AVG */
2189 +// XRX200_BM_GCTRL_P_SRES, /* Software Reset for PQM */
2190 +// XRX200_BM_GCTRL_F_SRES, /* Software Reset for FSQM */
2191 +// XRX200_BM_QUEUE_GCTRL, /* Queue Manager GlobalControl Register 0 */
2192 +// XRX200_BM_QUEUE_GCTRL_GL_MOD, /* WRED Mode Signal */
2193 +// XRX200_BM_QUEUE_GCTRL_AQUI, /* Average Queue Update Interval */
2194 +// XRX200_BM_QUEUE_GCTRL_AQWF, /* Average Queue Weight Factor */
2195 +// XRX200_BM_QUEUE_GCTRL_QAVGEN, /* Queue Average Calculation Enable */
2196 +// XRX200_BM_QUEUE_GCTRL_DPROB, /* Drop Probability Profile */
2197 +// XRX200_BM_WRED_RTH_0, /* WRED Red Threshold Register0 */
2198 +// XRX200_BM_WRED_RTH_0_MINTH, /* Minimum Threshold */
2199 +// XRX200_BM_WRED_RTH_1, /* WRED Red Threshold Register1 */
2200 +// XRX200_BM_WRED_RTH_1_MAXTH, /* Maximum Threshold */
2201 +// XRX200_BM_WRED_YTH_0, /* WRED Yellow ThresholdRegister 0 */
2202 +// XRX200_BM_WRED_YTH_0_MINTH, /* Minimum Threshold */
2203 +// XRX200_BM_WRED_YTH_1, /* WRED Yellow ThresholdRegister 1 */
2204 +// XRX200_BM_WRED_YTH_1_MAXTH, /* Maximum Threshold */
2205 +// XRX200_BM_WRED_GTH_0, /* WRED Green ThresholdRegister 0 */
2206 +// XRX200_BM_WRED_GTH_0_MINTH, /* Minimum Threshold */
2207 +// XRX200_BM_WRED_GTH_1, /* WRED Green ThresholdRegister 1 */
2208 +// XRX200_BM_WRED_GTH_1_MAXTH, /* Maximum Threshold */
2209 +// XRX200_BM_DROP_GTH_0_THR, /* Drop Threshold ConfigurationRegister 0 */
2210 +// XRX200_BM_DROP_GTH_0_THR_FQ, /* Threshold for frames marked red */
2211 +// XRX200_BM_DROP_GTH_1_THY, /* Drop Threshold ConfigurationRegister 1 */
2212 +// XRX200_BM_DROP_GTH_1_THY_FQ, /* Threshold for frames marked yellow */
2213 +// XRX200_BM_DROP_GTH_2_THG, /* Drop Threshold ConfigurationRegister 2 */
2214 +// XRX200_BM_DROP_GTH_2_THG_FQ, /* Threshold for frames marked green */
2215 +// XRX200_BM_IER, /* Buffer Manager Global InterruptEnable Register */
2216 +// XRX200_BM_IER_CNT4, /* Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */
2217 +// XRX200_BM_IER_CNT3, /* Counter Group 3 (RMON-PQM) Interrupt Enable */
2218 +// XRX200_BM_IER_CNT2, /* Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */
2219 +// XRX200_BM_IER_CNT1, /* Counter Group 1 (RMON-QFETCH) Interrupt Enable */
2220 +// XRX200_BM_IER_CNT0, /* Counter Group 0 (RMON-QSTOR) Interrupt Enable */
2221 +// XRX200_BM_IER_DEQ, /* PQM dequeue Interrupt Enable */
2222 +// XRX200_BM_IER_ENQ, /* PQM Enqueue Interrupt Enable */
2223 +// XRX200_BM_IER_FSQM, /* Buffer Empty Interrupt Enable */
2224 +// XRX200_BM_ISR, /* Buffer Manager Global InterruptStatus Register */
2225 +// XRX200_BM_ISR_CNT4, /* Counter Group 4 Interrupt */
2226 +// XRX200_BM_ISR_CNT3, /* Counter Group 3 Interrupt */
2227 +// XRX200_BM_ISR_CNT2, /* Counter Group 2 Interrupt */
2228 +// XRX200_BM_ISR_CNT1, /* Counter Group 1 Interrupt */
2229 +// XRX200_BM_ISR_CNT0, /* Counter Group 0 Interrupt */
2230 +// XRX200_BM_ISR_DEQ, /* PQM dequeue Interrupt Enable */
2231 +// XRX200_BM_ISR_ENQ, /* PQM Enqueue Interrupt */
2232 +// XRX200_BM_ISR_FSQM, /* Buffer Empty Interrupt */
2233 +// XRX200_BM_CISEL, /* Buffer Manager RMON CounterInterrupt Select Register */
2234 +// XRX200_BM_CISEL_PORT, /* Port Number */
2235 +// XRX200_BM_DEBUG_CTRL_DBG, /* Debug Control Register */
2236 +// XRX200_BM_DEBUG_CTRL_DBG_SEL, /* Select Signal for Debug Multiplexer */
2237 +// XRX200_BM_DEBUG_VAL_DBG, /* Debug Value Register */
2238 +// XRX200_BM_DEBUG_VAL_DBG_DAT, /* Debug Data Value */
2239 +// XRX200_BM_PCFG, /* Buffer Manager PortConfiguration Register */
2240 +// XRX200_BM_PCFG_CNTEN, /* RMON Counter Enable */
2241 +// XRX200_BM_RMON_CTRL_RAM1, /* Buffer ManagerRMON Control Register */
2242 +// XRX200_BM_RMON_CTRL_RAM2_RES, /* Software Reset for RMON RAM2 */
2243 +// XRX200_BM_RMON_CTRL_RAM1_RES, /* Software Reset for RMON RAM1 */
2244 +// XRX200_PQM_DP, /* Packet Queue ManagerDrop Probability Register */
2245 +// XRX200_PQM_DP_DPROB, /* Drop Probability Profile */
2246 +// XRX200_PQM_RS, /* Packet Queue ManagerRate Shaper Assignment Register */
2247 +// XRX200_PQM_RS_EN2, /* Rate Shaper 2 Enable */
2248 +// XRX200_PQM_RS_RS2, /* Rate Shaper 2 */
2249 +// XRX200_PQM_RS_EN1, /* Rate Shaper 1 Enable */
2250 +// XRX200_PQM_RS_RS1, /* Rate Shaper 1 */
2251 +// XRX200_RS_CTRL, /* Rate Shaper ControlRegister */
2252 +// XRX200_RS_CTRL_RSEN, /* Rate Shaper Enable */
2253 +// XRX200_RS_CBS, /* Rate Shaper CommittedBurst Size Register */
2254 +// XRX200_RS_CBS_CBS, /* Committed Burst Size */
2255 +// XRX200_RS_IBS, /* Rate Shaper InstantaneousBurst Size Register */
2256 +// XRX200_RS_IBS_IBS, /* Instantaneous Burst Size */
2257 +// XRX200_RS_CIR_EXP, /* Rate Shaper RateExponent Register */
2258 +// XRX200_RS_CIR_EXP_EXP, /* Exponent */
2259 +// XRX200_RS_CIR_MANT, /* Rate Shaper RateMantissa Register */
2260 +// XRX200_RS_CIR_MANT_MANT, /* Mantissa */
2261 + XRX200_PCE_TBL_KEY_7, /* Table Key Data 7 */
2262 +// XRX200_PCE_TBL_KEY_7_KEY7, /* Key Value[15:0] */
2263 + XRX200_PCE_TBL_KEY_6, /* Table Key Data 6 */
2264 +// XRX200_PCE_TBL_KEY_6_KEY6, /* Key Value[15:0] */
2265 + XRX200_PCE_TBL_KEY_5, /* Table Key Data 5 */
2266 +// XRX200_PCE_TBL_KEY_5_KEY5, /* Key Value[15:0] */
2267 + XRX200_PCE_TBL_KEY_4, /* Table Key Data 4 */
2268 +// XRX200_PCE_TBL_KEY_4_KEY4, /* Key Value[15:0] */
2269 + XRX200_PCE_TBL_KEY_3, /* Table Key Data 3 */
2270 +// XRX200_PCE_TBL_KEY_3_KEY3, /* Key Value[15:0] */
2271 + XRX200_PCE_TBL_KEY_2, /* Table Key Data 2 */
2272 +// XRX200_PCE_TBL_KEY_2_KEY2, /* Key Value[15:0] */
2273 + XRX200_PCE_TBL_KEY_1, /* Table Key Data 1 */
2274 +// XRX200_PCE_TBL_KEY_1_KEY1, /* Key Value[31:16] */
2275 + XRX200_PCE_TBL_KEY_0, /* Table Key Data 0 */
2276 +// XRX200_PCE_TBL_KEY_0_KEY0, /* Key Value[15:0] */
2277 + XRX200_PCE_TBL_MASK_0, /* Table Mask Write Register0 */
2278 +// XRX200_PCE_TBL_MASK_0_MASK0, /* Mask Pattern [15:0] */
2279 + XRX200_PCE_TBL_VAL_4, /* Table Value Register4 */
2280 +// XRX200_PCE_TBL_VAL_4_VAL4, /* Data value [15:0] */
2281 + XRX200_PCE_TBL_VAL_3, /* Table Value Register3 */
2282 +// XRX200_PCE_TBL_VAL_3_VAL3, /* Data value [15:0] */
2283 + XRX200_PCE_TBL_VAL_2, /* Table Value Register2 */
2284 +// XRX200_PCE_TBL_VAL_2_VAL2, /* Data value [15:0] */
2285 + XRX200_PCE_TBL_VAL_1, /* Table Value Register1 */
2286 +// XRX200_PCE_TBL_VAL_1_VAL1, /* Data value [15:0] */
2287 + XRX200_PCE_TBL_VAL_0, /* Table Value Register0 */
2288 +// XRX200_PCE_TBL_VAL_0_VAL0, /* Data value [15:0] */
2289 +// XRX200_PCE_TBL_ADDR, /* Table Entry AddressRegister */
2290 + XRX200_PCE_TBL_ADDR_ADDR, /* Table Address */
2291 +// XRX200_PCE_TBL_CTRL, /* Table Access ControlRegister */
2292 + XRX200_PCE_TBL_CTRL_BAS, /* Access Busy/Access Start */
2293 + XRX200_PCE_TBL_CTRL_TYPE, /* Lookup Entry Type */
2294 + XRX200_PCE_TBL_CTRL_VLD, /* Lookup Entry Valid */
2295 + XRX200_PCE_TBL_CTRL_GMAP, /* Group Map */
2296 + XRX200_PCE_TBL_CTRL_OPMOD, /* Lookup Table Access Operation Mode */
2297 + XRX200_PCE_TBL_CTRL_ADDR, /* Lookup Table Address */
2298 +// XRX200_PCE_TBL_STAT, /* Table General StatusRegister */
2299 +// XRX200_PCE_TBL_STAT_TBUSY, /* Table Access Busy */
2300 +// XRX200_PCE_TBL_STAT_TEMPT, /* Table Empty */
2301 +// XRX200_PCE_TBL_STAT_TFUL, /* Table Full */
2302 +// XRX200_PCE_AGE_0, /* Aging Counter ConfigurationRegister 0 */
2303 +// XRX200_PCE_AGE_0_EXP, /* Aging Counter Exponent Value */
2304 +// XRX200_PCE_AGE_1, /* Aging Counter ConfigurationRegister 1 */
2305 +// XRX200_PCE_AGE_1_MANT, /* Aging Counter Mantissa Value */
2306 +// XRX200_PCE_PMAP_1, /* Port Map Register 1 */
2307 +// XRX200_PCE_PMAP_1_MPMAP, /* Monitoring Port Map */
2308 +// XRX200_PCE_PMAP_2, /* Port Map Register 2 */
2309 +// XRX200_PCE_PMAP_2_DMCPMAP, /* Default Multicast Port Map */
2310 +// XRX200_PCE_PMAP_3, /* Port Map Register 3 */
2311 +// XRX200_PCE_PMAP_3_UUCMAP, /* Default Unknown Unicast Port Map */
2312 +// XRX200_PCE_GCTRL_0, /* PCE Global Control Register0 */
2313 +// XRX200_PCE_GCTRL_0_IGMP, /* IGMP Mode Selection */
2314 + XRX200_PCE_GCTRL_0_VLAN, /* VLAN-aware Switching */
2315 +// XRX200_PCE_GCTRL_0_NOPM, /* No Port Map Forwarding */
2316 +// XRX200_PCE_GCTRL_0_SCONUC, /* Unknown Unicast Storm Control */
2317 +// XRX200_PCE_GCTRL_0_SCONMC, /* Multicast Storm Control */
2318 +// XRX200_PCE_GCTRL_0_SCONBC, /* Broadcast Storm Control */
2319 +// XRX200_PCE_GCTRL_0_SCONMOD, /* Storm Control Mode */
2320 +// XRX200_PCE_GCTRL_0_SCONMET, /* Storm Control Metering Instance */
2321 +// XRX200_PCE_GCTRL_0_MC_VALID, /* Access Request */
2322 +// XRX200_PCE_GCTRL_0_PLCKMOD, /* Port Lock Mode */
2323 +// XRX200_PCE_GCTRL_0_PLIMMOD, /* MAC Address Learning Limitation Mode */
2324 +// XRX200_PCE_GCTRL_0_MTFL, /* MAC Table Flushing */
2325 +// XRX200_PCE_GCTRL_1, /* PCE Global Control Register1 */
2326 +// XRX200_PCE_GCTRL_1_PCE_DIS, /* PCE Disable after currently processed packet */
2327 +// XRX200_PCE_GCTRL_1_LRNMOD, /* MAC Address Learning Mode */
2328 +// XRX200_PCE_TCM_GLOB_CTRL, /* Three-color MarkerGlobal Control Register */
2329 +// XRX200_PCE_TCM_GLOB_CTRL_DPRED, /* Re-marking Drop Precedence Red Encoding */
2330 +// XRX200_PCE_TCM_GLOB_CTRL_DPYEL, /* Re-marking Drop Precedence Yellow Encoding */
2331 +// XRX200_PCE_TCM_GLOB_CTRL_DPGRN, /* Re-marking Drop Precedence Green Encoding */
2332 +// XRX200_PCE_IGMP_CTRL, /* IGMP Control Register */
2333 +// XRX200_PCE_IGMP_CTRL_FAGEEN, /* Force Aging of Table Entries Enable */
2334 +// XRX200_PCE_IGMP_CTRL_FLEAVE, /* Fast Leave Enable */
2335 +// XRX200_PCE_IGMP_CTRL_DMRTEN, /* Default Maximum Response Time Enable */
2336 +// XRX200_PCE_IGMP_CTRL_JASUP, /* Join Aggregation Suppression Enable */
2337 +// XRX200_PCE_IGMP_CTRL_REPSUP, /* Report Suppression Enable */
2338 +// XRX200_PCE_IGMP_CTRL_SRPEN, /* Snooping of Router Port Enable */
2339 +// XRX200_PCE_IGMP_CTRL_ROB, /* Robustness Variable */
2340 +// XRX200_PCE_IGMP_CTRL_DMRT, /* IGMP Default Maximum Response Time */
2341 +// XRX200_PCE_IGMP_DRPM, /* IGMP Default RouterPort Map Register */
2342 +// XRX200_PCE_IGMP_DRPM_DRPM, /* IGMP Default Router Port Map */
2343 +// XRX200_PCE_IGMP_AGE_0, /* IGMP Aging Register0 */
2344 +// XRX200_PCE_IGMP_AGE_0_MANT, /* IGMP Group Aging Time Mantissa */
2345 +// XRX200_PCE_IGMP_AGE_0_EXP, /* IGMP Group Aging Time Exponent */
2346 +// XRX200_PCE_IGMP_AGE_1, /* IGMP Aging Register1 */
2347 +// XRX200_PCE_IGMP_AGE_1_MANT, /* IGMP Router Port Aging Time Mantissa */
2348 +// XRX200_PCE_IGMP_STAT, /* IGMP Status Register */
2349 +// XRX200_PCE_IGMP_STAT_IGPM, /* IGMP Port Map */
2350 +// XRX200_WOL_GLB_CTRL, /* Wake-on-LAN ControlRegister */
2351 +// XRX200_WOL_GLB_CTRL_PASSEN, /* WoL Password Enable */
2352 +// XRX200_WOL_DA_0, /* Wake-on-LAN DestinationAddress Register 0 */
2353 +// XRX200_WOL_DA_0_DA0, /* WoL Destination Address [15:0] */
2354 +// XRX200_WOL_DA_1, /* Wake-on-LAN DestinationAddress Register 1 */
2355 +// XRX200_WOL_DA_1_DA1, /* WoL Destination Address [31:16] */
2356 +// XRX200_WOL_DA_2, /* Wake-on-LAN DestinationAddress Register 2 */
2357 +// XRX200_WOL_DA_2_DA2, /* WoL Destination Address [47:32] */
2358 +// XRX200_WOL_PW_0, /* Wake-on-LAN Password Register0 */
2359 +// XRX200_WOL_PW_0_PW0, /* WoL Password [15:0] */
2360 +// XRX200_WOL_PW_1, /* Wake-on-LAN Password Register1 */
2361 +// XRX200_WOL_PW_1_PW1, /* WoL Password [31:16] */
2362 +// XRX200_WOL_PW_2, /* Wake-on-LAN Password Register2 */
2363 +// XRX200_WOL_PW_2_PW2, /* WoL Password [47:32] */
2364 +// XRX200_PCE_IER_0_PINT, /* Parser and ClassificationEngine Global Interrupt Enable Register 0 */
2365 +// XRX200_PCE_IER_0_PINT_15, /* Port Interrupt Enable */
2366 +// XRX200_PCE_IER_0_PINT_14, /* Port Interrupt Enable */
2367 +// XRX200_PCE_IER_0_PINT_13, /* Port Interrupt Enable */
2368 +// XRX200_PCE_IER_0_PINT_12, /* Port Interrupt Enable */
2369 +// XRX200_PCE_IER_0_PINT_11, /* Port Interrupt Enable */
2370 +// XRX200_PCE_IER_0_PINT_10, /* Port Interrupt Enable */
2371 +// XRX200_PCE_IER_0_PINT_9, /* Port Interrupt Enable */
2372 +// XRX200_PCE_IER_0_PINT_8, /* Port Interrupt Enable */
2373 +// XRX200_PCE_IER_0_PINT_7, /* Port Interrupt Enable */
2374 +// XRX200_PCE_IER_0_PINT_6, /* Port Interrupt Enable */
2375 +// XRX200_PCE_IER_0_PINT_5, /* Port Interrupt Enable */
2376 +// XRX200_PCE_IER_0_PINT_4, /* Port Interrupt Enable */
2377 +// XRX200_PCE_IER_0_PINT_3, /* Port Interrupt Enable */
2378 +// XRX200_PCE_IER_0_PINT_2, /* Port Interrupt Enable */
2379 +// XRX200_PCE_IER_0_PINT_1, /* Port Interrupt Enable */
2380 +// XRX200_PCE_IER_0_PINT_0, /* Port Interrupt Enable */
2381 +// XRX200_PCE_IER_1, /* Parser and ClassificationEngine Global Interrupt Enable Register 1 */
2382 +// XRX200_PCE_IER_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched Interrupt Enable */
2383 +// XRX200_PCE_IER_1_CPH2, /* Classification Phase 2 Ready Interrupt Enable */
2384 +// XRX200_PCE_IER_1_CPH1, /* Classification Phase 1 Ready Interrupt Enable */
2385 +// XRX200_PCE_IER_1_CPH0, /* Classification Phase 0 Ready Interrupt Enable */
2386 +// XRX200_PCE_IER_1_PRDY, /* Parser Ready Interrupt Enable */
2387 +// XRX200_PCE_IER_1_IGTF, /* IGMP Table Full Interrupt Enable */
2388 +// XRX200_PCE_IER_1_MTF, /* MAC Table Full Interrupt Enable */
2389 +// XRX200_PCE_ISR_0_PINT, /* Parser and ClassificationEngine Global Interrupt Status Register 0 */
2390 +// XRX200_PCE_ISR_0_PINT_15, /* Port Interrupt */
2391 +// XRX200_PCE_ISR_0_PINT_14, /* Port Interrupt */
2392 +// XRX200_PCE_ISR_0_PINT_13, /* Port Interrupt */
2393 +// XRX200_PCE_ISR_0_PINT_12, /* Port Interrupt */
2394 +// XRX200_PCE_ISR_0_PINT_11, /* Port Interrupt */
2395 +// XRX200_PCE_ISR_0_PINT_10, /* Port Interrupt */
2396 +// XRX200_PCE_ISR_0_PINT_9, /* Port Interrupt */
2397 +// XRX200_PCE_ISR_0_PINT_8, /* Port Interrupt */
2398 +// XRX200_PCE_ISR_0_PINT_7, /* Port Interrupt */
2399 +// XRX200_PCE_ISR_0_PINT_6, /* Port Interrupt */
2400 +// XRX200_PCE_ISR_0_PINT_5, /* Port Interrupt */
2401 +// XRX200_PCE_ISR_0_PINT_4, /* Port Interrupt */
2402 +// XRX200_PCE_ISR_0_PINT_3, /* Port Interrupt */
2403 +// XRX200_PCE_ISR_0_PINT_2, /* Port Interrupt */
2404 +// XRX200_PCE_ISR_0_PINT_1, /* Port Interrupt */
2405 +// XRX200_PCE_ISR_0_PINT_0, /* Port Interrupt */
2406 +// XRX200_PCE_ISR_1, /* Parser and ClassificationEngine Global Interrupt Status Register 1 */
2407 +// XRX200_PCE_ISR_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched */
2408 +// XRX200_PCE_ISR_1_CPH2, /* Classification Phase 2 Ready Interrupt */
2409 +// XRX200_PCE_ISR_1_CPH1, /* Classification Phase 1 Ready Interrupt */
2410 +// XRX200_PCE_ISR_1_CPH0, /* Classification Phase 0 Ready Interrupt */
2411 +// XRX200_PCE_ISR_1_PRDY, /* Parser Ready Interrupt */
2412 +// XRX200_PCE_ISR_1_IGTF, /* IGMP Table Full Interrupt */
2413 +// XRX200_PCE_ISR_1_MTF, /* MAC Table Full Interrupt */
2414 +// XRX200_PARSER_STAT_FIFO, /* Parser Status Register */
2415 +// XRX200_PARSER_STAT_FSM_DAT_CNT, /* Parser FSM Data Counter */
2416 +// XRX200_PARSER_STAT_FSM_STATE, /* Parser FSM State */
2417 +// XRX200_PARSER_STAT_PKT_ERR, /* Packet error detected */
2418 +// XRX200_PARSER_STAT_FSM_FIN, /* Parser FSM finished */
2419 +// XRX200_PARSER_STAT_FSM_START, /* Parser FSM start */
2420 +// XRX200_PARSER_STAT_FIFO_RDY, /* Parser FIFO ready for read. */
2421 +// XRX200_PARSER_STAT_FIFO_FULL, /* Parser */
2422 +// XRX200_PCE_PCTRL_0, /* PCE Port ControlRegister 0 */
2423 +// XRX200_PCE_PCTRL_0_MCST, /* Multicast Forwarding Mode Selection */
2424 +// XRX200_PCE_PCTRL_0_EGSTEN, /* Table-based Egress Special Tag Enable */
2425 +// XRX200_PCE_PCTRL_0_IGSTEN, /* Ingress Special Tag Enable */
2426 +// XRX200_PCE_PCTRL_0_PCPEN, /* PCP Remarking Mode */
2427 +// XRX200_PCE_PCTRL_0_CLPEN, /* Class Remarking Mode */
2428 +// XRX200_PCE_PCTRL_0_DPEN, /* Drop Precedence Remarking Mode */
2429 +// XRX200_PCE_PCTRL_0_CMOD, /* Three-color Marker Color Mode */
2430 +// XRX200_PCE_PCTRL_0_VREP, /* VLAN Replacement Mode */
2431 + XRX200_PCE_PCTRL_0_TVM, /* Transparent VLAN Mode */
2432 +// XRX200_PCE_PCTRL_0_PLOCK, /* Port Locking Enable */
2433 +// XRX200_PCE_PCTRL_0_AGEDIS, /* Aging Disable */
2434 +// XRX200_PCE_PCTRL_0_PSTATE, /* Port State */
2435 +// XRX200_PCE_PCTRL_1, /* PCE Port ControlRegister 1 */
2436 +// XRX200_PCE_PCTRL_1_LRNLIM, /* MAC Address Learning Limit */
2437 +// XRX200_PCE_PCTRL_2, /* PCE Port ControlRegister 2 */
2438 +// XRX200_PCE_PCTRL_2_DSCPMOD, /* DSCP Mode Selection */
2439 +// XRX200_PCE_PCTRL_2_DSCP, /* Enable DSCP to select the Class of Service */
2440 +// XRX200_PCE_PCTRL_2_PCP, /* Enable VLAN PCP to select the Class of Service */
2441 +// XRX200_PCE_PCTRL_2_PCLASS, /* Port-based Traffic Class */
2442 +// XRX200_PCE_PCTRL_3_VIO, /* PCE Port ControlRegister 3 */
2443 +// XRX200_PCE_PCTRL_3_EDIR, /* Egress Redirection Mode */
2444 +// XRX200_PCE_PCTRL_3_RXDMIR, /* Receive Mirroring Enable for dropped frames */
2445 +// XRX200_PCE_PCTRL_3_RXVMIR, /* Receive Mirroring Enable for valid frames */
2446 +// XRX200_PCE_PCTRL_3_TXMIR, /* Transmit Mirroring Enable */
2447 +// XRX200_PCE_PCTRL_3_VIO_7, /* Violation Type 7 Mirroring Enable */
2448 +// XRX200_PCE_PCTRL_3_VIO_6, /* Violation Type 6 Mirroring Enable */
2449 +// XRX200_PCE_PCTRL_3_VIO_5, /* Violation Type 5 Mirroring Enable */
2450 +// XRX200_PCE_PCTRL_3_VIO_4, /* Violation Type 4 Mirroring Enable */
2451 +// XRX200_PCE_PCTRL_3_VIO_3, /* Violation Type 3 Mirroring Enable */
2452 +// XRX200_PCE_PCTRL_3_VIO_2, /* Violation Type 2 Mirroring Enable */
2453 +// XRX200_PCE_PCTRL_3_VIO_1, /* Violation Type 1 Mirroring Enable */
2454 +// XRX200_PCE_PCTRL_3_VIO_0, /* Violation Type 0 Mirroring Enable */
2455 +// XRX200_WOL_CTRL, /* Wake-on-LAN ControlRegister */
2456 +// XRX200_WOL_CTRL_PORT, /* WoL Enable */
2457 +// XRX200_PCE_VCTRL, /* PCE VLAN ControlRegister */
2458 + XRX200_PCE_VCTRL_VSR, /* VLAN Security Rule */
2459 + XRX200_PCE_VCTRL_VEMR, /* VLAN Egress Member Violation Rule */
2460 + XRX200_PCE_VCTRL_VIMR, /* VLAN Ingress Member Violation Rule */
2461 + XRX200_PCE_VCTRL_VINR, /* VLAN Ingress Tag Rule */
2462 + XRX200_PCE_VCTRL_UVR, /* Unknown VLAN Rule */
2463 +// XRX200_PCE_DEFPVID, /* PCE Default PortVID Register */
2464 + XRX200_PCE_DEFPVID_PVID, /* Default Port VID Index */
2465 +// XRX200_PCE_PSTAT, /* PCE Port StatusRegister */
2466 +// XRX200_PCE_PSTAT_LRNCNT, /* Learning Count */
2467 +// XRX200_PCE_PIER, /* Parser and ClassificationEngine Port Interrupt Enable Register */
2468 +// XRX200_PCE_PIER_CLDRP, /* Classification Drop Interrupt Enable */
2469 +// XRX200_PCE_PIER_PTDRP, /* Port Drop Interrupt Enable */
2470 +// XRX200_PCE_PIER_VLAN, /* VLAN Violation Interrupt Enable */
2471 +// XRX200_PCE_PIER_WOL, /* Wake-on-LAN Interrupt Enable */
2472 +// XRX200_PCE_PIER_LOCK, /* Port Limit Alert Interrupt Enable */
2473 +// XRX200_PCE_PIER_LIM, /* Port Lock Alert Interrupt Enable */
2474 +// XRX200_PCE_PISR, /* Parser and ClassificationEngine Port Interrupt Status Register */
2475 +// XRX200_PCE_PISR_CLDRP, /* Classification Drop Interrupt */
2476 +// XRX200_PCE_PISR_PTDRP, /* Port Drop Interrupt */
2477 +// XRX200_PCE_PISR_VLAN, /* VLAN Violation Interrupt */
2478 +// XRX200_PCE_PISR_WOL, /* Wake-on-LAN Interrupt */
2479 +// XRX200_PCE_PISR_LOCK, /* Port Lock Alert Interrupt */
2480 +// XRX200_PCE_PISR_LIMIT, /* Port Limitation Alert Interrupt */
2481 +// XRX200_PCE_TCM_CTRL, /* Three-colorMarker Control Register */
2482 +// XRX200_PCE_TCM_CTRL_TCMEN, /* Three-color Marker metering instance enable */
2483 +// XRX200_PCE_TCM_STAT, /* Three-colorMarker Status Register */
2484 +// XRX200_PCE_TCM_STAT_AL1, /* Three-color Marker Alert 1 Status */
2485 +// XRX200_PCE_TCM_STAT_AL0, /* Three-color Marker Alert 0 Status */
2486 +// XRX200_PCE_TCM_CBS, /* Three-color MarkerCommitted Burst Size Register */
2487 +// XRX200_PCE_TCM_CBS_CBS, /* Committed Burst Size */
2488 +// XRX200_PCE_TCM_EBS, /* Three-color MarkerExcess Burst Size Register */
2489 +// XRX200_PCE_TCM_EBS_EBS, /* Excess Burst Size */
2490 +// XRX200_PCE_TCM_IBS, /* Three-color MarkerInstantaneous Burst Size Register */
2491 +// XRX200_PCE_TCM_IBS_IBS, /* Instantaneous Burst Size */
2492 +// XRX200_PCE_TCM_CIR_MANT, /* Three-colorMarker Constant Information Rate Mantissa Register */
2493 +// XRX200_PCE_TCM_CIR_MANT_MANT, /* Rate Counter Mantissa */
2494 +// XRX200_PCE_TCM_CIR_EXP, /* Three-colorMarker Constant Information Rate Exponent Register */
2495 +// XRX200_PCE_TCM_CIR_EXP_EXP, /* Rate Counter Exponent */
2496 +// XRX200_MAC_TEST, /* MAC Test Register */
2497 +// XRX200_MAC_TEST_JTP, /* Jitter Test Pattern */
2498 +// XRX200_MAC_PFAD_CFG, /* MAC Pause FrameSource Address Configuration Register */
2499 +// XRX200_MAC_PFAD_CFG_SAMOD, /* Source Address Mode */
2500 +// XRX200_MAC_PFSA_0, /* Pause Frame SourceAddress Part 0 */
2501 +// XRX200_MAC_PFSA_0_PFAD, /* Pause Frame Source Address Part 0 */
2502 +// XRX200_MAC_PFSA_1, /* Pause Frame SourceAddress Part 1 */
2503 +// XRX200_MAC_PFSA_1_PFAD, /* Pause Frame Source Address Part 1 */
2504 +// XRX200_MAC_PFSA_2, /* Pause Frame SourceAddress Part 2 */
2505 +// XRX200_MAC_PFSA_2_PFAD, /* Pause Frame Source Address Part 2 */
2506 +// XRX200_MAC_FLEN, /* MAC Frame Length Register */
2507 +// XRX200_MAC_FLEN_LEN, /* Maximum Frame Length */
2508 +// XRX200_MAC_VLAN_ETYPE_0, /* MAC VLAN EthertypeRegister 0 */
2509 +// XRX200_MAC_VLAN_ETYPE_0_OUTER, /* Ethertype */
2510 +// XRX200_MAC_VLAN_ETYPE_1, /* MAC VLAN EthertypeRegister 1 */
2511 +// XRX200_MAC_VLAN_ETYPE_1_INNER, /* Ethertype */
2512 +// XRX200_MAC_IER, /* MAC Interrupt EnableRegister */
2513 +// XRX200_MAC_IER_MACIEN, /* MAC Interrupt Enable */
2514 +// XRX200_MAC_ISR, /* MAC Interrupt StatusRegister */
2515 +// XRX200_MAC_ISR_MACINT, /* MAC Interrupt */
2516 +// XRX200_MAC_PSTAT, /* MAC Port Status Register */
2517 +// XRX200_MAC_PSTAT_PACT, /* PHY Active Status */
2518 + XRX200_MAC_PSTAT_GBIT, /* Gigabit Speed Status */
2519 + XRX200_MAC_PSTAT_MBIT, /* Megabit Speed Status */
2520 + XRX200_MAC_PSTAT_FDUP, /* Full Duplex Status */
2521 +// XRX200_MAC_PSTAT_RXPAU, /* Receive Pause Status */
2522 +// XRX200_MAC_PSTAT_TXPAU, /* Transmit Pause Status */
2523 +// XRX200_MAC_PSTAT_RXPAUEN, /* Receive Pause Enable Status */
2524 +// XRX200_MAC_PSTAT_TXPAUEN, /* Transmit Pause Enable Status */
2525 + XRX200_MAC_PSTAT_LSTAT, /* Link Status */
2526 +// XRX200_MAC_PSTAT_CRS, /* Carrier Sense Status */
2527 +// XRX200_MAC_PSTAT_TXLPI, /* Transmit Low-power Idle Status */
2528 +// XRX200_MAC_PSTAT_RXLPI, /* Receive Low-power Idle Status */
2529 +// XRX200_MAC_PISR, /* MAC Interrupt Status Register */
2530 +// XRX200_MAC_PISR_PACT, /* PHY Active Status */
2531 +// XRX200_MAC_PISR_SPEED, /* Megabit Speed Status */
2532 +// XRX200_MAC_PISR_FDUP, /* Full Duplex Status */
2533 +// XRX200_MAC_PISR_RXPAUEN, /* Receive Pause Enable Status */
2534 +// XRX200_MAC_PISR_TXPAUEN, /* Transmit Pause Enable Status */
2535 +// XRX200_MAC_PISR_LPIOFF, /* Receive Low-power Idle Mode is left */
2536 +// XRX200_MAC_PISR_LPION, /* Receive Low-power Idle Mode is entered */
2537 +// XRX200_MAC_PISR_JAM, /* Jam Status Detected */
2538 +// XRX200_MAC_PISR_TOOSHORT, /* Too Short Frame Error Detected */
2539 +// XRX200_MAC_PISR_TOOLONG, /* Too Long Frame Error Detected */
2540 +// XRX200_MAC_PISR_LENERR, /* Length Mismatch Error Detected */
2541 +// XRX200_MAC_PISR_FCSERR, /* Frame Checksum Error Detected */
2542 +// XRX200_MAC_PISR_TXPAUSE, /* Pause Frame Transmitted */
2543 +// XRX200_MAC_PISR_RXPAUSE, /* Pause Frame Received */
2544 +// XRX200_MAC_PIER, /* MAC Interrupt Enable Register */
2545 +// XRX200_MAC_PIER_PACT, /* PHY Active Status */
2546 +// XRX200_MAC_PIER_SPEED, /* Megabit Speed Status */
2547 +// XRX200_MAC_PIER_FDUP, /* Full Duplex Status */
2548 +// XRX200_MAC_PIER_RXPAUEN, /* Receive Pause Enable Status */
2549 +// XRX200_MAC_PIER_TXPAUEN, /* Transmit Pause Enable Status */
2550 +// XRX200_MAC_PIER_LPIOFF, /* Low-power Idle Off Interrupt Mask */
2551 +// XRX200_MAC_PIER_LPION, /* Low-power Idle On Interrupt Mask */
2552 +// XRX200_MAC_PIER_JAM, /* Jam Status Interrupt Mask */
2553 +// XRX200_MAC_PIER_TOOSHORT, /* Too Short Frame Error Interrupt Mask */
2554 +// XRX200_MAC_PIER_TOOLONG, /* Too Long Frame Error Interrupt Mask */
2555 +// XRX200_MAC_PIER_LENERR, /* Length Mismatch Error Interrupt Mask */
2556 +// XRX200_MAC_PIER_FCSERR, /* Frame Checksum Error Interrupt Mask */
2557 +// XRX200_MAC_PIER_TXPAUSE, /* Transmit Pause Frame Interrupt Mask */
2558 +// XRX200_MAC_PIER_RXPAUSE, /* Receive Pause Frame Interrupt Mask */
2559 +// XRX200_MAC_CTRL_0, /* MAC Control Register0 */
2560 +// XRX200_MAC_CTRL_0_LCOL, /* Late Collision Control */
2561 +// XRX200_MAC_CTRL_0_BM, /* Burst Mode Control */
2562 +// XRX200_MAC_CTRL_0_APADEN, /* Automatic VLAN Padding Enable */
2563 +// XRX200_MAC_CTRL_0_VPAD2EN, /* Stacked VLAN Padding Enable */
2564 +// XRX200_MAC_CTRL_0_VPADEN, /* VLAN Padding Enable */
2565 +// XRX200_MAC_CTRL_0_PADEN, /* Padding Enable */
2566 +// XRX200_MAC_CTRL_0_FCS, /* Transmit FCS Control */
2567 + XRX200_MAC_CTRL_0_FCON, /* Flow Control Mode */
2568 +// XRX200_MAC_CTRL_0_FDUP, /* Full Duplex Control */
2569 +// XRX200_MAC_CTRL_0_GMII, /* GMII/MII interface mode selection */
2570 +// XRX200_MAC_CTRL_1, /* MAC Control Register1 */
2571 +// XRX200_MAC_CTRL_1_SHORTPRE, /* Short Preamble Control */
2572 +// XRX200_MAC_CTRL_1_IPG, /* Minimum Inter Packet Gap Size */
2573 +// XRX200_MAC_CTRL_2, /* MAC Control Register2 */
2574 +// XRX200_MAC_CTRL_2_MLEN, /* Maximum Untagged Frame Length */
2575 +// XRX200_MAC_CTRL_2_LCHKL, /* Frame Length Check Long Enable */
2576 +// XRX200_MAC_CTRL_2_LCHKS, /* Frame Length Check Short Enable */
2577 +// XRX200_MAC_CTRL_3, /* MAC Control Register3 */
2578 +// XRX200_MAC_CTRL_3_RCNT, /* Retry Count */
2579 +// XRX200_MAC_CTRL_4, /* MAC Control Register4 */
2580 +// XRX200_MAC_CTRL_4_LPIEN, /* LPI Mode Enable */
2581 +// XRX200_MAC_CTRL_4_WAIT, /* LPI Wait Time */
2582 +// XRX200_MAC_CTRL_5_PJPS, /* MAC Control Register5 */
2583 +// XRX200_MAC_CTRL_5_PJPS_NOBP, /* Prolonged Jam pattern size during no-backpressure state */
2584 +// XRX200_MAC_CTRL_5_PJPS_BP, /* Prolonged Jam pattern size during backpressure state */
2585 +// XRX200_MAC_CTRL_6_XBUF, /* Transmit and ReceiveBuffer Control Register */
2586 +// XRX200_MAC_CTRL_6_RBUF_DLY_WP, /* Delay */
2587 +// XRX200_MAC_CTRL_6_RBUF_INIT, /* Receive Buffer Initialization */
2588 +// XRX200_MAC_CTRL_6_RBUF_BYPASS, /* Bypass the Receive Buffer */
2589 +// XRX200_MAC_CTRL_6_XBUF_DLY_WP, /* Delay */
2590 +// XRX200_MAC_CTRL_6_XBUF_INIT, /* Initialize the Transmit Buffer */
2591 +// XRX200_MAC_CTRL_6_XBUF_BYPASS, /* Bypass the Transmit Buffer */
2592 +// XRX200_MAC_BUFST_XBUF, /* MAC Receive and TransmitBuffer Status Register */
2593 +// XRX200_MAC_BUFST_RBUF_UFL, /* Receive Buffer Underflow Indicator */
2594 +// XRX200_MAC_BUFST_RBUF_OFL, /* Receive Buffer Overflow Indicator */
2595 +// XRX200_MAC_BUFST_XBUF_UFL, /* Transmit Buffer Underflow Indicator */
2596 +// XRX200_MAC_BUFST_XBUF_OFL, /* Transmit Buffer Overflow Indicator */
2597 +// XRX200_MAC_TESTEN, /* MAC Test Enable Register */
2598 +// XRX200_MAC_TESTEN_JTEN, /* Jitter Test Enable */
2599 +// XRX200_MAC_TESTEN_TXER, /* Transmit Error Insertion */
2600 +// XRX200_MAC_TESTEN_LOOP, /* MAC Loopback Enable */
2601 +// XRX200_FDMA_CTRL, /* Ethernet Switch FetchDMA Control Register */
2602 +// XRX200_FDMA_CTRL_LPI_THRESHOLD, /* Low Power Idle Threshold */
2603 +// XRX200_FDMA_CTRL_LPI_MODE, /* Low Power Idle Mode */
2604 +// XRX200_FDMA_CTRL_EGSTAG, /* Egress Special Tag Size */
2605 +// XRX200_FDMA_CTRL_IGSTAG, /* Ingress Special Tag Size */
2606 +// XRX200_FDMA_CTRL_EXCOL, /* Excessive Collision Handling */
2607 +// XRX200_FDMA_STETYPE, /* Special Tag EthertypeControl Register */
2608 +// XRX200_FDMA_STETYPE_ETYPE, /* Special Tag Ethertype */
2609 +// XRX200_FDMA_VTETYPE, /* VLAN Tag EthertypeControl Register */
2610 +// XRX200_FDMA_VTETYPE_ETYPE, /* VLAN Tag Ethertype */
2611 +// XRX200_FDMA_STAT_0, /* FDMA Status Register0 */
2612 +// XRX200_FDMA_STAT_0_FSMS, /* FSM states status */
2613 +// XRX200_FDMA_IER, /* Fetch DMA Global InterruptEnable Register */
2614 +// XRX200_FDMA_IER_PCKD, /* Packet Drop Interrupt Enable */
2615 +// XRX200_FDMA_IER_PCKR, /* Packet Ready Interrupt Enable */
2616 +// XRX200_FDMA_IER_PCKT, /* Packet Sent Interrupt Enable */
2617 +// XRX200_FDMA_ISR, /* Fetch DMA Global InterruptStatus Register */
2618 +// XRX200_FDMA_ISR_PCKTD, /* Packet Drop */
2619 +// XRX200_FDMA_ISR_PCKR, /* Packet is Ready for Transmission */
2620 +// XRX200_FDMA_ISR_PCKT, /* Packet Sent Event */
2621 +// XRX200_FDMA_PCTRL, /* Ethernet SwitchFetch DMA Port Control Register */
2622 +// XRX200_FDMA_PCTRL_VLANMOD, /* VLAN Modification Enable */
2623 +// XRX200_FDMA_PCTRL_DSCPRM, /* DSCP Re-marking Enable */
2624 +// XRX200_FDMA_PCTRL_STEN, /* Special Tag Insertion Enable */
2625 +// XRX200_FDMA_PCTRL_EN, /* FDMA Port Enable */
2626 +// XRX200_FDMA_PRIO, /* Ethernet SwitchFetch DMA Port Priority Register */
2627 +// XRX200_FDMA_PRIO_PRIO, /* FDMA PRIO */
2628 +// XRX200_FDMA_PSTAT0, /* Ethernet SwitchFetch DMA Port Status Register 0 */
2629 +// XRX200_FDMA_PSTAT0_PKT_AVAIL, /* Port Egress Packet Available */
2630 +// XRX200_FDMA_PSTAT0_POK, /* Port Status OK */
2631 +// XRX200_FDMA_PSTAT0_PSEG, /* Port Egress Segment Count */
2632 +// XRX200_FDMA_PSTAT1_HDR, /* Ethernet SwitchFetch DMA Port Status Register 1 */
2633 +// XRX200_FDMA_PSTAT1_HDR_PTR, /* Header Pointer */
2634 +// XRX200_FDMA_TSTAMP0, /* Egress TimeStamp Register 0 */
2635 +// XRX200_FDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */
2636 +// XRX200_FDMA_TSTAMP1, /* Egress TimeStamp Register 1 */
2637 +// XRX200_FDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */
2638 +// XRX200_SDMA_CTRL, /* Ethernet Switch StoreDMA Control Register */
2639 +// XRX200_SDMA_CTRL_TSTEN, /* Time Stamp Enable */
2640 +// XRX200_SDMA_FCTHR1, /* SDMA Flow Control Threshold1 Register */
2641 +// XRX200_SDMA_FCTHR1_THR1, /* Threshold 1 */
2642 +// XRX200_SDMA_FCTHR2, /* SDMA Flow Control Threshold2 Register */
2643 +// XRX200_SDMA_FCTHR2_THR2, /* Threshold 2 */
2644 +// XRX200_SDMA_FCTHR3, /* SDMA Flow Control Threshold3 Register */
2645 +// XRX200_SDMA_FCTHR3_THR3, /* Threshold 3 */
2646 +// XRX200_SDMA_FCTHR4, /* SDMA Flow Control Threshold4 Register */
2647 +// XRX200_SDMA_FCTHR4_THR4, /* Threshold 4 */
2648 +// XRX200_SDMA_FCTHR5, /* SDMA Flow Control Threshold5 Register */
2649 +// XRX200_SDMA_FCTHR5_THR5, /* Threshold 5 */
2650 +// XRX200_SDMA_FCTHR6, /* SDMA Flow Control Threshold6 Register */
2651 +// XRX200_SDMA_FCTHR6_THR6, /* Threshold 6 */
2652 +// XRX200_SDMA_FCTHR7, /* SDMA Flow Control Threshold7 Register */
2653 +// XRX200_SDMA_FCTHR7_THR7, /* Threshold 7 */
2654 +// XRX200_SDMA_STAT_0, /* SDMA Status Register0 */
2655 +// XRX200_SDMA_STAT_0_BPS_FILL, /* Back Pressure Status */
2656 +// XRX200_SDMA_STAT_0_BPS_PNT, /* Back Pressure Status */
2657 +// XRX200_SDMA_STAT_0_DROP, /* Back Pressure Status */
2658 +// XRX200_SDMA_STAT_1, /* SDMA Status Register1 */
2659 +// XRX200_SDMA_STAT_1_FILL, /* Buffer Filling Level */
2660 +// XRX200_SDMA_STAT_2, /* SDMA Status Register2 */
2661 +// XRX200_SDMA_STAT_2_FSMS, /* FSM states status */
2662 +// XRX200_SDMA_IER, /* SDMA Interrupt Enable Register */
2663 +// XRX200_SDMA_IER_BPEX, /* Buffer Pointers Exceeded */
2664 +// XRX200_SDMA_IER_BFULL, /* Buffer Full */
2665 +// XRX200_SDMA_IER_FERR, /* Frame Error */
2666 +// XRX200_SDMA_IER_FRX, /* Frame Received Successfully */
2667 +// XRX200_SDMA_ISR, /* SDMA Interrupt Status Register */
2668 +// XRX200_SDMA_ISR_BPEX, /* Packet Descriptors Exceeded */
2669 +// XRX200_SDMA_ISR_BFULL, /* Buffer Full */
2670 +// XRX200_SDMA_ISR_FERR, /* Frame Error */
2671 +// XRX200_SDMA_ISR_FRX, /* Frame Received Successfully */
2672 +// XRX200_SDMA_PCTRL, /* Ethernet SwitchStore DMA Port Control Register */
2673 +// XRX200_SDMA_PCTRL_DTHR, /* Drop Threshold Selection */
2674 +// XRX200_SDMA_PCTRL_PTHR, /* Pause Threshold Selection */
2675 +// XRX200_SDMA_PCTRL_PHYEFWD, /* Forward PHY Error Frames */
2676 +// XRX200_SDMA_PCTRL_ALGFWD, /* Forward Alignment Error Frames */
2677 +// XRX200_SDMA_PCTRL_LENFWD, /* Forward Length Errored Frames */
2678 +// XRX200_SDMA_PCTRL_OSFWD, /* Forward Oversized Frames */
2679 +// XRX200_SDMA_PCTRL_USFWD, /* Forward Undersized Frames */
2680 +// XRX200_SDMA_PCTRL_FCSIGN, /* Ignore FCS Errors */
2681 +// XRX200_SDMA_PCTRL_FCSFWD, /* Forward FCS Errored Frames */
2682 +// XRX200_SDMA_PCTRL_PAUFWD, /* Pause Frame Forwarding */
2683 +// XRX200_SDMA_PCTRL_MFCEN, /* Metering Flow Control Enable */
2684 +// XRX200_SDMA_PCTRL_FCEN, /* Flow Control Enable */
2685 +// XRX200_SDMA_PCTRL_PEN, /* Port Enable */
2686 +// XRX200_SDMA_PRIO, /* Ethernet SwitchStore DMA Port Priority Register */
2687 +// XRX200_SDMA_PRIO_PRIO, /* SDMA PRIO */
2688 +// XRX200_SDMA_PSTAT0_HDR, /* Ethernet SwitchStore DMA Port Status Register 0 */
2689 +// XRX200_SDMA_PSTAT0_HDR_PTR, /* Port Ingress Queue Header Pointer */
2690 +// XRX200_SDMA_PSTAT1, /* Ethernet SwitchStore DMA Port Status Register 1 */
2691 +// XRX200_SDMA_PSTAT1_PPKT, /* Port Ingress Packet Count */
2692 +// XRX200_SDMA_TSTAMP0, /* Ingress TimeStamp Register 0 */
2693 +// XRX200_SDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */
2694 +// XRX200_SDMA_TSTAMP1, /* Ingress TimeStamp Register 1 */
2695 +// XRX200_SDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */
2696 +};
2697 +
2698 +
2699 +struct xrx200sw_reg {
2700 + int offset;
2701 + int shift;
2702 + int size;
2703 + int mult;
2704 +} xrx200sw_reg[] = {
2705 +// offeset shift size mult
2706 +// {0x0000, 0, 16, 0x00}, /* XRX200_ETHSW_SWRES Ethernet Switch ResetControl Register */
2707 +// {0x0000, 1, 1, 0x00}, /* XRX200_ETHSW_SWRES_R1 Hardware Reset */
2708 +// {0x0000, 0, 1, 0x00}, /* XRX200_ETHSW_SWRES_R0 Register Configuration */
2709 +// {0x0004, 0, 16, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT Ethernet Switch Clock ControlRegister */
2710 +// {0x0004, 12, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_SLEEP Exponent to put system into sleep */
2711 +// {0x0004, 8, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_WAKE Exponent to wake up system */
2712 +// {0x0004, 7, 1, 0x00}, /* XRX200_ETHSW_CLK_CLK2_EN CLK2 Input for MAC */
2713 +// {0x0004, 6, 1, 0x00}, /* XRX200_ETHSW_CLK_EXT_DIV_EN External Clock Divider Enable */
2714 +// {0x0004, 5, 1, 0x00}, /* XRX200_ETHSW_CLK_RAM_DBG_EN Clock Gating Enable */
2715 +// {0x0004, 4, 1, 0x00}, /* XRX200_ETHSW_CLK_REG_GAT_EN Clock Gating Enable */
2716 +// {0x0004, 3, 1, 0x00}, /* XRX200_ETHSW_CLK_GAT_EN Clock Gating Enable */
2717 +// {0x0004, 2, 1, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT_EN Clock Gating Enable */
2718 +// {0x0008, 0, 16, 0x00}, /* XRX200_ETHSW_DBG_STEP Ethernet Switch Debug ControlRegister */
2719 +// {0x0008, 12, 4, 0x00}, /* XRX200_ETHSW_DBG_CLK_SEL Trigger Enable */
2720 +// {0x0008, 11, 1, 0x00}, /* XRX200_ETHSW_DBG_MON_EN Monitoring Enable */
2721 +// {0x0008, 9, 2, 0x00}, /* XRX200_ETHSW_DBG_TRIG_EN Trigger Enable */
2722 +// {0x0008, 8, 1, 0x00}, /* XRX200_ETHSW_DBG_MODE Debug Mode */
2723 +// {0x0008, 0, 8, 0x00}, /* XRX200_ETHSW_DBG_STEP_TIME Clock Step Size */
2724 +// {0x000C, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_MODE Ethernet Switch SharedSegment Buffer Mode Register */
2725 +// {0x000C, 2, 4, 0x00}, /* XRX200_ETHSW_SSB_MODE_ADDE Memory Address */
2726 +// {0x000C, 0, 2, 0x00}, /* XRX200_ETHSW_SSB_MODE_MODE Memory Access Mode */
2727 +// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR Ethernet Switch SharedSegment Buffer Address Register */
2728 +// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR_ADDE Memory Address */
2729 +// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA Ethernet Switch SharedSegment Buffer Data Register */
2730 +// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA_DATA Data Value */
2731 +// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0 Ethernet Switch CapabilityRegister 0 */
2732 +// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0_SPEED Clock frequency */
2733 +// {0x001C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_1 Ethernet Switch CapabilityRegister 1 */
2734 +// {0x001C, 15, 1, 0x00}, /* XRX200_ETHSW_CAP_1_GMAC MAC operation mode */
2735 +// {0x001C, 8, 7, 0x00}, /* XRX200_ETHSW_CAP_1_QUEUE Number of queues */
2736 +// {0x001C, 4, 4, 0x00}, /* XRX200_ETHSW_CAP_1_VPORTS Number of virtual ports */
2737 +// {0x001C, 0, 4, 0x00}, /* XRX200_ETHSW_CAP_1_PPORTS Number of physical ports */
2738 +// {0x0020, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_2 Ethernet Switch CapabilityRegister 2 */
2739 +// {0x0020, 0, 11, 0x00}, /* XRX200_ETHSW_CAP_2_PACKETS Number of packets */
2740 +// {0x0024, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_3 Ethernet Switch CapabilityRegister 3 */
2741 +// {0x0024, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_3_METERS Number of traffic meters */
2742 +// {0x0024, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_3_SHAPERS Number of traffic shapers */
2743 +// {0x0028, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_4 Ethernet Switch CapabilityRegister 4 */
2744 +// {0x0028, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_4_PPPOE PPPoE table size */
2745 +// {0x0028, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_4_VLAN Active VLAN table size */
2746 +// {0x002C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_5 Ethernet Switch CapabilityRegister 5 */
2747 +// {0x002C, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_5_IPPLEN IP packet length table size */
2748 +// {0x002C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_5_PROT Protocol table size */
2749 +// {0x0030, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_6 Ethernet Switch CapabilityRegister 6 */
2750 +// {0x0030, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_6_MACDASA MAC DA/SA table size */
2751 +// {0x0030, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_6_APPL Application table size */
2752 +// {0x0034, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_7 Ethernet Switch CapabilityRegister 7 */
2753 +// {0x0034, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAM IP DA/SA MSB table size */
2754 +// {0x0034, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAL IP DA/SA LSB table size */
2755 +// {0x0038, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_8 Ethernet Switch CapabilityRegister 8 */
2756 +// {0x0038, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_8_MCAST Multicast table size */
2757 +// {0x003C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_9 Ethernet Switch CapabilityRegister 9 */
2758 +// {0x003C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_9_FLAGG Flow Aggregation table size */
2759 +// {0x0040, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_10 Ethernet Switch CapabilityRegister 10 */
2760 +// {0x0040, 0, 13, 0x00}, /* XRX200_ETHSW_CAP_10_MACBT MAC bridging table size */
2761 +// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11 Ethernet Switch CapabilityRegister 11 */
2762 +// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11_BSIZEL Packet buffer size (lower part, in byte) */
2763 +// {0x0048, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_12 Ethernet Switch CapabilityRegister 12 */
2764 +// {0x0048, 0, 3, 0x00}, /* XRX200_ETHSW_CAP_12_BSIZEH Packet buffer size (higher part, in byte) */
2765 +// {0x004C, 0, 16, 0x00}, /* XRX200_ETHSW_VERSION_REV Ethernet Switch VersionRegister */
2766 +// {0x004C, 8, 8, 0x00}, /* XRX200_ETHSW_VERSION_MOD_ID Module Identification */
2767 +// {0x004C, 0, 8, 0x00}, /* XRX200_ETHSW_VERSION_REV_ID Hardware Revision Identification */
2768 +// {0x0050, 0, 16, 0x00}, /* XRX200_ETHSW_IER Interrupt Enable Register */
2769 +// {0x0050, 4, 1, 0x00}, /* XRX200_ETHSW_IER_FDMAIE Fetch DMA Interrupt Enable */
2770 +// {0x0050, 3, 1, 0x00}, /* XRX200_ETHSW_IER_SDMAIE Store DMA Interrupt Enable */
2771 +// {0x0050, 2, 1, 0x00}, /* XRX200_ETHSW_IER_MACIE Ethernet MAC Interrupt Enable */
2772 +// {0x0050, 1, 1, 0x00}, /* XRX200_ETHSW_IER_PCEIE Parser and Classification Engine Interrupt Enable */
2773 +// {0x0050, 0, 1, 0x00}, /* XRX200_ETHSW_IER_BMIE Buffer Manager Interrupt Enable */
2774 +// {0x0054, 0, 16, 0x00}, /* XRX200_ETHSW_ISR Interrupt Status Register */
2775 +// {0x0054, 4, 1, 0x00}, /* XRX200_ETHSW_ISR_FDMAINT Fetch DMA Interrupt */
2776 +// {0x0054, 3, 1, 0x00}, /* XRX200_ETHSW_ISR_SDMAINT Store DMA Interrupt */
2777 +// {0x0054, 2, 1, 0x00}, /* XRX200_ETHSW_ISR_MACINT Ethernet MAC Interrupt */
2778 +// {0x0054, 1, 1, 0x00}, /* XRX200_ETHSW_ISR_PCEINT Parser and Classification Engine Interrupt */
2779 +// {0x0054, 0, 1, 0x00}, /* XRX200_ETHSW_ISR_BMINT Buffer Manager Interrupt */
2780 +// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0 Ethernet Switch SpareCells 0 */
2781 +// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0_SPARE SPARE0 */
2782 +// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1 Ethernet Switch SpareCells 1 */
2783 +// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1_SPARE SPARE1 */
2784 +// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2 Ethernet Switch SpareCells 2 */
2785 +// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2_SPARE SPARE2 */
2786 +// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3 Ethernet Switch SpareCells 3 */
2787 +// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3_SPARE SPARE3 */
2788 +// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4 Ethernet Switch SpareCells 4 */
2789 +// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4_SPARE SPARE4 */
2790 +// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5 Ethernet Switch SpareCells 5 */
2791 +// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5_SPARE SPARE5 */
2792 +// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6 Ethernet Switch SpareCells 6 */
2793 +// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6_SPARE SPARE6 */
2794 +// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7 Ethernet Switch SpareCells 7 */
2795 +// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7_SPARE SPARE7 */
2796 +// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8 Ethernet Switch SpareCells 8 */
2797 +// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8_SPARE SPARE8 */
2798 +// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9 Ethernet Switch SpareCells 9 */
2799 +// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9_SPARE SPARE9 */
2800 +// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10 Ethernet Switch SpareCells 10 */
2801 +// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10_SPARE SPARE10 */
2802 +// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11 Ethernet Switch SpareCells 11 */
2803 +// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11_SPARE SPARE11 */
2804 +// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12 Ethernet Switch SpareCells 12 */
2805 +// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12_SPARE SPARE12 */
2806 +// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13 Ethernet Switch SpareCells 13 */
2807 +// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13_SPARE SPARE13 */
2808 +// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14 Ethernet Switch SpareCells 14 */
2809 +// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14_SPARE SPARE14 */
2810 +// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15 Ethernet Switch SpareCells 15 */
2811 +// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15_SPARE SPARE15 */
2812 +// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3 RAM Value Register 3 */
2813 +// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3_VAL3 Data value [15:0] */
2814 +// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2 RAM Value Register 2 */
2815 +// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2_VAL2 Data value [15:0] */
2816 +// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1 RAM Value Register 1 */
2817 +// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1_VAL1 Data value [15:0] */
2818 +// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0 RAM Value Register 0 */
2819 +// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0_VAL0 Data value [15:0] */
2820 +// {0x0110, 0, 16, 0x00}, /* XRX200_BM_RAM_ADDR RAM Address Register */
2821 +// {0x0110, 0, 11, 0x00}, /* XRX200_BM_RAM_ADDR_ADDR RAM Address */
2822 +// {0x0114, 0, 16, 0x00}, /* XRX200_BM_RAM_CTRL RAM Access Control Register */
2823 +// {0x0114, 15, 1, 0x00}, /* XRX200_BM_RAM_CTRL_BAS Access Busy/Access Start */
2824 +// {0x0114, 5, 1, 0x00}, /* XRX200_BM_RAM_CTRL_OPMOD Lookup Table Access Operation Mode */
2825 +// {0x0114, 0, 5, 0x00}, /* XRX200_BM_RAM_CTRL_ADDR Address for RAM selection */
2826 +// {0x0118, 0, 16, 0x00}, /* XRX200_BM_FSQM_GCTRL Free Segment Queue ManagerGlobal Control Register */
2827 +// {0x0118, 0, 10, 0x00}, /* XRX200_BM_FSQM_GCTRL_SEGNUM Maximum Segment Number */
2828 +// {0x011C, 0, 16, 0x00}, /* XRX200_BM_CONS_SEG Number of Consumed SegmentsRegister */
2829 +// {0x011C, 0, 10, 0x00}, /* XRX200_BM_CONS_SEG_FSEG Number of Consumed Segments */
2830 +// {0x0120, 0, 16, 0x00}, /* XRX200_BM_CONS_PKT Number of Consumed PacketPointers Register */
2831 +// {0x0120, 0, 11, 0x00}, /* XRX200_BM_CONS_PKT_FQP Number of Consumed Packet Pointers */
2832 +// {0x0124, 0, 16, 0x00}, /* XRX200_BM_GCTRL_F Buffer Manager Global ControlRegister 0 */
2833 +// {0x0124, 13, 1, 0x00}, /* XRX200_BM_GCTRL_BM_STA Buffer Manager Initialization Status Bit */
2834 +// {0x0124, 12, 1, 0x00}, /* XRX200_BM_GCTRL_SAT RMON Counter Update Mode */
2835 +// {0x0124, 11, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RBC Freeze RMON RX Bad Byte 64 Bit Counter */
2836 +// {0x0124, 10, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RGC Freeze RMON RX Good Byte 64 Bit Counter */
2837 +// {0x0124, 9, 1, 0x00}, /* XRX200_BM_GCTRL_FR_TGC Freeze RMON TX Good Byte 64 Bit Counter */
2838 +// {0x0124, 8, 1, 0x00}, /* XRX200_BM_GCTRL_I_FIN RAM initialization finished */
2839 +// {0x0124, 7, 1, 0x00}, /* XRX200_BM_GCTRL_CX_INI PQM Context RAM initialization */
2840 +// {0x0124, 6, 1, 0x00}, /* XRX200_BM_GCTRL_FP_INI FPQM RAM initialization */
2841 +// {0x0124, 5, 1, 0x00}, /* XRX200_BM_GCTRL_FS_INI FSQM RAM initialization */
2842 +// {0x0124, 4, 1, 0x00}, /* XRX200_BM_GCTRL_R_SRES Software Reset for RMON */
2843 +// {0x0124, 3, 1, 0x00}, /* XRX200_BM_GCTRL_S_SRES Software Reset for Scheduler */
2844 +// {0x0124, 2, 1, 0x00}, /* XRX200_BM_GCTRL_A_SRES Software Reset for AVG */
2845 +// {0x0124, 1, 1, 0x00}, /* XRX200_BM_GCTRL_P_SRES Software Reset for PQM */
2846 +// {0x0124, 0, 1, 0x00}, /* XRX200_BM_GCTRL_F_SRES Software Reset for FSQM */
2847 +// {0x0128, 0, 16, 0x00}, /* XRX200_BM_QUEUE_GCTRL Queue Manager GlobalControl Register 0 */
2848 +// {0x0128, 10, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_GL_MOD WRED Mode Signal */
2849 +// {0x0128, 7, 3, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQUI Average Queue Update Interval */
2850 +// {0x0128, 3, 4, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQWF Average Queue Weight Factor */
2851 +// {0x0128, 2, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_QAVGEN Queue Average Calculation Enable */
2852 +// {0x0128, 0, 2, 0x00}, /* XRX200_BM_QUEUE_GCTRL_DPROB Drop Probability Profile */
2853 +// {0x012C, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_0 WRED Red Threshold Register0 */
2854 +// {0x012C, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_0_MINTH Minimum Threshold */
2855 +// {0x0130, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_1 WRED Red Threshold Register1 */
2856 +// {0x0130, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_1_MAXTH Maximum Threshold */
2857 +// {0x0134, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_0 WRED Yellow ThresholdRegister 0 */
2858 +// {0x0134, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_0_MINTH Minimum Threshold */
2859 +// {0x0138, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_1 WRED Yellow ThresholdRegister 1 */
2860 +// {0x0138, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_1_MAXTH Maximum Threshold */
2861 +// {0x013C, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_0 WRED Green ThresholdRegister 0 */
2862 +// {0x013C, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_0_MINTH Minimum Threshold */
2863 +// {0x0140, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_1 WRED Green ThresholdRegister 1 */
2864 +// {0x0140, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_1_MAXTH Maximum Threshold */
2865 +// {0x0144, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_0_THR Drop Threshold ConfigurationRegister 0 */
2866 +// {0x0144, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_0_THR_FQ Threshold for frames marked red */
2867 +// {0x0148, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_1_THY Drop Threshold ConfigurationRegister 1 */
2868 +// {0x0148, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_1_THY_FQ Threshold for frames marked yellow */
2869 +// {0x014C, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_2_THG Drop Threshold ConfigurationRegister 2 */
2870 +// {0x014C, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_2_THG_FQ Threshold for frames marked green */
2871 +// {0x0150, 0, 16, 0x00}, /* XRX200_BM_IER Buffer Manager Global InterruptEnable Register */
2872 +// {0x0150, 7, 1, 0x00}, /* XRX200_BM_IER_CNT4 Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */
2873 +// {0x0150, 6, 1, 0x00}, /* XRX200_BM_IER_CNT3 Counter Group 3 (RMON-PQM) Interrupt Enable */
2874 +// {0x0150, 5, 1, 0x00}, /* XRX200_BM_IER_CNT2 Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */
2875 +// {0x0150, 4, 1, 0x00}, /* XRX200_BM_IER_CNT1 Counter Group 1 (RMON-QFETCH) Interrupt Enable */
2876 +// {0x0150, 3, 1, 0x00}, /* XRX200_BM_IER_CNT0 Counter Group 0 (RMON-QSTOR) Interrupt Enable */
2877 +// {0x0150, 2, 1, 0x00}, /* XRX200_BM_IER_DEQ PQM dequeue Interrupt Enable */
2878 +// {0x0150, 1, 1, 0x00}, /* XRX200_BM_IER_ENQ PQM Enqueue Interrupt Enable */
2879 +// {0x0150, 0, 1, 0x00}, /* XRX200_BM_IER_FSQM Buffer Empty Interrupt Enable */
2880 +// {0x0154, 0, 16, 0x00}, /* XRX200_BM_ISR Buffer Manager Global InterruptStatus Register */
2881 +// {0x0154, 7, 1, 0x00}, /* XRX200_BM_ISR_CNT4 Counter Group 4 Interrupt */
2882 +// {0x0154, 6, 1, 0x00}, /* XRX200_BM_ISR_CNT3 Counter Group 3 Interrupt */
2883 +// {0x0154, 5, 1, 0x00}, /* XRX200_BM_ISR_CNT2 Counter Group 2 Interrupt */
2884 +// {0x0154, 4, 1, 0x00}, /* XRX200_BM_ISR_CNT1 Counter Group 1 Interrupt */
2885 +// {0x0154, 3, 1, 0x00}, /* XRX200_BM_ISR_CNT0 Counter Group 0 Interrupt */
2886 +// {0x0154, 2, 1, 0x00}, /* XRX200_BM_ISR_DEQ PQM dequeue Interrupt Enable */
2887 +// {0x0154, 1, 1, 0x00}, /* XRX200_BM_ISR_ENQ PQM Enqueue Interrupt */
2888 +// {0x0154, 0, 1, 0x00}, /* XRX200_BM_ISR_FSQM Buffer Empty Interrupt */
2889 +// {0x0158, 0, 16, 0x00}, /* XRX200_BM_CISEL Buffer Manager RMON CounterInterrupt Select Register */
2890 +// {0x0158, 0, 3, 0x00}, /* XRX200_BM_CISEL_PORT Port Number */
2891 +// {0x015C, 0, 16, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG Debug Control Register */
2892 +// {0x015C, 0, 8, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG_SEL Select Signal for Debug Multiplexer */
2893 +// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG Debug Value Register */
2894 +// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG_DAT Debug Data Value */
2895 +// {0x0200, 0, 16, 0x08}, /* XRX200_BM_PCFG Buffer Manager PortConfiguration Register */
2896 +// {0x0200, 0, 1, 0x08}, /* XRX200_BM_PCFG_CNTEN RMON Counter Enable */
2897 +// {0x0204, 0, 16, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1 Buffer ManagerRMON Control Register */
2898 +// {0x0204, 1, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM2_RES Software Reset for RMON RAM2 */
2899 +// {0x0204, 0, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1_RES Software Reset for RMON RAM1 */
2900 +// {0x0400, 0, 16, 0x08}, /* XRX200_PQM_DP Packet Queue ManagerDrop Probability Register */
2901 +// {0x0400, 0, 2, 0x08}, /* XRX200_PQM_DP_DPROB Drop Probability Profile */
2902 +// {0x0404, 0, 16, 0x08}, /* XRX200_PQM_RS Packet Queue ManagerRate Shaper Assignment Register */
2903 +// {0x0404, 15, 1, 0x08}, /* XRX200_PQM_RS_EN2 Rate Shaper 2 Enable */
2904 +// {0x0404, 8, 6, 0x08}, /* XRX200_PQM_RS_RS2 Rate Shaper 2 */
2905 +// {0x0404, 7, 1, 0x08}, /* XRX200_PQM_RS_EN1 Rate Shaper 1 Enable */
2906 +// {0x0404, 0, 6, 0x08}, /* XRX200_PQM_RS_RS1 Rate Shaper 1 */
2907 +// {0x0500, 0, 16, 0x14}, /* XRX200_RS_CTRL Rate Shaper ControlRegister */
2908 +// {0x0500, 0, 1, 0x14}, /* XRX200_RS_CTRL_RSEN Rate Shaper Enable */
2909 +// {0x0504, 0, 16, 0x14}, /* XRX200_RS_CBS Rate Shaper CommittedBurst Size Register */
2910 +// {0x0504, 0, 10, 0x14}, /* XRX200_RS_CBS_CBS Committed Burst Size */
2911 +// {0x0508, 0, 16, 0x14}, /* XRX200_RS_IBS Rate Shaper InstantaneousBurst Size Register */
2912 +// {0x0508, 0, 2, 0x14}, /* XRX200_RS_IBS_IBS Instantaneous Burst Size */
2913 +// {0x050C, 0, 16, 0x14}, /* XRX200_RS_CIR_EXP Rate Shaper RateExponent Register */
2914 +// {0x050C, 0, 4, 0x14}, /* XRX200_RS_CIR_EXP_EXP Exponent */
2915 +// {0x0510, 0, 16, 0x14}, /* XRX200_RS_CIR_MANT Rate Shaper RateMantissa Register */
2916 +// {0x0510, 0, 10, 0x14}, /* XRX200_RS_CIR_MANT_MANT Mantissa */
2917 + {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7 Table Key Data 7 */
2918 +// {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7_KEY7 Key Value[15:0] */
2919 + {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6 Table Key Data 6 */
2920 +// {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6_KEY6 Key Value[15:0] */
2921 + {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5 Table Key Data 5 */
2922 +// {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5_KEY5 Key Value[15:0] */
2923 + {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4 Table Key Data 4 */
2924 +// {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4_KEY4 Key Value[15:0] */
2925 + {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3 Table Key Data 3 */
2926 +// {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3_KEY3 Key Value[15:0] */
2927 + {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2 Table Key Data 2 */
2928 +// {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2_KEY2 Key Value[15:0] */
2929 + {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1 Table Key Data 1 */
2930 +// {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1_KEY1 Key Value[31:16] */
2931 + {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0 Table Key Data 0 */
2932 +// {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0_KEY0 Key Value[15:0] */
2933 + {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0 Table Mask Write Register0 */
2934 +// {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0_MASK0 Mask Pattern [15:0] */
2935 + {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4 Table Value Register4 */
2936 +// {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4_VAL4 Data value [15:0] */
2937 + {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3 Table Value Register3 */
2938 +// {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3_VAL3 Data value [15:0] */
2939 + {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2 Table Value Register2 */
2940 +// {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2_VAL2 Data value [15:0] */
2941 + {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1 Table Value Register1 */
2942 +// {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1_VAL1 Data value [15:0] */
2943 + {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0 Table Value Register0 */
2944 +// {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0_VAL0 Data value [15:0] */
2945 +// {0x1138, 0, 16, 0x00}, /* XRX200_PCE_TBL_ADDR Table Entry AddressRegister */
2946 + {0x1138, 0, 11, 0x00}, /* XRX200_PCE_TBL_ADDR_ADDR Table Address */
2947 +// {0x113C, 0, 16, 0x00}, /* XRX200_PCE_TBL_CTRL Table Access ControlRegister */
2948 + {0x113C, 15, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_BAS Access Busy/Access Start */
2949 + {0x113C, 13, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_TYPE Lookup Entry Type */
2950 + {0x113C, 12, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_VLD Lookup Entry Valid */
2951 + {0x113C, 7, 4, 0x00}, /* XRX200_PCE_TBL_CTRL_GMAP Group Map */
2952 + {0x113C, 5, 2, 0x00}, /* XRX200_PCE_TBL_CTRL_OPMOD Lookup Table Access Operation Mode */
2953 + {0x113C, 0, 5, 0x00}, /* XRX200_PCE_TBL_CTRL_ADDR Lookup Table Address */
2954 +// {0x1140, 0, 16, 0x00}, /* XRX200_PCE_TBL_STAT Table General StatusRegister */
2955 +// {0x1140, 2, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TBUSY Table Access Busy */
2956 +// {0x1140, 1, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TEMPT Table Empty */
2957 +// {0x1140, 0, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TFUL Table Full */
2958 +// {0x1144, 0, 16, 0x00}, /* XRX200_PCE_AGE_0 Aging Counter ConfigurationRegister 0 */
2959 +// {0x1144, 0, 4, 0x00}, /* XRX200_PCE_AGE_0_EXP Aging Counter Exponent Value */
2960 +// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1 Aging Counter ConfigurationRegister 1 */
2961 +// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1_MANT Aging Counter Mantissa Value */
2962 +// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1 Port Map Register 1 */
2963 +// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1_MPMAP Monitoring Port Map */
2964 +// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2 Port Map Register 2 */
2965 +// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2_DMCPMAP Default Multicast Port Map */
2966 +// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3 Port Map Register 3 */
2967 +// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3_UUCMAP Default Unknown Unicast Port Map */
2968 +// {0x1158, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_0 PCE Global Control Register0 */
2969 +// {0x1158, 15, 1, 0x00}, /* XRX200_PCE_GCTRL_0_IGMP IGMP Mode Selection */
2970 + {0x1158, 14, 1, 0x00}, /* XRX200_PCE_GCTRL_0_VLAN VLAN-aware Switching */
2971 +// {0x1158, 13, 1, 0x00}, /* XRX200_PCE_GCTRL_0_NOPM No Port Map Forwarding */
2972 +// {0x1158, 12, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONUC Unknown Unicast Storm Control */
2973 +// {0x1158, 11, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMC Multicast Storm Control */
2974 +// {0x1158, 10, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONBC Broadcast Storm Control */
2975 +// {0x1158, 8, 2, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMOD Storm Control Mode */
2976 +// {0x1158, 4, 4, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMET Storm Control Metering Instance */
2977 +// {0x1158, 3, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MC_VALID Access Request */
2978 +// {0x1158, 2, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLCKMOD Port Lock Mode */
2979 +// {0x1158, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLIMMOD MAC Address Learning Limitation Mode */
2980 +// {0x1158, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MTFL MAC Table Flushing */
2981 +// {0x115C, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_1 PCE Global Control Register1 */
2982 +// {0x115C, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_1_PCE_DIS PCE Disable after currently processed packet */
2983 +// {0x115C, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_1_LRNMOD MAC Address Learning Mode */
2984 +// {0x1160, 0, 16, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL Three-color MarkerGlobal Control Register */
2985 +// {0x1160, 6, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPRED Re-marking Drop Precedence Red Encoding */
2986 +// {0x1160, 3, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPYEL Re-marking Drop Precedence Yellow Encoding */
2987 +// {0x1160, 0, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPGRN Re-marking Drop Precedence Green Encoding */
2988 +// {0x1164, 0, 16, 0x00}, /* XRX200_PCE_IGMP_CTRL IGMP Control Register */
2989 +// {0x1164, 15, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FAGEEN Force Aging of Table Entries Enable */
2990 +// {0x1164, 14, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FLEAVE Fast Leave Enable */
2991 +// {0x1164, 13, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRTEN Default Maximum Response Time Enable */
2992 +// {0x1164, 12, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_JASUP Join Aggregation Suppression Enable */
2993 +// {0x1164, 11, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_REPSUP Report Suppression Enable */
2994 +// {0x1164, 10, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_SRPEN Snooping of Router Port Enable */
2995 +// {0x1164, 8, 2, 0x00}, /* XRX200_PCE_IGMP_CTRL_ROB Robustness Variable */
2996 +// {0x1164, 0, 8, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRT IGMP Default Maximum Response Time */
2997 +// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM IGMP Default RouterPort Map Register */
2998 +// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM_DRPM IGMP Default Router Port Map */
2999 +// {0x116C, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_0 IGMP Aging Register0 */
3000 +// {0x116C, 3, 8, 0x00}, /* XRX200_PCE_IGMP_AGE_0_MANT IGMP Group Aging Time Mantissa */
3001 +// {0x116C, 0, 3, 0x00}, /* XRX200_PCE_IGMP_AGE_0_EXP IGMP Group Aging Time Exponent */
3002 +// {0x1170, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_1 IGMP Aging Register1 */
3003 +// {0x1170, 0, 12, 0x00}, /* XRX200_PCE_IGMP_AGE_1_MANT IGMP Router Port Aging Time Mantissa */
3004 +// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT IGMP Status Register */
3005 +// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT_IGPM IGMP Port Map */
3006 +// {0x1178, 0, 16, 0x00}, /* XRX200_WOL_GLB_CTRL Wake-on-LAN ControlRegister */
3007 +// {0x1178, 0, 1, 0x00}, /* XRX200_WOL_GLB_CTRL_PASSEN WoL Password Enable */
3008 +// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0 Wake-on-LAN DestinationAddress Register 0 */
3009 +// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0_DA0 WoL Destination Address [15:0] */
3010 +// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1 Wake-on-LAN DestinationAddress Register 1 */
3011 +// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1_DA1 WoL Destination Address [31:16] */
3012 +// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2 Wake-on-LAN DestinationAddress Register 2 */
3013 +// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2_DA2 WoL Destination Address [47:32] */
3014 +// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0 Wake-on-LAN Password Register0 */
3015 +// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0_PW0 WoL Password [15:0] */
3016 +// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1 Wake-on-LAN Password Register1 */
3017 +// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1_PW1 WoL Password [31:16] */
3018 +// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2 Wake-on-LAN Password Register2 */
3019 +// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2_PW2 WoL Password [47:32] */
3020 +// {0x1194, 0, 16, 0x00}, /* XRX200_PCE_IER_0_PINT Parser and ClassificationEngine Global Interrupt Enable Register 0 */
3021 +// {0x1194, 15, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_15 Port Interrupt Enable */
3022 +// {0x1194, 14, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_14 Port Interrupt Enable */
3023 +// {0x1194, 13, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_13 Port Interrupt Enable */
3024 +// {0x1194, 12, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_12 Port Interrupt Enable */
3025 +// {0x1194, 11, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_11 Port Interrupt Enable */
3026 +// {0x1194, 10, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_10 Port Interrupt Enable */
3027 +// {0x1194, 9, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_9 Port Interrupt Enable */
3028 +// {0x1194, 8, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_8 Port Interrupt Enable */
3029 +// {0x1194, 7, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_7 Port Interrupt Enable */
3030 +// {0x1194, 6, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_6 Port Interrupt Enable */
3031 +// {0x1194, 5, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_5 Port Interrupt Enable */
3032 +// {0x1194, 4, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_4 Port Interrupt Enable */
3033 +// {0x1194, 3, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_3 Port Interrupt Enable */
3034 +// {0x1194, 2, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_2 Port Interrupt Enable */
3035 +// {0x1194, 1, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_1 Port Interrupt Enable */
3036 +// {0x1194, 0, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_0 Port Interrupt Enable */
3037 +// {0x1198, 0, 16, 0x00}, /* XRX200_PCE_IER_1 Parser and ClassificationEngine Global Interrupt Enable Register 1 */
3038 +// {0x1198, 6, 1, 0x00}, /* XRX200_PCE_IER_1_FLOWINT Traffic Flow Table Interrupt Rule matched Interrupt Enable */
3039 +// {0x1198, 5, 1, 0x00}, /* XRX200_PCE_IER_1_CPH2 Classification Phase 2 Ready Interrupt Enable */
3040 +// {0x1198, 4, 1, 0x00}, /* XRX200_PCE_IER_1_CPH1 Classification Phase 1 Ready Interrupt Enable */
3041 +// {0x1198, 3, 1, 0x00}, /* XRX200_PCE_IER_1_CPH0 Classification Phase 0 Ready Interrupt Enable */
3042 +// {0x1198, 2, 1, 0x00}, /* XRX200_PCE_IER_1_PRDY Parser Ready Interrupt Enable */
3043 +// {0x1198, 1, 1, 0x00}, /* XRX200_PCE_IER_1_IGTF IGMP Table Full Interrupt Enable */
3044 +// {0x1198, 0, 1, 0x00}, /* XRX200_PCE_IER_1_MTF MAC Table Full Interrupt Enable */
3045 +// {0x119C, 0, 16, 0x00}, /* XRX200_PCE_ISR_0_PINT Parser and ClassificationEngine Global Interrupt Status Register 0 */
3046 +// {0x119C, 15, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_15 Port Interrupt */
3047 +// {0x119C, 14, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_14 Port Interrupt */
3048 +// {0x119C, 13, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_13 Port Interrupt */
3049 +// {0x119C, 12, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_12 Port Interrupt */
3050 +// {0x119C, 11, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_11 Port Interrupt */
3051 +// {0x119C, 10, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_10 Port Interrupt */
3052 +// {0x119C, 9, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_9 Port Interrupt */
3053 +// {0x119C, 8, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_8 Port Interrupt */
3054 +// {0x119C, 7, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_7 Port Interrupt */
3055 +// {0x119C, 6, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_6 Port Interrupt */
3056 +// {0x119C, 5, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_5 Port Interrupt */
3057 +// {0x119C, 4, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_4 Port Interrupt */
3058 +// {0x119C, 3, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_3 Port Interrupt */
3059 +// {0x119C, 2, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_2 Port Interrupt */
3060 +// {0x119C, 1, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_1 Port Interrupt */
3061 +// {0x119C, 0, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_0 Port Interrupt */
3062 +// {0x11A0, 0, 16, 0x00}, /* XRX200_PCE_ISR_1 Parser and ClassificationEngine Global Interrupt Status Register 1 */
3063 +// {0x11A0, 6, 1, 0x00}, /* XRX200_PCE_ISR_1_FLOWINT Traffic Flow Table Interrupt Rule matched */
3064 +// {0x11A0, 5, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH2 Classification Phase 2 Ready Interrupt */
3065 +// {0x11A0, 4, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH1 Classification Phase 1 Ready Interrupt */
3066 +// {0x11A0, 3, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH0 Classification Phase 0 Ready Interrupt */
3067 +// {0x11A0, 2, 1, 0x00}, /* XRX200_PCE_ISR_1_PRDY Parser Ready Interrupt */
3068 +// {0x11A0, 1, 1, 0x00}, /* XRX200_PCE_ISR_1_IGTF IGMP Table Full Interrupt */
3069 +// {0x11A0, 0, 1, 0x00}, /* XRX200_PCE_ISR_1_MTF MAC Table Full Interrupt */
3070 +// {0x11A4, 0, 16, 0x00}, /* XRX200_PARSER_STAT_FIFO Parser Status Register */
3071 +// {0x11A4, 8, 8, 0x00}, /* XRX200_PARSER_STAT_FSM_DAT_CNT Parser FSM Data Counter */
3072 +// {0x11A4, 5, 3, 0x00}, /* XRX200_PARSER_STAT_FSM_STATE Parser FSM State */
3073 +// {0x11A4, 4, 1, 0x00}, /* XRX200_PARSER_STAT_PKT_ERR Packet error detected */
3074 +// {0x11A4, 3, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_FIN Parser FSM finished */
3075 +// {0x11A4, 2, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_START Parser FSM start */
3076 +// {0x11A4, 1, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_RDY Parser FIFO ready for read. */
3077 +// {0x11A4, 0, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_FULL Parser */
3078 +// {0x1200, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_0 PCE Port ControlRegister 0 */
3079 +// {0x1200, 13, 1, 0x28}, /* XRX200_PCE_PCTRL_0_MCST Multicast Forwarding Mode Selection */
3080 +// {0x1200, 12, 1, 0x28}, /* XRX200_PCE_PCTRL_0_EGSTEN Table-based Egress Special Tag Enable */
3081 +// {0x1200, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_0_IGSTEN Ingress Special Tag Enable */
3082 +// {0x1200, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PCPEN PCP Remarking Mode */
3083 +// {0x1200, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CLPEN Class Remarking Mode */
3084 +// {0x1200, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_0_DPEN Drop Precedence Remarking Mode */
3085 +// {0x1200, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CMOD Three-color Marker Color Mode */
3086 +// {0x1200, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_0_VREP VLAN Replacement Mode */
3087 + {0x1200, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_0_TVM Transparent VLAN Mode */
3088 +// {0x1200, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PLOCK Port Locking Enable */
3089 +// {0x1200, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_0_AGEDIS Aging Disable */
3090 +// {0x1200, 0, 3, 0x28}, /* XRX200_PCE_PCTRL_0_PSTATE Port State */
3091 +// {0x1204, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_1 PCE Port ControlRegister 1 */
3092 +// {0x1204, 0, 8, 0x28}, /* XRX200_PCE_PCTRL_1_LRNLIM MAC Address Learning Limit */
3093 +// {0x1208, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_2 PCE Port ControlRegister 2 */
3094 +// {0x1208, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_2_DSCPMOD DSCP Mode Selection */
3095 +// {0x1208, 5, 2, 0x28}, /* XRX200_PCE_PCTRL_2_DSCP Enable DSCP to select the Class of Service */
3096 +// {0x1208, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_2_PCP Enable VLAN PCP to select the Class of Service */
3097 +// {0x1208, 0, 4, 0x28}, /* XRX200_PCE_PCTRL_2_PCLASS Port-based Traffic Class */
3098 +// {0x120C, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_3_VIO PCE Port ControlRegister 3 */
3099 +// {0x120C, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_3_EDIR Egress Redirection Mode */
3100 +// {0x120C, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXDMIR Receive Mirroring Enable for dropped frames */
3101 +// {0x120C, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXVMIR Receive Mirroring Enable for valid frames */
3102 +// {0x120C, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_3_TXMIR Transmit Mirroring Enable */
3103 +// {0x120C, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_7 Violation Type 7 Mirroring Enable */
3104 +// {0x120C, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_6 Violation Type 6 Mirroring Enable */
3105 +// {0x120C, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_5 Violation Type 5 Mirroring Enable */
3106 +// {0x120C, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_4 Violation Type 4 Mirroring Enable */
3107 +// {0x120C, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_3 Violation Type 3 Mirroring Enable */
3108 +// {0x120C, 2, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_2 Violation Type 2 Mirroring Enable */
3109 +// {0x120C, 1, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_1 Violation Type 1 Mirroring Enable */
3110 +// {0x120C, 0, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_0 Violation Type 0 Mirroring Enable */
3111 +// {0x1210, 0, 16, 0x28}, /* XRX200_WOL_CTRL Wake-on-LAN ControlRegister */
3112 +// {0x1210, 0, 1, 0x28}, /* XRX200_WOL_CTRL_PORT WoL Enable */
3113 +// {0x1214, 0, 16, 0x28}, /* XRX200_PCE_VCTRL PCE VLAN ControlRegister */
3114 + {0x1214, 5, 1, 0x28}, /* XRX200_PCE_VCTRL_VSR VLAN Security Rule */
3115 + {0x1214, 4, 1, 0x28}, /* XRX200_PCE_VCTRL_VEMR VLAN Egress Member Violation Rule */
3116 + {0x1214, 3, 1, 0x28}, /* XRX200_PCE_VCTRL_VIMR VLAN Ingress Member Violation Rule */
3117 + {0x1214, 1, 2, 0x28}, /* XRX200_PCE_VCTRL_VINR VLAN Ingress Tag Rule */
3118 + {0x1214, 0, 1, 0x28}, /* XRX200_PCE_VCTRL_UVR Unknown VLAN Rule */
3119 +// {0x1218, 0, 16, 0x28}, /* XRX200_PCE_DEFPVID PCE Default PortVID Register */
3120 + {0x1218, 0, 6, 0x28}, /* XRX200_PCE_DEFPVID_PVID Default Port VID Index */
3121 +// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT PCE Port StatusRegister */
3122 +// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT_LRNCNT Learning Count */
3123 +// {0x1220, 0, 16, 0x28}, /* XRX200_PCE_PIER Parser and ClassificationEngine Port Interrupt Enable Register */
3124 +// {0x1220, 5, 1, 0x28}, /* XRX200_PCE_PIER_CLDRP Classification Drop Interrupt Enable */
3125 +// {0x1220, 4, 1, 0x28}, /* XRX200_PCE_PIER_PTDRP Port Drop Interrupt Enable */
3126 +// {0x1220, 3, 1, 0x28}, /* XRX200_PCE_PIER_VLAN VLAN Violation Interrupt Enable */
3127 +// {0x1220, 2, 1, 0x28}, /* XRX200_PCE_PIER_WOL Wake-on-LAN Interrupt Enable */
3128 +// {0x1220, 1, 1, 0x28}, /* XRX200_PCE_PIER_LOCK Port Limit Alert Interrupt Enable */
3129 +// {0x1220, 0, 1, 0x28}, /* XRX200_PCE_PIER_LIM Port Lock Alert Interrupt Enable */
3130 +// {0x1224, 0, 16, 0x28}, /* XRX200_PCE_PISR Parser and ClassificationEngine Port Interrupt Status Register */
3131 +// {0x1224, 5, 1, 0x28}, /* XRX200_PCE_PISR_CLDRP Classification Drop Interrupt */
3132 +// {0x1224, 4, 1, 0x28}, /* XRX200_PCE_PISR_PTDRP Port Drop Interrupt */
3133 +// {0x1224, 3, 1, 0x28}, /* XRX200_PCE_PISR_VLAN VLAN Violation Interrupt */
3134 +// {0x1224, 2, 1, 0x28}, /* XRX200_PCE_PISR_WOL Wake-on-LAN Interrupt */
3135 +// {0x1224, 1, 1, 0x28}, /* XRX200_PCE_PISR_LOCK Port Lock Alert Interrupt */
3136 +// {0x1224, 0, 1, 0x28}, /* XRX200_PCE_PISR_LIMIT Port Limitation Alert Interrupt */
3137 +// {0x1600, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CTRL Three-colorMarker Control Register */
3138 +// {0x1600, 0, 1, 0x1c}, /* XRX200_PCE_TCM_CTRL_TCMEN Three-color Marker metering instance enable */
3139 +// {0x1604, 0, 16, 0x1c}, /* XRX200_PCE_TCM_STAT Three-colorMarker Status Register */
3140 +// {0x1604, 1, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL1 Three-color Marker Alert 1 Status */
3141 +// {0x1604, 0, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL0 Three-color Marker Alert 0 Status */
3142 +// {0x1608, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CBS Three-color MarkerCommitted Burst Size Register */
3143 +// {0x1608, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CBS_CBS Committed Burst Size */
3144 +// {0x160C, 0, 16, 0x1c}, /* XRX200_PCE_TCM_EBS Three-color MarkerExcess Burst Size Register */
3145 +// {0x160C, 0, 10, 0x1c}, /* XRX200_PCE_TCM_EBS_EBS Excess Burst Size */
3146 +// {0x1610, 0, 16, 0x1c}, /* XRX200_PCE_TCM_IBS Three-color MarkerInstantaneous Burst Size Register */
3147 +// {0x1610, 0, 2, 0x1c}, /* XRX200_PCE_TCM_IBS_IBS Instantaneous Burst Size */
3148 +// {0x1614, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT Three-colorMarker Constant Information Rate Mantissa Register */
3149 +// {0x1614, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT_MANT Rate Counter Mantissa */
3150 +// {0x1618, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP Three-colorMarker Constant Information Rate Exponent Register */
3151 +// {0x1618, 0, 4, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP_EXP Rate Counter Exponent */
3152 +// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST MAC Test Register */
3153 +// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST_JTP Jitter Test Pattern */
3154 +// {0x2304, 0, 16, 0x00}, /* XRX200_MAC_PFAD_CFG MAC Pause FrameSource Address Configuration Register */
3155 +// {0x2304, 0, 1, 0x00}, /* XRX200_MAC_PFAD_CFG_SAMOD Source Address Mode */
3156 +// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0 Pause Frame SourceAddress Part 0 */
3157 +// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0_PFAD Pause Frame Source Address Part 0 */
3158 +// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1 Pause Frame SourceAddress Part 1 */
3159 +// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1_PFAD Pause Frame Source Address Part 1 */
3160 +// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2 Pause Frame SourceAddress Part 2 */
3161 +// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2_PFAD Pause Frame Source Address Part 2 */
3162 +// {0x2314, 0, 16, 0x00}, /* XRX200_MAC_FLEN MAC Frame Length Register */
3163 +// {0x2314, 0, 14, 0x00}, /* XRX200_MAC_FLEN_LEN Maximum Frame Length */
3164 +// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0 MAC VLAN EthertypeRegister 0 */
3165 +// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0_OUTER Ethertype */
3166 +// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1 MAC VLAN EthertypeRegister 1 */
3167 +// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1_INNER Ethertype */
3168 +// {0x2320, 0, 16, 0x00}, /* XRX200_MAC_IER MAC Interrupt EnableRegister */
3169 +// {0x2320, 0, 8, 0x00}, /* XRX200_MAC_IER_MACIEN MAC Interrupt Enable */
3170 +// {0x2324, 0, 16, 0x00}, /* XRX200_MAC_ISR MAC Interrupt StatusRegister */
3171 +// {0x2324, 0, 8, 0x00}, /* XRX200_MAC_ISR_MACINT MAC Interrupt */
3172 +// {0x2400, 0, 16, 0x30}, /* XRX200_MAC_PSTAT MAC Port Status Register */
3173 +// {0x2400, 11, 1, 0x30}, /* XRX200_MAC_PSTAT_PACT PHY Active Status */
3174 + {0x2400, 10, 1, 0x30}, /* XRX200_MAC_PSTAT_GBIT Gigabit Speed Status */
3175 + {0x2400, 9, 1, 0x30}, /* XRX200_MAC_PSTAT_MBIT Megabit Speed Status */
3176 + {0x2400, 8, 1, 0x30}, /* XRX200_MAC_PSTAT_FDUP Full Duplex Status */
3177 +// {0x2400, 7, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAU Receive Pause Status */
3178 +// {0x2400, 6, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAU Transmit Pause Status */
3179 +// {0x2400, 5, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAUEN Receive Pause Enable Status */
3180 +// {0x2400, 4, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAUEN Transmit Pause Enable Status */
3181 + {0x2400, 3, 1, 0x30}, /* XRX200_MAC_PSTAT_LSTAT Link Status */
3182 +// {0x2400, 2, 1, 0x30}, /* XRX200_MAC_PSTAT_CRS Carrier Sense Status */
3183 +// {0x2400, 1, 1, 0x30}, /* XRX200_MAC_PSTAT_TXLPI Transmit Low-power Idle Status */
3184 +// {0x2400, 0, 1, 0x30}, /* XRX200_MAC_PSTAT_RXLPI Receive Low-power Idle Status */
3185 +// {0x2404, 0, 16, 0x30}, /* XRX200_MAC_PISR MAC Interrupt Status Register */
3186 +// {0x2404, 13, 1, 0x30}, /* XRX200_MAC_PISR_PACT PHY Active Status */
3187 +// {0x2404, 12, 1, 0x30}, /* XRX200_MAC_PISR_SPEED Megabit Speed Status */
3188 +// {0x2404, 11, 1, 0x30}, /* XRX200_MAC_PISR_FDUP Full Duplex Status */
3189 +// {0x2404, 10, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUEN Receive Pause Enable Status */
3190 +// {0x2404, 9, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUEN Transmit Pause Enable Status */
3191 +// {0x2404, 8, 1, 0x30}, /* XRX200_MAC_PISR_LPIOFF Receive Low-power Idle Mode is left */
3192 +// {0x2404, 7, 1, 0x30}, /* XRX200_MAC_PISR_LPION Receive Low-power Idle Mode is entered */
3193 +// {0x2404, 6, 1, 0x30}, /* XRX200_MAC_PISR_JAM Jam Status Detected */
3194 +// {0x2404, 5, 1, 0x30}, /* XRX200_MAC_PISR_TOOSHORT Too Short Frame Error Detected */
3195 +// {0x2404, 4, 1, 0x30}, /* XRX200_MAC_PISR_TOOLONG Too Long Frame Error Detected */
3196 +// {0x2404, 3, 1, 0x30}, /* XRX200_MAC_PISR_LENERR Length Mismatch Error Detected */
3197 +// {0x2404, 2, 1, 0x30}, /* XRX200_MAC_PISR_FCSERR Frame Checksum Error Detected */
3198 +// {0x2404, 1, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUSE Pause Frame Transmitted */
3199 +// {0x2404, 0, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUSE Pause Frame Received */
3200 +// {0x2408, 0, 16, 0x30}, /* XRX200_MAC_PIER MAC Interrupt Enable Register */
3201 +// {0x2408, 13, 1, 0x30}, /* XRX200_MAC_PIER_PACT PHY Active Status */
3202 +// {0x2408, 12, 1, 0x30}, /* XRX200_MAC_PIER_SPEED Megabit Speed Status */
3203 +// {0x2408, 11, 1, 0x30}, /* XRX200_MAC_PIER_FDUP Full Duplex Status */
3204 +// {0x2408, 10, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUEN Receive Pause Enable Status */
3205 +// {0x2408, 9, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUEN Transmit Pause Enable Status */
3206 +// {0x2408, 8, 1, 0x30}, /* XRX200_MAC_PIER_LPIOFF Low-power Idle Off Interrupt Mask */
3207 +// {0x2408, 7, 1, 0x30}, /* XRX200_MAC_PIER_LPION Low-power Idle On Interrupt Mask */
3208 +// {0x2408, 6, 1, 0x30}, /* XRX200_MAC_PIER_JAM Jam Status Interrupt Mask */
3209 +// {0x2408, 5, 1, 0x30}, /* XRX200_MAC_PIER_TOOSHORT Too Short Frame Error Interrupt Mask */
3210 +// {0x2408, 4, 1, 0x30}, /* XRX200_MAC_PIER_TOOLONG Too Long Frame Error Interrupt Mask */
3211 +// {0x2408, 3, 1, 0x30}, /* XRX200_MAC_PIER_LENERR Length Mismatch Error Interrupt Mask */
3212 +// {0x2408, 2, 1, 0x30}, /* XRX200_MAC_PIER_FCSERR Frame Checksum Error Interrupt Mask */
3213 +// {0x2408, 1, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUSE Transmit Pause Frame Interrupt Mask */
3214 +// {0x2408, 0, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUSE Receive Pause Frame Interrupt Mask */
3215 +// {0x240C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_0 MAC Control Register0 */
3216 +// {0x240C, 13, 2, 0x30}, /* XRX200_MAC_CTRL_0_LCOL Late Collision Control */
3217 +// {0x240C, 12, 1, 0x30}, /* XRX200_MAC_CTRL_0_BM Burst Mode Control */
3218 +// {0x240C, 11, 1, 0x30}, /* XRX200_MAC_CTRL_0_APADEN Automatic VLAN Padding Enable */
3219 +// {0x240C, 10, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPAD2EN Stacked VLAN Padding Enable */
3220 +// {0x240C, 9, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPADEN VLAN Padding Enable */
3221 +// {0x240C, 8, 1, 0x30}, /* XRX200_MAC_CTRL_0_PADEN Padding Enable */
3222 +// {0x240C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_0_FCS Transmit FCS Control */
3223 + {0x240C, 4, 3, 0x30}, /* XRX200_MAC_CTRL_0_FCON Flow Control Mode */
3224 +// {0x240C, 2, 2, 0x30}, /* XRX200_MAC_CTRL_0_FDUP Full Duplex Control */
3225 +// {0x240C, 0, 2, 0x30}, /* XRX200_MAC_CTRL_0_GMII GMII/MII interface mode selection */
3226 +// {0x2410, 0, 16, 0x30}, /* XRX200_MAC_CTRL_1 MAC Control Register1 */
3227 +// {0x2410, 8, 1, 0x30}, /* XRX200_MAC_CTRL_1_SHORTPRE Short Preamble Control */
3228 +// {0x2410, 0, 4, 0x30}, /* XRX200_MAC_CTRL_1_IPG Minimum Inter Packet Gap Size */
3229 +// {0x2414, 0, 16, 0x30}, /* XRX200_MAC_CTRL_2 MAC Control Register2 */
3230 +// {0x2414, 3, 1, 0x30}, /* XRX200_MAC_CTRL_2_MLEN Maximum Untagged Frame Length */
3231 +// {0x2414, 2, 1, 0x30}, /* XRX200_MAC_CTRL_2_LCHKL Frame Length Check Long Enable */
3232 +// {0x2414, 0, 2, 0x30}, /* XRX200_MAC_CTRL_2_LCHKS Frame Length Check Short Enable */
3233 +// {0x2418, 0, 16, 0x30}, /* XRX200_MAC_CTRL_3 MAC Control Register3 */
3234 +// {0x2418, 0, 4, 0x30}, /* XRX200_MAC_CTRL_3_RCNT Retry Count */
3235 +// {0x241C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_4 MAC Control Register4 */
3236 +// {0x241C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_4_LPIEN LPI Mode Enable */
3237 +// {0x241C, 0, 7, 0x30}, /* XRX200_MAC_CTRL_4_WAIT LPI Wait Time */
3238 +// {0x2420, 0, 16, 0x30}, /* XRX200_MAC_CTRL_5_PJPS MAC Control Register5 */
3239 +// {0x2420, 1, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_NOBP Prolonged Jam pattern size during no-backpressure state */
3240 +// {0x2420, 0, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_BP Prolonged Jam pattern size during backpressure state */
3241 +// {0x2424, 0, 16, 0x30}, /* XRX200_MAC_CTRL_6_XBUF Transmit and ReceiveBuffer Control Register */
3242 +// {0x2424, 9, 3, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_DLY_WP Delay */
3243 +// {0x2424, 8, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_INIT Receive Buffer Initialization */
3244 +// {0x2424, 6, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_BYPASS Bypass the Receive Buffer */
3245 +// {0x2424, 3, 3, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_DLY_WP Delay */
3246 +// {0x2424, 2, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_INIT Initialize the Transmit Buffer */
3247 +// {0x2424, 0, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_BYPASS Bypass the Transmit Buffer */
3248 +// {0x2428, 0, 16, 0x30}, /* XRX200_MAC_BUFST_XBUF MAC Receive and TransmitBuffer Status Register */
3249 +// {0x2428, 3, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_UFL Receive Buffer Underflow Indicator */
3250 +// {0x2428, 2, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_OFL Receive Buffer Overflow Indicator */
3251 +// {0x2428, 1, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_UFL Transmit Buffer Underflow Indicator */
3252 +// {0x2428, 0, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_OFL Transmit Buffer Overflow Indicator */
3253 +// {0x242C, 0, 16, 0x30}, /* XRX200_MAC_TESTEN MAC Test Enable Register */
3254 +// {0x242C, 2, 1, 0x30}, /* XRX200_MAC_TESTEN_JTEN Jitter Test Enable */
3255 +// {0x242C, 1, 1, 0x30}, /* XRX200_MAC_TESTEN_TXER Transmit Error Insertion */
3256 +// {0x242C, 0, 1, 0x30}, /* XRX200_MAC_TESTEN_LOOP MAC Loopback Enable */
3257 +// {0x2900, 0, 16, 0x00}, /* XRX200_FDMA_CTRL Ethernet Switch FetchDMA Control Register */
3258 +// {0x2900, 7, 5, 0x00}, /* XRX200_FDMA_CTRL_LPI_THRESHOLD Low Power Idle Threshold */
3259 +// {0x2900, 4, 3, 0x00}, /* XRX200_FDMA_CTRL_LPI_MODE Low Power Idle Mode */
3260 +// {0x2900, 2, 2, 0x00}, /* XRX200_FDMA_CTRL_EGSTAG Egress Special Tag Size */
3261 +// {0x2900, 1, 1, 0x00}, /* XRX200_FDMA_CTRL_IGSTAG Ingress Special Tag Size */
3262 +// {0x2900, 0, 1, 0x00}, /* XRX200_FDMA_CTRL_EXCOL Excessive Collision Handling */
3263 +// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE Special Tag EthertypeControl Register */
3264 +// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE_ETYPE Special Tag Ethertype */
3265 +// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE VLAN Tag EthertypeControl Register */
3266 +// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE_ETYPE VLAN Tag Ethertype */
3267 +// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0 FDMA Status Register0 */
3268 +// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0_FSMS FSM states status */
3269 +// {0x2910, 0, 16, 0x00}, /* XRX200_FDMA_IER Fetch DMA Global InterruptEnable Register */
3270 +// {0x2910, 14, 1, 0x00}, /* XRX200_FDMA_IER_PCKD Packet Drop Interrupt Enable */
3271 +// {0x2910, 13, 1, 0x00}, /* XRX200_FDMA_IER_PCKR Packet Ready Interrupt Enable */
3272 +// {0x2910, 0, 8, 0x00}, /* XRX200_FDMA_IER_PCKT Packet Sent Interrupt Enable */
3273 +// {0x2914, 0, 16, 0x00}, /* XRX200_FDMA_ISR Fetch DMA Global InterruptStatus Register */
3274 +// {0x2914, 14, 1, 0x00}, /* XRX200_FDMA_ISR_PCKTD Packet Drop */
3275 +// {0x2914, 13, 1, 0x00}, /* XRX200_FDMA_ISR_PCKR Packet is Ready for Transmission */
3276 +// {0x2914, 0, 8, 0x00}, /* XRX200_FDMA_ISR_PCKT Packet Sent Event */
3277 +// {0x2A00, 0, 16, 0x18}, /* XRX200_FDMA_PCTRL Ethernet SwitchFetch DMA Port Control Register */
3278 +// {0x2A00, 3, 2, 0x18}, /* XRX200_FDMA_PCTRL_VLANMOD VLAN Modification Enable */
3279 +// {0x2A00, 2, 1, 0x18}, /* XRX200_FDMA_PCTRL_DSCPRM DSCP Re-marking Enable */
3280 +// {0x2A00, 1, 1, 0x18}, /* XRX200_FDMA_PCTRL_STEN Special Tag Insertion Enable */
3281 +// {0x2A00, 0, 1, 0x18}, /* XRX200_FDMA_PCTRL_EN FDMA Port Enable */
3282 +// {0x2A04, 0, 16, 0x18}, /* XRX200_FDMA_PRIO Ethernet SwitchFetch DMA Port Priority Register */
3283 +// {0x2A04, 0, 2, 0x18}, /* XRX200_FDMA_PRIO_PRIO FDMA PRIO */
3284 +// {0x2A08, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT0 Ethernet SwitchFetch DMA Port Status Register 0 */
3285 +// {0x2A08, 15, 1, 0x18}, /* XRX200_FDMA_PSTAT0_PKT_AVAIL Port Egress Packet Available */
3286 +// {0x2A08, 14, 1, 0x18}, /* XRX200_FDMA_PSTAT0_POK Port Status OK */
3287 +// {0x2A08, 0, 6, 0x18}, /* XRX200_FDMA_PSTAT0_PSEG Port Egress Segment Count */
3288 +// {0x2A0C, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT1_HDR Ethernet SwitchFetch DMA Port Status Register 1 */
3289 +// {0x2A0C, 0, 10, 0x18}, /* XRX200_FDMA_PSTAT1_HDR_PTR Header Pointer */
3290 +// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0 Egress TimeStamp Register 0 */
3291 +// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0_TSTL Time Stamp [15:0] */
3292 +// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1 Egress TimeStamp Register 1 */
3293 +// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1_TSTH Time Stamp [31:16] */
3294 +// {0x2D00, 0, 16, 0x00}, /* XRX200_SDMA_CTRL Ethernet Switch StoreDMA Control Register */
3295 +// {0x2D00, 0, 1, 0x00}, /* XRX200_SDMA_CTRL_TSTEN Time Stamp Enable */
3296 +// {0x2D04, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR1 SDMA Flow Control Threshold1 Register */
3297 +// {0x2D04, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR1_THR1 Threshold 1 */
3298 +// {0x2D08, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR2 SDMA Flow Control Threshold2 Register */
3299 +// {0x2D08, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR2_THR2 Threshold 2 */
3300 +// {0x2D0C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR3 SDMA Flow Control Threshold3 Register */
3301 +// {0x2D0C, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR3_THR3 Threshold 3 */
3302 +// {0x2D10, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR4 SDMA Flow Control Threshold4 Register */
3303 +// {0x2D10, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR4_THR4 Threshold 4 */
3304 +// {0x2D14, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR5 SDMA Flow Control Threshold5 Register */
3305 +// {0x2D14, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR5_THR5 Threshold 5 */
3306 +// {0x2D18, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR6 SDMA Flow Control Threshold6 Register */
3307 +// {0x2D18, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR6_THR6 Threshold 6 */
3308 +// {0x2D1C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR7 SDMA Flow Control Threshold7 Register */
3309 +// {0x2D1C, 0, 11, 0x00}, /* XRX200_SDMA_FCTHR7_THR7 Threshold 7 */
3310 +// {0x2D20, 0, 16, 0x00}, /* XRX200_SDMA_STAT_0 SDMA Status Register0 */
3311 +// {0x2D20, 4, 3, 0x00}, /* XRX200_SDMA_STAT_0_BPS_FILL Back Pressure Status */
3312 +// {0x2D20, 2, 2, 0x00}, /* XRX200_SDMA_STAT_0_BPS_PNT Back Pressure Status */
3313 +// {0x2D20, 0, 2, 0x00}, /* XRX200_SDMA_STAT_0_DROP Back Pressure Status */
3314 +// {0x2D24, 0, 16, 0x00}, /* XRX200_SDMA_STAT_1 SDMA Status Register1 */
3315 +// {0x2D24, 0, 10, 0x00}, /* XRX200_SDMA_STAT_1_FILL Buffer Filling Level */
3316 +// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2 SDMA Status Register2 */
3317 +// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2_FSMS FSM states status */
3318 +// {0x2D2C, 0, 16, 0x00}, /* XRX200_SDMA_IER SDMA Interrupt Enable Register */
3319 +// {0x2D2C, 15, 1, 0x00}, /* XRX200_SDMA_IER_BPEX Buffer Pointers Exceeded */
3320 +// {0x2D2C, 14, 1, 0x00}, /* XRX200_SDMA_IER_BFULL Buffer Full */
3321 +// {0x2D2C, 13, 1, 0x00}, /* XRX200_SDMA_IER_FERR Frame Error */
3322 +// {0x2D2C, 0, 8, 0x00}, /* XRX200_SDMA_IER_FRX Frame Received Successfully */
3323 +// {0x2D30, 0, 16, 0x00}, /* XRX200_SDMA_ISR SDMA Interrupt Status Register */
3324 +// {0x2D30, 15, 1, 0x00}, /* XRX200_SDMA_ISR_BPEX Packet Descriptors Exceeded */
3325 +// {0x2D30, 14, 1, 0x00}, /* XRX200_SDMA_ISR_BFULL Buffer Full */
3326 +// {0x2D30, 13, 1, 0x00}, /* XRX200_SDMA_ISR_FERR Frame Error */
3327 +// {0x2D30, 0, 8, 0x00}, /* XRX200_SDMA_ISR_FRX Frame Received Successfully */
3328 +// {0x2F00, 0, 16, 0x18}, /* XRX200_SDMA_PCTRL Ethernet SwitchStore DMA Port Control Register */
3329 +// {0x2F00, 13, 2, 0x18}, /* XRX200_SDMA_PCTRL_DTHR Drop Threshold Selection */
3330 +// {0x2F00, 11, 2, 0x18}, /* XRX200_SDMA_PCTRL_PTHR Pause Threshold Selection */
3331 +// {0x2F00, 10, 1, 0x18}, /* XRX200_SDMA_PCTRL_PHYEFWD Forward PHY Error Frames */
3332 +// {0x2F00, 9, 1, 0x18}, /* XRX200_SDMA_PCTRL_ALGFWD Forward Alignment Error Frames */
3333 +// {0x2F00, 8, 1, 0x18}, /* XRX200_SDMA_PCTRL_LENFWD Forward Length Errored Frames */
3334 +// {0x2F00, 7, 1, 0x18}, /* XRX200_SDMA_PCTRL_OSFWD Forward Oversized Frames */
3335 +// {0x2F00, 6, 1, 0x18}, /* XRX200_SDMA_PCTRL_USFWD Forward Undersized Frames */
3336 +// {0x2F00, 5, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSIGN Ignore FCS Errors */
3337 +// {0x2F00, 4, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSFWD Forward FCS Errored Frames */
3338 +// {0x2F00, 3, 1, 0x18}, /* XRX200_SDMA_PCTRL_PAUFWD Pause Frame Forwarding */
3339 +// {0x2F00, 2, 1, 0x18}, /* XRX200_SDMA_PCTRL_MFCEN Metering Flow Control Enable */
3340 +// {0x2F00, 1, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCEN Flow Control Enable */
3341 +// {0x2F00, 0, 1, 0x18}, /* XRX200_SDMA_PCTRL_PEN Port Enable */
3342 +// {0x2F04, 0, 16, 0x18}, /* XRX200_SDMA_PRIO Ethernet SwitchStore DMA Port Priority Register */
3343 +// {0x2F04, 0, 2, 0x18}, /* XRX200_SDMA_PRIO_PRIO SDMA PRIO */
3344 +// {0x2F08, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT0_HDR Ethernet SwitchStore DMA Port Status Register 0 */
3345 +// {0x2F08, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT0_HDR_PTR Port Ingress Queue Header Pointer */
3346 +// {0x2F0C, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT1 Ethernet SwitchStore DMA Port Status Register 1 */
3347 +// {0x2F0C, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT1_PPKT Port Ingress Packet Count */
3348 +// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0 Ingress TimeStamp Register 0 */
3349 +// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0_TSTL Time Stamp [15:0] */
3350 +// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1 Ingress TimeStamp Register 1 */
3351 +// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1_TSTH Time Stamp [31:16] */
3352 +};
3353 +
3354 +
3355 --
3356 1.7.10.4
3357