target/linux/lantiq/patches-3.2/0006-MIPS-lantiq-change-ltq_request_gpio-call-signature.patch

   1 From 2daf93364658fd26bf583b7a46b81c08fddaf1e4 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 11 Nov 2011 12:45:24 +0100
   4 Subject: [PATCH 06/73] MIPS: lantiq: change ltq_request_gpio() call signature
   5
   6 ltq_request_gpio() was using alt0/1 to multiplex the function of GPIO pins.
   7 This was XWAY specific. In order to also accomodate SoCs that require more bits
   8 we use a 32bit mask instead. This way the call signature is consistent between
   9 XWAY and FALC-ON.
  10
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  13 ---
  14  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    4 +-
  15  arch/mips/lantiq/xway/gpio.c                       |    8 ++--
  16  arch/mips/lantiq/xway/gpio_stp.c                   |    6 ++--
  17  arch/mips/pci/pci-lantiq.c                         |   36 +++++++++----------
  18  4 files changed, 26 insertions(+), 28 deletions(-)
  19
  20 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  21 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  22 @@ -135,8 +135,8 @@ extern __iomem void *ltq_ebu_membase;
  23  extern __iomem void *ltq_cgu_membase;
  24
  25  /* request a non-gpio and set the PIO config */
  26 -extern int  ltq_gpio_request(unsigned int pin, unsigned int alt0,
  27 -       unsigned int alt1, unsigned int dir, const char *name);
  28 +extern int  ltq_gpio_request(unsigned int pin, unsigned int mux,
  29 +                               unsigned int dir, const char *name);
  30  extern void ltq_pmu_enable(unsigned int module);
  31  extern void ltq_pmu_disable(unsigned int module);
  32  extern void ltq_cgu_enable(unsigned int clk);
  33 --- a/arch/mips/lantiq/xway/gpio.c
  34 +++ b/arch/mips/lantiq/xway/gpio.c
  35 @@ -48,8 +48,8 @@ int irq_to_gpio(unsigned int gpio)
  36  }
  37  EXPORT_SYMBOL(irq_to_gpio);
  38
  39 -int ltq_gpio_request(unsigned int pin, unsigned int alt0,
  40 -       unsigned int alt1, unsigned int dir, const char *name)
  41 +int ltq_gpio_request(unsigned int pin, unsigned int mux,
  42 +                       unsigned int dir, const char *name)
  43  {
  44         int id = 0;
  45
  46 @@ -67,13 +67,13 @@ int ltq_gpio_request(unsigned int pin, u
  47                 pin -= PINS_PER_PORT;
  48                 id++;
  49         }
  50 -       if (alt0)
  51 +       if (mux & 0x2)
  52                 ltq_gpio_setbit(ltq_gpio_port[id].membase,
  53                         LTQ_GPIO_ALTSEL0, pin);
  54         else
  55                 ltq_gpio_clearbit(ltq_gpio_port[id].membase,
  56                         LTQ_GPIO_ALTSEL0, pin);
  57 -       if (alt1)
  58 +       if (mux & 0x1)
  59                 ltq_gpio_setbit(ltq_gpio_port[id].membase,
  60                         LTQ_GPIO_ALTSEL1, pin);
  61         else
  62 --- a/arch/mips/lantiq/xway/gpio_stp.c
  63 +++ b/arch/mips/lantiq/xway/gpio_stp.c
  64 @@ -79,9 +79,9 @@ static struct gpio_chip ltq_stp_chip = {
  65  static int ltq_stp_hw_init(void)
  66  {
  67         /* the 3 pins used to control the external stp */
  68 -       ltq_gpio_request(4, 1, 0, 1, "stp-st");
  69 -       ltq_gpio_request(5, 1, 0, 1, "stp-d");
  70 -       ltq_gpio_request(6, 1, 0, 1, "stp-sh");
  71 +       ltq_gpio_request(4, 2, 1, "stp-st");
  72 +       ltq_gpio_request(5, 2, 1, "stp-d");
  73 +       ltq_gpio_request(6, 2, 1, "stp-sh");
  74
  75         /* sane defaults */
  76         ltq_stp_w32(0, LTQ_STP_AR);
  77 --- a/arch/mips/pci/pci-lantiq.c
  78 +++ b/arch/mips/pci/pci-lantiq.c
  79 @@ -70,28 +70,27 @@
  80
  81  struct ltq_pci_gpio_map {
  82         int pin;
  83 -       int alt0;
  84 -       int alt1;
  85 +       int mux;
  86         int dir;
  87         char *name;
  88  };
  89
  90  /* the pci core can make use of the following gpios */
  91  static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
  92 -       { 0, 1, 0, 0, "pci-exin0" },
  93 -       { 1, 1, 0, 0, "pci-exin1" },
  94 -       { 2, 1, 0, 0, "pci-exin2" },
  95 -       { 39, 1, 0, 0, "pci-exin3" },
  96 -       { 10, 1, 0, 0, "pci-exin4" },
  97 -       { 9, 1, 0, 0, "pci-exin5" },
  98 -       { 30, 1, 0, 1, "pci-gnt1" },
  99 -       { 23, 1, 0, 1, "pci-gnt2" },
 100 -       { 19, 1, 0, 1, "pci-gnt3" },
 101 -       { 38, 1, 0, 1, "pci-gnt4" },
 102 -       { 29, 1, 0, 0, "pci-req1" },
 103 -       { 31, 1, 0, 0, "pci-req2" },
 104 -       { 3, 1, 0, 0, "pci-req3" },
 105 -       { 37, 1, 0, 0, "pci-req4" },
 106 +       { 0, 2, 0, "pci-exin0" },
 107 +       { 1, 2, 0, "pci-exin1" },
 108 +       { 2, 2, 0, "pci-exin2" },
 109 +       { 39, 2, 0, "pci-exin3" },
 110 +       { 10, 2, 0, "pci-exin4" },
 111 +       { 9, 2, 0, "pci-exin5" },
 112 +       { 30, 2, 1, "pci-gnt1" },
 113 +       { 23, 2, 1, "pci-gnt2" },
 114 +       { 19, 2, 1, "pci-gnt3" },
 115 +       { 38, 2, 1, "pci-gnt4" },
 116 +       { 29, 2, 0, "pci-req1" },
 117 +       { 31, 2, 0, "pci-req2" },
 118 +       { 3, 2, 0, "pci-req3" },
 119 +       { 37, 2, 0, "pci-req4" },
 120  };
 121
 122  __iomem void *ltq_pci_mapped_cfg;
 123 @@ -157,13 +156,12 @@ static void ltq_pci_setup_gpio(int gpio)
 124         for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
 125                 if (gpio & (1 << i)) {
 126                         ltq_gpio_request(ltq_pci_gpio_map[i].pin,
 127 -                               ltq_pci_gpio_map[i].alt0,
 128 -                               ltq_pci_gpio_map[i].alt1,
 129 +                               ltq_pci_gpio_map[i].mux,
 130                                 ltq_pci_gpio_map[i].dir,
 131                                 ltq_pci_gpio_map[i].name);
 132                 }
 133         }
 134 -       ltq_gpio_request(21, 0, 0, 1, "pci-reset");
 135 +       ltq_gpio_request(21, 0, 1, "pci-reset");
 136         ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
 137  }
 138