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kernel: update linux 3.2 to 3.2.15
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.2 / 0008-MIPS-lantiq-add-basic-support-for-FALC-ON.patch
1 From 9124a4d02b182c47c61fc9e58234cde9a070d2d5 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 11 Aug 2011 14:33:04 +0200
4 Subject: [PATCH 08/73] MIPS: lantiq: add basic support for FALC-ON
5
6 Adds support for the FALC-ON SoC. This SoC is from the FTTH/GPON SoC family.
7
8 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 ---
11 .../include/asm/mach-lantiq/falcon/falcon_irq.h | 268 ++++++++++++++++++++
12 arch/mips/include/asm/mach-lantiq/falcon/irq.h | 18 ++
13 .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 143 +++++++++++
14 arch/mips/include/asm/mach-lantiq/lantiq.h | 1 +
15 arch/mips/lantiq/Kconfig | 4 +
16 arch/mips/lantiq/Makefile | 1 +
17 arch/mips/lantiq/Platform | 1 +
18 arch/mips/lantiq/falcon/Makefile | 1 +
19 arch/mips/lantiq/falcon/clk.c | 44 ++++
20 arch/mips/lantiq/falcon/devices.c | 87 +++++++
21 arch/mips/lantiq/falcon/devices.h | 18 ++
22 arch/mips/lantiq/falcon/prom.c | 93 +++++++
23 arch/mips/lantiq/falcon/reset.c | 87 +++++++
24 arch/mips/lantiq/falcon/sysctrl.c | 183 +++++++++++++
25 14 files changed, 949 insertions(+), 0 deletions(-)
26 create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
27 create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h
28 create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
29 create mode 100644 arch/mips/lantiq/falcon/Makefile
30 create mode 100644 arch/mips/lantiq/falcon/clk.c
31 create mode 100644 arch/mips/lantiq/falcon/devices.c
32 create mode 100644 arch/mips/lantiq/falcon/devices.h
33 create mode 100644 arch/mips/lantiq/falcon/prom.c
34 create mode 100644 arch/mips/lantiq/falcon/reset.c
35 create mode 100644 arch/mips/lantiq/falcon/sysctrl.c
36
37 --- /dev/null
38 +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
39 @@ -0,0 +1,268 @@
40 +/*
41 + * This program is free software; you can redistribute it and/or modify it
42 + * under the terms of the GNU General Public License version 2 as published
43 + * by the Free Software Foundation.
44 + *
45 + * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
46 + */
47 +
48 +#ifndef _FALCON_IRQ__
49 +#define _FALCON_IRQ__
50 +
51 +#define INT_NUM_IRQ0 8
52 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
53 +#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
54 +#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
55 +#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
56 +#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
57 +#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
58 +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
59 +
60 +#define MIPS_CPU_TIMER_IRQ 7
61 +
62 +/* HOST IF Event Interrupt */
63 +#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0)
64 +/* HOST IF Mailbox0 Receive Interrupt */
65 +#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1)
66 +/* HOST IF Mailbox0 Transmit Interrupt */
67 +#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2)
68 +/* HOST IF Mailbox1 Receive Interrupt */
69 +#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3)
70 +/* HOST IF Mailbox1 Transmit Interrupt */
71 +#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4)
72 +/* I2C Last Single Data Transfer Request */
73 +#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8)
74 +/* I2C Single Data Transfer Request */
75 +#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9)
76 +/* I2C Last Burst Data Transfer Request */
77 +#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10)
78 +/* I2C Burst Data Transfer Request */
79 +#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11)
80 +/* I2C Error Interrupt */
81 +#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12)
82 +/* I2C Protocol Interrupt */
83 +#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13)
84 +/* SSC Transmit Interrupt */
85 +#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14)
86 +/* SSC Receive Interrupt */
87 +#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15)
88 +/* SSC Error Interrupt */
89 +#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16)
90 +/* SSC Frame Interrupt */
91 +#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17)
92 +/* Advanced Encryption Standard Interrupt */
93 +#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27)
94 +/* Secure Hash Algorithm Interrupt */
95 +#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28)
96 +/* PCM Receive Interrupt */
97 +#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29)
98 +/* PCM Transmit Interrupt */
99 +#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30)
100 +/* PCM Transmit Crash Interrupt */
101 +#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31)
102 +
103 +/* EBU Serial Flash Command Error */
104 +#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0)
105 +/* EBU Serial Flash Command Overwrite Error */
106 +#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1)
107 +/* EBU Serial Flash Busy */
108 +#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2)
109 +/* External Interrupt from GPIO P0 */
110 +#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4)
111 +/* External Interrupt from GPIO P1 */
112 +#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5)
113 +/* External Interrupt from GPIO P2 */
114 +#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6)
115 +/* External Interrupt from GPIO P3 */
116 +#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7)
117 +/* External Interrupt from GPIO P4 */
118 +#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8)
119 +/* 8kHz backup interrupt derived from core-PLL */
120 +#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10)
121 +/* FSC Timer Interrupt 0 */
122 +#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11)
123 +/* FSC Timer Interrupt 1 */
124 +#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12)
125 +/* 8kHz root interrupt derived from GPON interface */
126 +#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13)
127 +/* Time of Day */
128 +#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14)
129 +/* PMA Interrupt from IntNode of the 200MHz Domain */
130 +#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15)
131 +/* PMA Interrupt from IntNode of the TX Clk Domain */
132 +#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16)
133 +/* PMA Interrupt from IntNode of the RX Clk Domain */
134 +#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17)
135 +/* SYS1 Interrupt */
136 +#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20)
137 +/* SYS GPE Interrupt */
138 +#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21)
139 +/* Watchdog Access Error Interrupt */
140 +#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24)
141 +/* Watchdog Prewarning Interrupt */
142 +#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25)
143 +/* SBIU interrupt */
144 +#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27)
145 +/* FPI Bus Control Unit Interrupt */
146 +#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29)
147 +/* DDR Controller Interrupt */
148 +#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30)
149 +/* Crossbar Error Interrupt */
150 +#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31)
151 +
152 +/* ICTRLL 0 Interrupt */
153 +#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0)
154 +/* ICTRLL 1 Interrupt */
155 +#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1)
156 +/* ICTRLL 2 Interrupt */
157 +#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2)
158 +/* ICTRLL 3 Interrupt */
159 +#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3)
160 +/* OCTRLL 0 Interrupt */
161 +#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4)
162 +/* OCTRLL 1 Interrupt */
163 +#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5)
164 +/* OCTRLL 2 Interrupt */
165 +#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6)
166 +/* OCTRLL 3 Interrupt */
167 +#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7)
168 +/* OCTRLG Interrupt */
169 +#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9)
170 +/* IQM Interrupt */
171 +#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10)
172 +/* FSQM Interrupt */
173 +#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11)
174 +/* TMU Interrupt */
175 +#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12)
176 +/* LINK1 Interrupt */
177 +#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14)
178 +/* ICTRLC 0 Interrupt */
179 +#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16)
180 +/* ICTRLC 1 Interrupt */
181 +#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17)
182 +/* OCTRLC Interrupt */
183 +#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18)
184 +/* CONFIG Break Interrupt */
185 +#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19)
186 +/* CONFIG Interrupt */
187 +#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20)
188 +/* Dispatcher Interrupt */
189 +#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21)
190 +/* TBM Interrupt */
191 +#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22)
192 +/* GTC Downstream Interrupt */
193 +#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29)
194 +/* GTC Upstream Interrupt */
195 +#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30)
196 +/* EIM Interrupt */
197 +#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31)
198 +
199 +/* ASC0 Transmit Interrupt */
200 +#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0)
201 +/* ASC0 Receive Interrupt */
202 +#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1)
203 +/* ASC0 Error Interrupt */
204 +#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2)
205 +/* ASC0 Transmit Buffer Interrupt */
206 +#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3)
207 +/* ASC0 Autobaud Start Interrupt */
208 +#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4)
209 +/* ASC0 Autobaud Detection Interrupt */
210 +#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5)
211 +/* ASC1 Modem Status Interrupt */
212 +#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6)
213 +/* ASC0 Soft Flow Control Interrupt */
214 +#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7)
215 +/* ASC1 Transmit Interrupt */
216 +#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8)
217 +/* ASC1 Receive Interrupt */
218 +#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9)
219 +/* ASC1 Error Interrupt */
220 +#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10)
221 +/* ASC1 Transmit Buffer Interrupt */
222 +#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11)
223 +/* ASC1 Autobaud Start Interrupt */
224 +#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12)
225 +/* ASC1 Autobaud Detection Interrupt */
226 +#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13)
227 +/* ASC1 Modem Status Interrupt */
228 +#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14)
229 +/* ASC1 Soft Flow Control Interrupt */
230 +#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15)
231 +/* GPTC Timer/Counter 1A Interrupt */
232 +#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16)
233 +/* GPTC Timer/Counter 1B Interrupt */
234 +#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17)
235 +/* GPTC Timer/Counter 2A Interrupt */
236 +#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18)
237 +/* GPTC Timer/Counter 2B Interrupt */
238 +#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19)
239 +/* GPTC Timer/Counter 3A Interrupt */
240 +#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20)
241 +/* GPTC Timer/Counter 3B Interrupt */
242 +#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21)
243 +/* DFEV0, Channel 1 Transmit Interrupt */
244 +#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26)
245 +/* DFEV0, Channel 1 Receive Interrupt */
246 +#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27)
247 +/* DFEV0, Channel 1 General Purpose Interrupt */
248 +#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28)
249 +/* DFEV0, Channel 0 Transmit Interrupt */
250 +#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29)
251 +/* DFEV0, Channel 0 Receive Interrupt */
252 +#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30)
253 +/* DFEV0, Channel 0 General Purpose Interrupt */
254 +#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31)
255 +
256 +/* ICTRLL 0 Error */
257 +#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0)
258 +/* ICTRLL 1 Error */
259 +#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1)
260 +/* ICTRLL 2 Error */
261 +#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2)
262 +/* ICTRLL 3 Error */
263 +#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3)
264 +/* OCTRLL 0 Error */
265 +#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4)
266 +/* OCTRLL 1 Error */
267 +#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5)
268 +/* OCTRLL 2 Error */
269 +#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6)
270 +/* OCTRLL 3 Error */
271 +#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7)
272 +/* ICTRLG Error */
273 +#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8)
274 +/* OCTRLG Error */
275 +#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9)
276 +/* IQM Error */
277 +#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10)
278 +/* FSQM Error */
279 +#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11)
280 +/* TMU Error */
281 +#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12)
282 +/* MPS Status Interrupt #0 (VPE1 to VPE0) */
283 +#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14)
284 +/* MPS Status Interrupt #1 (VPE1 to VPE0) */
285 +#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15)
286 +/* MPS Status Interrupt #2 (VPE1 to VPE0) */
287 +#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16)
288 +/* MPS Status Interrupt #3 (VPE1 to VPE0) */
289 +#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17)
290 +/* MPS Status Interrupt #4 (VPE1 to VPE0) */
291 +#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18)
292 +/* MPS Status Interrupt #5 (VPE1 to VPE0) */
293 +#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19)
294 +/* MPS Status Interrupt #6 (VPE1 to VPE0) */
295 +#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20)
296 +/* MPS Status Interrupt #7 (VPE1 to VPE0) */
297 +#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21)
298 +/* MPS Status Interrupt #8 (VPE1 to VPE0) */
299 +#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22)
300 +/* VPE0 Exception Level Flag Interrupt */
301 +#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29)
302 +/* VPE0 Error Level Flag Interrupt */
303 +#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30)
304 +/* VPE0 Performance Monitoring Counter Interrupt */
305 +#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31)
306 +
307 +#endif /* _FALCON_IRQ__ */
308 --- /dev/null
309 +++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
310 @@ -0,0 +1,18 @@
311 +/*
312 + * This program is free software; you can redistribute it and/or modify it
313 + * under the terms of the GNU General Public License version 2 as published
314 + * by the Free Software Foundation.
315 + *
316 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
317 + */
318 +
319 +#ifndef __FALCON_IRQ_H
320 +#define __FALCON_IRQ_H
321 +
322 +#include <falcon_irq.h>
323 +
324 +#define NR_IRQS 328
325 +
326 +#include_next <irq.h>
327 +
328 +#endif
329 --- /dev/null
330 +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
331 @@ -0,0 +1,143 @@
332 +/*
333 + * This program is free software; you can redistribute it and/or modify it
334 + * under the terms of the GNU General Public License version 2 as published
335 + * by the Free Software Foundation.
336 + *
337 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
338 + */
339 +
340 +#ifndef _LTQ_FALCON_H__
341 +#define _LTQ_FALCON_H__
342 +
343 +#ifdef CONFIG_SOC_FALCON
344 +
345 +#include <lantiq.h>
346 +
347 +/* Chip IDs */
348 +#define SOC_ID_FALCON 0x01B8
349 +
350 +/* SoC Types */
351 +#define SOC_TYPE_FALCON 0x01
352 +
353 +/* ASC0/1 - serial port */
354 +#define LTQ_ASC0_BASE_ADDR 0x1E100C00
355 +#define LTQ_ASC1_BASE_ADDR 0x1E100B00
356 +#define LTQ_ASC_SIZE 0x100
357 +
358 +#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
359 +#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
360 +#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
361 +
362 +/*
363 + * during early_printk no ioremap possible at this early stage
364 + * lets use KSEG1 instead
365 + */
366 +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
367 +
368 +/* ICU - interrupt control unit */
369 +#define LTQ_ICU_BASE_ADDR 0x1F880200
370 +#define LTQ_ICU_SIZE 0x100
371 +
372 +/* WDT */
373 +#define LTQ_WDT_BASE_ADDR 0x1F8803F0
374 +#define LTQ_WDT_SIZE 0x10
375 +
376 +#define LTQ_RST_CAUSE_WDTRST 0x0002
377 +
378 +/* EBU - external bus unit */
379 +#define LTQ_EBU_BASE_ADDR 0x18000000
380 +#define LTQ_EBU_SIZE 0x0100
381 +
382 +#define LTQ_EBU_MODCON 0x000C
383 +
384 +/* GPIO */
385 +#define LTQ_GPIO0_BASE_ADDR 0x1D810000
386 +#define LTQ_GPIO0_SIZE 0x0080
387 +#define LTQ_GPIO1_BASE_ADDR 0x1E800100
388 +#define LTQ_GPIO1_SIZE 0x0080
389 +#define LTQ_GPIO2_BASE_ADDR 0x1D810100
390 +#define LTQ_GPIO2_SIZE 0x0080
391 +#define LTQ_GPIO3_BASE_ADDR 0x1E800200
392 +#define LTQ_GPIO3_SIZE 0x0080
393 +#define LTQ_GPIO4_BASE_ADDR 0x1E800300
394 +#define LTQ_GPIO4_SIZE 0x0080
395 +#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000
396 +#define LTQ_PADCTRL0_SIZE 0x0100
397 +#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400
398 +#define LTQ_PADCTRL1_SIZE 0x0100
399 +#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000
400 +#define LTQ_PADCTRL2_SIZE 0x0100
401 +#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500
402 +#define LTQ_PADCTRL3_SIZE 0x0100
403 +#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600
404 +#define LTQ_PADCTRL4_SIZE 0x0100
405 +
406 +/* CHIP ID */
407 +#define LTQ_STATUS_BASE_ADDR 0x1E802000
408 +
409 +#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
410 +#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
411 +#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
412 +
413 +/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
414 +#define LTQ_SYS1_BASE_ADDR 0x1EF00000
415 +#define LTQ_SYS1_SIZE 0x0100
416 +#define LTQ_STATUS_BASE_ADDR 0x1E802000
417 +#define LTQ_STATUS_SIZE 0x0080
418 +#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000
419 +#define LTQ_SYS_ETH_SIZE 0x0100
420 +#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000
421 +#define LTQ_SYS_GPE_SIZE 0x0100
422 +
423 +#define SYSCTL_SYS1 0
424 +#define SYSCTL_SYSETH 1
425 +#define SYSCTL_SYSGPE 2
426 +
427 +/* Activation Status Register */
428 +#define ACTS_ASC1_ACT 0x00000800
429 +#define ACTS_P0 0x00010000
430 +#define ACTS_P1 0x00010000
431 +#define ACTS_P2 0x00020000
432 +#define ACTS_P3 0x00020000
433 +#define ACTS_P4 0x00040000
434 +#define ACTS_PADCTRL0 0x00100000
435 +#define ACTS_PADCTRL1 0x00100000
436 +#define ACTS_PADCTRL2 0x00200000
437 +#define ACTS_PADCTRL3 0x00200000
438 +#define ACTS_PADCTRL4 0x00400000
439 +
440 +extern void ltq_sysctl_activate(int module, unsigned int mask);
441 +extern void ltq_sysctl_deactivate(int module, unsigned int mask);
442 +extern void ltq_sysctl_clken(int module, unsigned int mask);
443 +extern void ltq_sysctl_clkdis(int module, unsigned int mask);
444 +extern void ltq_sysctl_reboot(int module, unsigned int mask);
445 +extern int ltq_gpe_is_activated(unsigned int mask);
446 +
447 +/* global register ranges */
448 +extern __iomem void *ltq_ebu_membase;
449 +extern __iomem void *ltq_sys1_membase;
450 +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
451 +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
452 +#define ltq_ebu_w32_mask(clear, set, reg) \
453 + ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg)
454 +
455 +#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y))
456 +#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x))
457 +#define ltq_sys1_w32_mask(clear, set, reg) \
458 + ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
459 +
460 +/* gpio_request wrapper to help configure the pin */
461 +extern int ltq_gpio_request(unsigned int pin, unsigned int mux,
462 + unsigned int dir, const char *name);
463 +extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
464 +
465 +/* to keep the irq code generic we need to define these to 0 as falcon
466 + has no EIU/EBU */
467 +#define LTQ_EIU_BASE_ADDR 0
468 +#define LTQ_EBU_PCC_ISTAT 0
469 +
470 +#define ltq_is_ar9() 0
471 +#define ltq_is_vr9() 0
472 +
473 +#endif /* CONFIG_SOC_FALCON */
474 +#endif /* _LTQ_XWAY_H__ */
475 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
476 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
477 @@ -25,6 +25,7 @@ extern unsigned int ltq_get_soc_type(voi
478 /* clock speeds */
479 #define CLOCK_60M 60000000
480 #define CLOCK_83M 83333333
481 +#define CLOCK_100M 100000000
482 #define CLOCK_111M 111111111
483 #define CLOCK_133M 133333333
484 #define CLOCK_167M 166666667
485 --- a/arch/mips/lantiq/Kconfig
486 +++ b/arch/mips/lantiq/Kconfig
487 @@ -16,8 +16,12 @@ config SOC_XWAY
488 bool "XWAY"
489 select SOC_TYPE_XWAY
490 select HW_HAS_PCI
491 +
492 +config SOC_FALCON
493 + bool "FALCON"
494 endchoice
495
496 source "arch/mips/lantiq/xway/Kconfig"
497 +source "arch/mips/lantiq/falcon/Kconfig"
498
499 endif
500 --- a/arch/mips/lantiq/Makefile
501 +++ b/arch/mips/lantiq/Makefile
502 @@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devi
503 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
504
505 obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
506 +obj-$(CONFIG_SOC_FALCON) += falcon/
507 --- a/arch/mips/lantiq/Platform
508 +++ b/arch/mips/lantiq/Platform
509 @@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/
510 cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
511 load-$(CONFIG_LANTIQ) = 0xffffffff80002000
512 cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
513 +cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
514 --- /dev/null
515 +++ b/arch/mips/lantiq/falcon/Makefile
516 @@ -0,0 +1 @@
517 +obj-y := clk.o prom.o reset.o sysctrl.o devices.o
518 --- /dev/null
519 +++ b/arch/mips/lantiq/falcon/clk.c
520 @@ -0,0 +1,44 @@
521 +/*
522 + * This program is free software; you can redistribute it and/or modify it
523 + * under the terms of the GNU General Public License version 2 as published
524 + * by the Free Software Foundation.
525 + *
526 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
527 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
528 + */
529 +
530 +#include <linux/ioport.h>
531 +#include <linux/export.h>
532 +
533 +#include <lantiq_soc.h>
534 +
535 +#include "devices.h"
536 +
537 +/* CPU0 Clock Control Register */
538 +#define LTQ_SYS1_CPU0CC 0x0040
539 +/* clock divider bit */
540 +#define LTQ_CPU0CC_CPUDIV 0x0001
541 +
542 +unsigned int
543 +ltq_get_io_region_clock(void)
544 +{
545 + return CLOCK_200M;
546 +}
547 +EXPORT_SYMBOL(ltq_get_io_region_clock);
548 +
549 +unsigned int
550 +ltq_get_cpu_hz(void)
551 +{
552 + if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
553 + return CLOCK_200M;
554 + else
555 + return CLOCK_400M;
556 +}
557 +EXPORT_SYMBOL(ltq_get_cpu_hz);
558 +
559 +unsigned int
560 +ltq_get_fpi_hz(void)
561 +{
562 + return CLOCK_100M;
563 +}
564 +EXPORT_SYMBOL(ltq_get_fpi_hz);
565 --- /dev/null
566 +++ b/arch/mips/lantiq/falcon/devices.c
567 @@ -0,0 +1,87 @@
568 +/*
569 + * This program is free software; you can redistribute it and/or modify it
570 + * under the terms of the GNU General Public License version 2 as published
571 + * by the Free Software Foundation.
572 + *
573 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
574 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
575 + */
576 +
577 +#include <linux/platform_device.h>
578 +#include <linux/mtd/nand.h>
579 +
580 +#include <lantiq_soc.h>
581 +
582 +#include "devices.h"
583 +
584 +/* nand flash */
585 +/* address lines used for NAND control signals */
586 +#define NAND_ADDR_ALE 0x10000
587 +#define NAND_ADDR_CLE 0x20000
588 +/* Ready/Busy Status */
589 +#define MODCON_STS 0x0002
590 +/* Ready/Busy Status Edge */
591 +#define MODCON_STSEDGE 0x0004
592 +
593 +static const char *part_probes[] = { "cmdlinepart", NULL };
594 +
595 +static int
596 +falcon_nand_ready(struct mtd_info *mtd)
597 +{
598 + u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON);
599 +
600 + return (((modcon & (MODCON_STS | MODCON_STSEDGE)) ==
601 + (MODCON_STS | MODCON_STSEDGE)));
602 +}
603 +
604 +static void
605 +falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
606 +{
607 + struct nand_chip *this = mtd->priv;
608 + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
609 +
610 + if (ctrl & NAND_CTRL_CHANGE) {
611 + nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
612 +
613 + if (ctrl & NAND_CLE)
614 + nandaddr |= NAND_ADDR_CLE;
615 + if (ctrl & NAND_ALE)
616 + nandaddr |= NAND_ADDR_ALE;
617 +
618 + this->IO_ADDR_W = (void __iomem *) nandaddr;
619 + }
620 +
621 + if (cmd != NAND_CMD_NONE)
622 + writeb(cmd, this->IO_ADDR_W);
623 +}
624 +
625 +static struct platform_nand_data falcon_flash_nand_data = {
626 + .chip = {
627 + .nr_chips = 1,
628 + .chip_delay = 25,
629 + .part_probe_types = part_probes,
630 + },
631 + .ctrl = {
632 + .cmd_ctrl = falcon_hwcontrol,
633 + .dev_ready = falcon_nand_ready,
634 + }
635 +};
636 +
637 +static struct resource ltq_nand_res =
638 + MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX);
639 +
640 +static struct platform_device ltq_flash_nand = {
641 + .name = "gen_nand",
642 + .id = -1,
643 + .num_resources = 1,
644 + .resource = &ltq_nand_res,
645 + .dev = {
646 + .platform_data = &falcon_flash_nand_data,
647 + },
648 +};
649 +
650 +void __init
651 +falcon_register_nand(void)
652 +{
653 + platform_device_register(&ltq_flash_nand);
654 +}
655 --- /dev/null
656 +++ b/arch/mips/lantiq/falcon/devices.h
657 @@ -0,0 +1,18 @@
658 +/*
659 + * This program is free software; you can redistribute it and/or modify
660 + * it under the terms of the GNU General Public License as published by
661 + * the Free Software Foundation; either version 2 of the License, or
662 + * (at your option) any later version.
663 + *
664 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
665 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
666 + */
667 +
668 +#ifndef _FALCON_DEVICES_H__
669 +#define _FALCON_DEVICES_H__
670 +
671 +#include "../devices.h"
672 +
673 +extern void falcon_register_nand(void);
674 +
675 +#endif
676 --- /dev/null
677 +++ b/arch/mips/lantiq/falcon/prom.c
678 @@ -0,0 +1,93 @@
679 +/*
680 + * This program is free software; you can redistribute it and/or modify it
681 + * under the terms of the GNU General Public License version 2 as published
682 + * by the Free Software Foundation.
683 + *
684 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
685 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
686 + */
687 +
688 +#include <lantiq_soc.h>
689 +
690 +#include "devices.h"
691 +
692 +#include "../prom.h"
693 +
694 +#define SOC_FALCON "Falcon"
695 +#define SOC_FALCON_D "Falcon-D"
696 +#define SOC_FALCON_V "Falcon-V"
697 +#define SOC_FALCON_M "Falcon-M"
698 +
699 +#define PART_SHIFT 12
700 +#define PART_MASK 0x0FFFF000
701 +#define REV_SHIFT 28
702 +#define REV_MASK 0xF0000000
703 +#define SREV_SHIFT 22
704 +#define SREV_MASK 0x03C00000
705 +#define TYPE_SHIFT 26
706 +#define TYPE_MASK 0x3C000000
707 +
708 +#define MUXC_SIF_RX_PIN 112
709 +#define MUXC_SIF_TX_PIN 113
710 +
711 +/* this parameter allows us enable/disable asc1 via commandline */
712 +static int register_asc1;
713 +static int __init
714 +ltq_parse_asc1(char *p)
715 +{
716 + register_asc1 = 1;
717 + return 0;
718 +}
719 +__setup("use_asc1", ltq_parse_asc1);
720 +
721 +void __init
722 +ltq_soc_setup(void)
723 +{
724 + ltq_register_asc(0);
725 + ltq_register_wdt();
726 + falcon_register_gpio();
727 + if (register_asc1) {
728 + ltq_register_asc(1);
729 + if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx"))
730 + pr_err("failed to request asc1-rx");
731 + if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx"))
732 + pr_err("failed to request asc1-tx");
733 + ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT);
734 + }
735 +}
736 +
737 +void __init
738 +ltq_soc_detect(struct ltq_soc_info *i)
739 +{
740 + u32 type;
741 + i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
742 + i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
743 + i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT);
744 + sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
745 + i->rev & 0x7, (i->srev & 0x3) + 1);
746 +
747 + switch (i->partnum) {
748 + case SOC_ID_FALCON:
749 + type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT;
750 + switch (type) {
751 + case 0:
752 + i->name = SOC_FALCON_D;
753 + break;
754 + case 1:
755 + i->name = SOC_FALCON_V;
756 + break;
757 + case 2:
758 + i->name = SOC_FALCON_M;
759 + break;
760 + default:
761 + i->name = SOC_FALCON;
762 + break;
763 + }
764 + i->type = SOC_TYPE_FALCON;
765 + break;
766 +
767 + default:
768 + unreachable();
769 + break;
770 + }
771 +}
772 --- /dev/null
773 +++ b/arch/mips/lantiq/falcon/reset.c
774 @@ -0,0 +1,87 @@
775 +/*
776 + * This program is free software; you can redistribute it and/or modify it
777 + * under the terms of the GNU General Public License version 2 as published
778 + * by the Free Software Foundation.
779 + *
780 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
781 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
782 + */
783 +
784 +#include <linux/init.h>
785 +#include <linux/io.h>
786 +#include <linux/pm.h>
787 +#include <asm/reboot.h>
788 +#include <linux/export.h>
789 +
790 +#include <lantiq_soc.h>
791 +
792 +/* CPU0 Reset Source Register */
793 +#define LTQ_SYS1_CPU0RS 0x0040
794 +/* reset cause mask */
795 +#define LTQ_CPU0RS_MASK 0x0003
796 +
797 +int
798 +ltq_reset_cause(void)
799 +{
800 + return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK;
801 +}
802 +EXPORT_SYMBOL_GPL(ltq_reset_cause);
803 +
804 +#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
805 +#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
806 +#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
807 +#define BOOT_PW1 0x4C545100
808 +#define BOOT_PW2 0x0051544C
809 +
810 +#define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
811 +#define WDT_PW1 0x00BE0000
812 +#define WDT_PW2 0x00DC0000
813 +
814 +static void
815 +ltq_machine_restart(char *command)
816 +{
817 + pr_notice("System restart\n");
818 + local_irq_disable();
819 +
820 + /* reboot magic */
821 + ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
822 + ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
823 + ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
824 +
825 + /* watchdog magic */
826 + ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
827 + ltq_w32(WDT_PW2 |
828 + (0x3 << 26) | /* PWL */
829 + (0x2 << 24) | /* CLKDIV */
830 + (0x1 << 31) | /* enable */
831 + (1), /* reload */
832 + (void *)WDT_REG_BASE);
833 + unreachable();
834 +}
835 +
836 +static void
837 +ltq_machine_halt(void)
838 +{
839 + pr_notice("System halted.\n");
840 + local_irq_disable();
841 + unreachable();
842 +}
843 +
844 +static void
845 +ltq_machine_power_off(void)
846 +{
847 + pr_notice("Please turn off the power now.\n");
848 + local_irq_disable();
849 + unreachable();
850 +}
851 +
852 +static int __init
853 +mips_reboot_setup(void)
854 +{
855 + _machine_restart = ltq_machine_restart;
856 + _machine_halt = ltq_machine_halt;
857 + pm_power_off = ltq_machine_power_off;
858 + return 0;
859 +}
860 +
861 +arch_initcall(mips_reboot_setup);
862 --- /dev/null
863 +++ b/arch/mips/lantiq/falcon/sysctrl.c
864 @@ -0,0 +1,183 @@
865 +/*
866 + * This program is free software; you can redistribute it and/or modify it
867 + * under the terms of the GNU General Public License version 2 as published
868 + * by the Free Software Foundation.
869 + *
870 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
871 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
872 + */
873 +
874 +#include <linux/ioport.h>
875 +#include <linux/export.h>
876 +#include <asm/delay.h>
877 +
878 +#include <lantiq_soc.h>
879 +
880 +#include "devices.h"
881 +
882 +/* infrastructure control register */
883 +#define SYS1_INFRAC 0x00bc
884 +/* Configuration fuses for drivers and pll */
885 +#define STATUS_CONFIG 0x0040
886 +
887 +/* GPE frequency selection */
888 +#define GPPC_OFFSET 24
889 +#define GPEFREQ_MASK 0x00000C0
890 +#define GPEFREQ_OFFSET 10
891 +/* Clock status register */
892 +#define LTQ_SYSCTL_CLKS 0x0000
893 +/* Clock enable register */
894 +#define LTQ_SYSCTL_CLKEN 0x0004
895 +/* Clock clear register */
896 +#define LTQ_SYSCTL_CLKCLR 0x0008
897 +/* Activation Status Register */
898 +#define LTQ_SYSCTL_ACTS 0x0020
899 +/* Activation Register */
900 +#define LTQ_SYSCTL_ACT 0x0024
901 +/* Deactivation Register */
902 +#define LTQ_SYSCTL_DEACT 0x0028
903 +/* reboot Register */
904 +#define LTQ_SYSCTL_RBT 0x002c
905 +
906 +static struct resource ltq_sysctl_res[] = {
907 + MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE),
908 + MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE),
909 + MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE),
910 +};
911 +
912 +static struct resource ltq_status_res =
913 + MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE);
914 +static struct resource ltq_ebu_res =
915 + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
916 +
917 +static void __iomem *ltq_sysctl[3];
918 +static void __iomem *ltq_status_membase;
919 +void __iomem *ltq_sys1_membase;
920 +void __iomem *ltq_ebu_membase;
921 +
922 +#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y))
923 +#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x))
924 +#define ltq_reg_w32_mask(m, clear, set, reg) \
925 + ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg)
926 +
927 +#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y))
928 +#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x))
929 +
930 +static inline void
931 +ltq_sysctl_wait(int module, unsigned int mask,
932 + unsigned int test, unsigned int reg)
933 +{
934 + int err = 1000000;
935 +
936 + do {} while (--err && ((ltq_reg_r32(module, reg)
937 + & mask) != test));
938 + if (!err)
939 + pr_err("module de/activation failed %d %08X %08X\n",
940 + module, mask, test);
941 +}
942 +
943 +void
944 +ltq_sysctl_activate(int module, unsigned int mask)
945 +{
946 + if (module > SYSCTL_SYSGPE)
947 + return;
948 +
949 + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
950 + ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT);
951 + ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
952 +}
953 +EXPORT_SYMBOL(ltq_sysctl_activate);
954 +
955 +void
956 +ltq_sysctl_deactivate(int module, unsigned int mask)
957 +{
958 + if (module > SYSCTL_SYSGPE)
959 + return;
960 +
961 + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
962 + ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT);
963 + ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS);
964 +}
965 +EXPORT_SYMBOL(ltq_sysctl_deactivate);
966 +
967 +void
968 +ltq_sysctl_clken(int module, unsigned int mask)
969 +{
970 + if (module > SYSCTL_SYSGPE)
971 + return;
972 +
973 + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
974 + ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS);
975 +}
976 +EXPORT_SYMBOL(ltq_sysctl_clken);
977 +
978 +void
979 +ltq_sysctl_clkdis(int module, unsigned int mask)
980 +{
981 + if (module > SYSCTL_SYSGPE)
982 + return;
983 +
984 + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
985 + ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS);
986 +}
987 +EXPORT_SYMBOL(ltq_sysctl_clkdis);
988 +
989 +void
990 +ltq_sysctl_reboot(int module, unsigned int mask)
991 +{
992 + unsigned int act;
993 +
994 + if (module > SYSCTL_SYSGPE)
995 + return;
996 +
997 + act = ltq_reg_r32(module, LTQ_SYSCTL_ACT);
998 + if ((~act & mask) != 0)
999 + ltq_sysctl_activate(module, ~act & mask);
1000 + ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT);
1001 + ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
1002 +}
1003 +EXPORT_SYMBOL(ltq_sysctl_reboot);
1004 +
1005 +/* enable the ONU core */
1006 +static void
1007 +ltq_gpe_enable(void)
1008 +{
1009 + unsigned int freq;
1010 + unsigned int status;
1011 +
1012 + /* if if the clock is already enabled */
1013 + status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC);
1014 + if (status & (1 << (GPPC_OFFSET + 1)))
1015 + return;
1016 +
1017 + if (ltq_status_r32(STATUS_CONFIG) == 0)
1018 + freq = 1; /* use 625MHz on unfused chip */
1019 + else
1020 + freq = (ltq_status_r32(STATUS_CONFIG) &
1021 + GPEFREQ_MASK) >>
1022 + GPEFREQ_OFFSET;
1023 +
1024 + /* apply new frequency */
1025 + ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
1026 + freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
1027 + udelay(1);
1028 +
1029 + /* enable new frequency */
1030 + ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
1031 + udelay(1);
1032 +}
1033 +
1034 +void __init
1035 +ltq_soc_init(void)
1036 +{
1037 + int i;
1038 +
1039 + for (i = 0; i < 3; i++)
1040 + ltq_sysctl[i] = ltq_remap_resource(&ltq_sysctl_res[i]);
1041 +
1042 + ltq_sys1_membase = ltq_sysctl[0];
1043 + ltq_status_membase = ltq_remap_resource(&ltq_status_res);
1044 + ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_res);
1045 +
1046 + ltq_gpe_enable();
1047 +}
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