target/linux/lantiq/patches-3.2/0037-MIPS-lantiq-add-additional-soc-ids.patch

   1 From 5585147ea9462778decc7146667ac54413acd91f Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 12 Mar 2012 15:23:39 +0100
   4 Subject: [PATCH 37/73] MIPS: lantiq: add additional soc ids
   5
   6 ---
   7  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   38 +++++++++++++++----
   8  arch/mips/lantiq/xway/prom.c                       |   35 ++++++++++++++++--
   9  2 files changed, 61 insertions(+), 12 deletions(-)
  10
  11 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  12 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  13 @@ -17,20 +17,32 @@
  14  #define SOC_ID_DANUBE1         0x129
  15  #define SOC_ID_DANUBE2         0x12B
  16  #define SOC_ID_TWINPASS                0x12D
  17 -#define SOC_ID_AMAZON_SE       0x152
  18 +#define SOC_ID_AMAZON_SE_1     0x152 /* 50601 */
  19 +#define SOC_ID_AMAZON_SE_2     0x153 /* 50600 */
  20  #define SOC_ID_ARX188          0x16C
  21 -#define SOC_ID_ARX168          0x16D
  22 +#define SOC_ID_ARX168_1                0x16D
  23 +#define SOC_ID_ARX168_2                0x16E
  24  #define SOC_ID_ARX182          0x16F
  25 -#define SOC_ID_VRX288          0x1C0 /* VRX288 v1.1 */
  26 -#define SOC_ID_VRX268          0x1C2 /* VRX268 v1.1 */
  27 -#define SOC_ID_GRX288          0x1C9 /* GRX288 v1.1 */
  28 +#define SOC_ID_GRX188          0x170
  29 +#define SOC_ID_GRX168          0x171
  30 +
  31 +#define SOC_ID_VRX288          0x1C0 /* v1.1 */
  32 +#define SOC_ID_VRX282          0x1C1 /* v1.1 */
  33 +#define SOC_ID_VRX268          0x1C2 /* v1.1 */
  34 +#define SOC_ID_GRX268          0x1C8 /* v1.1 */
  35 +#define SOC_ID_GRX288          0x1C9 /* v1.1 */
  36 +#define SOC_ID_VRX288_2                0x00B /* v1.2 */
  37 +#define SOC_ID_VRX268_2                0x00C /* v1.2 */
  38 +#define SOC_ID_GRX288_2                0x00D /* v1.2 */
  39 +#define SOC_ID_GRX282_2                0x00E /* v1.2 */
  40
  41  /* SoC Types */
  42  #define SOC_TYPE_DANUBE                0x01
  43  #define SOC_TYPE_TWINPASS      0x02
  44  #define SOC_TYPE_AR9           0x03
  45 -#define SOC_TYPE_VR9           0x04
  46 -#define SOC_TYPE_AMAZON_SE     0x05
  47 +#define SOC_TYPE_VR9_1         0x04 /* v1.1 */
  48 +#define SOC_TYPE_VR9_2         0x05 /* v1.2 */
  49 +#define SOC_TYPE_AMAZON_SE     0x06
  50
  51  /* ASC0/1 - serial port */
  52  #define LTQ_ASC0_BASE_ADDR     0x1E100400
  53 @@ -149,9 +161,19 @@ static inline int ltq_is_ar9(void)
  54         return (ltq_get_soc_type() == SOC_TYPE_AR9);
  55  }
  56
  57 +static inline int ltq_is_vr9_1(void)
  58 +{
  59 +       return (ltq_get_soc_type() == SOC_TYPE_VR9_1);
  60 +}
  61 +
  62 +static inline int ltq_is_vr9_2(void)
  63 +{
  64 +       return (ltq_get_soc_type() == SOC_TYPE_VR9_2);
  65 +}
  66 +
  67  static inline int ltq_is_vr9(void)
  68  {
  69 -       return (ltq_get_soc_type() == SOC_TYPE_VR9);
  70 +       return (ltq_is_vr9_1() || ltq_is_vr9_2());
  71  }
  72
  73  static inline int ltq_is_falcon(void)
  74 --- a/arch/mips/lantiq/xway/prom.c
  75 +++ b/arch/mips/lantiq/xway/prom.c
  76 @@ -18,7 +18,9 @@
  77
  78  #define SOC_DANUBE     "Danube"
  79  #define SOC_TWINPASS   "Twinpass"
  80 +#define SOC_AMAZON_SE  "Amazon_SE"
  81  #define SOC_AR9                "AR9"
  82 +#define SOC_GR9                "GR9"
  83  #define SOC_VR9                "VR9"
  84
  85  #define PART_SHIFT     12
  86 @@ -26,7 +28,6 @@
  87  #define REV_SHIFT      28
  88  #define REV_MASK       0xF0000000
  89
  90 -#define SOC_AMAZON_SE  "Amazon_SE"
  91
  92  void __init ltq_soc_detect(struct ltq_soc_info *i)
  93  {
  94 @@ -46,13 +47,21 @@ void __init ltq_soc_detect(struct ltq_so
  95                 break;
  96
  97         case SOC_ID_ARX188:
  98 -       case SOC_ID_ARX168:
  99 +       case SOC_ID_ARX168_1:
 100 +       case SOC_ID_ARX168_2:
 101         case SOC_ID_ARX182:
 102                 i->name = SOC_AR9;
 103                 i->type = SOC_TYPE_AR9;
 104                 break;
 105
 106 -       case SOC_ID_AMAZON_SE:
 107 +       case SOC_ID_GRX188:
 108 +       case SOC_ID_GRX168:
 109 +               i->name = SOC_GR9;
 110 +               i->type = SOC_TYPE_AR9;
 111 +               break;
 112 +
 113 +       case SOC_ID_AMAZON_SE_1:
 114 +       case SOC_ID_AMAZON_SE_2:
 115                 i->name = SOC_AMAZON_SE;
 116                 i->type = SOC_TYPE_AMAZON_SE;
 117  #ifdef CONFIG_PCI
 118 @@ -60,12 +69,30 @@ void __init ltq_soc_detect(struct ltq_so
 119  #endif
 120                 break;
 121
 122 +       case SOC_ID_VRX282:
 123         case SOC_ID_VRX268:
 124         case SOC_ID_VRX288:
 125                 i->name = SOC_VR9;
 126 -               i->type = SOC_TYPE_VR9;
 127 +               i->type = SOC_TYPE_VR9_1;
 128                 break;
 129
 130 +       case SOC_ID_GRX268:
 131 +       case SOC_ID_GRX288:
 132 +               i->name = SOC_GR9;
 133 +               i->type = SOC_TYPE_VR9_1;
 134 +               break;
 135 +
 136 +       case SOC_ID_VRX268_2:
 137 +       case SOC_ID_VRX288_2:
 138 +               i->name = SOC_VR9;
 139 +               i->type = SOC_TYPE_VR9_2;
 140 +               break;
 141 +
 142 +       case SOC_ID_GRX282_2:
 143 +       case SOC_ID_GRX288_2:
 144 +               i->name = SOC_GR9;
 145 +               i->type = SOC_TYPE_VR9_2;
 146 +
 147         default:
 148                 unreachable();
 149                 break;