target/linux/lantiq/patches-3.2/0039-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch

   1 From 9732ec2d97f001961f670d12f342df9b70db27ea Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 4 Nov 2011 16:00:34 +0100
   4 Subject: [PATCH 39/73] I2C: MIPS: lantiq: add FALC-ON i2c bus master
   5
   6 This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs.
   7
   8 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Cc: linux-i2c@vger.kernel.org
  11 ---
  12  .../include/asm/mach-lantiq/falcon/lantiq_soc.h    |    5 +
  13  arch/mips/lantiq/falcon/clk.c                      |   44 -
  14  arch/mips/lantiq/falcon/devices.c                  |   16 +
  15  arch/mips/lantiq/falcon/devices.h                  |    1 +
  16  arch/mips/lantiq/falcon/mach-easy98000.c           |    1 +
  17  drivers/i2c/busses/Kconfig                         |   10 +
  18  drivers/i2c/busses/Makefile                        |    1 +
  19  drivers/i2c/busses/i2c-falcon.c                    | 1040 ++++++++++++++++++++
  20  8 files changed, 1074 insertions(+), 44 deletions(-)
  21  delete mode 100644 arch/mips/lantiq/falcon/clk.c
  22  create mode 100644 drivers/i2c/busses/i2c-falcon.c
  23
  24 --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
  25 +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
  26 @@ -72,6 +72,10 @@
  27  #define LTQ_PADCTRL4_BASE_ADDR  0x1E800600
  28  #define LTQ_PADCTRL4_SIZE       0x0100
  29
  30 +/* I2C */
  31 +#define GPON_I2C_BASE          0x1E200000
  32 +#define GPON_I2C_SIZE          0x00010000
  33 +
  34  /* CHIP ID */
  35  #define LTQ_STATUS_BASE_ADDR   0x1E802000
  36
  37 @@ -106,6 +110,7 @@
  38  #define ACTS_PADCTRL2  0x00200000
  39  #define ACTS_PADCTRL3  0x00200000
  40  #define ACTS_PADCTRL4  0x00400000
  41 +#define ACTS_I2C_ACT   0x00004000
  42
  43  /* global register ranges */
  44  extern __iomem void *ltq_ebu_membase;
  45 --- a/arch/mips/lantiq/falcon/clk.c
  46 +++ /dev/null
  47 @@ -1,44 +0,0 @@
  48 -/*
  49 - * This program is free software; you can redistribute it and/or modify it
  50 - * under the terms of the GNU General Public License version 2 as published
  51 - * by the Free Software Foundation.
  52 - *
  53 - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
  54 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  55 - */
  56 -
  57 -#include <linux/ioport.h>
  58 -#include <linux/export.h>
  59 -
  60 -#include <lantiq_soc.h>
  61 -
  62 -#include "devices.h"
  63 -
  64 -/* CPU0 Clock Control Register */
  65 -#define LTQ_SYS1_CPU0CC                0x0040
  66 -/* clock divider bit */
  67 -#define LTQ_CPU0CC_CPUDIV      0x0001
  68 -
  69 -unsigned int
  70 -ltq_get_io_region_clock(void)
  71 -{
  72 -       return CLOCK_200M;
  73 -}
  74 -EXPORT_SYMBOL(ltq_get_io_region_clock);
  75 -
  76 -unsigned int
  77 -ltq_get_cpu_hz(void)
  78 -{
  79 -       if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
  80 -               return CLOCK_200M;
  81 -       else
  82 -               return CLOCK_400M;
  83 -}
  84 -EXPORT_SYMBOL(ltq_get_cpu_hz);
  85 -
  86 -unsigned int
  87 -ltq_get_fpi_hz(void)
  88 -{
  89 -       return CLOCK_100M;
  90 -}
  91 -EXPORT_SYMBOL(ltq_get_fpi_hz);
  92 --- a/arch/mips/lantiq/falcon/devices.c
  93 +++ b/arch/mips/lantiq/falcon/devices.c
  94 @@ -134,3 +134,19 @@ falcon_register_spi_flash(struct spi_boa
  95         spi_register_board_info(data, 1);
  96         platform_device_register(&ltq_spi);
  97  }
  98 +
  99 +/* i2c */
 100 +static struct resource falcon_i2c_resources[] = {
 101 +       MEM_RES("i2c", GPON_I2C_BASE, GPON_I2C_SIZE),
 102 +       IRQ_RES(i2c_lb, FALCON_IRQ_I2C_LBREQ),
 103 +       IRQ_RES(i2c_b, FALCON_IRQ_I2C_BREQ),
 104 +       IRQ_RES(i2c_err, FALCON_IRQ_I2C_I2C_ERR),
 105 +       IRQ_RES(i2c_p, FALCON_IRQ_I2C_I2C_P),
 106 +};
 107 +
 108 +void __init
 109 +falcon_register_i2c(void)
 110 +{
 111 +       platform_device_register_simple("i2c-falcon", 0,
 112 +               falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
 113 +}
 114 --- a/arch/mips/lantiq/falcon/devices.h
 115 +++ b/arch/mips/lantiq/falcon/devices.h
 116 @@ -20,5 +20,6 @@ extern void falcon_register_nand(void);
 117  extern void falcon_register_gpio(void);
 118  extern void falcon_register_gpio_extra(void);
 119  extern void falcon_register_spi_flash(struct spi_board_info *data);
 120 +extern void falcon_register_i2c(void);
 121
 122  #endif
 123 --- a/arch/mips/lantiq/falcon/mach-easy98000.c
 124 +++ b/arch/mips/lantiq/falcon/mach-easy98000.c
 125 @@ -98,6 +98,7 @@ easy98000_init_common(void)
 126  {
 127         spi_register_board_info(&easy98000_spi_gpio_devices, 1);
 128         platform_device_register(&easy98000_spi_gpio_device);
 129 +       falcon_register_i2c();
 130  }
 131
 132  static void __init
 133 --- a/drivers/i2c/busses/Kconfig
 134 +++ b/drivers/i2c/busses/Kconfig
 135 @@ -369,6 +369,16 @@ config I2C_DESIGNWARE_PCI
 136           This driver can also be built as a module.  If so, the module
 137           will be called i2c-designware-pci.
 138
 139 +config I2C_FALCON
 140 +       tristate "Falcon I2C interface"
 141 +       depends on SOC_FALCON
 142 +       help
 143 +         If you say yes to this option, support will be included for the
 144 +         Lantiq FALC-ON I2C core.
 145 +
 146 +         This driver can also be built as a module. If so, the module
 147 +         will be called i2c-falcon.
 148 +
 149  config I2C_GPIO
 150         tristate "GPIO-based bitbanging I2C"
 151         depends on GENERIC_GPIO
 152 --- a/drivers/i2c/busses/Makefile
 153 +++ b/drivers/i2c/busses/Makefile
 154 @@ -37,6 +37,7 @@ obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) +=
 155  i2c-designware-platform-objs := i2c-designware-platdrv.o i2c-designware-core.o
 156  obj-$(CONFIG_I2C_DESIGNWARE_PCI)       += i2c-designware-pci.o
 157  i2c-designware-pci-objs := i2c-designware-pcidrv.o i2c-designware-core.o
 158 +obj-$(CONFIG_I2C_FALCON)       += i2c-falcon.o
 159  obj-$(CONFIG_I2C_GPIO)         += i2c-gpio.o
 160  obj-$(CONFIG_I2C_HIGHLANDER)   += i2c-highlander.o
 161  obj-$(CONFIG_I2C_IBM_IIC)      += i2c-ibm_iic.o
 162 --- /dev/null
 163 +++ b/drivers/i2c/busses/i2c-falcon.c
 164 @@ -0,0 +1,1040 @@
 165 +/*
 166 + * Lantiq FALC(tm) ON - I2C bus adapter
 167 + *
 168 + * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33
 169 + *
 170 + * This program is free software; you can redistribute it and/or modify
 171 + * it under the terms of the GNU General Public License as published by
 172 + * the Free Software Foundation; either version 2 of the License, or
 173 + * (at your option) any later version.
 174 + *
 175 + * This program is distributed in the hope that it will be useful,
 176 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 177 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 178 + * GNU General Public License for more details.
 179 + *
 180 + * You should have received a copy of the GNU General Public License
 181 + * along with this program; if not, write to the Free Software
 182 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 183 + *
 184 + * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
 185 + */
 186 +
 187 +/*
 188 + * CURRENT ISSUES:
 189 + * - no high speed support
 190 + * - supports only master mode
 191 + * - ten bit mode is not tested (no slave devices)
 192 + */
 193 +
 194 +#include <linux/kernel.h>
 195 +#include <linux/module.h>
 196 +#include <linux/delay.h>
 197 +#include <linux/slab.h>
 198 +#include <linux/i2c.h>
 199 +#include <linux/clk.h>
 200 +#include <linux/errno.h>
 201 +#include <linux/sched.h>
 202 +#include <linux/err.h>
 203 +#include <linux/interrupt.h>
 204 +#include <linux/platform_device.h>
 205 +#include <linux/io.h>
 206 +#include <linux/err.h>
 207 +#include <linux/gpio.h>
 208 +
 209 +#include <lantiq_soc.h>
 210 +
 211 +/* I2C Identification Register */
 212 +/* Module ID */
 213 +#define I2C_ID_ID_MASK 0x0000FF00
 214 +/* field offset */
 215 +#define I2C_ID_ID_OFFSET 8
 216 +/* Revision */
 217 +#define I2C_ID_REV_MASK 0x000000FF
 218 +/* field offset */
 219 +#define I2C_ID_REV_OFFSET 0
 220 +
 221 +/* I2C Error Interrupt Request Source Status Register */
 222 +/* TXF_OFL */
 223 +#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
 224 +/* TXF_UFL */
 225 +#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
 226 +/* RXF_OFL */
 227 +#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
 228 +/* RXF_UFL */
 229 +#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
 230 +
 231 +/* I2C Bus Status Register */
 232 +/* Bus Status */
 233 +#define I2C_BUS_STAT_BS_MASK 0x00000003
 234 +/* I2C Bus is free. */
 235 +#define I2C_BUS_STAT_BS_FREE 0x00000000
 236 +/*
 237 + * The device is working as master and has claimed the control
 238 + * on the I2C-bus (busy master).
 239 + */
 240 +#define I2C_BUS_STAT_BS_BM 0x00000002
 241 +
 242 +/* I2C Interrupt Clear Register */
 243 +/* Clear */
 244 +#define I2C_ICR_BREQ_INT_CLR 0x00000008
 245 +/* Clear */
 246 +#define I2C_ICR_LBREQ_INT_CLR 0x00000004
 247 +
 248 +/* I2C RUN Control Register */
 249 +/* Enable */
 250 +#define I2C_RUN_CTRL_RUN_EN 0x00000001
 251 +
 252 +/* I2C Kernel Clock Control Register */
 253 +/* field offset */
 254 +#define I2C_CLC_RMC_OFFSET 8
 255 +/* Enable */
 256 +#define I2C_IMSC_I2C_P_INT_EN 0x00000020
 257 +/* Enable */
 258 +#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
 259 +/* Enable */
 260 +#define I2C_IMSC_BREQ_INT_EN 0x00000008
 261 +/* Enable */
 262 +#define I2C_IMSC_LBREQ_INT_EN 0x00000004
 263 +
 264 +/* I2C Fractional Divider Configuration Register */
 265 +/* field offset */
 266 +#define I2C_FDIV_CFG_INC_OFFSET 16
 267 +/* field offset */
 268 +#define I2C_FDIV_CFG_DEC_OFFSET 0
 269 +
 270 +/* I2C Fractional Divider (highspeed mode) Configuration Register */
 271 +/* field offset */
 272 +#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16
 273 +/* field offset */
 274 +#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0
 275 +
 276 +/* I2C Address Register */
 277 +/* Enable */
 278 +#define I2C_ADDR_CFG_SOPE_EN 0x00200000
 279 +/* Enable */
 280 +#define I2C_ADDR_CFG_SONA_EN 0x00100000
 281 +/* Enable */
 282 +#define I2C_ADDR_CFG_MnS_EN 0x00080000
 283 +
 284 +/* I2C Protocol Interrupt Request Source Status Register */
 285 +/* RX */
 286 +#define I2C_P_IRQSS_RX 0x00000040
 287 +/* TX_END */
 288 +#define I2C_P_IRQSS_TX_END 0x00000020
 289 +/* NACK */
 290 +#define I2C_P_IRQSS_NACK 0x00000010
 291 +/* AL */
 292 +#define I2C_P_IRQSS_AL 0x00000008
 293 +
 294 +/* I2C Raw Interrupt Status Register */
 295 +/* Read: Interrupt occurred. */
 296 +#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
 297 +/* Read: Interrupt occurred. */
 298 +#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
 299 +
 300 +/* I2C End Data Control Register */
 301 +/*
 302 + * Set End of Transmission - Note: Do not write '1' to this bit when bus is
 303 + * free. This will cause an abort after the first byte when a new transfer
 304 + * is started.
 305 + */
 306 +#define I2C_ENDD_CTRL_SETEND 0x00000002
 307 +/* TX FIFO Flow Control */
 308 +#define I2C_FIFO_CFG_TXFC 0x00020000
 309 +/* RX FIFO Flow Control */
 310 +#define I2C_FIFO_CFG_RXFC 0x00010000
 311 +/* Word aligned (character alignment of four characters) */
 312 +#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
 313 +/* Word aligned (character alignment of four characters) */
 314 +#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
 315 +/* 1 word */
 316 +#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
 317 +/* 1 word */
 318 +#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
 319 +
 320 +
 321 +/* I2C register structure */
 322 +struct gpon_reg_i2c {
 323 +       /* I2C Kernel Clock Control Register */
 324 +       unsigned int clc; /* 0x00000000 */
 325 +       /* Reserved */
 326 +       unsigned int res_0; /* 0x00000004 */
 327 +       /* I2C Identification Register */
 328 +       unsigned int id; /* 0x00000008 */
 329 +       /* Reserved */
 330 +       unsigned int res_1; /* 0x0000000C */
 331 +       /*
 332 +        * I2C RUN Control Register - This register enables and disables the I2C
 333 +        * peripheral. Before enabling, the I2C has to be configured properly.
 334 +        * After enabling no configuration is possible
 335 +        */
 336 +       unsigned int run_ctrl; /* 0x00000010 */
 337 +       /*
 338 +        * I2C End Data Control Register - This register is used to either turn
 339 +        * around the data transmission direction or to address another slave
 340 +        * without sending a stop condition. Also the software can stop the
 341 +        * slave-transmitter by sending a not-accolade when working as
 342 +        * master-receiver or even stop data transmission immediately when
 343 +        * operating as master-transmitter. The writing to the bits of this
 344 +        * control register is only effective when in MASTER RECEIVES BYTES,
 345 +        * MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state
 346 +        */
 347 +       unsigned int endd_ctrl; /* 0x00000014 */
 348 +       /*
 349 +        * I2C Fractional Divider Configuration Register - These register is
 350 +        * used to program the fractional divider of the I2C bus. Before the
 351 +        * peripheral is switched on by setting the RUN-bit the two (fixed)
 352 +        * values for the two operating frequencies are programmed into these
 353 +        * (configuration) registers. The Register FDIV_HIGH_CFG has the same
 354 +        * layout as I2C_FDIV_CFG.
 355 +        */
 356 +       unsigned int fdiv_cfg; /* 0x00000018 */
 357 +       /*
 358 +        * I2C Fractional Divider (highspeed mode) Configuration Register
 359 +        * These register is used to program the fractional divider of the I2C
 360 +        * bus. Before the peripheral is switched on by setting the RUN-bit the
 361 +        * two (fixed) values for the two operating frequencies are programmed
 362 +        * into these (configuration) registers. The Register FDIV_CFG has the
 363 +        * same layout as I2C_FDIV_CFG.
 364 +        */
 365 +       unsigned int fdiv_high_cfg; /* 0x0000001C */
 366 +       /* I2C Address Configuration Register */
 367 +       unsigned int addr_cfg; /* 0x00000020 */
 368 +       /*
 369 +        * I2C Bus Status Register - This register gives a status information
 370 +        * of the I2C. This additional information can be used by the software
 371 +        * to start proper actions.
 372 +        */
 373 +       unsigned int bus_stat; /* 0x00000024 */
 374 +       /* I2C FIFO Configuration Register */
 375 +       unsigned int fifo_cfg; /* 0x00000028 */
 376 +       /* I2C Maximum Received Packet Size Register */
 377 +       unsigned int mrps_ctrl; /* 0x0000002C */
 378 +       /* I2C Received Packet Size Status Register */
 379 +       unsigned int rps_stat; /* 0x00000030 */
 380 +       /* I2C Transmit Packet Size Register */
 381 +       unsigned int tps_ctrl; /* 0x00000034 */
 382 +       /* I2C Filled FIFO Stages Status Register */
 383 +       unsigned int ffs_stat; /* 0x00000038 */
 384 +       /* Reserved */
 385 +       unsigned int res_2; /* 0x0000003C */
 386 +       /* I2C Timing Configuration Register */
 387 +       unsigned int tim_cfg; /* 0x00000040 */
 388 +       /* Reserved */
 389 +               unsigned int res_3[7]; /* 0x00000044 */
 390 +       /* I2C Error Interrupt Request Source Mask Register */
 391 +       unsigned int err_irqsm; /* 0x00000060 */
 392 +       /* I2C Error Interrupt Request Source Status Register */
 393 +       unsigned int err_irqss; /* 0x00000064 */
 394 +       /* I2C Error Interrupt Request Source Clear Register */
 395 +       unsigned int err_irqsc; /* 0x00000068 */
 396 +       /* Reserved */
 397 +       unsigned int res_4; /* 0x0000006C */
 398 +       /* I2C Protocol Interrupt Request Source Mask Register */
 399 +       unsigned int p_irqsm; /* 0x00000070 */
 400 +       /* I2C Protocol Interrupt Request Source Status Register */
 401 +       unsigned int p_irqss; /* 0x00000074 */
 402 +       /* I2C Protocol Interrupt Request Source Clear Register */
 403 +       unsigned int p_irqsc; /* 0x00000078 */
 404 +       /* Reserved */
 405 +       unsigned int res_5; /* 0x0000007C */
 406 +       /* I2C Raw Interrupt Status Register */
 407 +       unsigned int ris; /* 0x00000080 */
 408 +       /* I2C Interrupt Mask Control Register */
 409 +       unsigned int imsc; /* 0x00000084 */
 410 +       /* I2C Masked Interrupt Status Register */
 411 +       unsigned int mis; /* 0x00000088 */
 412 +       /* I2C Interrupt Clear Register */
 413 +       unsigned int icr; /* 0x0000008C */
 414 +       /* I2C Interrupt Set Register */
 415 +       unsigned int isr; /* 0x00000090 */
 416 +       /* I2C DMA Enable Register */
 417 +       unsigned int dmae; /* 0x00000094 */
 418 +       /* Reserved */
 419 +       unsigned int res_6[8154]; /* 0x00000098 */
 420 +       /* I2C Transmit Data Register */
 421 +       unsigned int txd; /* 0x00008000 */
 422 +       /* Reserved */
 423 +       unsigned int res_7[4095]; /* 0x00008004 */
 424 +       /* I2C Receive Data Register */
 425 +       unsigned int rxd; /* 0x0000C000 */
 426 +       /* Reserved */
 427 +       unsigned int res_8[4095]; /* 0x0000C004 */
 428 +};
 429 +
 430 +/* mapping for access macros */
 431 +#define i2c    ((struct gpon_reg_i2c *)priv->membase)
 432 +#define reg_r32(reg)           __raw_readl(reg)
 433 +#define reg_w32(val, reg)      __raw_writel(val, reg)
 434 +#define reg_w32_mask(clear, set, reg)  \
 435 +                               reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
 436 +#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)&reg)[idx])
 437 +#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)&reg)[idx])
 438 +
 439 +#define i2c_r32(reg) reg_r32(&i2c->reg)
 440 +#define i2c_w32(val, reg) reg_w32(val, &i2c->reg)
 441 +#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg)
 442 +
 443 +#define DRV_NAME "i2c-falcon"
 444 +#define DRV_VERSION "1.01"
 445 +
 446 +#define FALCON_I2C_BUSY_TIMEOUT                20 /* ms */
 447 +
 448 +#ifdef DEBUG
 449 +#define FALCON_I2C_XFER_TIMEOUT                (25 * HZ)
 450 +#else
 451 +#define FALCON_I2C_XFER_TIMEOUT                HZ
 452 +#endif
 453 +#if defined(DEBUG) && 0
 454 +#define PRINTK(arg...) pr_info(arg)
 455 +#else
 456 +#define PRINTK(arg...) do {} while (0)
 457 +#endif
 458 +
 459 +#define FALCON_I2C_IMSC_DEFAULT_MASK   (I2C_IMSC_I2C_P_INT_EN | \
 460 +                                        I2C_IMSC_I2C_ERR_INT_EN)
 461 +
 462 +#define FALCON_I2C_ARB_LOST    (1 << 0)
 463 +#define FALCON_I2C_NACK                (1 << 1)
 464 +#define FALCON_I2C_RX_UFL      (1 << 2)
 465 +#define FALCON_I2C_RX_OFL      (1 << 3)
 466 +#define FALCON_I2C_TX_UFL      (1 << 4)
 467 +#define FALCON_I2C_TX_OFL      (1 << 5)
 468 +
 469 +struct falcon_i2c {
 470 +       struct mutex mutex;
 471 +
 472 +       enum {
 473 +               FALCON_I2C_MODE_100     = 1,
 474 +               FALCON_I2C_MODE_400     = 2,
 475 +               FALCON_I2C_MODE_3400    = 3
 476 +       } mode;                         /* current speed mode */
 477 +
 478 +       struct clk *clk;                /* clock input for i2c hardware block */
 479 +       struct gpon_reg_i2c __iomem *membase;   /* base of mapped registers */
 480 +       int irq_lb, irq_b, irq_err, irq_p;      /* last burst, burst, error,
 481 +                                                  protocol IRQs */
 482 +
 483 +       struct i2c_adapter adap;
 484 +       struct device *dev;
 485 +
 486 +       struct completion       cmd_complete;
 487 +
 488 +       /* message transfer data */
 489 +       /* current message */
 490 +       struct i2c_msg          *current_msg;
 491 +       /* number of messages to handle */
 492 +       int                     msgs_num;
 493 +       /* current buffer */
 494 +       u8                      *msg_buf;
 495 +       /* remaining length of current buffer */
 496 +       u32                     msg_buf_len;
 497 +       /* error status of the current transfer */
 498 +       int                     msg_err;
 499 +
 500 +       /* master status codes */
 501 +       enum {
 502 +               STATUS_IDLE,
 503 +               STATUS_ADDR,    /* address phase */
 504 +               STATUS_WRITE,
 505 +               STATUS_READ,
 506 +               STATUS_READ_END,
 507 +               STATUS_STOP
 508 +       } status;
 509 +};
 510 +
 511 +static irqreturn_t falcon_i2c_isr(int irq, void *dev_id);
 512 +
 513 +static inline void enable_burst_irq(struct falcon_i2c *priv)
 514 +{
 515 +       i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
 516 +}
 517 +static inline void disable_burst_irq(struct falcon_i2c *priv)
 518 +{
 519 +       i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
 520 +}
 521 +
 522 +static void prepare_msg_send_addr(struct falcon_i2c *priv)
 523 +{
 524 +       struct i2c_msg *msg = priv->current_msg;
 525 +       int rd = !!(msg->flags & I2C_M_RD);
 526 +       u16 addr = msg->addr;
 527 +
 528 +       /* new i2c_msg */
 529 +       priv->msg_buf = msg->buf;
 530 +       priv->msg_buf_len = msg->len;
 531 +       if (rd)
 532 +               priv->status = STATUS_READ;
 533 +       else
 534 +               priv->status = STATUS_WRITE;
 535 +
 536 +       /* send slave address */
 537 +       if (msg->flags & I2C_M_TEN) {
 538 +               i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);
 539 +               i2c_w32(addr & 0xff, txd);
 540 +       } else
 541 +               i2c_w32((addr & 0x7f) << 1 | rd, txd);
 542 +}
 543 +
 544 +static void set_tx_len(struct falcon_i2c *priv)
 545 +{
 546 +       struct i2c_msg *msg = priv->current_msg;
 547 +       int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
 548 +
 549 +       PRINTK("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? ('R') : ('T'));
 550 +
 551 +       priv->status = STATUS_ADDR;
 552 +
 553 +       if (!(msg->flags & I2C_M_RD)) {
 554 +               len += msg->len;
 555 +       } else {
 556 +               /* set maximum received packet size (before rx int!) */
 557 +               i2c_w32(msg->len, mrps_ctrl);
 558 +       }
 559 +       i2c_w32(len, tps_ctrl);
 560 +       enable_burst_irq(priv);
 561 +}
 562 +
 563 +static int falcon_i2c_hw_init(struct i2c_adapter *adap)
 564 +{
 565 +       struct falcon_i2c *priv = i2c_get_adapdata(adap);
 566 +
 567 +       /* disable bus */
 568 +       i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 569 +
 570 +#ifndef DEBUG
 571 +       /* set normal operation clock divider */
 572 +       i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
 573 +#else
 574 +       /* for debugging a higher divider value! */
 575 +       i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);
 576 +#endif
 577 +
 578 +       /* set frequency */
 579 +       if (priv->mode == FALCON_I2C_MODE_100) {
 580 +               dev_dbg(priv->dev, "set standard mode (100 kHz)\n");
 581 +               i2c_w32(0, fdiv_high_cfg);
 582 +               i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) |
 583 +                       (499 << I2C_FDIV_CFG_DEC_OFFSET),
 584 +                       fdiv_cfg);
 585 +       } else if (priv->mode == FALCON_I2C_MODE_400) {
 586 +               dev_dbg(priv->dev, "set fast mode (400 kHz)\n");
 587 +               i2c_w32(0, fdiv_high_cfg);
 588 +               i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) |
 589 +                       (124 << I2C_FDIV_CFG_DEC_OFFSET),
 590 +                       fdiv_cfg);
 591 +       } else if (priv->mode == FALCON_I2C_MODE_3400) {
 592 +               dev_dbg(priv->dev, "set high mode (3.4 MHz)\n");
 593 +               i2c_w32(0, fdiv_cfg);
 594 +               /* TODO recalculate value for 100MHz input */
 595 +               i2c_w32((41 << I2C_FDIV_HIGH_CFG_INC_OFFSET) |
 596 +                       (152 << I2C_FDIV_HIGH_CFG_DEC_OFFSET),
 597 +                       fdiv_high_cfg);
 598 +       } else {
 599 +               dev_warn(priv->dev, "unknown mode\n");
 600 +               return -ENODEV;
 601 +       }
 602 +
 603 +       /* configure fifo */
 604 +       i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */
 605 +               I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */
 606 +               I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */
 607 +               I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */
 608 +               I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */
 609 +               I2C_FIFO_CFG_RXBS_RXBS0,  /* rx fifo burst size is 1 word */
 610 +               fifo_cfg);
 611 +
 612 +       /* configure address */
 613 +       i2c_w32(I2C_ADDR_CFG_SOPE_EN |  /* generate stop when no more data
 614 +                                          in the fifo */
 615 +               I2C_ADDR_CFG_SONA_EN |  /* generate stop when NA received */
 616 +               I2C_ADDR_CFG_MnS_EN |   /* we are master device */
 617 +               0,                      /* our slave address (not used!) */
 618 +               addr_cfg);
 619 +
 620 +       /* enable bus */
 621 +       i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
 622 +
 623 +       return 0;
 624 +}
 625 +
 626 +static int falcon_i2c_wait_bus_not_busy(struct falcon_i2c *priv)
 627 +{
 628 +       int timeout = FALCON_I2C_BUSY_TIMEOUT;
 629 +
 630 +       while ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK)
 631 +                                != I2C_BUS_STAT_BS_FREE) {
 632 +               if (timeout <= 0) {
 633 +                       dev_warn(priv->dev, "timeout waiting for bus ready\n");
 634 +                       return -ETIMEDOUT;
 635 +               }
 636 +               timeout--;
 637 +               mdelay(1);
 638 +       }
 639 +
 640 +       return 0;
 641 +}
 642 +
 643 +static void falcon_i2c_tx(struct falcon_i2c *priv, int last)
 644 +{
 645 +       if (priv->msg_buf_len && priv->msg_buf) {
 646 +               i2c_w32(*priv->msg_buf, txd);
 647 +
 648 +               if (--priv->msg_buf_len)
 649 +                       priv->msg_buf++;
 650 +               else
 651 +                       priv->msg_buf = NULL;
 652 +       } else
 653 +               last = 1;
 654 +
 655 +       if (last)
 656 +               disable_burst_irq(priv);
 657 +}
 658 +
 659 +static void falcon_i2c_rx(struct falcon_i2c *priv, int last)
 660 +{
 661 +       u32 fifo_stat, timeout;
 662 +       if (priv->msg_buf_len && priv->msg_buf) {
 663 +               timeout = 5000000;
 664 +               do {
 665 +                       fifo_stat = i2c_r32(ffs_stat);
 666 +               } while (!fifo_stat && --timeout);
 667 +               if (!timeout) {
 668 +                       last = 1;
 669 +                       PRINTK("\nrx timeout\n");
 670 +                       goto err;
 671 +               }
 672 +               while (fifo_stat) {
 673 +                       *priv->msg_buf = i2c_r32(rxd);
 674 +                       if (--priv->msg_buf_len)
 675 +                               priv->msg_buf++;
 676 +                       else {
 677 +                               priv->msg_buf = NULL;
 678 +                               last = 1;
 679 +                               break;
 680 +                       }
 681 +                       #if 0
 682 +                       fifo_stat = i2c_r32(ffs_stat);
 683 +                       #else
 684 +                       /* do not read more than burst size, otherwise no "last
 685 +                       burst" is generated and the transaction is blocked! */
 686 +                       fifo_stat = 0;
 687 +                       #endif
 688 +               }
 689 +       } else {
 690 +               last = 1;
 691 +       }
 692 +err:
 693 +       if (last) {
 694 +               disable_burst_irq(priv);
 695 +
 696 +               if (priv->status == STATUS_READ_END) {
 697 +                       /* do the STATUS_STOP and complete() here, as sometimes
 698 +                          the tx_end is already seen before this is finished */
 699 +                       priv->status = STATUS_STOP;
 700 +                       complete(&priv->cmd_complete);
 701 +               } else {
 702 +                       i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
 703 +                       priv->status = STATUS_READ_END;
 704 +               }
 705 +       }
 706 +}
 707 +
 708 +static void falcon_i2c_xfer_init(struct falcon_i2c *priv)
 709 +{
 710 +       /* enable interrupts */
 711 +       i2c_w32(FALCON_I2C_IMSC_DEFAULT_MASK, imsc);
 712 +
 713 +       /* trigger transfer of first msg */
 714 +       set_tx_len(priv);
 715 +}
 716 +
 717 +static void dump_msgs(struct i2c_msg msgs[], int num, int rx)
 718 +{
 719 +#if defined(DEBUG)
 720 +       int i, j;
 721 +       pr_info("Messages %d %s\n", num, rx ? "out" : "in");
 722 +       for (i = 0; i < num; i++) {
 723 +               pr_info("%2d %cX Msg(%d) addr=0x%X: ", i,
 724 +                       (msgs[i].flags & I2C_M_RD) ? ('R') : ('T'),
 725 +                       msgs[i].len, msgs[i].addr);
 726 +               if (!(msgs[i].flags & I2C_M_RD) || rx) {
 727 +                       for (j = 0; j < msgs[i].len; j++)
 728 +                               printk("%02X ", msgs[i].buf[j]);
 729 +               }
 730 +               printk("\n");
 731 +       }
 732 +#endif
 733 +}
 734 +
 735 +static void falcon_i2c_release_bus(struct falcon_i2c *priv)
 736 +{
 737 +       if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)
 738 +               i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
 739 +}
 740 +
 741 +static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 742 +                          int num)
 743 +{
 744 +       struct falcon_i2c *priv = i2c_get_adapdata(adap);
 745 +       int ret;
 746 +
 747 +       dev_dbg(priv->dev, "xfer %u messages\n", num);
 748 +       dump_msgs(msgs, num, 0);
 749 +
 750 +       mutex_lock(&priv->mutex);
 751 +
 752 +       INIT_COMPLETION(priv->cmd_complete);
 753 +       priv->current_msg = msgs;
 754 +       priv->msgs_num = num;
 755 +       priv->msg_err = 0;
 756 +       priv->status = STATUS_IDLE;
 757 +
 758 +       /* wait for the bus to become ready */
 759 +       ret = falcon_i2c_wait_bus_not_busy(priv);
 760 +       if (ret)
 761 +               goto done;
 762 +
 763 +       while (priv->msgs_num) {
 764 +               /* start the transfers */
 765 +               falcon_i2c_xfer_init(priv);
 766 +
 767 +               /* wait for transfers to complete */
 768 +               ret = wait_for_completion_interruptible_timeout(
 769 +                       &priv->cmd_complete, FALCON_I2C_XFER_TIMEOUT);
 770 +               if (ret == 0) {
 771 +                       dev_err(priv->dev, "controller timed out\n");
 772 +                       falcon_i2c_hw_init(adap);
 773 +                       ret = -ETIMEDOUT;
 774 +                       goto done;
 775 +               } else if (ret < 0)
 776 +                       goto done;
 777 +
 778 +               if (priv->msg_err) {
 779 +                       if (priv->msg_err & FALCON_I2C_NACK)
 780 +                               ret = -ENXIO;
 781 +                       else
 782 +                               ret = -EREMOTEIO;
 783 +                       goto done;
 784 +               }
 785 +               if (--priv->msgs_num)
 786 +                       priv->current_msg++;
 787 +       }
 788 +       /* no error? */
 789 +       ret = num;
 790 +
 791 +done:
 792 +       falcon_i2c_release_bus(priv);
 793 +
 794 +       mutex_unlock(&priv->mutex);
 795 +
 796 +       if (ret >= 0)
 797 +               dump_msgs(msgs, num, 1);
 798 +
 799 +       PRINTK("XFER ret %d\n", ret);
 800 +       return ret;
 801 +}
 802 +
 803 +static irqreturn_t falcon_i2c_isr_burst(int irq, void *dev_id)
 804 +{
 805 +       struct falcon_i2c *priv = dev_id;
 806 +       struct i2c_msg *msg = priv->current_msg;
 807 +       int last = (irq == priv->irq_lb);
 808 +
 809 +       if (last)
 810 +               PRINTK("LB ");
 811 +       else
 812 +               PRINTK("B ");
 813 +
 814 +       if (msg->flags & I2C_M_RD) {
 815 +               switch (priv->status) {
 816 +               case STATUS_ADDR:
 817 +                       PRINTK("X");
 818 +                       prepare_msg_send_addr(priv);
 819 +                       disable_burst_irq(priv);
 820 +                       break;
 821 +               case STATUS_READ:
 822 +               case STATUS_READ_END:
 823 +                       PRINTK("R");
 824 +                       falcon_i2c_rx(priv, last);
 825 +                       break;
 826 +               default:
 827 +                       disable_burst_irq(priv);
 828 +                       PRINTK("Status R %d\n", priv->status);
 829 +                       break;
 830 +               }
 831 +       } else {
 832 +               switch (priv->status) {
 833 +               case STATUS_ADDR:
 834 +                       PRINTK("x");
 835 +                       prepare_msg_send_addr(priv);
 836 +                       break;
 837 +               case STATUS_WRITE:
 838 +                       PRINTK("w");
 839 +                       falcon_i2c_tx(priv, last);
 840 +                       break;
 841 +               default:
 842 +                       disable_burst_irq(priv);
 843 +                       PRINTK("Status W %d\n", priv->status);
 844 +                       break;
 845 +               }
 846 +       }
 847 +
 848 +       i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);
 849 +       return IRQ_HANDLED;
 850 +}
 851 +
 852 +static void falcon_i2c_isr_prot(struct falcon_i2c *priv)
 853 +{
 854 +       u32 i_pro = i2c_r32(p_irqss);
 855 +
 856 +       PRINTK("i2c-p");
 857 +
 858 +       /* not acknowledge */
 859 +       if (i_pro & I2C_P_IRQSS_NACK) {
 860 +               priv->msg_err |= FALCON_I2C_NACK;
 861 +               PRINTK(" nack");
 862 +       }
 863 +
 864 +       /* arbitration lost */
 865 +       if (i_pro & I2C_P_IRQSS_AL) {
 866 +               priv->msg_err |= FALCON_I2C_ARB_LOST;
 867 +               PRINTK(" arb-lost");
 868 +       }
 869 +       /* tx -> rx switch */
 870 +       if (i_pro & I2C_P_IRQSS_RX)
 871 +               PRINTK(" rx");
 872 +
 873 +       /* tx end */
 874 +       if (i_pro & I2C_P_IRQSS_TX_END)
 875 +               PRINTK(" txend");
 876 +       PRINTK("\n");
 877 +
 878 +       if (!priv->msg_err) {
 879 +               /* tx -> rx switch */
 880 +               if (i_pro & I2C_P_IRQSS_RX) {
 881 +                       priv->status = STATUS_READ;
 882 +                       enable_burst_irq(priv);
 883 +               }
 884 +               if (i_pro & I2C_P_IRQSS_TX_END) {
 885 +                       if (priv->status == STATUS_READ)
 886 +                               priv->status = STATUS_READ_END;
 887 +                       else {
 888 +                               disable_burst_irq(priv);
 889 +                               priv->status = STATUS_STOP;
 890 +                       }
 891 +               }
 892 +       }
 893 +
 894 +       i2c_w32(i_pro, p_irqsc);
 895 +}
 896 +
 897 +static irqreturn_t falcon_i2c_isr(int irq, void *dev_id)
 898 +{
 899 +       u32 i_raw, i_err = 0;
 900 +       struct falcon_i2c *priv = dev_id;
 901 +
 902 +       i_raw = i2c_r32(mis);
 903 +       PRINTK("i_raw 0x%08X\n", i_raw);
 904 +
 905 +       /* error interrupt */
 906 +       if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
 907 +               i_err = i2c_r32(err_irqss);
 908 +               PRINTK("i_err 0x%08X bus_stat 0x%04X\n",
 909 +                       i_err, i2c_r32(bus_stat));
 910 +
 911 +               /* tx fifo overflow (8) */
 912 +               if (i_err & I2C_ERR_IRQSS_TXF_OFL)
 913 +                       priv->msg_err |= FALCON_I2C_TX_OFL;
 914 +
 915 +               /* tx fifo underflow (4) */
 916 +               if (i_err & I2C_ERR_IRQSS_TXF_UFL)
 917 +                       priv->msg_err |= FALCON_I2C_TX_UFL;
 918 +
 919 +               /* rx fifo overflow (2) */
 920 +               if (i_err & I2C_ERR_IRQSS_RXF_OFL)
 921 +                       priv->msg_err |= FALCON_I2C_RX_OFL;
 922 +
 923 +               /* rx fifo underflow (1) */
 924 +               if (i_err & I2C_ERR_IRQSS_RXF_UFL)
 925 +                       priv->msg_err |= FALCON_I2C_RX_UFL;
 926 +
 927 +               i2c_w32(i_err, err_irqsc);
 928 +       }
 929 +
 930 +       /* protocol interrupt */
 931 +       if (i_raw & I2C_RIS_I2C_P_INT_INTOCC)
 932 +               falcon_i2c_isr_prot(priv);
 933 +
 934 +       if ((priv->msg_err) || (priv->status == STATUS_STOP))
 935 +               complete(&priv->cmd_complete);
 936 +
 937 +       return IRQ_HANDLED;
 938 +}
 939 +
 940 +static u32 falcon_i2c_functionality(struct i2c_adapter *adap)
 941 +{
 942 +       return  I2C_FUNC_I2C |
 943 +               I2C_FUNC_10BIT_ADDR |
 944 +               I2C_FUNC_SMBUS_EMUL;
 945 +}
 946 +
 947 +static struct i2c_algorithm falcon_i2c_algorithm = {
 948 +       .master_xfer    = falcon_i2c_xfer,
 949 +       .functionality  = falcon_i2c_functionality,
 950 +};
 951 +
 952 +static int __devinit falcon_i2c_probe(struct platform_device *pdev)
 953 +{
 954 +       int ret = 0;
 955 +       struct falcon_i2c *priv;
 956 +       struct i2c_adapter *adap;
 957 +       struct resource *mmres, *ioarea,
 958 +                       *irqres_lb, *irqres_b, *irqres_err, *irqres_p;
 959 +       struct clk *clk;
 960 +
 961 +       dev_dbg(&pdev->dev, "probing\n");
 962 +
 963 +       mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 964 +       irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 965 +                                                "i2c_lb");
 966 +       irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b");
 967 +       irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 968 +                                                 "i2c_err");
 969 +       irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p");
 970 +
 971 +       if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) {
 972 +               dev_err(&pdev->dev, "no resources\n");
 973 +               return -ENODEV;
 974 +       }
 975 +
 976 +       clk = clk_get_fpi();
 977 +       if (IS_ERR(clk)) {
 978 +               dev_err(&pdev->dev, "failed to get fpi clk\n");
 979 +               return -ENOENT;
 980 +       }
 981 +
 982 +       if (clk_get_rate(clk) != 100000000) {
 983 +               dev_err(&pdev->dev, "input clock is not 100MHz\n");
 984 +               return -ENOENT;
 985 +       }
 986 +       clk = clk_get(&pdev->dev, NULL);
 987 +       if (IS_ERR(clk)) {
 988 +               dev_err(&pdev->dev, "failed to get i2c clk\n");
 989 +               return -ENOENT;
 990 +       }
 991 +
 992 +       /* allocate private data */
 993 +       priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 994 +       if (!priv) {
 995 +               dev_err(&pdev->dev, "can't allocate private data\n");
 996 +               return -ENOMEM;
 997 +       }
 998 +
 999 +       adap = &priv->adap;
1000 +       i2c_set_adapdata(adap, priv);
1001 +       adap->owner = THIS_MODULE;
1002 +       adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1003 +       strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
1004 +       adap->algo = &falcon_i2c_algorithm;
1005 +
1006 +       priv->mode = FALCON_I2C_MODE_100;
1007 +       priv->clk = clk;
1008 +       priv->dev = &pdev->dev;
1009 +
1010 +       init_completion(&priv->cmd_complete);
1011 +       mutex_init(&priv->mutex);
1012 +
1013 +       if (ltq_gpio_request(&pdev->dev, 107, 0, 0, DRV_NAME":sda") ||
1014 +               ltq_gpio_request(&pdev->dev, 108, 0, 0, DRV_NAME":scl"))
1015 +       {
1016 +               dev_err(&pdev->dev, "I2C gpios not available\n");
1017 +               ret = -ENXIO;
1018 +               goto err_free_priv;
1019 +       }
1020 +
1021 +       ioarea = request_mem_region(mmres->start, resource_size(mmres),
1022 +                                        pdev->name);
1023 +
1024 +       if (ioarea == NULL) {
1025 +               dev_err(&pdev->dev, "I2C region already claimed\n");
1026 +               ret = -ENXIO;
1027 +               goto err_free_gpio;
1028 +       }
1029 +
1030 +       /* map memory */
1031 +       priv->membase = ioremap_nocache(mmres->start & ~KSEG1,
1032 +               resource_size(mmres));
1033 +       if (priv->membase == NULL) {
1034 +               ret = -ENOMEM;
1035 +               goto err_release_region;
1036 +       }
1037 +
1038 +       priv->irq_lb = irqres_lb->start;
1039 +       ret = request_irq(priv->irq_lb, falcon_i2c_isr_burst, IRQF_DISABLED,
1040 +                         irqres_lb->name, priv);
1041 +       if (ret) {
1042 +               dev_err(&pdev->dev, "can't get last burst IRQ %d\n",
1043 +                                       irqres_lb->start);
1044 +               ret = -ENODEV;
1045 +               goto err_unmap_mem;
1046 +       }
1047 +
1048 +       priv->irq_b = irqres_b->start;
1049 +       ret = request_irq(priv->irq_b, falcon_i2c_isr_burst, IRQF_DISABLED,
1050 +                         irqres_b->name, priv);
1051 +       if (ret) {
1052 +               dev_err(&pdev->dev, "can't get burst IRQ %d\n",
1053 +                                       irqres_b->start);
1054 +               ret = -ENODEV;
1055 +               goto err_free_lb_irq;
1056 +       }
1057 +
1058 +       priv->irq_err = irqres_err->start;
1059 +       ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED,
1060 +                         irqres_err->name, priv);
1061 +       if (ret) {
1062 +               dev_err(&pdev->dev, "can't get error IRQ %d\n",
1063 +                                       irqres_err->start);
1064 +               ret = -ENODEV;
1065 +               goto err_free_b_irq;
1066 +       }
1067 +
1068 +       priv->irq_p = irqres_p->start;
1069 +       ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED,
1070 +                         irqres_p->name, priv);
1071 +       if (ret) {
1072 +               dev_err(&pdev->dev, "can't get protocol IRQ %d\n",
1073 +                                       irqres_p->start);
1074 +               ret = -ENODEV;
1075 +               goto err_free_err_irq;
1076 +       }
1077 +
1078 +       dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
1079 +       dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start,
1080 +           irqres_b->start, irqres_err->start, irqres_p->start);
1081 +
1082 +       /* add our adapter to the i2c stack */
1083 +       ret = i2c_add_numbered_adapter(adap);
1084 +       if (ret) {
1085 +               dev_err(&pdev->dev, "can't register I2C adapter\n");
1086 +               goto err_free_p_irq;
1087 +       }
1088 +
1089 +       platform_set_drvdata(pdev, priv);
1090 +       i2c_set_adapdata(adap, priv);
1091 +
1092 +       /* print module version information */
1093 +       dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
1094 +               (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
1095 +               (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
1096 +
1097 +       /* initialize HW */
1098 +       ret = falcon_i2c_hw_init(adap);
1099 +       if (ret) {
1100 +               dev_err(&pdev->dev, "can't configure adapter\n");
1101 +               goto err_remove_adapter;
1102 +       }
1103 +
1104 +       dev_info(&pdev->dev, "version %s\n", DRV_VERSION);
1105 +
1106 +       return 0;
1107 +
1108 +err_remove_adapter:
1109 +       i2c_del_adapter(adap);
1110 +       platform_set_drvdata(pdev, NULL);
1111 +
1112 +err_free_p_irq:
1113 +       free_irq(priv->irq_p, priv);
1114 +
1115 +err_free_err_irq:
1116 +       free_irq(priv->irq_err, priv);
1117 +
1118 +err_free_b_irq:
1119 +       free_irq(priv->irq_b, priv);
1120 +
1121 +err_free_lb_irq:
1122 +       free_irq(priv->irq_lb, priv);
1123 +
1124 +err_unmap_mem:
1125 +       iounmap(priv->membase);
1126 +
1127 +err_release_region:
1128 +       release_mem_region(mmres->start, resource_size(mmres));
1129 +
1130 +err_free_gpio:
1131 +       gpio_free(108);
1132 +       gpio_free(107);
1133 +
1134 +err_free_priv:
1135 +       kfree(priv);
1136 +
1137 +       return ret;
1138 +}
1139 +
1140 +static int __devexit falcon_i2c_remove(struct platform_device *pdev)
1141 +{
1142 +       struct falcon_i2c *priv = platform_get_drvdata(pdev);
1143 +       struct resource *mmres;
1144 +
1145 +       /* disable bus */
1146 +       i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
1147 +
1148 +       /* remove driver */
1149 +       platform_set_drvdata(pdev, NULL);
1150 +       i2c_del_adapter(&priv->adap);
1151 +
1152 +       free_irq(priv->irq_lb, priv);
1153 +       free_irq(priv->irq_b, priv);
1154 +       free_irq(priv->irq_err, priv);
1155 +       free_irq(priv->irq_p, priv);
1156 +
1157 +       iounmap(priv->membase);
1158 +
1159 +       gpio_free(108);
1160 +       gpio_free(107);
1161 +
1162 +       kfree(priv);
1163 +
1164 +       mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1165 +       release_mem_region(mmres->start, resource_size(mmres));
1166 +
1167 +       dev_dbg(&pdev->dev, "removed\n");
1168 +
1169 +       return 0;
1170 +}
1171 +
1172 +static struct platform_driver falcon_i2c_driver = {
1173 +       .probe  = falcon_i2c_probe,
1174 +       .remove = __devexit_p(falcon_i2c_remove),
1175 +       .driver = {
1176 +               .name   = DRV_NAME,
1177 +               .owner  = THIS_MODULE,
1178 +       },
1179 +};
1180 +
1181 +static int __init falcon_i2c_init(void)
1182 +{
1183 +       int ret;
1184 +
1185 +       ret = platform_driver_register(&falcon_i2c_driver);
1186 +
1187 +       if (ret)
1188 +               pr_debug(DRV_NAME ": can't register platform driver\n");
1189 +
1190 +       return ret;
1191 +}
1192 +
1193 +static void __exit falcon_i2c_exit(void)
1194 +{
1195 +       platform_driver_unregister(&falcon_i2c_driver);
1196 +}
1197 +
1198 +module_init(falcon_i2c_init);
1199 +module_exit(falcon_i2c_exit);
1200 +
1201 +MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter");
1202 +MODULE_ALIAS("platform:" DRV_NAME);
1203 +MODULE_LICENSE("GPL");
1204 +MODULE_VERSION(DRV_VERSION);