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[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.2 / 0042-SPI-MIPS-lantiq-adds-spi-xway.patch
1 From b257baf20b44e97770a2654a07f196fcbcd46e92 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 10 Oct 2011 22:29:13 +0200
4 Subject: [PATCH 42/70] SPI: MIPS: lantiq: adds spi xway
5
6 ---
7 .../mips/include/asm/mach-lantiq/lantiq_platform.h | 9 +
8 .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 2 +
9 drivers/spi/Kconfig | 8 +
10 drivers/spi/Makefile | 1 +
11 drivers/spi/spi-xway.c | 1068 ++++++++++++++++++++
12 5 files changed, 1088 insertions(+), 0 deletions(-)
13 create mode 100644 drivers/spi/spi-xway.c
14
15 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
16 index a305f1d..38ed938 100644
17 --- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
18 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
19 @@ -50,4 +50,13 @@ struct ltq_eth_data {
20 int mii_mode;
21 };
22
23 +
24 +struct ltq_spi_platform_data {
25 + u16 num_chipselect;
26 +};
27 +
28 +struct ltq_spi_controller_data {
29 + unsigned gpio;
30 +};
31 +
32 #endif
33 diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
34 index 2a8d5ad..b7f10e6 100644
35 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
36 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
37 @@ -27,6 +27,8 @@
38
39 #define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
40 #define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
41 +#define LTQ_SSC_TIR_AR9 (INT_NUM_IM0_IRL0 + 14)
42 +#define LTQ_SSC_RIR_AR9 (INT_NUM_IM0_IRL0 + 15)
43 #define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
44
45 #define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
46 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
47 index b8424ba..ca4189c 100644
48 --- a/drivers/spi/Kconfig
49 +++ b/drivers/spi/Kconfig
50 @@ -384,6 +384,14 @@ config SPI_NUC900
51 help
52 SPI driver for Nuvoton NUC900 series ARM SoCs
53
54 +config SPI_XWAY
55 + tristate "Lantiq XWAY SPI controller"
56 + depends on LANTIQ && SOC_TYPE_XWAY
57 + select SPI_BITBANG
58 + help
59 + This driver supports the Lantiq SoC SPI controller in master
60 + mode.
61 +
62 #
63 # Add new SPI master controllers in alphabetical order above this line
64 #
65 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
66 index 570894c..a465d9a 100644
67 --- a/drivers/spi/Makefile
68 +++ b/drivers/spi/Makefile
69 @@ -59,4 +59,5 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
70 obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
71 obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
72 obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
73 +obj-$(CONFIG_SPI_XWAY) += spi-xway.o
74
75 diff --git a/drivers/spi/spi-xway.c b/drivers/spi/spi-xway.c
76 new file mode 100644
77 index 0000000..016a6d0
78 --- /dev/null
79 +++ b/drivers/spi/spi-xway.c
80 @@ -0,0 +1,1068 @@
81 +/*
82 + * Lantiq SoC SPI controller
83 + *
84 + * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
85 + *
86 + * This program is free software; you can distribute it and/or modify it
87 + * under the terms of the GNU General Public License (Version 2) as
88 + * published by the Free Software Foundation.
89 + */
90 +
91 +#include <linux/init.h>
92 +#include <linux/module.h>
93 +#include <linux/workqueue.h>
94 +#include <linux/platform_device.h>
95 +#include <linux/io.h>
96 +#include <linux/sched.h>
97 +#include <linux/delay.h>
98 +#include <linux/interrupt.h>
99 +#include <linux/completion.h>
100 +#include <linux/spinlock.h>
101 +#include <linux/err.h>
102 +#include <linux/clk.h>
103 +#include <linux/gpio.h>
104 +#include <linux/spi/spi.h>
105 +#include <linux/spi/spi_bitbang.h>
106 +
107 +#include <lantiq_soc.h>
108 +#include <lantiq_platform.h>
109 +
110 +#define LTQ_SPI_CLC 0x00 /* Clock control */
111 +#define LTQ_SPI_PISEL 0x04 /* Port input select */
112 +#define LTQ_SPI_ID 0x08 /* Identification */
113 +#define LTQ_SPI_CON 0x10 /* Control */
114 +#define LTQ_SPI_STAT 0x14 /* Status */
115 +#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */
116 +#define LTQ_SPI_TB 0x20 /* Transmit buffer */
117 +#define LTQ_SPI_RB 0x24 /* Receive buffer */
118 +#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */
119 +#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */
120 +#define LTQ_SPI_FSTAT 0x38 /* FIFO status */
121 +#define LTQ_SPI_BRT 0x40 /* Baudrate timer */
122 +#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */
123 +#define LTQ_SPI_SFCON 0x60 /* Serial frame control */
124 +#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */
125 +#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */
126 +#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */
127 +#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */
128 +#define LTQ_SPI_RXREQ 0x80 /* Receive request */
129 +#define LTQ_SPI_RXCNT 0x84 /* Receive count */
130 +#define LTQ_SPI_DMACON 0xEC /* DMA control */
131 +#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */
132 +#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */
133 +#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */
134 +
135 +#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */
136 +#define LTQ_SPI_CLC_SMC_MASK 0xFF
137 +#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */
138 +#define LTQ_SPI_CLC_RMC_MASK 0xFF
139 +#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
140 +#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
141 +
142 +#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */
143 +#define LTQ_SPI_ID_TXFS_MASK 0x3F
144 +#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */
145 +#define LTQ_SPI_ID_RXFS_MASK 0x3F
146 +#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */
147 +#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */
148 +
149 +#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */
150 +#define LTQ_SPI_CON_BM_MASK 0x1F
151 +#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
152 +#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
153 +#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
154 +#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
155 +#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
156 +#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
157 +#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
158 +#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
159 +#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
160 +#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
161 +#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
162 +#define LTQ_SPI_CON_HB BIT(4) /* Heading control */
163 +#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
164 +#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
165 +
166 +#define LTQ_SPI_STAT_RXBV_MASK 0x7
167 +#define LTQ_SPI_STAT_RXBV_SHIFT 28
168 +#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
169 +#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
170 +#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
171 +#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
172 +#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
173 +#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
174 +#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
175 +#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
176 +
177 +#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
178 +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
179 +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
180 +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
181 +#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
182 +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
183 +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
184 +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
185 +#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
186 +#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
187 +#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
188 +#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
189 +#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
190 +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
191 +#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
192 +#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
193 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50
194 +
195 +#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */
196 +#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F
197 +#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
198 +#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
199 +
200 +#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */
201 +#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F
202 +#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
203 +#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
204 +
205 +#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f
206 +#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0
207 +#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f
208 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8
209 +
210 +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8
211 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0
212 +
213 +#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8
214 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0
215 +
216 +#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */
217 +#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */
218 +
219 +#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
220 +#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
221 +#define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */
222 +#define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */
223 +#define LTQ_SPI_IRNEN_ALL 0xF
224 +
225 +/* Hard-wired GPIOs used by SPI controller */
226 +#define LTQ_SPI_GPIO_DI 16
227 +#define LTQ_SPI_GPIO_DO 17
228 +#define LTQ_SPI_GPIO_CLK 18
229 +
230 +struct ltq_spi {
231 + struct spi_bitbang bitbang;
232 + struct completion done;
233 + spinlock_t lock;
234 +
235 + struct device *dev;
236 + void __iomem *base;
237 + struct clk *fpiclk;
238 + struct clk *spiclk;
239 +
240 + int status;
241 + int irq[3];
242 +
243 + const u8 *tx;
244 + u8 *rx;
245 + u32 tx_cnt;
246 + u32 rx_cnt;
247 + u32 len;
248 + struct spi_transfer *curr_transfer;
249 +
250 + u32 (*get_tx) (struct ltq_spi *);
251 +
252 + u16 txfs;
253 + u16 rxfs;
254 + unsigned dma_support:1;
255 + unsigned cfg_mode:1;
256 +
257 +};
258 +
259 +struct ltq_spi_controller_state {
260 + void (*cs_activate) (struct spi_device *);
261 + void (*cs_deactivate) (struct spi_device *);
262 +};
263 +
264 +struct ltq_spi_irq_map {
265 + char *name;
266 + irq_handler_t handler;
267 +};
268 +
269 +struct ltq_spi_cs_gpio_map {
270 + unsigned gpio;
271 + unsigned mux;
272 +};
273 +
274 +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
275 +{
276 + return spi_master_get_devdata(spi->master);
277 +}
278 +
279 +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
280 +{
281 + return ioread32be(hw->base + reg);
282 +}
283 +
284 +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
285 +{
286 + iowrite32be(val, hw->base + reg);
287 +}
288 +
289 +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
290 +{
291 + u32 val;
292 +
293 + val = ltq_spi_reg_read(hw, reg);
294 + val |= bits;
295 + ltq_spi_reg_write(hw, val, reg);
296 +}
297 +
298 +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
299 +{
300 + u32 val;
301 +
302 + val = ltq_spi_reg_read(hw, reg);
303 + val &= ~bits;
304 + ltq_spi_reg_write(hw, val, reg);
305 +}
306 +
307 +static void ltq_spi_hw_enable(struct ltq_spi *hw)
308 +{
309 + u32 clc;
310 +
311 + /* Power-up mdule */
312 + clk_enable(hw->spiclk);
313 +
314 + /*
315 + * Set clock divider for run mode to 1 to
316 + * run at same frequency as FPI bus
317 + */
318 + clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
319 + ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
320 +}
321 +
322 +static void ltq_spi_hw_disable(struct ltq_spi *hw)
323 +{
324 + /* Set clock divider to 0 and set module disable bit */
325 + ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
326 +
327 + /* Power-down mdule */
328 + clk_disable(hw->spiclk);
329 +}
330 +
331 +static void ltq_spi_reset_fifos(struct ltq_spi *hw)
332 +{
333 + u32 val;
334 +
335 + /*
336 + * Enable and flush FIFOs. Set interrupt trigger level to
337 + * half of FIFO count implemented in hardware.
338 + */
339 + if (hw->txfs > 1) {
340 + val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
341 + val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
342 + ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
343 + }
344 +
345 + if (hw->rxfs > 1) {
346 + val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
347 + val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
348 + ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
349 + }
350 +}
351 +
352 +static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
353 +{
354 + u32 stat;
355 + unsigned long timeout;
356 +
357 + timeout = jiffies + msecs_to_jiffies(200);
358 +
359 + do {
360 + stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
361 + if (!(stat & LTQ_SPI_STAT_BSY))
362 + return 0;
363 +
364 + cond_resched();
365 + } while (!time_after_eq(jiffies, timeout));
366 +
367 + dev_err(hw->dev, "SPI wait ready timed out\n");
368 +
369 + return -ETIMEDOUT;
370 +}
371 +
372 +static void ltq_spi_config_mode_set(struct ltq_spi *hw)
373 +{
374 + if (hw->cfg_mode)
375 + return;
376 +
377 + /*
378 + * Putting the SPI module in config mode is only safe if no
379 + * transfer is in progress as indicated by busy flag STATE.BSY.
380 + */
381 + if (ltq_spi_wait_ready(hw)) {
382 + ltq_spi_reset_fifos(hw);
383 + hw->status = -ETIMEDOUT;
384 + }
385 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
386 +
387 + hw->cfg_mode = 1;
388 +}
389 +
390 +static void ltq_spi_run_mode_set(struct ltq_spi *hw)
391 +{
392 + if (!hw->cfg_mode)
393 + return;
394 +
395 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
396 +
397 + hw->cfg_mode = 0;
398 +}
399 +
400 +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
401 +{
402 + const u8 *tx = hw->tx;
403 + u32 data = *tx++;
404 +
405 + hw->tx_cnt++;
406 + hw->tx++;
407 +
408 + return data;
409 +}
410 +
411 +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
412 +{
413 + const u16 *tx = (u16 *) hw->tx;
414 + u32 data = *tx++;
415 +
416 + hw->tx_cnt += 2;
417 + hw->tx += 2;
418 +
419 + return data;
420 +}
421 +
422 +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
423 +{
424 + const u32 *tx = (u32 *) hw->tx;
425 + u32 data = *tx++;
426 +
427 + hw->tx_cnt += 4;
428 + hw->tx += 4;
429 +
430 + return data;
431 +}
432 +
433 +static void ltq_spi_bits_per_word_set(struct spi_device *spi)
434 +{
435 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
436 + u32 bm;
437 + u8 bits_per_word = spi->bits_per_word;
438 +
439 + /*
440 + * Use either default value of SPI device or value
441 + * from current transfer.
442 + */
443 + if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
444 + bits_per_word = hw->curr_transfer->bits_per_word;
445 +
446 + if (bits_per_word <= 8)
447 + hw->get_tx = ltq_spi_tx_word_u8;
448 + else if (bits_per_word <= 16)
449 + hw->get_tx = ltq_spi_tx_word_u16;
450 + else if (bits_per_word <= 32)
451 + hw->get_tx = ltq_spi_tx_word_u32;
452 +
453 + /* CON.BM value = bits_per_word - 1 */
454 + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
455 +
456 + ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
457 + LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
458 + ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
459 +}
460 +
461 +static void ltq_spi_speed_set(struct spi_device *spi)
462 +{
463 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
464 + u32 br, max_speed_hz, spi_clk;
465 + u32 speed_hz = spi->max_speed_hz;
466 +
467 + /*
468 + * Use either default value of SPI device or value
469 + * from current transfer.
470 + */
471 + if (hw->curr_transfer && hw->curr_transfer->speed_hz)
472 + speed_hz = hw->curr_transfer->speed_hz;
473 +
474 + /*
475 + * SPI module clock is derived from FPI bus clock dependent on
476 + * divider value in CLC.RMS which is always set to 1.
477 + */
478 + spi_clk = clk_get_rate(hw->fpiclk);
479 +
480 + /*
481 + * Maximum SPI clock frequency in master mode is half of
482 + * SPI module clock frequency. Maximum reload value of
483 + * baudrate generator BR is 2^16.
484 + */
485 + max_speed_hz = spi_clk / 2;
486 + if (speed_hz >= max_speed_hz)
487 + br = 0;
488 + else
489 + br = (max_speed_hz / speed_hz) - 1;
490 +
491 + if (br > 0xFFFF)
492 + br = 0xFFFF;
493 +
494 + ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
495 +}
496 +
497 +static void ltq_spi_clockmode_set(struct spi_device *spi)
498 +{
499 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
500 + u32 con;
501 +
502 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
503 +
504 + /*
505 + * SPI mode mapping in CON register:
506 + * Mode CPOL CPHA CON.PO CON.PH
507 + * 0 0 0 0 1
508 + * 1 0 1 0 0
509 + * 2 1 0 1 1
510 + * 3 1 1 1 0
511 + */
512 + if (spi->mode & SPI_CPHA)
513 + con &= ~LTQ_SPI_CON_PH;
514 + else
515 + con |= LTQ_SPI_CON_PH;
516 +
517 + if (spi->mode & SPI_CPOL)
518 + con |= LTQ_SPI_CON_PO;
519 + else
520 + con &= ~LTQ_SPI_CON_PO;
521 +
522 + /* Set heading control */
523 + if (spi->mode & SPI_LSB_FIRST)
524 + con &= ~LTQ_SPI_CON_HB;
525 + else
526 + con |= LTQ_SPI_CON_HB;
527 +
528 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
529 +}
530 +
531 +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
532 +{
533 + u32 con;
534 +
535 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
536 +
537 + if (t) {
538 + if (t->tx_buf && t->rx_buf) {
539 + con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
540 + } else if (t->rx_buf) {
541 + con &= ~LTQ_SPI_CON_RXOFF;
542 + con |= LTQ_SPI_CON_TXOFF;
543 + } else if (t->tx_buf) {
544 + con &= ~LTQ_SPI_CON_TXOFF;
545 + con |= LTQ_SPI_CON_RXOFF;
546 + }
547 + } else
548 + con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
549 +
550 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
551 +}
552 +
553 +static void ltq_spi_gpio_cs_activate(struct spi_device *spi)
554 +{
555 + struct ltq_spi_controller_data *cdata = spi->controller_data;
556 + int val = spi->mode & SPI_CS_HIGH ? 1 : 0;
557 +
558 + gpio_set_value(cdata->gpio, val);
559 +}
560 +
561 +static void ltq_spi_gpio_cs_deactivate(struct spi_device *spi)
562 +{
563 + struct ltq_spi_controller_data *cdata = spi->controller_data;
564 + int val = spi->mode & SPI_CS_HIGH ? 0 : 1;
565 +
566 + gpio_set_value(cdata->gpio, val);
567 +}
568 +
569 +static void ltq_spi_internal_cs_activate(struct spi_device *spi)
570 +{
571 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
572 + u32 fgpo;
573 +
574 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
575 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
576 +}
577 +
578 +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
579 +{
580 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
581 + u32 fgpo;
582 +
583 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
584 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
585 +}
586 +
587 +static void ltq_spi_chipselect(struct spi_device *spi, int cs)
588 +{
589 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
590 + struct ltq_spi_controller_state *cstate = spi->controller_state;
591 +
592 + switch (cs) {
593 + case BITBANG_CS_ACTIVE:
594 + ltq_spi_bits_per_word_set(spi);
595 + ltq_spi_speed_set(spi);
596 + ltq_spi_clockmode_set(spi);
597 + ltq_spi_run_mode_set(hw);
598 +
599 + cstate->cs_activate(spi);
600 + break;
601 +
602 + case BITBANG_CS_INACTIVE:
603 + cstate->cs_deactivate(spi);
604 +
605 + ltq_spi_config_mode_set(hw);
606 +
607 + break;
608 + }
609 +}
610 +
611 +static int ltq_spi_setup_transfer(struct spi_device *spi,
612 + struct spi_transfer *t)
613 +{
614 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
615 + u8 bits_per_word = spi->bits_per_word;
616 +
617 + hw->curr_transfer = t;
618 +
619 + if (t && t->bits_per_word)
620 + bits_per_word = t->bits_per_word;
621 +
622 + if (bits_per_word > 32)
623 + return -EINVAL;
624 +
625 + ltq_spi_config_mode_set(hw);
626 +
627 + return 0;
628 +}
629 +
630 +static const struct ltq_spi_cs_gpio_map ltq_spi_cs[] = {
631 + { 15, 2 },
632 + { 22, 2 },
633 + { 13, 1 },
634 + { 10, 1 },
635 + { 9, 1 },
636 + { 11, 3 },
637 +};
638 +
639 +static int ltq_spi_setup(struct spi_device *spi)
640 +{
641 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
642 + struct ltq_spi_controller_data *cdata = spi->controller_data;
643 + struct ltq_spi_controller_state *cstate;
644 + u32 gpocon, fgpo;
645 + int ret;
646 +
647 + /* Set default word length to 8 if not set */
648 + if (!spi->bits_per_word)
649 + spi->bits_per_word = 8;
650 +
651 + if (spi->bits_per_word > 32)
652 + return -EINVAL;
653 +
654 + if (!spi->controller_state) {
655 + cstate = kzalloc(sizeof(struct ltq_spi_controller_state),
656 + GFP_KERNEL);
657 + if (!cstate)
658 + return -ENOMEM;
659 +
660 + spi->controller_state = cstate;
661 + } else
662 + return 0;
663 +
664 + /*
665 + * Up to six GPIOs can be connected to the SPI module
666 + * via GPIO alternate function to control the chip select lines.
667 + * For more flexibility in board layout this driver can also control
668 + * the CS lines via GPIO API. If GPIOs should be used, board setup code
669 + * have to register the SPI device with struct ltq_spi_controller_data
670 + * attached.
671 + */
672 + if (cdata && cdata->gpio) {
673 + ret = gpio_request(cdata->gpio, "spi-cs");
674 + if (ret)
675 + return -EBUSY;
676 +
677 + ret = spi->mode & SPI_CS_HIGH ? 0 : 1;
678 + gpio_direction_output(cdata->gpio, ret);
679 +
680 + cstate->cs_activate = ltq_spi_gpio_cs_activate;
681 + cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate;
682 + } else {
683 + ret = ltq_gpio_request(&spi->dev, ltq_spi_cs[spi->chip_select].gpio,
684 + ltq_spi_cs[spi->chip_select].mux,
685 + 1, "spi-cs");
686 + if (ret)
687 + return -EBUSY;
688 +
689 + gpocon = (1 << (spi->chip_select +
690 + LTQ_SPI_GPOCON_ISCSBN_SHIFT));
691 +
692 + if (spi->mode & SPI_CS_HIGH)
693 + gpocon |= (1 << spi->chip_select);
694 +
695 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
696 +
697 + ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
698 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
699 +
700 + cstate->cs_activate = ltq_spi_internal_cs_activate;
701 + cstate->cs_deactivate = ltq_spi_internal_cs_deactivate;
702 + }
703 +
704 + return 0;
705 +}
706 +
707 +static void ltq_spi_cleanup(struct spi_device *spi)
708 +{
709 + struct ltq_spi_controller_data *cdata = spi->controller_data;
710 + struct ltq_spi_controller_state *cstate = spi->controller_state;
711 + unsigned gpio;
712 +
713 + if (cdata && cdata->gpio)
714 + gpio = cdata->gpio;
715 + else
716 + gpio = ltq_spi_cs[spi->chip_select].gpio;
717 +
718 + gpio_free(gpio);
719 + kfree(cstate);
720 +}
721 +
722 +static void ltq_spi_txfifo_write(struct ltq_spi *hw)
723 +{
724 + u32 fstat, data;
725 + u16 fifo_space;
726 +
727 + /* Determine how much FIFOs are free for TX data */
728 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
729 + fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
730 + LTQ_SPI_FSTAT_TXFFL_MASK);
731 +
732 + if (!fifo_space)
733 + return;
734 +
735 + while (hw->tx_cnt < hw->len && fifo_space) {
736 + data = hw->get_tx(hw);
737 + ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
738 + fifo_space--;
739 + }
740 +}
741 +
742 +static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
743 +{
744 + u32 fstat, data, *rx32;
745 + u16 fifo_fill;
746 + u8 rxbv, shift, *rx8;
747 +
748 + /* Determine how much FIFOs are filled with RX data */
749 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
750 + fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
751 + & LTQ_SPI_FSTAT_RXFFL_MASK);
752 +
753 + if (!fifo_fill)
754 + return;
755 +
756 + /*
757 + * The 32 bit FIFO is always used completely independent from the
758 + * bits_per_word value. Thus four bytes have to be read at once
759 + * per FIFO.
760 + */
761 + rx32 = (u32 *) hw->rx;
762 + while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
763 + *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
764 + hw->rx_cnt += 4;
765 + hw->rx += 4;
766 + fifo_fill--;
767 + }
768 +
769 + /*
770 + * If there are remaining bytes, read byte count from STAT.RXBV
771 + * register and read the data byte-wise.
772 + */
773 + while (fifo_fill && hw->rx_cnt < hw->len) {
774 + rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
775 + LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
776 + data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
777 +
778 + shift = (rxbv - 1) * 8;
779 + rx8 = hw->rx;
780 +
781 + while (rxbv) {
782 + *rx8++ = (data >> shift) & 0xFF;
783 + rxbv--;
784 + shift -= 8;
785 + hw->rx_cnt++;
786 + hw->rx++;
787 + }
788 +
789 + fifo_fill--;
790 + }
791 +}
792 +
793 +static void ltq_spi_rxreq_set(struct ltq_spi *hw)
794 +{
795 + u32 rxreq, rxreq_max, rxtodo;
796 +
797 + rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
798 +
799 + /*
800 + * In RX-only mode the serial clock is activated only after writing
801 + * the expected amount of RX bytes into RXREQ register.
802 + * To avoid receive overflows at high clocks it is better to request
803 + * only the amount of bytes that fits into all FIFOs. This value
804 + * depends on the FIFO size implemented in hardware.
805 + */
806 + rxreq = hw->len - hw->rx_cnt;
807 + rxreq_max = hw->rxfs << 2;
808 + rxreq = min(rxreq_max, rxreq);
809 +
810 + if (!rxtodo && rxreq)
811 + ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
812 +}
813 +
814 +static inline void ltq_spi_complete(struct ltq_spi *hw)
815 +{
816 + complete(&hw->done);
817 +}
818 +
819 +irqreturn_t ltq_spi_tx_irq(int irq, void *data)
820 +{
821 + struct ltq_spi *hw = data;
822 + unsigned long flags;
823 + int completed = 0;
824 +
825 + spin_lock_irqsave(&hw->lock, flags);
826 +
827 + if (hw->tx_cnt < hw->len)
828 + ltq_spi_txfifo_write(hw);
829 +
830 + if (hw->tx_cnt == hw->len)
831 + completed = 1;
832 +
833 + spin_unlock_irqrestore(&hw->lock, flags);
834 +
835 + if (completed)
836 + ltq_spi_complete(hw);
837 +
838 + return IRQ_HANDLED;
839 +}
840 +
841 +irqreturn_t ltq_spi_rx_irq(int irq, void *data)
842 +{
843 + struct ltq_spi *hw = data;
844 + unsigned long flags;
845 + int completed = 0;
846 +
847 + spin_lock_irqsave(&hw->lock, flags);
848 +
849 + if (hw->rx_cnt < hw->len) {
850 + ltq_spi_rxfifo_read(hw);
851 +
852 + if (hw->tx && hw->tx_cnt < hw->len)
853 + ltq_spi_txfifo_write(hw);
854 + }
855 +
856 + if (hw->rx_cnt == hw->len)
857 + completed = 1;
858 + else if (!hw->tx)
859 + ltq_spi_rxreq_set(hw);
860 +
861 + spin_unlock_irqrestore(&hw->lock, flags);
862 +
863 + if (completed)
864 + ltq_spi_complete(hw);
865 +
866 + return IRQ_HANDLED;
867 +}
868 +
869 +irqreturn_t ltq_spi_err_irq(int irq, void *data)
870 +{
871 + struct ltq_spi *hw = data;
872 + unsigned long flags;
873 +
874 + spin_lock_irqsave(&hw->lock, flags);
875 +
876 + /* Disable all interrupts */
877 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
878 +
879 + /* Clear all error flags */
880 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
881 +
882 + /* Flush FIFOs */
883 + ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
884 + ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
885 +
886 + hw->status = -EIO;
887 + spin_unlock_irqrestore(&hw->lock, flags);
888 +
889 + ltq_spi_complete(hw);
890 +
891 + return IRQ_HANDLED;
892 +}
893 +
894 +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
895 +{
896 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
897 + u32 irq_flags = 0;
898 +
899 + hw->tx = t->tx_buf;
900 + hw->rx = t->rx_buf;
901 + hw->len = t->len;
902 + hw->tx_cnt = 0;
903 + hw->rx_cnt = 0;
904 + hw->status = 0;
905 + INIT_COMPLETION(hw->done);
906 +
907 + ltq_spi_xmit_set(hw, t);
908 +
909 + /* Enable error interrupts */
910 + ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
911 +
912 + if (hw->tx) {
913 + /* Initially fill TX FIFO with as much data as possible */
914 + ltq_spi_txfifo_write(hw);
915 + irq_flags |= LTQ_SPI_IRNEN_T;
916 +
917 + /* Always enable RX interrupt in Full Duplex mode */
918 + if (hw->rx)
919 + irq_flags |= LTQ_SPI_IRNEN_R;
920 + } else if (hw->rx) {
921 + /* Start RX clock */
922 + ltq_spi_rxreq_set(hw);
923 +
924 + /* Enable RX interrupt to receive data from RX FIFOs */
925 + irq_flags |= LTQ_SPI_IRNEN_R;
926 + }
927 +
928 + /* Enable TX or RX interrupts */
929 + ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
930 + wait_for_completion_interruptible(&hw->done);
931 +
932 + /* Disable all interrupts */
933 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
934 +
935 + /*
936 + * Return length of current transfer for bitbang utility code if
937 + * no errors occured during transmission.
938 + */
939 + if (!hw->status)
940 + hw->status = hw->len;
941 +
942 + return hw->status;
943 +}
944 +
945 +static const struct ltq_spi_irq_map ltq_spi_irqs[] = {
946 + { "spi_tx", ltq_spi_tx_irq },
947 + { "spi_rx", ltq_spi_rx_irq },
948 + { "spi_err", ltq_spi_err_irq },
949 +};
950 +
951 +static int __init ltq_spi_probe(struct platform_device *pdev)
952 +{
953 + struct spi_master *master;
954 + struct resource *r;
955 + struct ltq_spi *hw;
956 + struct ltq_spi_platform_data *pdata = pdev->dev.platform_data;
957 + int ret, i;
958 + u32 data, id;
959 +
960 + master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
961 + if (!master) {
962 + dev_err(&pdev->dev, "spi_alloc_master\n");
963 + ret = -ENOMEM;
964 + goto err;
965 + }
966 +
967 + hw = spi_master_get_devdata(master);
968 +
969 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
970 + if (r == NULL) {
971 + dev_err(&pdev->dev, "platform_get_resource\n");
972 + ret = -ENOENT;
973 + goto err_master;
974 + }
975 +
976 + r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
977 + pdev->name);
978 + if (!r) {
979 + dev_err(&pdev->dev, "devm_request_mem_region\n");
980 + ret = -ENXIO;
981 + goto err_master;
982 + }
983 +
984 + hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
985 + if (!hw->base) {
986 + dev_err(&pdev->dev, "devm_ioremap_nocache\n");
987 + ret = -ENXIO;
988 + goto err_master;
989 + }
990 +
991 + hw->fpiclk = clk_get_fpi();
992 + if (IS_ERR(hw->fpiclk)) {
993 + dev_err(&pdev->dev, "clk_get\n");
994 + ret = PTR_ERR(hw->fpiclk);
995 + goto err_master;
996 + }
997 +
998 + hw->spiclk = clk_get(&pdev->dev, NULL);
999 + if (IS_ERR(hw->spiclk)) {
1000 + dev_err(&pdev->dev, "clk_get\n");
1001 + ret = PTR_ERR(hw->spiclk);
1002 + goto err_master;
1003 + }
1004 +
1005 + memset(hw->irq, 0, sizeof(hw->irq));
1006 + for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
1007 + ret = platform_get_irq_byname(pdev, ltq_spi_irqs[i].name);
1008 + if (0 > ret) {
1009 + dev_err(&pdev->dev, "platform_get_irq_byname\n");
1010 + goto err_irq;
1011 + }
1012 +
1013 + hw->irq[i] = ret;
1014 + ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
1015 + 0, ltq_spi_irqs[i].name, hw);
1016 + if (ret) {
1017 + dev_err(&pdev->dev, "request_irq\n");
1018 + goto err_irq;
1019 + }
1020 + }
1021 +
1022 + hw->bitbang.master = spi_master_get(master);
1023 + hw->bitbang.chipselect = ltq_spi_chipselect;
1024 + hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
1025 + hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
1026 +
1027 + master->bus_num = pdev->id;
1028 + master->num_chipselect = pdata->num_chipselect;
1029 + master->setup = ltq_spi_setup;
1030 + master->cleanup = ltq_spi_cleanup;
1031 +
1032 + hw->dev = &pdev->dev;
1033 + init_completion(&hw->done);
1034 + spin_lock_init(&hw->lock);
1035 +
1036 + /* Set GPIO alternate functions to SPI */
1037 + ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_DI, 2, 0, "spi-di");
1038 + ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_DO, 2, 1, "spi-do");
1039 + ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_CLK, 2, 1, "spi-clk");
1040 +
1041 + ltq_spi_hw_enable(hw);
1042 +
1043 + /* Read module capabilities */
1044 + id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
1045 + hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
1046 + hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
1047 + hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
1048 +
1049 + ltq_spi_config_mode_set(hw);
1050 +
1051 + /* Enable error checking, disable TX/RX, set idle value high */
1052 + data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
1053 + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
1054 + LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
1055 + ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
1056 +
1057 + /* Enable master mode and clear error flags */
1058 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
1059 + LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
1060 +
1061 + /* Reset GPIO/CS registers */
1062 + ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
1063 + ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
1064 +
1065 + /* Enable and flush FIFOs */
1066 + ltq_spi_reset_fifos(hw);
1067 +
1068 + ret = spi_bitbang_start(&hw->bitbang);
1069 + if (ret) {
1070 + dev_err(&pdev->dev, "spi_bitbang_start\n");
1071 + goto err_bitbang;
1072 + }
1073 +
1074 + platform_set_drvdata(pdev, hw);
1075 +
1076 + pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
1077 + id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
1078 +
1079 + return 0;
1080 +
1081 +err_bitbang:
1082 + ltq_spi_hw_disable(hw);
1083 +
1084 +err_irq:
1085 + clk_put(hw->fpiclk);
1086 +
1087 + for (; i > 0; i--)
1088 + free_irq(hw->irq[i], hw);
1089 +
1090 +err_master:
1091 + spi_master_put(master);
1092 +
1093 +err:
1094 + return ret;
1095 +}
1096 +
1097 +static int __exit ltq_spi_remove(struct platform_device *pdev)
1098 +{
1099 + struct ltq_spi *hw = platform_get_drvdata(pdev);
1100 + int ret, i;
1101 +
1102 + ret = spi_bitbang_stop(&hw->bitbang);
1103 + if (ret)
1104 + return ret;
1105 +
1106 + platform_set_drvdata(pdev, NULL);
1107 +
1108 + ltq_spi_config_mode_set(hw);
1109 + ltq_spi_hw_disable(hw);
1110 +
1111 + for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
1112 + if (0 < hw->irq[i])
1113 + free_irq(hw->irq[i], hw);
1114 +
1115 + gpio_free(LTQ_SPI_GPIO_DI);
1116 + gpio_free(LTQ_SPI_GPIO_DO);
1117 + gpio_free(LTQ_SPI_GPIO_CLK);
1118 +
1119 + clk_put(hw->fpiclk);
1120 + spi_master_put(hw->bitbang.master);
1121 +
1122 + return 0;
1123 +}
1124 +
1125 +static struct platform_driver ltq_spi_driver = {
1126 + .driver = {
1127 + .name = "ltq_spi",
1128 + .owner = THIS_MODULE,
1129 + },
1130 + .remove = __exit_p(ltq_spi_remove),
1131 +};
1132 +
1133 +static int __init ltq_spi_init(void)
1134 +{
1135 + return platform_driver_probe(&ltq_spi_driver, ltq_spi_probe);
1136 +}
1137 +module_init(ltq_spi_init);
1138 +
1139 +static void __exit ltq_spi_exit(void)
1140 +{
1141 + platform_driver_unregister(&ltq_spi_driver);
1142 +}
1143 +module_exit(ltq_spi_exit);
1144 +
1145 +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1146 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1147 +MODULE_LICENSE("GPL");
1148 +MODULE_ALIAS("platform:ltq-spi");
1149 --
1150 1.7.7.1
1151
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