target/linux/lantiq/patches-3.2/0060-MIPS-clean-up-clock-code.patch

   1 From 720f8d0381c60af85f049353464a12fbed903edb Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 20 Mar 2012 08:26:04 +0100
   4 Subject: [PATCH 60/73] MIPS: clean up clock code
   5
   6 ---
   7  arch/mips/lantiq/clk.c          |   11 +++
   8  arch/mips/lantiq/clk.h          |    3 +-
   9  arch/mips/lantiq/xway/devices.c |    2 +-
  10  arch/mips/lantiq/xway/sysctrl.c |  166 ++++++++++++++++++++++++++++++---------
  11  4 files changed, 143 insertions(+), 39 deletions(-)
  12
  13 --- a/arch/mips/lantiq/clk.c
  14 +++ b/arch/mips/lantiq/clk.c
  15 @@ -44,6 +44,7 @@ struct clk *clk_get_fpi(void)
  16  {
  17         return &cpu_clk_generic[1];
  18  }
  19 +EXPORT_SYMBOL_GPL(clk_get_fpi);
  20
  21  struct clk *clk_get_io(void)
  22  {
  23 @@ -70,6 +71,16 @@ unsigned long clk_get_rate(struct clk *c
  24  }
  25  EXPORT_SYMBOL(clk_get_rate);
  26
  27 +int clk_set_rate(struct clk *clk, unsigned long rate)
  28 +{
  29 +       if (unlikely(!clk_good(clk)))
  30 +               return 0;
  31 +
  32 +       clk->rate = rate;
  33 +       return 0;
  34 +}
  35 +EXPORT_SYMBOL(clk_set_rate);
  36 +
  37  int clk_enable(struct clk *clk)
  38  {
  39         if (unlikely(!clk_good(clk)))
  40 --- a/arch/mips/lantiq/clk.h
  41 +++ b/arch/mips/lantiq/clk.h
  42 @@ -12,6 +12,7 @@
  43  #include <linux/clkdev.h>
  44
  45  /* clock speeds */
  46 +#define CLOCK_33M      33333333
  47  #define CLOCK_60M      60000000
  48  #define CLOCK_62_5M    62500000
  49  #define CLOCK_83M      83333333
  50 @@ -38,9 +39,9 @@
  51  struct clk {
  52         struct clk_lookup cl;
  53         unsigned long rate;
  54 -       unsigned long (*get_rate) (void);
  55         unsigned int module;
  56         unsigned int bits;
  57 +       unsigned long (*get_rate) (void);
  58         int (*enable) (struct clk *clk);
  59         void (*disable) (struct clk *clk);
  60         int (*activate) (struct clk *clk);
  61 --- a/arch/mips/lantiq/xway/devices.c
  62 +++ b/arch/mips/lantiq/xway/devices.c
  63 @@ -59,7 +59,7 @@ static struct resource ltq_stp_resource
  64
  65  void __init ltq_register_gpio_stp(void)
  66  {
  67 -       platform_device_register_simple("ltq_stp", 0, &ltq_stp_resource, 1);
  68 +       platform_device_register_simple("ltq_stp", -1, &ltq_stp_resource, 1);
  69  }
  70
  71  /* asc ports - amazon se has its own serial mapping */
  72 --- a/arch/mips/lantiq/xway/sysctrl.c
  73 +++ b/arch/mips/lantiq/xway/sysctrl.c
  74 @@ -16,40 +16,57 @@
  75  #include "../devices.h"
  76
  77  /* clock control register */
  78 -#define LTQ_CGU_IFCCR  0x0018
  79 +#define CGU_IFCCR      0x0018
  80  /* system clock register */
  81 -#define LTQ_CGU_SYS     0x0010
  82 -
  83 -/* the enable / disable registers */
  84 -#define LTQ_PMU_PWDCR  0x1C
  85 -#define LTQ_PMU_PWDSR  0x20
  86 -#define LTQ_PMU_PWDCR1 0x24
  87 -#define LTQ_PMU_PWDSR1 0x28
  88 -
  89 -#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR))
  90 -#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR))
  91 -
  92 -/* CGU - clock generation unit */
  93 -#define CGU_EPHY               0x10
  94 +#define CGU_SYS                0x0010
  95 +/* pci control register */
  96 +#define CGU_PCICR      0x0034
  97 +/* ephy configuration register */
  98 +#define CGU_EPHY       0x10
  99 +/* power control register */
 100 +#define PMU_PWDCR      0x1C
 101 +/* power status register */
 102 +#define PMU_PWDSR      0x20
 103 +/* power control register */
 104 +#define PMU_PWDCR1     0x24
 105 +/* power status register */
 106 +#define PMU_PWDSR1     0x28
 107 +/* power control register */
 108 +#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
 109 +/* power status register */
 110 +#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
 111
 112  /* PMU - power management unit */
 113 -#define PMU_DMA                        0x0020
 114 -#define PMU_SPI                        0x0100
 115 -#define PMU_EPHY               0x0080
 116 -#define PMU_USB                        0x8041
 117 -#define PMU_STP                        0x0800
 118 -#define PMU_GPT                        0x1000
 119 -#define PMU_PPE                        0x2000
 120 -#define PMU_FPI                        0x4000
 121 -#define PMU_SWITCH             0x10000000
 122 -#define PMU_AHBS               0x2000
 123 -#define PMU_AHBM               0x8000
 124 -#define PMU_PCIE_CLK            0x80000000
 125 -
 126 -#define PMU1_PCIE_PHY          0x0001
 127 -#define PMU1_PCIE_CTL          0x0002
 128 -#define PMU1_PCIE_MSI          0x0020
 129 -#define PMU1_PCIE_PDI          0x0010
 130 +#define PMU_USB0_P     BIT(0)
 131 +#define PMU_PCI                BIT(4)
 132 +#define PMU_DMA                BIT(5)
 133 +#define PMU_USB0       BIT(5)
 134 +#define PMU_SPI                BIT(8)
 135 +#define PMU_EPHY       BIT(7)
 136 +#define PMU_EBU                BIT(10)
 137 +#define PMU_STP                BIT(11)
 138 +#define PMU_GPT                BIT(12)
 139 +#define PMU_PPE                BIT(13)
 140 +#define PMU_AHBS       BIT(13) /* vr9 */
 141 +#define PMU_FPI                BIT(14)
 142 +#define PMU_AHBM       BIT(15)
 143 +#define PMU_PPE_QSB    BIT(18)
 144 +#define PMU_PPE_SLL01  BIT(19)
 145 +#define PMU_PPE_TC     BIT(21)
 146 +#define PMU_PPE_EMA    BIT(22)
 147 +#define PMU_PPE_DPLUM  BIT(23)
 148 +#define PMU_PPE_DPLUS  BIT(24)
 149 +#define PMU_USB1_P     BIT(26)
 150 +#define PMU_USB1       BIT(27)
 151 +#define PMU_SWITCH     BIT(28)
 152 +#define PMU_PPE_TOP    BIT(29)
 153 +#define PMU_GPHY       BIT(30)
 154 +#define PMU_PCIE_CLK   BIT(31)
 155 +
 156 +#define PMU1_PCIE_PHY  BIT(0)
 157 +#define PMU1_PCIE_CTL  BIT(1)
 158 +#define PMU1_PCIE_PDI  BIT(4)
 159 +#define PMU1_PCIE_MSI  BIT(5)
 160
 161  #define ltq_pmu_w32(x, y)      ltq_w32((x), ltq_pmu_membase + (y))
 162  #define ltq_pmu_r32(x)         ltq_r32(ltq_pmu_membase + (x))
 163 @@ -69,13 +86,13 @@ static void __iomem *ltq_pmu_membase;
 164
 165  static int ltq_cgu_enable(struct clk *clk)
 166  {
 167 -       ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR);
 168 +       ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR);
 169         return 0;
 170  }
 171
 172  static void ltq_cgu_disable(struct clk *clk)
 173  {
 174 -       ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR);
 175 +       ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR);
 176  }
 177
 178  static int ltq_pmu_enable(struct clk *clk)
 179 @@ -94,9 +111,49 @@ static int ltq_pmu_enable(struct clk *cl
 180
 181  static void ltq_pmu_disable(struct clk *clk)
 182  {
 183 -       ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR);
 184 +       ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) | clk->bits,
 185 +               PWDCR(clk->module));
 186  }
 187
 188 +static int ltq_pci_enable(struct clk *clk)
 189 +{
 190 +       unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
 191 +       /* set clock bus speed */
 192 +       if (ltq_is_ar9()) {
 193 +               ifccr &= ~0x1f00000;
 194 +               if (clk->rate == CLOCK_33M)
 195 +                       ifccr |= 0xe00000;
 196 +               else
 197 +                       ifccr |= 0x700000; /* 62.5M */
 198 +       } else {
 199 +               ifccr &= ~0xf00000;
 200 +               if (clk->rate == CLOCK_33M)
 201 +                       ifccr |= 0x800000;
 202 +               else
 203 +                       ifccr |= 0x400000; /* 62.5M */
 204 +       }
 205 +       ltq_cgu_w32(ifccr, CGU_IFCCR);
 206 +       return 0;
 207 +}
 208 +
 209 +static int ltq_pci_ext_enable(struct clk *clk)
 210 +{
 211 +       /* enable external pci clock */
 212 +       ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16),
 213 +               CGU_IFCCR);
 214 +       ltq_cgu_w32((1 << 30), CGU_PCICR);
 215 +       return 0;
 216 +}
 217 +
 218 +static void ltq_pci_ext_disable(struct clk *clk)
 219 +{
 220 +       /* enable external pci clock */
 221 +       ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
 222 +               CGU_IFCCR);
 223 +       ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
 224 +}
 225 +
 226 +/* manage the clock gates via PMU */
 227  static inline void clkdev_add_pmu(const char *dev, const char *con,
 228                                         unsigned int module, unsigned int bits)
 229  {
 230 @@ -112,6 +169,7 @@ static inline void clkdev_add_pmu(const
 231         clkdev_add(&clk->cl);
 232  }
 233
 234 +/* manage the clock generator */
 235  static inline void clkdev_add_cgu(const char *dev, const char *con,
 236                                         unsigned int bits)
 237  {
 238 @@ -126,6 +184,33 @@ static inline void clkdev_add_cgu(const
 239         clkdev_add(&clk->cl);
 240  }
 241
 242 +/* pci needs its own enable function */
 243 +static inline void clkdev_add_pci(void)
 244 +{
 245 +       struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 246 +       struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
 247 +
 248 +       /* main pci clock */
 249 +       clk->cl.dev_id = "ltq_pci";
 250 +       clk->cl.con_id = NULL;
 251 +       clk->cl.clk = clk;
 252 +       clk->rate = CLOCK_33M;
 253 +       clk->enable = ltq_pci_enable;
 254 +       clk->disable = ltq_pmu_disable;
 255 +       clk->module = 0;
 256 +       clk->bits = PMU_PCI;
 257 +       clkdev_add(&clk->cl);
 258 +
 259 +       /* use internal/external bus clock */
 260 +       clk_ext->cl.dev_id = "ltq_pci";
 261 +       clk_ext->cl.con_id = "external";
 262 +       clk_ext->cl.clk = clk_ext;
 263 +       clk_ext->enable = ltq_pci_ext_enable;
 264 +       clk_ext->disable = ltq_pci_ext_disable;
 265 +       clkdev_add(&clk_ext->cl);
 266 +
 267 +}
 268 +
 269  void __init ltq_soc_init(void)
 270  {
 271         ltq_pmu_membase = ltq_remap_resource(&ltq_pmu_resource);
 272 @@ -144,14 +229,16 @@ void __init ltq_soc_init(void)
 273         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 274
 275         /* add our clocks */
 276 +       clkdev_add_pmu("ltq_fpi", NULL, 0, PMU_FPI);
 277         clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
 278         clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
 279         clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
 280          clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT);
 281 +        clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU);
 282         if (!ltq_is_vr9())
 283                 clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
 284         if (ltq_is_ase()) {
 285 -               if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
 286 +               if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 287                         clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
 288                 else
 289                         clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
 290 @@ -166,11 +253,16 @@ void __init ltq_soc_init(void)
 291                 clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
 292                 clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
 293                 clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
 294 -               clkdev_add_pmu("usb0", NULL, 0, (1<<6) | 1);
 295 -               clkdev_add_pmu("usb1", NULL, 0, (1<<26) | (1<<27));
 296 +               clkdev_add_pmu("usb0", NULL, 0, PMU_USB0 | PMU_USB0_P);
 297 +               clkdev_add_pmu("usb1", NULL, 0, PMU_USB1 | PMU_USB1_P);
 298 +               clkdev_add_pmu("ltq_vrx200", NULL, 0,
 299 +                       PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
 300 +                       PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 301 +                       PMU_PPE_QSB);
 302         } else {
 303                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 304                                         ltq_danube_io_region_clock());
 305 +               clkdev_add_pci();
 306                 if (ltq_is_ar9())
 307                         clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
 308         }