target/linux/lantiq/patches-3.2/0064-MIPS-adds-dsl-clocks.patch

   1 From 76d01e1bc369026d9ec47d2c8355871c083134d2 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 20 Mar 2012 13:05:11 +0100
   4 Subject: [PATCH 64/73] MIPS: adds dsl clocks
   5
   6 ---
   7  arch/mips/lantiq/xway/sysctrl.c |   15 +++++++++++++--
   8  1 files changed, 13 insertions(+), 2 deletions(-)
   9
  10 --- a/arch/mips/lantiq/xway/sysctrl.c
  11 +++ b/arch/mips/lantiq/xway/sysctrl.c
  12 @@ -41,8 +41,9 @@
  13  #define PMU_PCI                BIT(4)
  14  #define PMU_DMA                BIT(5)
  15  #define PMU_USB0       BIT(5)
  16 +#define PMU_EPHY       BIT(7)  /* ase */
  17  #define PMU_SPI                BIT(8)
  18 -#define PMU_EPHY       BIT(7)
  19 +#define PMU_DFE                BIT(9)
  20  #define PMU_EBU                BIT(10)
  21  #define PMU_STP                BIT(11)
  22  #define PMU_GPT                BIT(12)
  23 @@ -147,7 +148,7 @@ static int ltq_pci_ext_enable(struct clk
  24
  25  static void ltq_pci_ext_disable(struct clk *clk)
  26  {
  27 -       /* enable external pci clock */
  28 +       /* disable external pci clock (internal) */
  29         ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
  30                 CGU_IFCCR);
  31         ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
  32 @@ -246,6 +247,9 @@ void __init ltq_soc_init(void)
  33                         clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
  34                 clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
  35                 clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
  36 +               clkdev_add_pmu("ltq_dsl", NULL, 0,
  37 +                       PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
  38 +                       PMU_AHBS | PMU_DFE);
  39         } else if (ltq_is_vr9()) {
  40                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
  41                         ltq_vr9_fpi_hz());
  42 @@ -261,12 +265,19 @@ void __init ltq_soc_init(void)
  43                         PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
  44                         PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
  45                         PMU_PPE_QSB);
  46 +               clkdev_add_pmu("ltq_dsl", NULL, 0, PMU_DFE | PMU_AHBS);
  47         } else if (ltq_is_ar9()) {
  48                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
  49                         ltq_ar9_fpi_hz());
  50                 clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
  51 +               clkdev_add_pmu("ltq_dsl", NULL, 0,
  52 +                       PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
  53 +                       PMU_PPE_QSB | PMU_AHBS | PMU_DFE);
  54         } else {
  55                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
  56                         ltq_danube_io_region_clock());
  57 +               clkdev_add_pmu("ltq_dsl", NULL, 0,
  58 +                       PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
  59 +                       PMU_PPE_QSB | PMU_AHBS | PMU_DFE);
  60         }
  61  }