target/linux/lantiq/patches-3.3/0003-MIPS-lantiq-change-ltq_request_gpio-call-signature.patch

   1 From 834353ea867a84649d452bac03b97ce32dc6e318 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 11 Nov 2011 12:45:24 +0100
   4 Subject: [PATCH 03/70] MIPS: lantiq: change ltq_request_gpio() call signature
   5
   6 ltq_request_gpio() was using alt0/1 to multiplex the function of GPIO pins.
   7 This was XWAY specific. In order to also accomodate SoCs that require more bits
   8 we use a 32bit mask instead. This way the call signature is consistent between
   9 XWAY and FALC-ON.
  10
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  13 ---
  14  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    4 +-
  15  arch/mips/lantiq/xway/gpio.c                       |    8 ++--
  16  arch/mips/lantiq/xway/gpio_stp.c                   |    6 ++--
  17  arch/mips/pci/pci-lantiq.c                         |   36 +++++++++----------
  18  4 files changed, 26 insertions(+), 28 deletions(-)
  19
  20 diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  21 index 9b7ee366..87f6d24 100644
  22 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  23 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  24 @@ -135,8 +135,8 @@ extern __iomem void *ltq_ebu_membase;
  25  extern __iomem void *ltq_cgu_membase;
  26
  27  /* request a non-gpio and set the PIO config */
  28 -extern int  ltq_gpio_request(unsigned int pin, unsigned int alt0,
  29 -       unsigned int alt1, unsigned int dir, const char *name);
  30 +extern int  ltq_gpio_request(unsigned int pin, unsigned int mux,
  31 +                               unsigned int dir, const char *name);
  32  extern void ltq_pmu_enable(unsigned int module);
  33  extern void ltq_pmu_disable(unsigned int module);
  34  extern void ltq_cgu_enable(unsigned int clk);
  35 diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
  36 index d2fa98f..f204f6c 100644
  37 --- a/arch/mips/lantiq/xway/gpio.c
  38 +++ b/arch/mips/lantiq/xway/gpio.c
  39 @@ -48,8 +48,8 @@ int irq_to_gpio(unsigned int gpio)
  40  }
  41  EXPORT_SYMBOL(irq_to_gpio);
  42
  43 -int ltq_gpio_request(unsigned int pin, unsigned int alt0,
  44 -       unsigned int alt1, unsigned int dir, const char *name)
  45 +int ltq_gpio_request(unsigned int pin, unsigned int mux,
  46 +                       unsigned int dir, const char *name)
  47  {
  48         int id = 0;
  49
  50 @@ -67,13 +67,13 @@ int ltq_gpio_request(unsigned int pin, unsigned int alt0,
  51                 pin -= PINS_PER_PORT;
  52                 id++;
  53         }
  54 -       if (alt0)
  55 +       if (mux & 0x2)
  56                 ltq_gpio_setbit(ltq_gpio_port[id].membase,
  57                         LTQ_GPIO_ALTSEL0, pin);
  58         else
  59                 ltq_gpio_clearbit(ltq_gpio_port[id].membase,
  60                         LTQ_GPIO_ALTSEL0, pin);
  61 -       if (alt1)
  62 +       if (mux & 0x1)
  63                 ltq_gpio_setbit(ltq_gpio_port[id].membase,
  64                         LTQ_GPIO_ALTSEL1, pin);
  65         else
  66 diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
  67 index ff9991c..2c78660 100644
  68 --- a/arch/mips/lantiq/xway/gpio_stp.c
  69 +++ b/arch/mips/lantiq/xway/gpio_stp.c
  70 @@ -79,9 +79,9 @@ static struct gpio_chip ltq_stp_chip = {
  71  static int ltq_stp_hw_init(void)
  72  {
  73         /* the 3 pins used to control the external stp */
  74 -       ltq_gpio_request(4, 1, 0, 1, "stp-st");
  75 -       ltq_gpio_request(5, 1, 0, 1, "stp-d");
  76 -       ltq_gpio_request(6, 1, 0, 1, "stp-sh");
  77 +       ltq_gpio_request(4, 2, 1, "stp-st");
  78 +       ltq_gpio_request(5, 2, 1, "stp-d");
  79 +       ltq_gpio_request(6, 2, 1, "stp-sh");
  80
  81         /* sane defaults */
  82         ltq_stp_w32(0, LTQ_STP_AR);
  83 diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
  84 index be1e1af..c001c5a 100644
  85 --- a/arch/mips/pci/pci-lantiq.c
  86 +++ b/arch/mips/pci/pci-lantiq.c
  87 @@ -70,28 +70,27 @@
  88
  89  struct ltq_pci_gpio_map {
  90         int pin;
  91 -       int alt0;
  92 -       int alt1;
  93 +       int mux;
  94         int dir;
  95         char *name;
  96  };
  97
  98  /* the pci core can make use of the following gpios */
  99  static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
 100 -       { 0, 1, 0, 0, "pci-exin0" },
 101 -       { 1, 1, 0, 0, "pci-exin1" },
 102 -       { 2, 1, 0, 0, "pci-exin2" },
 103 -       { 39, 1, 0, 0, "pci-exin3" },
 104 -       { 10, 1, 0, 0, "pci-exin4" },
 105 -       { 9, 1, 0, 0, "pci-exin5" },
 106 -       { 30, 1, 0, 1, "pci-gnt1" },
 107 -       { 23, 1, 0, 1, "pci-gnt2" },
 108 -       { 19, 1, 0, 1, "pci-gnt3" },
 109 -       { 38, 1, 0, 1, "pci-gnt4" },
 110 -       { 29, 1, 0, 0, "pci-req1" },
 111 -       { 31, 1, 0, 0, "pci-req2" },
 112 -       { 3, 1, 0, 0, "pci-req3" },
 113 -       { 37, 1, 0, 0, "pci-req4" },
 114 +       { 0, 2, 0, "pci-exin0" },
 115 +       { 1, 2, 0, "pci-exin1" },
 116 +       { 2, 2, 0, "pci-exin2" },
 117 +       { 39, 2, 0, "pci-exin3" },
 118 +       { 10, 2, 0, "pci-exin4" },
 119 +       { 9, 2, 0, "pci-exin5" },
 120 +       { 30, 2, 1, "pci-gnt1" },
 121 +       { 23, 2, 1, "pci-gnt2" },
 122 +       { 19, 2, 1, "pci-gnt3" },
 123 +       { 38, 2, 1, "pci-gnt4" },
 124 +       { 29, 2, 0, "pci-req1" },
 125 +       { 31, 2, 0, "pci-req2" },
 126 +       { 3, 2, 0, "pci-req3" },
 127 +       { 37, 2, 0, "pci-req4" },
 128  };
 129
 130  __iomem void *ltq_pci_mapped_cfg;
 131 @@ -157,13 +156,12 @@ static void ltq_pci_setup_gpio(int gpio)
 132         for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
 133                 if (gpio & (1 << i)) {
 134                         ltq_gpio_request(ltq_pci_gpio_map[i].pin,
 135 -                               ltq_pci_gpio_map[i].alt0,
 136 -                               ltq_pci_gpio_map[i].alt1,
 137 +                               ltq_pci_gpio_map[i].mux,
 138                                 ltq_pci_gpio_map[i].dir,
 139                                 ltq_pci_gpio_map[i].name);
 140                 }
 141         }
 142 -       ltq_gpio_request(21, 0, 0, 1, "pci-reset");
 143 +       ltq_gpio_request(21, 0, 1, "pci-reset");
 144         ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
 145  }
 146
 147 --
 148 1.7.9.1
 149