[mcs814x] nuport-mac: properly protect the phy interrupt handler
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.3 / 0004-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch
1 From 9eabaa2969af9aa157d50b7cfbb447f65db95f06 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 11 Aug 2011 12:25:55 +0200
4 Subject: [PATCH 04/70] MIPS: lantiq: make irq.c support the FALC-ON
5
6 There are minor differences in how irqs work on xway and falcon socs.
7 Xway needs 2 quirks that we need to disable for falcon to also work with
8 this code.
9
10 * EBU irq does not need to send a special ack to the EBU
11 * The EIU does not exist
12
13 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
14 Signed-off-by: John Crispin <blogic@openwrt.org>
15 ---
16 arch/mips/lantiq/irq.c | 24 +++++++++++++-----------
17 1 files changed, 13 insertions(+), 11 deletions(-)
18
19 --- a/arch/mips/lantiq/irq.c
20 +++ b/arch/mips/lantiq/irq.c
21 @@ -195,7 +195,7 @@ static void ltq_hw_irqdispatch(int modul
22 do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
23
24 /* if this is a EBU irq, we need to ack it or get a deadlock */
25 - if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
26 + if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
27 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
28 LTQ_EBU_PCC_ISTAT);
29 }
30 @@ -259,17 +259,19 @@ void __init arch_init_irq(void)
31 if (!ltq_icu_membase)
32 panic("Failed to remap icu memory");
33
34 - if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
35 - panic("Failed to insert eiu memory");
36 + if (LTQ_EIU_BASE_ADDR) {
37 + if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
38 + panic("Failed to insert eiu memory\n");
39 +
40 + if (request_mem_region(ltq_eiu_resource.start,
41 + resource_size(&ltq_eiu_resource), "eiu") < 0)
42 + panic("Failed to request eiu memory\n");
43
44 - if (request_mem_region(ltq_eiu_resource.start,
45 - resource_size(&ltq_eiu_resource), "eiu") < 0)
46 - panic("Failed to request eiu memory");
47 -
48 - ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
49 + ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
50 resource_size(&ltq_eiu_resource));
51 - if (!ltq_eiu_membase)
52 - panic("Failed to remap eiu memory");
53 + if (!ltq_eiu_membase)
54 + panic("Failed to remap eiu memory\n");
55 + }
56
57 /* make sure all irqs are turned off by default */
58 for (i = 0; i < 5; i++)
59 @@ -295,8 +297,8 @@ void __init arch_init_irq(void)
60
61 for (i = INT_NUM_IRQ0;
62 i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
63 - if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
64 - (i == LTQ_EIU_IR2))
65 + if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
66 + (i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR)
67 irq_set_chip_and_handler(i, &ltq_eiu_type,
68 handle_level_irq);
69 /* EIU3-5 only exist on ar9 and vr9 */