target/linux/lantiq/patches-3.3/0048-MIPS-lantiq-pci-rename-variable-inside.patch

   1 From 202f1bad2707e843dccc0fb08233692f8c845f90 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 8 Mar 2012 12:00:17 +0100
   4 Subject: [PATCH 48/70] MIPS: lantiq: pci: rename variable inside
   5
   6 * rename a global var inside the pci code
   7 ---
   8  arch/mips/pci/ops-lantiq.c |    6 +++---
   9  arch/mips/pci/pci-lantiq.c |    6 +++---
  10  arch/mips/pci/pci-lantiq.h |    2 +-
  11  3 files changed, 7 insertions(+), 7 deletions(-)
  12
  13 --- a/arch/mips/pci/ops-lantiq.c
  14 +++ b/arch/mips/pci/ops-lantiq.c
  15 @@ -41,7 +41,7 @@ static int ltq_pci_config_access(unsigne
  16
  17         spin_lock_irqsave(&ebu_lock, flags);
  18
  19 -       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
  20 +       cfg_base = (unsigned long) ltq_pci_cfgbase;
  21         cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
  22                         LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
  23
  24 @@ -55,11 +55,11 @@ static int ltq_pci_config_access(unsigne
  25         wmb();
  26
  27         /* clean possible Master abort */
  28 -       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
  29 +       cfg_base = (unsigned long) ltq_pci_cfgbase;
  30         cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
  31         temp = ltq_r32(((u32 *)(cfg_base)));
  32         temp = swab32(temp);
  33 -       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
  34 +       cfg_base = (unsigned long) ltq_pci_cfgbase;
  35         cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
  36         ltq_w32(temp, ((u32 *)cfg_base));
  37
  38 --- a/arch/mips/pci/pci-lantiq.c
  39 +++ b/arch/mips/pci/pci-lantiq.c
  40 @@ -65,8 +65,8 @@
  41  #define ltq_pci_w32(x, y)      ltq_w32((x), ltq_pci_membase + (y))
  42  #define ltq_pci_r32(x)         ltq_r32(ltq_pci_membase + (x))
  43
  44 -#define ltq_pci_cfg_w32(x, y)  ltq_w32((x), ltq_pci_mapped_cfg + (y))
  45 -#define ltq_pci_cfg_r32(x)     ltq_r32(ltq_pci_mapped_cfg + (x))
  46 +#define ltq_pci_cfg_w32(x, y)  ltq_w32((x), ltq_pci_cfgbase + (y))
  47 +#define ltq_pci_cfg_r32(x)     ltq_r32(ltq_pci_cfgbase + (x))
  48
  49  struct ltq_pci_gpio_map {
  50         int pin;
  51 @@ -273,7 +273,7 @@ static int __devinit ltq_pci_probe(struc
  52         pci_probe_only = 0;
  53         ltq_pci_irq_map = ltq_pci_data->irq;
  54         ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
  55 -       ltq_pci_mapped_cfg =
  56 +       ltq_pci_cfgbase =
  57                 ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
  58         ltq_pci_controller.io_map_base =
  59                 (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
  60 --- a/arch/mips/pci/pci-lantiq.h
  61 +++ b/arch/mips/pci/pci-lantiq.h
  62 @@ -9,7 +9,7 @@
  63  #ifndef _LTQ_PCI_H__
  64  #define _LTQ_PCI_H__
  65
  66 -extern __iomem void *ltq_pci_mapped_cfg;
  67 +extern __iomem void *ltq_pci_cfgbase;
  68  extern int ltq_pci_read_config_dword(struct pci_bus *bus,
  69         unsigned int devfn, int where, int size, u32 *val);
  70  extern int ltq_pci_write_config_dword(struct pci_bus *bus,