target/linux/lantiq/patches-3.3/0052-MIPS-lantiq-make-GPIO3-work-on-AR9.patch

   1 From 85859883ce603bf0db782c03294873dad39176e5 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 13 Aug 2011 13:59:50 +0200
   4 Subject: [PATCH 52/70] MIPS: lantiq: make GPIO3 work on AR9
   5
   6 There are 3 16bit and 1 8bit gpio ports on AR9. The gpio driver needs a hack
   7 at 2 places to make the different register layout of the GPIO3 work properly
   8 with the driver. Before only GPIO0-2 were supported. As the GPIO number scheme
   9 clashes with the new size, we also move the other gpio chips to new offsets.
  10
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  13 ---
  14  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    2 +
  15  arch/mips/lantiq/xway/devices.c                    |    3 +
  16  arch/mips/lantiq/xway/gpio.c                       |   84 ++++++++++++++++----
  17  arch/mips/lantiq/xway/gpio_ebu.c                   |    3 +-
  18  arch/mips/lantiq/xway/gpio_stp.c                   |    3 +-
  19  5 files changed, 75 insertions(+), 20 deletions(-)
  20
  21 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  22 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  23 @@ -126,7 +126,9 @@
  24  #define LTQ_GPIO0_BASE_ADDR    0x1E100B10
  25  #define LTQ_GPIO1_BASE_ADDR    0x1E100B40
  26  #define LTQ_GPIO2_BASE_ADDR    0x1E100B70
  27 +#define LTQ_GPIO3_BASE_ADDR    0x1E100BA0
  28  #define LTQ_GPIO_SIZE          0x30
  29 +#define LTQ_GPIO3_SIZE         0x10
  30
  31  /* SSC */
  32  #define LTQ_SSC_BASE_ADDR      0x1e100800
  33 --- a/arch/mips/lantiq/xway/devices.c
  34 +++ b/arch/mips/lantiq/xway/devices.c
  35 @@ -34,6 +34,7 @@ static struct resource ltq_gpio_resource
  36         MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
  37         MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
  38         MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
  39 +       MEM_RES("gpio3", LTQ_GPIO3_BASE_ADDR, LTQ_GPIO3_SIZE),
  40  };
  41
  42  void __init ltq_register_gpio(void)
  43 @@ -47,6 +48,8 @@ void __init ltq_register_gpio(void)
  44         if (ltq_is_ar9() || ltq_is_vr9()) {
  45                 platform_device_register_simple("ltq_gpio", 2,
  46                         &ltq_gpio_resource[2], 1);
  47 +               platform_device_register_simple("ltq_gpio", 3,
  48 +                       &ltq_gpio_resource[3], 1);
  49         }
  50  }
  51
  52 --- a/arch/mips/lantiq/xway/gpio.c
  53 +++ b/arch/mips/lantiq/xway/gpio.c
  54 @@ -23,9 +23,17 @@
  55  #define LTQ_GPIO_OD            0x14
  56  #define LTQ_GPIO_PUDSEL                0x1C
  57  #define LTQ_GPIO_PUDEN         0x20
  58 +#define LTQ_GPIO3_OD           0x24
  59 +#define LTQ_GPIO3_ALTSEL1      0x24
  60 +#define LTQ_GPIO3_PUDSEL       0x28
  61 +#define LTQ_GPIO3_PUDEN                0x2C
  62
  63 +/* PORT3 only has 8 pins and its register layout
  64 +   is slightly different */
  65  #define PINS_PER_PORT          16
  66 -#define MAX_PORTS              3
  67 +#define PINS_PORT3             8
  68 +#define MAX_PORTS              4
  69 +#define MAX_PIN                        56
  70
  71  #define ltq_gpio_getbit(m, r, p)       (!!(ltq_r32(m + r) & (1 << p)))
  72  #define ltq_gpio_setbit(m, r, p)       ltq_w32_mask(0, (1 << p), m + r)
  73 @@ -55,7 +63,7 @@ int ltq_gpio_request(struct device *dev,
  74  {
  75         int id = 0;
  76
  77 -       if (pin >= (MAX_PORTS * PINS_PER_PORT))
  78 +       if (pin >= MAX_PIN)
  79                 return -EINVAL;
  80         if (devm_gpio_request(dev, pin, name)) {
  81                 pr_err("failed to setup lantiq gpio: %s\n", name);
  82 @@ -75,12 +83,21 @@ int ltq_gpio_request(struct device *dev,
  83         else
  84                 ltq_gpio_clearbit(ltq_gpio_port[id].membase,
  85                         LTQ_GPIO_ALTSEL0, pin);
  86 -       if (mux & 0x1)
  87 -               ltq_gpio_setbit(ltq_gpio_port[id].membase,
  88 -                       LTQ_GPIO_ALTSEL1, pin);
  89 -       else
  90 -               ltq_gpio_clearbit(ltq_gpio_port[id].membase,
  91 -                       LTQ_GPIO_ALTSEL1, pin);
  92 +       if (id == 3) {
  93 +               if (mux & 0x1)
  94 +                       ltq_gpio_setbit(ltq_gpio_port[1].membase,
  95 +                               LTQ_GPIO3_ALTSEL1, pin);
  96 +               else
  97 +                       ltq_gpio_clearbit(ltq_gpio_port[1].membase,
  98 +                               LTQ_GPIO3_ALTSEL1, pin);
  99 +       } else {
 100 +               if (mux & 0x1)
 101 +                       ltq_gpio_setbit(ltq_gpio_port[id].membase,
 102 +                               LTQ_GPIO_ALTSEL1, pin);
 103 +               else
 104 +                       ltq_gpio_clearbit(ltq_gpio_port[id].membase,
 105 +                               LTQ_GPIO_ALTSEL1, pin);
 106 +       }
 107         return 0;
 108  }
 109  EXPORT_SYMBOL(ltq_gpio_request);
 110 @@ -106,10 +123,19 @@ static int ltq_gpio_direction_input(stru
 111  {
 112         struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
 113
 114 -       ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
 115 +       if (chip->ngpio == PINS_PORT3) {
 116 +               ltq_gpio_clearbit(ltq_gpio_port[0].membase,
 117 +                               LTQ_GPIO3_OD, offset);
 118 +               ltq_gpio_setbit(ltq_gpio_port[0].membase,
 119 +                               LTQ_GPIO3_PUDSEL, offset);
 120 +               ltq_gpio_setbit(ltq_gpio_port[0].membase,
 121 +                               LTQ_GPIO3_PUDEN, offset);
 122 +       } else {
 123 +               ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
 124 +               ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
 125 +               ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
 126 +       }
 127         ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
 128 -       ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
 129 -       ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
 130
 131         return 0;
 132  }
 133 @@ -119,10 +145,19 @@ static int ltq_gpio_direction_output(str
 134  {
 135         struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
 136
 137 -       ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
 138 +       if (chip->ngpio == PINS_PORT3) {
 139 +               ltq_gpio_setbit(ltq_gpio_port[0].membase,
 140 +                               LTQ_GPIO3_OD, offset);
 141 +               ltq_gpio_clearbit(ltq_gpio_port[0].membase,
 142 +                               LTQ_GPIO3_PUDSEL, offset);
 143 +               ltq_gpio_clearbit(ltq_gpio_port[0].membase,
 144 +                               LTQ_GPIO3_PUDEN, offset);
 145 +       } else {
 146 +               ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
 147 +               ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
 148 +               ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
 149 +       }
 150         ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
 151 -       ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
 152 -       ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
 153         ltq_gpio_set(chip, offset, value);
 154
 155         return 0;
 156 @@ -133,7 +168,11 @@ static int ltq_gpio_req(struct gpio_chip
 157         struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
 158
 159         ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
 160 -       ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
 161 +       if (chip->ngpio == PINS_PORT3)
 162 +               ltq_gpio_clearbit(ltq_gpio_port[1].membase,
 163 +                               LTQ_GPIO3_ALTSEL1, offset);
 164 +       else
 165 +               ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
 166         return 0;
 167  }
 168
 169 @@ -146,6 +185,16 @@ static int ltq_gpio_probe(struct platfor
 170                         pdev->id);
 171                 return -EINVAL;
 172         }
 173 +
 174 +       /* dirty hack - The registers of port3 are not mapped linearly.
 175 +          Port 3 may only load if Port 1/2 are mapped */
 176 +       if ((pdev->id == 3) && (!ltq_gpio_port[1].membase
 177 +                                       || !ltq_gpio_port[2].membase)) {
 178 +               dev_err(&pdev->dev,
 179 +                       "ports 1/2 need to be loaded before port 3 works\n");
 180 +               return -ENOMEM;
 181 +       }
 182 +
 183         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 184         if (!res) {
 185                 dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
 186 @@ -175,7 +224,10 @@ static int ltq_gpio_probe(struct platfor
 187         ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
 188         ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
 189         ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
 190 -       ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
 191 +       if (pdev->id == 3)
 192 +               ltq_gpio_port[pdev->id].chip.ngpio = PINS_PORT3;
 193 +       else
 194 +               ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
 195         platform_set_drvdata(pdev, &ltq_gpio_port[pdev->id]);
 196         return gpiochip_add(&ltq_gpio_port[pdev->id].chip);
 197  }
 198 --- a/arch/mips/lantiq/xway/gpio_ebu.c
 199 +++ b/arch/mips/lantiq/xway/gpio_ebu.c
 200 @@ -61,9 +61,8 @@ static struct gpio_chip ltq_ebu_chip = {
 201         .label = "ltq_ebu",
 202         .direction_output = ltq_ebu_direction_output,
 203         .set = ltq_ebu_set,
 204 -       .base = 72,
 205 +       .base = 100,
 206         .ngpio = 16,
 207 -       .can_sleep = 1,
 208         .owner = THIS_MODULE,
 209  };
 210
 211 --- a/arch/mips/lantiq/xway/gpio_stp.c
 212 +++ b/arch/mips/lantiq/xway/gpio_stp.c
 213 @@ -74,9 +74,8 @@ static struct gpio_chip ltq_stp_chip = {
 214         .label = "ltq_stp",
 215         .direction_output = ltq_stp_direction_output,
 216         .set = ltq_stp_set,
 217 -       .base = 48,
 218 +       .base = 200,
 219         .ngpio = 24,
 220 -       .can_sleep = 1,
 221         .owner = THIS_MODULE,
 222  };
 223