[lantiq] Add missing 3.3 patches
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.3 / 100-falcon_bsp_header.patch
1 --- /dev/null
2 +++ b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h
3 @@ -0,0 +1,376 @@
4 +/******************************************************************************
5 +
6 + Copyright (c) 2010
7 + Lantiq Deutschland GmbH
8 +
9 + For licensing information, see the file 'LICENSE' in the root folder of
10 + this software module.
11 +
12 +******************************************************************************/
13 +
14 +#ifndef _gpon_reg_base_h
15 +#define _gpon_reg_base_h
16 +
17 +/** \addtogroup GPON_BASE
18 + @{
19 +*/
20 +
21 +#ifndef KSEG1
22 +#define KSEG1 0xA0000000
23 +#endif
24 +
25 +/** address range for ebu
26 + 0x18000000--0x180000FF */
27 +#define GPON_EBU_BASE (KSEG1 | 0x18000000)
28 +#define GPON_EBU_END (KSEG1 | 0x180000FF)
29 +#define GPON_EBU_SIZE 0x00000100
30 +/** address range for gpearb
31 + 0x1D400100--0x1D4001FF */
32 +#define GPON_GPEARB_BASE (KSEG1 | 0x1D400100)
33 +#define GPON_GPEARB_END (KSEG1 | 0x1D4001FF)
34 +#define GPON_GPEARB_SIZE 0x00000100
35 +/** address range for tmu
36 + 0x1D404000--0x1D404FFF */
37 +#define GPON_TMU_BASE (KSEG1 | 0x1D404000)
38 +#define GPON_TMU_END (KSEG1 | 0x1D404FFF)
39 +#define GPON_TMU_SIZE 0x00001000
40 +/** address range for iqm
41 + 0x1D410000--0x1D41FFFF */
42 +#define GPON_IQM_BASE (KSEG1 | 0x1D410000)
43 +#define GPON_IQM_END (KSEG1 | 0x1D41FFFF)
44 +#define GPON_IQM_SIZE 0x00010000
45 +/** address range for octrlg
46 + 0x1D420000--0x1D42FFFF */
47 +#define GPON_OCTRLG_BASE (KSEG1 | 0x1D420000)
48 +#define GPON_OCTRLG_END (KSEG1 | 0x1D42FFFF)
49 +#define GPON_OCTRLG_SIZE 0x00010000
50 +/** address range for octrll0
51 + 0x1D440000--0x1D4400FF */
52 +#define GPON_OCTRLL0_BASE (KSEG1 | 0x1D440000)
53 +#define GPON_OCTRLL0_END (KSEG1 | 0x1D4400FF)
54 +#define GPON_OCTRLL0_SIZE 0x00000100
55 +/** address range for octrll1
56 + 0x1D440100--0x1D4401FF */
57 +#define GPON_OCTRLL1_BASE (KSEG1 | 0x1D440100)
58 +#define GPON_OCTRLL1_END (KSEG1 | 0x1D4401FF)
59 +#define GPON_OCTRLL1_SIZE 0x00000100
60 +/** address range for octrll2
61 + 0x1D440200--0x1D4402FF */
62 +#define GPON_OCTRLL2_BASE (KSEG1 | 0x1D440200)
63 +#define GPON_OCTRLL2_END (KSEG1 | 0x1D4402FF)
64 +#define GPON_OCTRLL2_SIZE 0x00000100
65 +/** address range for octrll3
66 + 0x1D440300--0x1D4403FF */
67 +#define GPON_OCTRLL3_BASE (KSEG1 | 0x1D440300)
68 +#define GPON_OCTRLL3_END (KSEG1 | 0x1D4403FF)
69 +#define GPON_OCTRLL3_SIZE 0x00000100
70 +/** address range for octrlc
71 + 0x1D441000--0x1D4410FF */
72 +#define GPON_OCTRLC_BASE (KSEG1 | 0x1D441000)
73 +#define GPON_OCTRLC_END (KSEG1 | 0x1D4410FF)
74 +#define GPON_OCTRLC_SIZE 0x00000100
75 +/** address range for ictrlg
76 + 0x1D450000--0x1D45FFFF */
77 +#define GPON_ICTRLG_BASE (KSEG1 | 0x1D450000)
78 +#define GPON_ICTRLG_END (KSEG1 | 0x1D45FFFF)
79 +#define GPON_ICTRLG_SIZE 0x00010000
80 +/** address range for ictrll0
81 + 0x1D460000--0x1D4601FF */
82 +#define GPON_ICTRLL0_BASE (KSEG1 | 0x1D460000)
83 +#define GPON_ICTRLL0_END (KSEG1 | 0x1D4601FF)
84 +#define GPON_ICTRLL0_SIZE 0x00000200
85 +/** address range for ictrll1
86 + 0x1D460200--0x1D4603FF */
87 +#define GPON_ICTRLL1_BASE (KSEG1 | 0x1D460200)
88 +#define GPON_ICTRLL1_END (KSEG1 | 0x1D4603FF)
89 +#define GPON_ICTRLL1_SIZE 0x00000200
90 +/** address range for ictrll2
91 + 0x1D460400--0x1D4605FF */
92 +#define GPON_ICTRLL2_BASE (KSEG1 | 0x1D460400)
93 +#define GPON_ICTRLL2_END (KSEG1 | 0x1D4605FF)
94 +#define GPON_ICTRLL2_SIZE 0x00000200
95 +/** address range for ictrll3
96 + 0x1D460600--0x1D4607FF */
97 +#define GPON_ICTRLL3_BASE (KSEG1 | 0x1D460600)
98 +#define GPON_ICTRLL3_END (KSEG1 | 0x1D4607FF)
99 +#define GPON_ICTRLL3_SIZE 0x00000200
100 +/** address range for ictrlc0
101 + 0x1D461000--0x1D4610FF */
102 +#define GPON_ICTRLC0_BASE (KSEG1 | 0x1D461000)
103 +#define GPON_ICTRLC0_END (KSEG1 | 0x1D4610FF)
104 +#define GPON_ICTRLC0_SIZE 0x00000100
105 +/** address range for ictrlc1
106 + 0x1D461100--0x1D4611FF */
107 +#define GPON_ICTRLC1_BASE (KSEG1 | 0x1D461100)
108 +#define GPON_ICTRLC1_END (KSEG1 | 0x1D4611FF)
109 +#define GPON_ICTRLC1_SIZE 0x00000100
110 +/** address range for fsqm
111 + 0x1D500000--0x1D5FFFFF */
112 +#define GPON_FSQM_BASE (KSEG1 | 0x1D500000)
113 +#define GPON_FSQM_END (KSEG1 | 0x1D5FFFFF)
114 +#define GPON_FSQM_SIZE 0x00100000
115 +/** address range for pctrl
116 + 0x1D600000--0x1D6001FF */
117 +#define GPON_PCTRL_BASE (KSEG1 | 0x1D600000)
118 +#define GPON_PCTRL_END (KSEG1 | 0x1D6001FF)
119 +#define GPON_PCTRL_SIZE 0x00000200
120 +/** address range for link0
121 + 0x1D600200--0x1D6002FF */
122 +#define GPON_LINK0_BASE (KSEG1 | 0x1D600200)
123 +#define GPON_LINK0_END (KSEG1 | 0x1D6002FF)
124 +#define GPON_LINK0_SIZE 0x00000100
125 +/** address range for link1
126 + 0x1D600300--0x1D6003FF */
127 +#define GPON_LINK1_BASE (KSEG1 | 0x1D600300)
128 +#define GPON_LINK1_END (KSEG1 | 0x1D6003FF)
129 +#define GPON_LINK1_SIZE 0x00000100
130 +/** address range for link2
131 + 0x1D600400--0x1D6004FF */
132 +#define GPON_LINK2_BASE (KSEG1 | 0x1D600400)
133 +#define GPON_LINK2_END (KSEG1 | 0x1D6004FF)
134 +#define GPON_LINK2_SIZE 0x00000100
135 +/** address range for disp
136 + 0x1D600500--0x1D6005FF */
137 +#define GPON_DISP_BASE (KSEG1 | 0x1D600500)
138 +#define GPON_DISP_END (KSEG1 | 0x1D6005FF)
139 +#define GPON_DISP_SIZE 0x00000100
140 +/** address range for merge
141 + 0x1D600600--0x1D6006FF */
142 +#define GPON_MERGE_BASE (KSEG1 | 0x1D600600)
143 +#define GPON_MERGE_END (KSEG1 | 0x1D6006FF)
144 +#define GPON_MERGE_SIZE 0x00000100
145 +/** address range for tbm
146 + 0x1D600700--0x1D6007FF */
147 +#define GPON_TBM_BASE (KSEG1 | 0x1D600700)
148 +#define GPON_TBM_END (KSEG1 | 0x1D6007FF)
149 +#define GPON_TBM_SIZE 0x00000100
150 +/** address range for pe0
151 + 0x1D610000--0x1D61FFFF */
152 +#define GPON_PE0_BASE (KSEG1 | 0x1D610000)
153 +#define GPON_PE0_END (KSEG1 | 0x1D61FFFF)
154 +#define GPON_PE0_SIZE 0x00010000
155 +/** address range for pe1
156 + 0x1D620000--0x1D62FFFF */
157 +#define GPON_PE1_BASE (KSEG1 | 0x1D620000)
158 +#define GPON_PE1_END (KSEG1 | 0x1D62FFFF)
159 +#define GPON_PE1_SIZE 0x00010000
160 +/** address range for pe2
161 + 0x1D630000--0x1D63FFFF */
162 +#define GPON_PE2_BASE (KSEG1 | 0x1D630000)
163 +#define GPON_PE2_END (KSEG1 | 0x1D63FFFF)
164 +#define GPON_PE2_SIZE 0x00010000
165 +/** address range for pe3
166 + 0x1D640000--0x1D64FFFF */
167 +#define GPON_PE3_BASE (KSEG1 | 0x1D640000)
168 +#define GPON_PE3_END (KSEG1 | 0x1D64FFFF)
169 +#define GPON_PE3_SIZE 0x00010000
170 +/** address range for pe4
171 + 0x1D650000--0x1D65FFFF */
172 +#define GPON_PE4_BASE (KSEG1 | 0x1D650000)
173 +#define GPON_PE4_END (KSEG1 | 0x1D65FFFF)
174 +#define GPON_PE4_SIZE 0x00010000
175 +/** address range for pe5
176 + 0x1D660000--0x1D66FFFF */
177 +#define GPON_PE5_BASE (KSEG1 | 0x1D660000)
178 +#define GPON_PE5_END (KSEG1 | 0x1D66FFFF)
179 +#define GPON_PE5_SIZE 0x00010000
180 +/** address range for sys_gpe
181 + 0x1D700000--0x1D7000FF */
182 +#define GPON_SYS_GPE_BASE (KSEG1 | 0x1D700000)
183 +#define GPON_SYS_GPE_END (KSEG1 | 0x1D7000FF)
184 +#define GPON_SYS_GPE_SIZE 0x00000100
185 +/** address range for eim
186 + 0x1D800000--0x1D800FFF */
187 +#define GPON_EIM_BASE (KSEG1 | 0x1D800000)
188 +#define GPON_EIM_END (KSEG1 | 0x1D800FFF)
189 +#define GPON_EIM_SIZE 0x00001000
190 +/** address range for sxgmii
191 + 0x1D808800--0x1D8088FF */
192 +#define GPON_SXGMII_BASE (KSEG1 | 0x1D808800)
193 +#define GPON_SXGMII_END (KSEG1 | 0x1D8088FF)
194 +#define GPON_SXGMII_SIZE 0x00000100
195 +/** address range for sgmii
196 + 0x1D808C00--0x1D808CFF */
197 +#define GPON_SGMII_BASE (KSEG1 | 0x1D808C00)
198 +#define GPON_SGMII_END (KSEG1 | 0x1D808CFF)
199 +#define GPON_SGMII_SIZE 0x00000100
200 +/** address range for gpio0
201 + 0x1D810000--0x1D81007F */
202 +#define GPON_GPIO0_BASE (KSEG1 | 0x1D810000)
203 +#define GPON_GPIO0_END (KSEG1 | 0x1D81007F)
204 +#define GPON_GPIO0_SIZE 0x00000080
205 +/** address range for gpio2
206 + 0x1D810100--0x1D81017F */
207 +#define GPON_GPIO2_BASE (KSEG1 | 0x1D810100)
208 +#define GPON_GPIO2_END (KSEG1 | 0x1D81017F)
209 +#define GPON_GPIO2_SIZE 0x00000080
210 +/** address range for sys_eth
211 + 0x1DB00000--0x1DB000FF */
212 +#define GPON_SYS_ETH_BASE (KSEG1 | 0x1DB00000)
213 +#define GPON_SYS_ETH_END (KSEG1 | 0x1DB000FF)
214 +#define GPON_SYS_ETH_SIZE 0x00000100
215 +/** address range for padctrl0
216 + 0x1DB01000--0x1DB010FF */
217 +#define GPON_PADCTRL0_BASE (KSEG1 | 0x1DB01000)
218 +#define GPON_PADCTRL0_END (KSEG1 | 0x1DB010FF)
219 +#define GPON_PADCTRL0_SIZE 0x00000100
220 +/** address range for padctrl2
221 + 0x1DB02000--0x1DB020FF */
222 +#define GPON_PADCTRL2_BASE (KSEG1 | 0x1DB02000)
223 +#define GPON_PADCTRL2_END (KSEG1 | 0x1DB020FF)
224 +#define GPON_PADCTRL2_SIZE 0x00000100
225 +/** address range for gtc
226 + 0x1DC05000--0x1DC052D4 */
227 +#define GPON_GTC_BASE (KSEG1 | 0x1DC05000)
228 +#define GPON_GTC_END (KSEG1 | 0x1DC052D4)
229 +#define GPON_GTC_SIZE 0x000002D5
230 +/** address range for pma
231 + 0x1DD00000--0x1DD003FF */
232 +#define GPON_PMA_BASE (KSEG1 | 0x1DD00000)
233 +#define GPON_PMA_END (KSEG1 | 0x1DD003FF)
234 +#define GPON_PMA_SIZE 0x00000400
235 +/** address range for fcsic
236 + 0x1DD00600--0x1DD0061F */
237 +#define GPON_FCSIC_BASE (KSEG1 | 0x1DD00600)
238 +#define GPON_FCSIC_END (KSEG1 | 0x1DD0061F)
239 +#define GPON_FCSIC_SIZE 0x00000020
240 +/** address range for pma_int200
241 + 0x1DD00700--0x1DD0070F */
242 +#define GPON_PMA_INT200_BASE (KSEG1 | 0x1DD00700)
243 +#define GPON_PMA_INT200_END (KSEG1 | 0x1DD0070F)
244 +#define GPON_PMA_INT200_SIZE 0x00000010
245 +/** address range for pma_inttx
246 + 0x1DD00720--0x1DD0072F */
247 +#define GPON_PMA_INTTX_BASE (KSEG1 | 0x1DD00720)
248 +#define GPON_PMA_INTTX_END (KSEG1 | 0x1DD0072F)
249 +#define GPON_PMA_INTTX_SIZE 0x00000010
250 +/** address range for pma_intrx
251 + 0x1DD00740--0x1DD0074F */
252 +#define GPON_PMA_INTRX_BASE (KSEG1 | 0x1DD00740)
253 +#define GPON_PMA_INTRX_END (KSEG1 | 0x1DD0074F)
254 +#define GPON_PMA_INTRX_SIZE 0x00000010
255 +/** address range for gtc_pma
256 + 0x1DEFFF00--0x1DEFFFFF */
257 +#define GPON_GTC_PMA_BASE (KSEG1 | 0x1DEFFF00)
258 +#define GPON_GTC_PMA_END (KSEG1 | 0x1DEFFFFF)
259 +#define GPON_GTC_PMA_SIZE 0x00000100
260 +/** address range for sys
261 + 0x1DF00000--0x1DF000FF */
262 +#define GPON_SYS_BASE (KSEG1 | 0x1DF00000)
263 +#define GPON_SYS_END (KSEG1 | 0x1DF000FF)
264 +#define GPON_SYS_SIZE 0x00000100
265 +/** address range for asc1
266 + 0x1E100B00--0x1E100BFF */
267 +#define GPON_ASC1_BASE (KSEG1 | 0x1E100B00)
268 +#define GPON_ASC1_END (KSEG1 | 0x1E100BFF)
269 +#define GPON_ASC1_SIZE 0x00000100
270 +/** address range for asc0
271 + 0x1E100C00--0x1E100CFF */
272 +#define GPON_ASC0_BASE (KSEG1 | 0x1E100C00)
273 +#define GPON_ASC0_END (KSEG1 | 0x1E100CFF)
274 +#define GPON_ASC0_SIZE 0x00000100
275 +/** address range for i2c
276 + 0x1E200000--0x1E20FFFF */
277 +#define GPON_I2C_BASE (KSEG1 | 0x1E200000)
278 +#define GPON_I2C_END (KSEG1 | 0x1E20FFFF)
279 +#define GPON_I2C_SIZE 0x00010000
280 +/** address range for gpio1
281 + 0x1E800100--0x1E80017F */
282 +#define GPON_GPIO1_BASE (KSEG1 | 0x1E800100)
283 +#define GPON_GPIO1_END (KSEG1 | 0x1E80017F)
284 +#define GPON_GPIO1_SIZE 0x00000080
285 +/** address range for gpio3
286 + 0x1E800200--0x1E80027F */
287 +#define GPON_GPIO3_BASE (KSEG1 | 0x1E800200)
288 +#define GPON_GPIO3_END (KSEG1 | 0x1E80027F)
289 +#define GPON_GPIO3_SIZE 0x00000080
290 +/** address range for gpio4
291 + 0x1E800300--0x1E80037F */
292 +#define GPON_GPIO4_BASE (KSEG1 | 0x1E800300)
293 +#define GPON_GPIO4_END (KSEG1 | 0x1E80037F)
294 +#define GPON_GPIO4_SIZE 0x00000080
295 +/** address range for padctrl1
296 + 0x1E800400--0x1E8004FF */
297 +#define GPON_PADCTRL1_BASE (KSEG1 | 0x1E800400)
298 +#define GPON_PADCTRL1_END (KSEG1 | 0x1E8004FF)
299 +#define GPON_PADCTRL1_SIZE 0x00000100
300 +/** address range for padctrl3
301 + 0x1E800500--0x1E8005FF */
302 +#define GPON_PADCTRL3_BASE (KSEG1 | 0x1E800500)
303 +#define GPON_PADCTRL3_END (KSEG1 | 0x1E8005FF)
304 +#define GPON_PADCTRL3_SIZE 0x00000100
305 +/** address range for padctrl4
306 + 0x1E800600--0x1E8006FF */
307 +#define GPON_PADCTRL4_BASE (KSEG1 | 0x1E800600)
308 +#define GPON_PADCTRL4_END (KSEG1 | 0x1E8006FF)
309 +#define GPON_PADCTRL4_SIZE 0x00000100
310 +/** address range for status
311 + 0x1E802000--0x1E80207F */
312 +#define GPON_STATUS_BASE (KSEG1 | 0x1E802000)
313 +#define GPON_STATUS_END (KSEG1 | 0x1E80207F)
314 +#define GPON_STATUS_SIZE 0x00000080
315 +/** address range for dcdc_1v0
316 + 0x1E803000--0x1E8033FF */
317 +#define GPON_DCDC_1V0_BASE (KSEG1 | 0x1E803000)
318 +#define GPON_DCDC_1V0_END (KSEG1 | 0x1E8033FF)
319 +#define GPON_DCDC_1V0_SIZE 0x00000400
320 +/** address range for dcdc_ddr
321 + 0x1E804000--0x1E8043FF */
322 +#define GPON_DCDC_DDR_BASE (KSEG1 | 0x1E804000)
323 +#define GPON_DCDC_DDR_END (KSEG1 | 0x1E8043FF)
324 +#define GPON_DCDC_DDR_SIZE 0x00000400
325 +/** address range for dcdc_apd
326 + 0x1E805000--0x1E8053FF */
327 +#define GPON_DCDC_APD_BASE (KSEG1 | 0x1E805000)
328 +#define GPON_DCDC_APD_END (KSEG1 | 0x1E8053FF)
329 +#define GPON_DCDC_APD_SIZE 0x00000400
330 +/** address range for sys1
331 + 0x1EF00000--0x1EF000FF */
332 +#define GPON_SYS1_BASE (KSEG1 | 0x1EF00000)
333 +#define GPON_SYS1_END (KSEG1 | 0x1EF000FF)
334 +#define GPON_SYS1_SIZE 0x00000100
335 +/** address range for sbs0ctrl
336 + 0x1F080000--0x1F0801FF */
337 +#define GPON_SBS0CTRL_BASE (KSEG1 | 0x1F080000)
338 +#define GPON_SBS0CTRL_END (KSEG1 | 0x1F0801FF)
339 +#define GPON_SBS0CTRL_SIZE 0x00000200
340 +/** address range for sbs0red
341 + 0x1F080200--0x1F08027F */
342 +#define GPON_SBS0RED_BASE (KSEG1 | 0x1F080200)
343 +#define GPON_SBS0RED_END (KSEG1 | 0x1F08027F)
344 +#define GPON_SBS0RED_SIZE 0x00000080
345 +/** address range for sbs0ram
346 + 0x1F200000--0x1F32FFFF */
347 +#define GPON_SBS0RAM_BASE (KSEG1 | 0x1F200000)
348 +#define GPON_SBS0RAM_END (KSEG1 | 0x1F32FFFF)
349 +#define GPON_SBS0RAM_SIZE 0x00130000
350 +/** address range for ddrdb
351 + 0x1F701000--0x1F701FFF */
352 +#define GPON_DDRDB_BASE (KSEG1 | 0x1F701000)
353 +#define GPON_DDRDB_END (KSEG1 | 0x1F701FFF)
354 +#define GPON_DDRDB_SIZE 0x00001000
355 +/** address range for sbiu
356 + 0x1F880000--0x1F8800FF */
357 +#define GPON_SBIU_BASE (KSEG1 | 0x1F880000)
358 +#define GPON_SBIU_END (KSEG1 | 0x1F8800FF)
359 +#define GPON_SBIU_SIZE 0x00000100
360 +/** address range for icu0
361 + 0x1F880200--0x1F8802DF */
362 +#define GPON_ICU0_BASE (KSEG1 | 0x1F880200)
363 +#define GPON_ICU0_END (KSEG1 | 0x1F8802DF)
364 +#define GPON_ICU0_SIZE 0x000000E0
365 +/** address range for icu1
366 + 0x1F880300--0x1F8803DF */
367 +#define GPON_ICU1_BASE (KSEG1 | 0x1F880300)
368 +#define GPON_ICU1_END (KSEG1 | 0x1F8803DF)
369 +#define GPON_ICU1_SIZE 0x000000E0
370 +/** address range for wdt
371 + 0x1F8803F0--0x1F8803FF */
372 +#define GPON_WDT_BASE (KSEG1 | 0x1F8803F0)
373 +#define GPON_WDT_END (KSEG1 | 0x1F8803FF)
374 +#define GPON_WDT_SIZE 0x00000010
375 +
376 +/*! @} */ /* GPON_BASE */
377 +
378 +#endif /* _gpon_reg_base_h */
379 +
380 --- /dev/null
381 +++ b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h
382 @@ -0,0 +1,830 @@
383 +/******************************************************************************
384 +
385 + Copyright (c) 2010
386 + Lantiq Deutschland GmbH
387 +
388 + For licensing information, see the file 'LICENSE' in the root folder of
389 + this software module.
390 +
391 +******************************************************************************/
392 +
393 +#ifndef _i2c_reg_h
394 +#define _i2c_reg_h
395 +
396 +/** \addtogroup I2C_REGISTER
397 + @{
398 +*/
399 +/* access macros */
400 +#define i2c_r32(reg) reg_r32(&i2c->reg)
401 +#define i2c_w32(val, reg) reg_w32(val, &i2c->reg)
402 +#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg)
403 +#define i2c_r32_table(reg, idx) reg_r32_table(i2c->reg, idx)
404 +#define i2c_w32_table(val, reg, idx) reg_w32_table(val, i2c->reg, idx)
405 +#define i2c_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, i2c->reg, idx)
406 +#define i2c_adr_table(reg, idx) adr_table(i2c->reg, idx)
407 +
408 +
409 +/** I2C register structure */
410 +struct gpon_reg_i2c
411 +{
412 + /** I2C Kernel Clock Control Register */
413 + unsigned int clc; /* 0x00000000 */
414 + /** Reserved */
415 + unsigned int res_0; /* 0x00000004 */
416 + /** I2C Identification Register */
417 + unsigned int id; /* 0x00000008 */
418 + /** Reserved */
419 + unsigned int res_1; /* 0x0000000C */
420 + /** I2C RUN Control Register
421 + This register enables and disables the I2C peripheral. Before enabling, the I2C has to be configured properly. After enabling no configuration is possible */
422 + unsigned int run_ctrl; /* 0x00000010 */
423 + /** I2C End Data Control Register
424 + This register is used to either turn around the data transmission direction or to address another slave without sending a stop condition. Also the software can stop the slave-transmitter by sending a not-accolade when working as master-receiver or even stop data transmission immediately when operating as master-transmitter. The writing to the bits of this control register is only effective when in MASTER RECEIVES BYTES, MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state */
425 + unsigned int endd_ctrl; /* 0x00000014 */
426 + /** I2C Fractional Divider Configuration Register
427 + These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_HIGH_CFG has the same layout as I2C_FDIV_CFG. */
428 + unsigned int fdiv_cfg; /* 0x00000018 */
429 + /** I2C Fractional Divider (highspeed mode) Configuration Register
430 + These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_CFG has the same layout as I2C_FDIV_CFG. */
431 + unsigned int fdiv_high_cfg; /* 0x0000001C */
432 + /** I2C Address Configuration Register */
433 + unsigned int addr_cfg; /* 0x00000020 */
434 + /** I2C Bus Status Register
435 + This register gives a status information of the I2C. This additional information can be used by the software to start proper actions. */
436 + unsigned int bus_stat; /* 0x00000024 */
437 + /** I2C FIFO Configuration Register */
438 + unsigned int fifo_cfg; /* 0x00000028 */
439 + /** I2C Maximum Received Packet Size Register */
440 + unsigned int mrps_ctrl; /* 0x0000002C */
441 + /** I2C Received Packet Size Status Register */
442 + unsigned int rps_stat; /* 0x00000030 */
443 + /** I2C Transmit Packet Size Register */
444 + unsigned int tps_ctrl; /* 0x00000034 */
445 + /** I2C Filled FIFO Stages Status Register */
446 + unsigned int ffs_stat; /* 0x00000038 */
447 + /** Reserved */
448 + unsigned int res_2; /* 0x0000003C */
449 + /** I2C Timing Configuration Register */
450 + unsigned int tim_cfg; /* 0x00000040 */
451 + /** Reserved */
452 + unsigned int res_3[7]; /* 0x00000044 */
453 + /** I2C Error Interrupt Request Source Mask Register */
454 + unsigned int err_irqsm; /* 0x00000060 */
455 + /** I2C Error Interrupt Request Source Status Register */
456 + unsigned int err_irqss; /* 0x00000064 */
457 + /** I2C Error Interrupt Request Source Clear Register */
458 + unsigned int err_irqsc; /* 0x00000068 */
459 + /** Reserved */
460 + unsigned int res_4; /* 0x0000006C */
461 + /** I2C Protocol Interrupt Request Source Mask Register */
462 + unsigned int p_irqsm; /* 0x00000070 */
463 + /** I2C Protocol Interrupt Request Source Status Register */
464 + unsigned int p_irqss; /* 0x00000074 */
465 + /** I2C Protocol Interrupt Request Source Clear Register */
466 + unsigned int p_irqsc; /* 0x00000078 */
467 + /** Reserved */
468 + unsigned int res_5; /* 0x0000007C */
469 + /** I2C Raw Interrupt Status Register */
470 + unsigned int ris; /* 0x00000080 */
471 + /** I2C Interrupt Mask Control Register */
472 + unsigned int imsc; /* 0x00000084 */
473 + /** I2C Masked Interrupt Status Register */
474 + unsigned int mis; /* 0x00000088 */
475 + /** I2C Interrupt Clear Register */
476 + unsigned int icr; /* 0x0000008C */
477 + /** I2C Interrupt Set Register */
478 + unsigned int isr; /* 0x00000090 */
479 + /** I2C DMA Enable Register */
480 + unsigned int dmae; /* 0x00000094 */
481 + /** Reserved */
482 + unsigned int res_6[8154]; /* 0x00000098 */
483 + /** I2C Transmit Data Register */
484 + unsigned int txd; /* 0x00008000 */
485 + /** Reserved */
486 + unsigned int res_7[4095]; /* 0x00008004 */
487 + /** I2C Receive Data Register */
488 + unsigned int rxd; /* 0x0000C000 */
489 + /** Reserved */
490 + unsigned int res_8[4095]; /* 0x0000C004 */
491 +};
492 +
493 +
494 +/* Fields of "I2C Kernel Clock Control Register" */
495 +/** Clock Divider for Optional Run Mode (AHB peripherals)
496 + Max 8-bit divider value. Note: As long as the new divider value ORMC is not valid, the register returns 0x0000 00xx on reading. */
497 +#define I2C_CLC_ORMC_MASK 0x00FF0000
498 +/** field offset */
499 +#define I2C_CLC_ORMC_OFFSET 16
500 +/** Clock Divider for Normal Run Mode
501 + Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long as the new divider value RMC is not valid, the register returns 0x0000 00xx on reading. */
502 +#define I2C_CLC_RMC_MASK 0x0000FF00
503 +/** field offset */
504 +#define I2C_CLC_RMC_OFFSET 8
505 +/** Fast Shut-Off Enable Bit */
506 +#define I2C_CLC_FSOE 0x00000020
507 +/* Disable
508 +#define I2C_CLC_FSOE_DIS 0x00000000 */
509 +/** Enable */
510 +#define I2C_CLC_FSOE_EN 0x00000020
511 +/** Suspend Bit Write Enable for OCDS */
512 +#define I2C_CLC_SBWE 0x00000010
513 +/* Disable
514 +#define I2C_CLC_SBWE_DIS 0x00000000 */
515 +/** Enable */
516 +#define I2C_CLC_SBWE_EN 0x00000010
517 +/** Disable External Request Disable */
518 +#define I2C_CLC_EDIS 0x00000008
519 +/* Enable
520 +#define I2C_CLC_EDIS_EN 0x00000000 */
521 +/** Disable */
522 +#define I2C_CLC_EDIS_DIS 0x00000008
523 +/** Suspend Enable Bit for OCDS */
524 +#define I2C_CLC_SPEN 0x00000004
525 +/* Disable
526 +#define I2C_CLC_SPEN_DIS 0x00000000 */
527 +/** Enable */
528 +#define I2C_CLC_SPEN_EN 0x00000004
529 +/** Disable Status Bit
530 + Bit DISS can be modified only by writing to bit DISR */
531 +#define I2C_CLC_DISS 0x00000002
532 +/* Enable
533 +#define I2C_CLC_DISS_EN 0x00000000 */
534 +/** Disable */
535 +#define I2C_CLC_DISS_DIS 0x00000002
536 +/** Disable Request Bit */
537 +#define I2C_CLC_DISR 0x00000001
538 +/* Module disable not requested
539 +#define I2C_CLC_DISR_OFF 0x00000000 */
540 +/** Module disable requested */
541 +#define I2C_CLC_DISR_ON 0x00000001
542 +
543 +/* Fields of "I2C Identification Register" */
544 +/** Module ID */
545 +#define I2C_ID_ID_MASK 0x0000FF00
546 +/** field offset */
547 +#define I2C_ID_ID_OFFSET 8
548 +/** Revision */
549 +#define I2C_ID_REV_MASK 0x000000FF
550 +/** field offset */
551 +#define I2C_ID_REV_OFFSET 0
552 +
553 +/* Fields of "I2C RUN Control Register" */
554 +/** Enabling I2C Interface
555 + Only when this bit is set to zero, the configuration registers of the I2C peripheral are writable by SW. */
556 +#define I2C_RUN_CTRL_RUN 0x00000001
557 +/* Disable
558 +#define I2C_RUN_CTRL_RUN_DIS 0x00000000 */
559 +/** Enable */
560 +#define I2C_RUN_CTRL_RUN_EN 0x00000001
561 +
562 +/* Fields of "I2C End Data Control Register" */
563 +/** Set End of Transmission
564 + Note:Do not write '1' to this bit when bus is free. This will cause an abort after the first byte when a new transfer is started. */
565 +#define I2C_ENDD_CTRL_SETEND 0x00000002
566 +/* No-Operation
567 +#define I2C_ENDD_CTRL_SETEND_NOP 0x00000000 */
568 +/** Master Receives Bytes */
569 +#define I2C_ENDD_CTRL_SETEND_MRB 0x00000002
570 +/** Set Restart Condition */
571 +#define I2C_ENDD_CTRL_SETRSC 0x00000001
572 +/* No-Operation
573 +#define I2C_ENDD_CTRL_SETRSC_NOP 0x00000000 */
574 +/** Master Restart */
575 +#define I2C_ENDD_CTRL_SETRSC_RESTART 0x00000001
576 +
577 +/* Fields of "I2C Fractional Divider Configuration Register" */
578 +/** Decrement Value of fractional divider */
579 +#define I2C_FDIV_CFG_INC_MASK 0x00FF0000
580 +/** field offset */
581 +#define I2C_FDIV_CFG_INC_OFFSET 16
582 +/** Increment Value of fractional divider */
583 +#define I2C_FDIV_CFG_DEC_MASK 0x000007FF
584 +/** field offset */
585 +#define I2C_FDIV_CFG_DEC_OFFSET 0
586 +
587 +/* Fields of "I2C Fractional Divider (highspeed mode) Configuration Register" */
588 +/** Decrement Value of fractional divider */
589 +#define I2C_FDIV_HIGH_CFG_INC_MASK 0x00FF0000
590 +/** field offset */
591 +#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16
592 +/** Increment Value of fractional divider */
593 +#define I2C_FDIV_HIGH_CFG_DEC_MASK 0x000007FF
594 +/** field offset */
595 +#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0
596 +
597 +/* Fields of "I2C Address Configuration Register" */
598 +/** Stop on Packet End
599 + If device works as receiver a not acknowledge is generated in both cases. After successful transmission of a master code (during high speed mode) SOPE is not considered till a stop condition is manually generated by SETEND. */
600 +#define I2C_ADDR_CFG_SOPE 0x00200000
601 +/* Disable
602 +#define I2C_ADDR_CFG_SOPE_DIS 0x00000000 */
603 +/** Enable */
604 +#define I2C_ADDR_CFG_SOPE_EN 0x00200000
605 +/** Stop on Not Acknowledge
606 + After successful transmission of a master code (during high speed mode) SONA is not considered till a stop condition is manually generated by SETEND. */
607 +#define I2C_ADDR_CFG_SONA 0x00100000
608 +/* Disable
609 +#define I2C_ADDR_CFG_SONA_DIS 0x00000000 */
610 +/** Enable */
611 +#define I2C_ADDR_CFG_SONA_EN 0x00100000
612 +/** Master Enable */
613 +#define I2C_ADDR_CFG_MnS 0x00080000
614 +/* Disable
615 +#define I2C_ADDR_CFG_MnS_DIS 0x00000000 */
616 +/** Enable */
617 +#define I2C_ADDR_CFG_MnS_EN 0x00080000
618 +/** Master Code Enable */
619 +#define I2C_ADDR_CFG_MCE 0x00040000
620 +/* Disable
621 +#define I2C_ADDR_CFG_MCE_DIS 0x00000000 */
622 +/** Enable */
623 +#define I2C_ADDR_CFG_MCE_EN 0x00040000
624 +/** General Call Enable */
625 +#define I2C_ADDR_CFG_GCE 0x00020000
626 +/* Disable
627 +#define I2C_ADDR_CFG_GCE_DIS 0x00000000 */
628 +/** Enable */
629 +#define I2C_ADDR_CFG_GCE_EN 0x00020000
630 +/** Ten Bit Address Mode */
631 +#define I2C_ADDR_CFG_TBAM 0x00010000
632 +/* 7-bit address mode enabled.
633 +#define I2C_ADDR_CFG_TBAM_7bit 0x00000000 */
634 +/** 10-bit address mode enabled. */
635 +#define I2C_ADDR_CFG_TBAM_10bit 0x00010000
636 +/** I2C Bus device address
637 + This is the address of this device. (Watch out for reserved addresses by referring to Phillips Spec V2.1) This could either be a 7bit- address (bits [7:1]) or a 10bit- address (bits [9:0]). Note:The validity of the bits are in accordance with the TBAM bit. Bit-1 (Bit-0) is the LSB of the device address. */
638 +#define I2C_ADDR_CFG_ADR_MASK 0x000003FF
639 +/** field offset */
640 +#define I2C_ADDR_CFG_ADR_OFFSET 0
641 +
642 +/* Fields of "I2C Bus Status Register" */
643 +/** Read / not Write */
644 +#define I2C_BUS_STAT_RNW 0x00000004
645 +/* Write to I2C Bus.
646 +#define I2C_BUS_STAT_RNW_WRITE 0x00000000 */
647 +/** Read from I2C Bus. */
648 +#define I2C_BUS_STAT_RNW_READ 0x00000004
649 +/** Bus Status */
650 +#define I2C_BUS_STAT_BS_MASK 0x00000003
651 +/** field offset */
652 +#define I2C_BUS_STAT_BS_OFFSET 0
653 +/** I2C Bus is free. */
654 +#define I2C_BUS_STAT_BS_FREE 0x00000000
655 +/** A start condition has been detected on the bus (bus busy). */
656 +#define I2C_BUS_STAT_BS_SC 0x00000001
657 +/** The device is working as master and has claimed the control on the I2C-bus (busy master). */
658 +#define I2C_BUS_STAT_BS_BM 0x00000002
659 +/** A remote master has accessed this device as slave. */
660 +#define I2C_BUS_STAT_BS_RM 0x00000003
661 +
662 +/* Fields of "I2C FIFO Configuration Register" */
663 +/** TX FIFO Flow Control */
664 +#define I2C_FIFO_CFG_TXFC 0x00020000
665 +/* TX FIFO not as Flow Controller
666 +#define I2C_FIFO_CFG_TXFC_TXNFC 0x00000000 */
667 +/** RX FIFO Flow Control */
668 +#define I2C_FIFO_CFG_RXFC 0x00010000
669 +/* RX FIFO not as Flow Controller
670 +#define I2C_FIFO_CFG_RXFC_RXNFC 0x00000000 */
671 +/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */
672 +#define I2C_FIFO_CFG_TXFA_MASK 0x00003000
673 +/** field offset */
674 +#define I2C_FIFO_CFG_TXFA_OFFSET 12
675 +/** Byte aligned (character alignment) */
676 +#define I2C_FIFO_CFG_TXFA_TXFA0 0x00000000
677 +/** Half word aligned (character alignment of two characters) */
678 +#define I2C_FIFO_CFG_TXFA_TXFA1 0x00001000
679 +/** Word aligned (character alignment of four characters) */
680 +#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
681 +/** Double word aligned (character alignment of eight */
682 +#define I2C_FIFO_CFG_TXFA_TXFA3 0x00003000
683 +/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */
684 +#define I2C_FIFO_CFG_RXFA_MASK 0x00000300
685 +/** field offset */
686 +#define I2C_FIFO_CFG_RXFA_OFFSET 8
687 +/** Byte aligned (character alignment) */
688 +#define I2C_FIFO_CFG_RXFA_RXFA0 0x00000000
689 +/** Half word aligned (character alignment of two characters) */
690 +#define I2C_FIFO_CFG_RXFA_RXFA1 0x00000100
691 +/** Word aligned (character alignment of four characters) */
692 +#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
693 +/** Double word aligned (character alignment of eight */
694 +#define I2C_FIFO_CFG_RXFA_RXFA3 0x00000300
695 +/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */
696 +#define I2C_FIFO_CFG_TXBS_MASK 0x00000030
697 +/** field offset */
698 +#define I2C_FIFO_CFG_TXBS_OFFSET 4
699 +/** 1 word */
700 +#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
701 +/** 2 words */
702 +#define I2C_FIFO_CFG_TXBS_TXBS1 0x00000010
703 +/** 4 words */
704 +#define I2C_FIFO_CFG_TXBS_TXBS2 0x00000020
705 +/** 8 words */
706 +#define I2C_FIFO_CFG_TXBS_TXBS3 0x00000030
707 +/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */
708 +#define I2C_FIFO_CFG_RXBS_MASK 0x00000003
709 +/** field offset */
710 +#define I2C_FIFO_CFG_RXBS_OFFSET 0
711 +/** 1 word */
712 +#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
713 +/** 2 words */
714 +#define I2C_FIFO_CFG_RXBS_RXBS1 0x00000001
715 +/** 4 words */
716 +#define I2C_FIFO_CFG_RXBS_RXBS2 0x00000002
717 +/** 8 words */
718 +#define I2C_FIFO_CFG_RXBS_RXBS3 0x00000003
719 +
720 +/* Fields of "I2C Maximum Received Packet Size Register" */
721 +/** MRPS */
722 +#define I2C_MRPS_CTRL_MRPS_MASK 0x00003FFF
723 +/** field offset */
724 +#define I2C_MRPS_CTRL_MRPS_OFFSET 0
725 +
726 +/* Fields of "I2C Received Packet Size Status Register" */
727 +/** RPS */
728 +#define I2C_RPS_STAT_RPS_MASK 0x00003FFF
729 +/** field offset */
730 +#define I2C_RPS_STAT_RPS_OFFSET 0
731 +
732 +/* Fields of "I2C Transmit Packet Size Register" */
733 +/** TPS */
734 +#define I2C_TPS_CTRL_TPS_MASK 0x00003FFF
735 +/** field offset */
736 +#define I2C_TPS_CTRL_TPS_OFFSET 0
737 +
738 +/* Fields of "I2C Filled FIFO Stages Status Register" */
739 +/** FFS */
740 +#define I2C_FFS_STAT_FFS_MASK 0x0000000F
741 +/** field offset */
742 +#define I2C_FFS_STAT_FFS_OFFSET 0
743 +
744 +/* Fields of "I2C Timing Configuration Register" */
745 +/** SDA Delay Stages for Start/Stop bit in High Speed Mode
746 + The actual delay is calculated as the value of this field + 3 */
747 +#define I2C_TIM_CFG_HS_SDA_DEL_MASK 0x00070000
748 +/** field offset */
749 +#define I2C_TIM_CFG_HS_SDA_DEL_OFFSET 16
750 +/** Enable Fast Mode SCL Low period timing */
751 +#define I2C_TIM_CFG_FS_SCL_LOW 0x00008000
752 +/* Disable
753 +#define I2C_TIM_CFG_FS_SCL_LOW_DIS 0x00000000 */
754 +/** Enable */
755 +#define I2C_TIM_CFG_FS_SCL_LOW_EN 0x00008000
756 +/** SCL Delay Stages for Hold Time Start (Restart) Bit.
757 + The actual delay is calculated as the value of this field + 2 */
758 +#define I2C_TIM_CFG_SCL_DEL_HD_STA_MASK 0x00000E00
759 +/** field offset */
760 +#define I2C_TIM_CFG_SCL_DEL_HD_STA_OFFSET 9
761 +/** SDA Delay Stages for Start/Stop bit in High Speed Mode
762 + The actual delay is calculated as the value of this field + 3 */
763 +#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_MASK 0x000001C0
764 +/** field offset */
765 +#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_OFFSET 6
766 +/** SDA Delay Stages for Start/Stop bit in High Speed Mode
767 + The actual delay is calculated as the value of this field + 3 */
768 +#define I2C_TIM_CFG_SDA_DEL_HD_DAT_MASK 0x0000003F
769 +/** field offset */
770 +#define I2C_TIM_CFG_SDA_DEL_HD_DAT_OFFSET 0
771 +
772 +/* Fields of "I2C Error Interrupt Request Source Mask Register" */
773 +/** Enables the corresponding error interrupt. */
774 +#define I2C_ERR_IRQSM_TXF_OFL 0x00000008
775 +/* Disable
776 +#define I2C_ERR_IRQSM_TXF_OFL_DIS 0x00000000 */
777 +/** Enable */
778 +#define I2C_ERR_IRQSM_TXF_OFL_EN 0x00000008
779 +/** Enables the corresponding error interrupt. */
780 +#define I2C_ERR_IRQSM_TXF_UFL 0x00000004
781 +/* Disable
782 +#define I2C_ERR_IRQSM_TXF_UFL_DIS 0x00000000 */
783 +/** Enable */
784 +#define I2C_ERR_IRQSM_TXF_UFL_EN 0x00000004
785 +/** Enables the corresponding error interrupt. */
786 +#define I2C_ERR_IRQSM_RXF_OFL 0x00000002
787 +/* Disable
788 +#define I2C_ERR_IRQSM_RXF_OFL_DIS 0x00000000 */
789 +/** Enable */
790 +#define I2C_ERR_IRQSM_RXF_OFL_EN 0x00000002
791 +/** Enables the corresponding error interrupt. */
792 +#define I2C_ERR_IRQSM_RXF_UFL 0x00000001
793 +/* Disable
794 +#define I2C_ERR_IRQSM_RXF_UFL_DIS 0x00000000 */
795 +/** Enable */
796 +#define I2C_ERR_IRQSM_RXF_UFL_EN 0x00000001
797 +
798 +/* Fields of "I2C Error Interrupt Request Source Status Register" */
799 +/** TXF_OFL */
800 +#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
801 +/* Nothing
802 +#define I2C_ERR_IRQSS_TXF_OFL_NULL 0x00000000 */
803 +/** Read: Interrupt occurred. */
804 +#define I2C_ERR_IRQSS_TXF_OFL_INTOCC 0x00000008
805 +/** TXF_UFL */
806 +#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
807 +/* Nothing
808 +#define I2C_ERR_IRQSS_TXF_UFL_NULL 0x00000000 */
809 +/** Read: Interrupt occurred. */
810 +#define I2C_ERR_IRQSS_TXF_UFL_INTOCC 0x00000004
811 +/** RXF_OFL */
812 +#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
813 +/* Nothing
814 +#define I2C_ERR_IRQSS_RXF_OFL_NULL 0x00000000 */
815 +/** Read: Interrupt occurred. */
816 +#define I2C_ERR_IRQSS_RXF_OFL_INTOCC 0x00000002
817 +/** RXF_UFL */
818 +#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
819 +/* Nothing
820 +#define I2C_ERR_IRQSS_RXF_UFL_NULL 0x00000000 */
821 +/** Read: Interrupt occurred. */
822 +#define I2C_ERR_IRQSS_RXF_UFL_INTOCC 0x00000001
823 +
824 +/* Fields of "I2C Error Interrupt Request Source Clear Register" */
825 +/** TXF_OFL */
826 +#define I2C_ERR_IRQSC_TXF_OFL 0x00000008
827 +/* No-Operation
828 +#define I2C_ERR_IRQSC_TXF_OFL_NOP 0x00000000 */
829 +/** Clear */
830 +#define I2C_ERR_IRQSC_TXF_OFL_CLR 0x00000008
831 +/** TXF_UFL */
832 +#define I2C_ERR_IRQSC_TXF_UFL 0x00000004
833 +/* No-Operation
834 +#define I2C_ERR_IRQSC_TXF_UFL_NOP 0x00000000 */
835 +/** Clear */
836 +#define I2C_ERR_IRQSC_TXF_UFL_CLR 0x00000004
837 +/** RXF_OFL */
838 +#define I2C_ERR_IRQSC_RXF_OFL 0x00000002
839 +/* No-Operation
840 +#define I2C_ERR_IRQSC_RXF_OFL_NOP 0x00000000 */
841 +/** Clear */
842 +#define I2C_ERR_IRQSC_RXF_OFL_CLR 0x00000002
843 +/** RXF_UFL */
844 +#define I2C_ERR_IRQSC_RXF_UFL 0x00000001
845 +/* No-Operation
846 +#define I2C_ERR_IRQSC_RXF_UFL_NOP 0x00000000 */
847 +/** Clear */
848 +#define I2C_ERR_IRQSC_RXF_UFL_CLR 0x00000001
849 +
850 +/* Fields of "I2C Protocol Interrupt Request Source Mask Register" */
851 +/** Enables the corresponding interrupt. */
852 +#define I2C_P_IRQSM_RX 0x00000040
853 +/* Disable
854 +#define I2C_P_IRQSM_RX_DIS 0x00000000 */
855 +/** Enable */
856 +#define I2C_P_IRQSM_RX_EN 0x00000040
857 +/** Enables the corresponding interrupt. */
858 +#define I2C_P_IRQSM_TX_END 0x00000020
859 +/* Disable
860 +#define I2C_P_IRQSM_TX_END_DIS 0x00000000 */
861 +/** Enable */
862 +#define I2C_P_IRQSM_TX_END_EN 0x00000020
863 +/** Enables the corresponding interrupt. */
864 +#define I2C_P_IRQSM_NACK 0x00000010
865 +/* Disable
866 +#define I2C_P_IRQSM_NACK_DIS 0x00000000 */
867 +/** Enable */
868 +#define I2C_P_IRQSM_NACK_EN 0x00000010
869 +/** Enables the corresponding interrupt. */
870 +#define I2C_P_IRQSM_AL 0x00000008
871 +/* Disable
872 +#define I2C_P_IRQSM_AL_DIS 0x00000000 */
873 +/** Enable */
874 +#define I2C_P_IRQSM_AL_EN 0x00000008
875 +/** Enables the corresponding interrupt. */
876 +#define I2C_P_IRQSM_MC 0x00000004
877 +/* Disable
878 +#define I2C_P_IRQSM_MC_DIS 0x00000000 */
879 +/** Enable */
880 +#define I2C_P_IRQSM_MC_EN 0x00000004
881 +/** Enables the corresponding interrupt. */
882 +#define I2C_P_IRQSM_GC 0x00000002
883 +/* Disable
884 +#define I2C_P_IRQSM_GC_DIS 0x00000000 */
885 +/** Enable */
886 +#define I2C_P_IRQSM_GC_EN 0x00000002
887 +/** Enables the corresponding interrupt. */
888 +#define I2C_P_IRQSM_AM 0x00000001
889 +/* Disable
890 +#define I2C_P_IRQSM_AM_DIS 0x00000000 */
891 +/** Enable */
892 +#define I2C_P_IRQSM_AM_EN 0x00000001
893 +
894 +/* Fields of "I2C Protocol Interrupt Request Source Status Register" */
895 +/** RX */
896 +#define I2C_P_IRQSS_RX 0x00000040
897 +/* Nothing
898 +#define I2C_P_IRQSS_RX_NULL 0x00000000 */
899 +/** Read: Interrupt occurred. */
900 +#define I2C_P_IRQSS_RX_INTOCC 0x00000040
901 +/** TX_END */
902 +#define I2C_P_IRQSS_TX_END 0x00000020
903 +/* Nothing
904 +#define I2C_P_IRQSS_TX_END_NULL 0x00000000 */
905 +/** Read: Interrupt occurred. */
906 +#define I2C_P_IRQSS_TX_END_INTOCC 0x00000020
907 +/** NACK */
908 +#define I2C_P_IRQSS_NACK 0x00000010
909 +/* Nothing
910 +#define I2C_P_IRQSS_NACK_NULL 0x00000000 */
911 +/** Read: Interrupt occurred. */
912 +#define I2C_P_IRQSS_NACK_INTOCC 0x00000010
913 +/** AL */
914 +#define I2C_P_IRQSS_AL 0x00000008
915 +/* Nothing
916 +#define I2C_P_IRQSS_AL_NULL 0x00000000 */
917 +/** Read: Interrupt occurred. */
918 +#define I2C_P_IRQSS_AL_INTOCC 0x00000008
919 +/** MC */
920 +#define I2C_P_IRQSS_MC 0x00000004
921 +/* Nothing
922 +#define I2C_P_IRQSS_MC_NULL 0x00000000 */
923 +/** Read: Interrupt occurred. */
924 +#define I2C_P_IRQSS_MC_INTOCC 0x00000004
925 +/** GC */
926 +#define I2C_P_IRQSS_GC 0x00000002
927 +/* Nothing
928 +#define I2C_P_IRQSS_GC_NULL 0x00000000 */
929 +/** Read: Interrupt occurred. */
930 +#define I2C_P_IRQSS_GC_INTOCC 0x00000002
931 +/** AM */
932 +#define I2C_P_IRQSS_AM 0x00000001
933 +/* Nothing
934 +#define I2C_P_IRQSS_AM_NULL 0x00000000 */
935 +/** Read: Interrupt occurred. */
936 +#define I2C_P_IRQSS_AM_INTOCC 0x00000001
937 +
938 +/* Fields of "I2C Protocol Interrupt Request Source Clear Register" */
939 +/** RX */
940 +#define I2C_P_IRQSC_RX 0x00000040
941 +/* No-Operation
942 +#define I2C_P_IRQSC_RX_NOP 0x00000000 */
943 +/** Clear */
944 +#define I2C_P_IRQSC_RX_CLR 0x00000040
945 +/** TX_END */
946 +#define I2C_P_IRQSC_TX_END 0x00000020
947 +/* No-Operation
948 +#define I2C_P_IRQSC_TX_END_NOP 0x00000000 */
949 +/** Clear */
950 +#define I2C_P_IRQSC_TX_END_CLR 0x00000020
951 +/** NACK */
952 +#define I2C_P_IRQSC_NACK 0x00000010
953 +/* No-Operation
954 +#define I2C_P_IRQSC_NACK_NOP 0x00000000 */
955 +/** Clear */
956 +#define I2C_P_IRQSC_NACK_CLR 0x00000010
957 +/** AL */
958 +#define I2C_P_IRQSC_AL 0x00000008
959 +/* No-Operation
960 +#define I2C_P_IRQSC_AL_NOP 0x00000000 */
961 +/** Clear */
962 +#define I2C_P_IRQSC_AL_CLR 0x00000008
963 +/** MC */
964 +#define I2C_P_IRQSC_MC 0x00000004
965 +/* No-Operation
966 +#define I2C_P_IRQSC_MC_NOP 0x00000000 */
967 +/** Clear */
968 +#define I2C_P_IRQSC_MC_CLR 0x00000004
969 +/** GC */
970 +#define I2C_P_IRQSC_GC 0x00000002
971 +/* No-Operation
972 +#define I2C_P_IRQSC_GC_NOP 0x00000000 */
973 +/** Clear */
974 +#define I2C_P_IRQSC_GC_CLR 0x00000002
975 +/** AM */
976 +#define I2C_P_IRQSC_AM 0x00000001
977 +/* No-Operation
978 +#define I2C_P_IRQSC_AM_NOP 0x00000000 */
979 +/** Clear */
980 +#define I2C_P_IRQSC_AM_CLR 0x00000001
981 +
982 +/* Fields of "I2C Raw Interrupt Status Register" */
983 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
984 +#define I2C_RIS_I2C_P_INT 0x00000020
985 +/* Nothing
986 +#define I2C_RIS_I2C_P_INT_NULL 0x00000000 */
987 +/** Read: Interrupt occurred. */
988 +#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
989 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
990 +#define I2C_RIS_I2C_ERR_INT 0x00000010
991 +/* Nothing
992 +#define I2C_RIS_I2C_ERR_INT_NULL 0x00000000 */
993 +/** Read: Interrupt occurred. */
994 +#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
995 +/** BREQ_INT */
996 +#define I2C_RIS_BREQ_INT 0x00000008
997 +/* Nothing
998 +#define I2C_RIS_BREQ_INT_NULL 0x00000000 */
999 +/** Read: Interrupt occurred. */
1000 +#define I2C_RIS_BREQ_INT_INTOCC 0x00000008
1001 +/** LBREQ_INT */
1002 +#define I2C_RIS_LBREQ_INT 0x00000004
1003 +/* Nothing
1004 +#define I2C_RIS_LBREQ_INT_NULL 0x00000000 */
1005 +/** Read: Interrupt occurred. */
1006 +#define I2C_RIS_LBREQ_INT_INTOCC 0x00000004
1007 +/** SREQ_INT */
1008 +#define I2C_RIS_SREQ_INT 0x00000002
1009 +/* Nothing
1010 +#define I2C_RIS_SREQ_INT_NULL 0x00000000 */
1011 +/** Read: Interrupt occurred. */
1012 +#define I2C_RIS_SREQ_INT_INTOCC 0x00000002
1013 +/** LSREQ_INT */
1014 +#define I2C_RIS_LSREQ_INT 0x00000001
1015 +/* Nothing
1016 +#define I2C_RIS_LSREQ_INT_NULL 0x00000000 */
1017 +/** Read: Interrupt occurred. */
1018 +#define I2C_RIS_LSREQ_INT_INTOCC 0x00000001
1019 +
1020 +/* Fields of "I2C Interrupt Mask Control Register" */
1021 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1022 +#define I2C_IMSC_I2C_P_INT 0x00000020
1023 +/* Disable
1024 +#define I2C_IMSC_I2C_P_INT_DIS 0x00000000 */
1025 +/** Enable */
1026 +#define I2C_IMSC_I2C_P_INT_EN 0x00000020
1027 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1028 +#define I2C_IMSC_I2C_ERR_INT 0x00000010
1029 +/* Disable
1030 +#define I2C_IMSC_I2C_ERR_INT_DIS 0x00000000 */
1031 +/** Enable */
1032 +#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
1033 +/** BREQ_INT */
1034 +#define I2C_IMSC_BREQ_INT 0x00000008
1035 +/* Disable
1036 +#define I2C_IMSC_BREQ_INT_DIS 0x00000000 */
1037 +/** Enable */
1038 +#define I2C_IMSC_BREQ_INT_EN 0x00000008
1039 +/** LBREQ_INT */
1040 +#define I2C_IMSC_LBREQ_INT 0x00000004
1041 +/* Disable
1042 +#define I2C_IMSC_LBREQ_INT_DIS 0x00000000 */
1043 +/** Enable */
1044 +#define I2C_IMSC_LBREQ_INT_EN 0x00000004
1045 +/** SREQ_INT */
1046 +#define I2C_IMSC_SREQ_INT 0x00000002
1047 +/* Disable
1048 +#define I2C_IMSC_SREQ_INT_DIS 0x00000000 */
1049 +/** Enable */
1050 +#define I2C_IMSC_SREQ_INT_EN 0x00000002
1051 +/** LSREQ_INT */
1052 +#define I2C_IMSC_LSREQ_INT 0x00000001
1053 +/* Disable
1054 +#define I2C_IMSC_LSREQ_INT_DIS 0x00000000 */
1055 +/** Enable */
1056 +#define I2C_IMSC_LSREQ_INT_EN 0x00000001
1057 +
1058 +/* Fields of "I2C Masked Interrupt Status Register" */
1059 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1060 +#define I2C_MIS_I2C_P_INT 0x00000020
1061 +/* Nothing
1062 +#define I2C_MIS_I2C_P_INT_NULL 0x00000000 */
1063 +/** Read: Interrupt occurred. */
1064 +#define I2C_MIS_I2C_P_INT_INTOCC 0x00000020
1065 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1066 +#define I2C_MIS_I2C_ERR_INT 0x00000010
1067 +/* Nothing
1068 +#define I2C_MIS_I2C_ERR_INT_NULL 0x00000000 */
1069 +/** Read: Interrupt occurred. */
1070 +#define I2C_MIS_I2C_ERR_INT_INTOCC 0x00000010
1071 +/** BREQ_INT */
1072 +#define I2C_MIS_BREQ_INT 0x00000008
1073 +/* Nothing
1074 +#define I2C_MIS_BREQ_INT_NULL 0x00000000 */
1075 +/** Read: Interrupt occurred. */
1076 +#define I2C_MIS_BREQ_INT_INTOCC 0x00000008
1077 +/** LBREQ_INT */
1078 +#define I2C_MIS_LBREQ_INT 0x00000004
1079 +/* Nothing
1080 +#define I2C_MIS_LBREQ_INT_NULL 0x00000000 */
1081 +/** Read: Interrupt occurred. */
1082 +#define I2C_MIS_LBREQ_INT_INTOCC 0x00000004
1083 +/** SREQ_INT */
1084 +#define I2C_MIS_SREQ_INT 0x00000002
1085 +/* Nothing
1086 +#define I2C_MIS_SREQ_INT_NULL 0x00000000 */
1087 +/** Read: Interrupt occurred. */
1088 +#define I2C_MIS_SREQ_INT_INTOCC 0x00000002
1089 +/** LSREQ_INT */
1090 +#define I2C_MIS_LSREQ_INT 0x00000001
1091 +/* Nothing
1092 +#define I2C_MIS_LSREQ_INT_NULL 0x00000000 */
1093 +/** Read: Interrupt occurred. */
1094 +#define I2C_MIS_LSREQ_INT_INTOCC 0x00000001
1095 +
1096 +/* Fields of "I2C Interrupt Clear Register" */
1097 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1098 +#define I2C_ICR_I2C_P_INT 0x00000020
1099 +/* No-Operation
1100 +#define I2C_ICR_I2C_P_INT_NOP 0x00000000 */
1101 +/** Clear */
1102 +#define I2C_ICR_I2C_P_INT_CLR 0x00000020
1103 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1104 +#define I2C_ICR_I2C_ERR_INT 0x00000010
1105 +/* No-Operation
1106 +#define I2C_ICR_I2C_ERR_INT_NOP 0x00000000 */
1107 +/** Clear */
1108 +#define I2C_ICR_I2C_ERR_INT_CLR 0x00000010
1109 +/** BREQ_INT */
1110 +#define I2C_ICR_BREQ_INT 0x00000008
1111 +/* No-Operation
1112 +#define I2C_ICR_BREQ_INT_NOP 0x00000000 */
1113 +/** Clear */
1114 +#define I2C_ICR_BREQ_INT_CLR 0x00000008
1115 +/** LBREQ_INT */
1116 +#define I2C_ICR_LBREQ_INT 0x00000004
1117 +/* No-Operation
1118 +#define I2C_ICR_LBREQ_INT_NOP 0x00000000 */
1119 +/** Clear */
1120 +#define I2C_ICR_LBREQ_INT_CLR 0x00000004
1121 +/** SREQ_INT */
1122 +#define I2C_ICR_SREQ_INT 0x00000002
1123 +/* No-Operation
1124 +#define I2C_ICR_SREQ_INT_NOP 0x00000000 */
1125 +/** Clear */
1126 +#define I2C_ICR_SREQ_INT_CLR 0x00000002
1127 +/** LSREQ_INT */
1128 +#define I2C_ICR_LSREQ_INT 0x00000001
1129 +/* No-Operation
1130 +#define I2C_ICR_LSREQ_INT_NOP 0x00000000 */
1131 +/** Clear */
1132 +#define I2C_ICR_LSREQ_INT_CLR 0x00000001
1133 +
1134 +/* Fields of "I2C Interrupt Set Register" */
1135 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1136 +#define I2C_ISR_I2C_P_INT 0x00000020
1137 +/* No-Operation
1138 +#define I2C_ISR_I2C_P_INT_NOP 0x00000000 */
1139 +/** Set */
1140 +#define I2C_ISR_I2C_P_INT_SET 0x00000020
1141 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1142 +#define I2C_ISR_I2C_ERR_INT 0x00000010
1143 +/* No-Operation
1144 +#define I2C_ISR_I2C_ERR_INT_NOP 0x00000000 */
1145 +/** Set */
1146 +#define I2C_ISR_I2C_ERR_INT_SET 0x00000010
1147 +/** BREQ_INT */
1148 +#define I2C_ISR_BREQ_INT 0x00000008
1149 +/* No-Operation
1150 +#define I2C_ISR_BREQ_INT_NOP 0x00000000 */
1151 +/** Set */
1152 +#define I2C_ISR_BREQ_INT_SET 0x00000008
1153 +/** LBREQ_INT */
1154 +#define I2C_ISR_LBREQ_INT 0x00000004
1155 +/* No-Operation
1156 +#define I2C_ISR_LBREQ_INT_NOP 0x00000000 */
1157 +/** Set */
1158 +#define I2C_ISR_LBREQ_INT_SET 0x00000004
1159 +/** SREQ_INT */
1160 +#define I2C_ISR_SREQ_INT 0x00000002
1161 +/* No-Operation
1162 +#define I2C_ISR_SREQ_INT_NOP 0x00000000 */
1163 +/** Set */
1164 +#define I2C_ISR_SREQ_INT_SET 0x00000002
1165 +/** LSREQ_INT */
1166 +#define I2C_ISR_LSREQ_INT 0x00000001
1167 +/* No-Operation
1168 +#define I2C_ISR_LSREQ_INT_NOP 0x00000000 */
1169 +/** Set */
1170 +#define I2C_ISR_LSREQ_INT_SET 0x00000001
1171 +
1172 +/* Fields of "I2C DMA Enable Register" */
1173 +/** BREQ_INT */
1174 +#define I2C_DMAE_BREQ_INT 0x00000008
1175 +/* Disable
1176 +#define I2C_DMAE_BREQ_INT_DIS 0x00000000 */
1177 +/** Enable */
1178 +#define I2C_DMAE_BREQ_INT_EN 0x00000008
1179 +/** LBREQ_INT */
1180 +#define I2C_DMAE_LBREQ_INT 0x00000004
1181 +/* Disable
1182 +#define I2C_DMAE_LBREQ_INT_DIS 0x00000000 */
1183 +/** Enable */
1184 +#define I2C_DMAE_LBREQ_INT_EN 0x00000004
1185 +/** SREQ_INT */
1186 +#define I2C_DMAE_SREQ_INT 0x00000002
1187 +/* Disable
1188 +#define I2C_DMAE_SREQ_INT_DIS 0x00000000 */
1189 +/** Enable */
1190 +#define I2C_DMAE_SREQ_INT_EN 0x00000002
1191 +/** LSREQ_INT */
1192 +#define I2C_DMAE_LSREQ_INT 0x00000001
1193 +/* Disable
1194 +#define I2C_DMAE_LSREQ_INT_DIS 0x00000000 */
1195 +/** Enable */
1196 +#define I2C_DMAE_LSREQ_INT_EN 0x00000001
1197 +
1198 +/* Fields of "I2C Transmit Data Register" */
1199 +/** Characters to be transmitted */
1200 +#define I2C_TXD_TXD_MASK 0xFFFFFFFF
1201 +/** field offset */
1202 +#define I2C_TXD_TXD_OFFSET 0
1203 +
1204 +/* Fields of "I2C Receive Data Register" */
1205 +/** Received characters */
1206 +#define I2C_RXD_RXD_MASK 0xFFFFFFFF
1207 +/** field offset */
1208 +#define I2C_RXD_RXD_OFFSET 0
1209 +
1210 +/*! @} */ /* I2C_REGISTER */
1211 +
1212 +#endif /* _i2c_reg_h */
1213 --- /dev/null
1214 +++ b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h
1215 @@ -0,0 +1,4324 @@
1216 +/******************************************************************************
1217 +
1218 + Copyright (c) 2010
1219 + Lantiq Deutschland GmbH
1220 +
1221 + For licensing information, see the file 'LICENSE' in the root folder of
1222 + this software module.
1223 +
1224 +******************************************************************************/
1225 +
1226 +#ifndef _icu0_reg_h
1227 +#define _icu0_reg_h
1228 +
1229 +/** \addtogroup ICU0_REGISTER
1230 + @{
1231 +*/
1232 +/* access macros */
1233 +#define icu0_r32(reg) reg_r32(&icu0->reg)
1234 +#define icu0_w32(val, reg) reg_w32(val, &icu0->reg)
1235 +#define icu0_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &icu0->reg)
1236 +#define icu0_r32_table(reg, idx) reg_r32_table(icu0->reg, idx)
1237 +#define icu0_w32_table(val, reg, idx) reg_w32_table(val, icu0->reg, idx)
1238 +#define icu0_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, icu0->reg, idx)
1239 +#define icu0_adr_table(reg, idx) adr_table(icu0->reg, idx)
1240 +
1241 +
1242 +/** ICU0 register structure */
1243 +struct gpon_reg_icu0
1244 +{
1245 + /** IM0 Interrupt Status Register
1246 + A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1247 + unsigned int im0_isr; /* 0x00000000 */
1248 + /** Reserved */
1249 + unsigned int res_0; /* 0x00000004 */
1250 + /** IM0 Interrupt Enable Register
1251 + This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM0_IOSR register and are not signalled via the interrupt line towards the controller. */
1252 + unsigned int im0_ier; /* 0x00000008 */
1253 + /** Reserved */
1254 + unsigned int res_1; /* 0x0000000C */
1255 + /** IM0 Interrupt Output Status Register
1256 + This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM0_IER register. */
1257 + unsigned int im0_iosr; /* 0x00000010 */
1258 + /** Reserved */
1259 + unsigned int res_2; /* 0x00000014 */
1260 + /** IM0 Interrupt Request Set Register
1261 + A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1262 + unsigned int im0_irsr; /* 0x00000018 */
1263 + /** Reserved */
1264 + unsigned int res_3; /* 0x0000001C */
1265 + /** IM0 Interrupt Mode Register
1266 + This register shows the type of interrupt for each bit. */
1267 + unsigned int im0_imr; /* 0x00000020 */
1268 + /** Reserved */
1269 + unsigned int res_4; /* 0x00000024 */
1270 + /** IM1 Interrupt Status Register
1271 + A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1272 + unsigned int im1_isr; /* 0x00000028 */
1273 + /** Reserved */
1274 + unsigned int res_5; /* 0x0000002C */
1275 + /** IM1 Interrupt Enable Register
1276 + This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM1_IOSR register and are not signalled via the interrupt line towards the controller. */
1277 + unsigned int im1_ier; /* 0x00000030 */
1278 + /** Reserved */
1279 + unsigned int res_6; /* 0x00000034 */
1280 + /** IM1 Interrupt Output Status Register
1281 + This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM1_IER register. */
1282 + unsigned int im1_iosr; /* 0x00000038 */
1283 + /** Reserved */
1284 + unsigned int res_7; /* 0x0000003C */
1285 + /** IM1 Interrupt Request Set Register
1286 + A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1287 + unsigned int im1_irsr; /* 0x00000040 */
1288 + /** Reserved */
1289 + unsigned int res_8; /* 0x00000044 */
1290 + /** IM1 Interrupt Mode Register
1291 + This register shows the type of interrupt for each bit. */
1292 + unsigned int im1_imr; /* 0x00000048 */
1293 + /** Reserved */
1294 + unsigned int res_9; /* 0x0000004C */
1295 + /** IM2 Interrupt Status Register
1296 + A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1297 + unsigned int im2_isr; /* 0x00000050 */
1298 + /** Reserved */
1299 + unsigned int res_10; /* 0x00000054 */
1300 + /** IM2 Interrupt Enable Register
1301 + This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM2_IOSR register and are not signalled via the interrupt line towards the controller. */
1302 + unsigned int im2_ier; /* 0x00000058 */
1303 + /** Reserved */
1304 + unsigned int res_11; /* 0x0000005C */
1305 + /** IM2 Interrupt Output Status Register
1306 + This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM2_IER register. */
1307 + unsigned int im2_iosr; /* 0x00000060 */
1308 + /** Reserved */
1309 + unsigned int res_12; /* 0x00000064 */
1310 + /** IM2 Interrupt Request Set Register
1311 + A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1312 + unsigned int im2_irsr; /* 0x00000068 */
1313 + /** Reserved */
1314 + unsigned int res_13; /* 0x0000006C */
1315 + /** IM2 Interrupt Mode Register
1316 + This register shows the type of interrupt for each bit. */
1317 + unsigned int im2_imr; /* 0x00000070 */
1318 + /** Reserved */
1319 + unsigned int res_14; /* 0x00000074 */
1320 + /** IM3 Interrupt Status Register
1321 + A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1322 + unsigned int im3_isr; /* 0x00000078 */
1323 + /** Reserved */
1324 + unsigned int res_15; /* 0x0000007C */
1325 + /** IM3 Interrupt Enable Register
1326 + This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM3_IOSR register and are not signalled via the interrupt line towards the controller. */
1327 + unsigned int im3_ier; /* 0x00000080 */
1328 + /** Reserved */
1329 + unsigned int res_16; /* 0x00000084 */
1330 + /** IM3 Interrupt Output Status Register
1331 + This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM3_IER register. */
1332 + unsigned int im3_iosr; /* 0x00000088 */
1333 + /** Reserved */
1334 + unsigned int res_17; /* 0x0000008C */
1335 + /** IM3 Interrupt Request Set Register
1336 + A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1337 + unsigned int im3_irsr; /* 0x00000090 */
1338 + /** Reserved */
1339 + unsigned int res_18; /* 0x00000094 */
1340 + /** IM3 Interrupt Mode Register
1341 + This register shows the type of interrupt for each bit. */
1342 + unsigned int im3_imr; /* 0x00000098 */
1343 + /** Reserved */
1344 + unsigned int res_19; /* 0x0000009C */
1345 + /** IM4 Interrupt Status Register
1346 + A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1347 + unsigned int im4_isr; /* 0x000000A0 */
1348 + /** Reserved */
1349 + unsigned int res_20; /* 0x000000A4 */
1350 + /** IM4 Interrupt Enable Register
1351 + This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM4_IOSR register and are not signalled via the interrupt line towards the controller. */
1352 + unsigned int im4_ier; /* 0x000000A8 */
1353 + /** Reserved */
1354 + unsigned int res_21; /* 0x000000AC */
1355 + /** IM4 Interrupt Output Status Register
1356 + This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM4_IER register. */
1357 + unsigned int im4_iosr; /* 0x000000B0 */
1358 + /** Reserved */
1359 + unsigned int res_22; /* 0x000000B4 */
1360 + /** IM4 Interrupt Request Set Register
1361 + A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1362 + unsigned int im4_irsr; /* 0x000000B8 */
1363 + /** Reserved */
1364 + unsigned int res_23; /* 0x000000BC */
1365 + /** IM4 Interrupt Mode Register
1366 + This register shows the type of interrupt for each bit. */
1367 + unsigned int im4_imr; /* 0x000000C0 */
1368 + /** Reserved */
1369 + unsigned int res_24; /* 0x000000C4 */
1370 + /** ICU Interrupt Vector Register (5 bit variant)
1371 + Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */
1372 + unsigned int icu_ivec; /* 0x000000C8 */
1373 + /** Reserved */
1374 + unsigned int res_25; /* 0x000000CC */
1375 + /** ICU Interrupt Vector Register (6 bit variant)
1376 + Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */
1377 + unsigned int icu_ivec_6; /* 0x000000D0 */
1378 + /** Reserved */
1379 + unsigned int res_26[3]; /* 0x000000D4 */
1380 +};
1381 +
1382 +
1383 +/* Fields of "IM0 Interrupt Status Register" */
1384 +/** PCM Transmit Crash Interrupt
1385 + This bit is an indirect interrupt. */
1386 +#define ICU0_IM0_ISR_PCM_HW2_CRASH 0x80000000
1387 +/* Nothing
1388 +#define ICU0_IM0_ISR_PCM_HW2_CRASH_NULL 0x00000000 */
1389 +/** Write: Acknowledge the interrupt. */
1390 +#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTACK 0x80000000
1391 +/** Read: Interrupt occurred. */
1392 +#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTOCC 0x80000000
1393 +/** PCM Transmit Interrupt
1394 + This bit is an indirect interrupt. */
1395 +#define ICU0_IM0_ISR_PCM_TX 0x40000000
1396 +/* Nothing
1397 +#define ICU0_IM0_ISR_PCM_TX_NULL 0x00000000 */
1398 +/** Write: Acknowledge the interrupt. */
1399 +#define ICU0_IM0_ISR_PCM_TX_INTACK 0x40000000
1400 +/** Read: Interrupt occurred. */
1401 +#define ICU0_IM0_ISR_PCM_TX_INTOCC 0x40000000
1402 +/** PCM Receive Interrupt
1403 + This bit is an indirect interrupt. */
1404 +#define ICU0_IM0_ISR_PCM_RX 0x20000000
1405 +/* Nothing
1406 +#define ICU0_IM0_ISR_PCM_RX_NULL 0x00000000 */
1407 +/** Write: Acknowledge the interrupt. */
1408 +#define ICU0_IM0_ISR_PCM_RX_INTACK 0x20000000
1409 +/** Read: Interrupt occurred. */
1410 +#define ICU0_IM0_ISR_PCM_RX_INTOCC 0x20000000
1411 +/** Secure Hash Algorithm Interrupt
1412 + This bit is a direct interrupt. */
1413 +#define ICU0_IM0_ISR_SHA1_HASH 0x10000000
1414 +/* Nothing
1415 +#define ICU0_IM0_ISR_SHA1_HASH_NULL 0x00000000 */
1416 +/** Write: Acknowledge the interrupt. */
1417 +#define ICU0_IM0_ISR_SHA1_HASH_INTACK 0x10000000
1418 +/** Read: Interrupt occurred. */
1419 +#define ICU0_IM0_ISR_SHA1_HASH_INTOCC 0x10000000
1420 +/** Advanced Encryption Standard Interrupt
1421 + This bit is a direct interrupt. */
1422 +#define ICU0_IM0_ISR_AES_AES 0x08000000
1423 +/* Nothing
1424 +#define ICU0_IM0_ISR_AES_AES_NULL 0x00000000 */
1425 +/** Write: Acknowledge the interrupt. */
1426 +#define ICU0_IM0_ISR_AES_AES_INTACK 0x08000000
1427 +/** Read: Interrupt occurred. */
1428 +#define ICU0_IM0_ISR_AES_AES_INTOCC 0x08000000
1429 +/** SSC Frame Interrupt
1430 + This bit is a direct interrupt. */
1431 +#define ICU0_IM0_ISR_SSC0_F 0x00020000
1432 +/* Nothing
1433 +#define ICU0_IM0_ISR_SSC0_F_NULL 0x00000000 */
1434 +/** Write: Acknowledge the interrupt. */
1435 +#define ICU0_IM0_ISR_SSC0_F_INTACK 0x00020000
1436 +/** Read: Interrupt occurred. */
1437 +#define ICU0_IM0_ISR_SSC0_F_INTOCC 0x00020000
1438 +/** SSC Error Interrupt
1439 + This bit is a direct interrupt. */
1440 +#define ICU0_IM0_ISR_SSC0_E 0x00010000
1441 +/* Nothing
1442 +#define ICU0_IM0_ISR_SSC0_E_NULL 0x00000000 */
1443 +/** Write: Acknowledge the interrupt. */
1444 +#define ICU0_IM0_ISR_SSC0_E_INTACK 0x00010000
1445 +/** Read: Interrupt occurred. */
1446 +#define ICU0_IM0_ISR_SSC0_E_INTOCC 0x00010000
1447 +/** SSC Receive Interrupt
1448 + This bit is a direct interrupt. */
1449 +#define ICU0_IM0_ISR_SSC0_R 0x00008000
1450 +/* Nothing
1451 +#define ICU0_IM0_ISR_SSC0_R_NULL 0x00000000 */
1452 +/** Write: Acknowledge the interrupt. */
1453 +#define ICU0_IM0_ISR_SSC0_R_INTACK 0x00008000
1454 +/** Read: Interrupt occurred. */
1455 +#define ICU0_IM0_ISR_SSC0_R_INTOCC 0x00008000
1456 +/** SSC Transmit Interrupt
1457 + This bit is a direct interrupt. */
1458 +#define ICU0_IM0_ISR_SSC0_T 0x00004000
1459 +/* Nothing
1460 +#define ICU0_IM0_ISR_SSC0_T_NULL 0x00000000 */
1461 +/** Write: Acknowledge the interrupt. */
1462 +#define ICU0_IM0_ISR_SSC0_T_INTACK 0x00004000
1463 +/** Read: Interrupt occurred. */
1464 +#define ICU0_IM0_ISR_SSC0_T_INTOCC 0x00004000
1465 +/** I2C Peripheral Interrupt
1466 + This bit is an indirect interrupt. */
1467 +#define ICU0_IM0_ISR_I2C_I2C_P_INT 0x00002000
1468 +/* Nothing
1469 +#define ICU0_IM0_ISR_I2C_I2C_P_INT_NULL 0x00000000 */
1470 +/** Write: Acknowledge the interrupt. */
1471 +#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTACK 0x00002000
1472 +/** Read: Interrupt occurred. */
1473 +#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTOCC 0x00002000
1474 +/** I2C Error Interrupt
1475 + This bit is an indirect interrupt. */
1476 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT 0x00001000
1477 +/* Nothing
1478 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_NULL 0x00000000 */
1479 +/** Write: Acknowledge the interrupt. */
1480 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTACK 0x00001000
1481 +/** Read: Interrupt occurred. */
1482 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTOCC 0x00001000
1483 +/** I2C Burst Data Transfer Request
1484 + This bit is an indirect interrupt. */
1485 +#define ICU0_IM0_ISR_I2C_BREQ_INT 0x00000800
1486 +/* Nothing
1487 +#define ICU0_IM0_ISR_I2C_BREQ_INT_NULL 0x00000000 */
1488 +/** Write: Acknowledge the interrupt. */
1489 +#define ICU0_IM0_ISR_I2C_BREQ_INT_INTACK 0x00000800
1490 +/** Read: Interrupt occurred. */
1491 +#define ICU0_IM0_ISR_I2C_BREQ_INT_INTOCC 0x00000800
1492 +/** I2C Last Burst Data Transfer Request
1493 + This bit is an indirect interrupt. */
1494 +#define ICU0_IM0_ISR_I2C_LBREQ_INT 0x00000400
1495 +/* Nothing
1496 +#define ICU0_IM0_ISR_I2C_LBREQ_INT_NULL 0x00000000 */
1497 +/** Write: Acknowledge the interrupt. */
1498 +#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTACK 0x00000400
1499 +/** Read: Interrupt occurred. */
1500 +#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTOCC 0x00000400
1501 +/** I2C Single Data Transfer Request
1502 + This bit is an indirect interrupt. */
1503 +#define ICU0_IM0_ISR_I2C_SREQ_INT 0x00000200
1504 +/* Nothing
1505 +#define ICU0_IM0_ISR_I2C_SREQ_INT_NULL 0x00000000 */
1506 +/** Write: Acknowledge the interrupt. */
1507 +#define ICU0_IM0_ISR_I2C_SREQ_INT_INTACK 0x00000200
1508 +/** Read: Interrupt occurred. */
1509 +#define ICU0_IM0_ISR_I2C_SREQ_INT_INTOCC 0x00000200
1510 +/** I2C Last Single Data Transfer Request
1511 + This bit is an indirect interrupt. */
1512 +#define ICU0_IM0_ISR_I2C_LSREQ_INT 0x00000100
1513 +/* Nothing
1514 +#define ICU0_IM0_ISR_I2C_LSREQ_INT_NULL 0x00000000 */
1515 +/** Write: Acknowledge the interrupt. */
1516 +#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTACK 0x00000100
1517 +/** Read: Interrupt occurred. */
1518 +#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTOCC 0x00000100
1519 +/** HOST IF Mailbox1 Transmit Interrupt
1520 + This bit is an indirect interrupt. */
1521 +#define ICU0_IM0_ISR_HOST_MB1_TIR 0x00000010
1522 +/* Nothing
1523 +#define ICU0_IM0_ISR_HOST_MB1_TIR_NULL 0x00000000 */
1524 +/** Write: Acknowledge the interrupt. */
1525 +#define ICU0_IM0_ISR_HOST_MB1_TIR_INTACK 0x00000010
1526 +/** Read: Interrupt occurred. */
1527 +#define ICU0_IM0_ISR_HOST_MB1_TIR_INTOCC 0x00000010
1528 +/** HOST IF Mailbox1 Receive Interrupt
1529 + This bit is an indirect interrupt. */
1530 +#define ICU0_IM0_ISR_HOST_MB1_RIR 0x00000008
1531 +/* Nothing
1532 +#define ICU0_IM0_ISR_HOST_MB1_RIR_NULL 0x00000000 */
1533 +/** Write: Acknowledge the interrupt. */
1534 +#define ICU0_IM0_ISR_HOST_MB1_RIR_INTACK 0x00000008
1535 +/** Read: Interrupt occurred. */
1536 +#define ICU0_IM0_ISR_HOST_MB1_RIR_INTOCC 0x00000008
1537 +/** HOST IF Mailbox0 Transmit Interrupt
1538 + This bit is an indirect interrupt. */
1539 +#define ICU0_IM0_ISR_HOST_MB0_TIR 0x00000004
1540 +/* Nothing
1541 +#define ICU0_IM0_ISR_HOST_MB0_TIR_NULL 0x00000000 */
1542 +/** Write: Acknowledge the interrupt. */
1543 +#define ICU0_IM0_ISR_HOST_MB0_TIR_INTACK 0x00000004
1544 +/** Read: Interrupt occurred. */
1545 +#define ICU0_IM0_ISR_HOST_MB0_TIR_INTOCC 0x00000004
1546 +/** HOST IF Mailbox0 Receive Interrupt
1547 + This bit is an indirect interrupt. */
1548 +#define ICU0_IM0_ISR_HOST_MB0_RIR 0x00000002
1549 +/* Nothing
1550 +#define ICU0_IM0_ISR_HOST_MB0_RIR_NULL 0x00000000 */
1551 +/** Write: Acknowledge the interrupt. */
1552 +#define ICU0_IM0_ISR_HOST_MB0_RIR_INTACK 0x00000002
1553 +/** Read: Interrupt occurred. */
1554 +#define ICU0_IM0_ISR_HOST_MB0_RIR_INTOCC 0x00000002
1555 +/** HOST IF Event Interrupt
1556 + This bit is an indirect interrupt. */
1557 +#define ICU0_IM0_ISR_HOST_EIR 0x00000001
1558 +/* Nothing
1559 +#define ICU0_IM0_ISR_HOST_EIR_NULL 0x00000000 */
1560 +/** Write: Acknowledge the interrupt. */
1561 +#define ICU0_IM0_ISR_HOST_EIR_INTACK 0x00000001
1562 +/** Read: Interrupt occurred. */
1563 +#define ICU0_IM0_ISR_HOST_EIR_INTOCC 0x00000001
1564 +
1565 +/* Fields of "IM0 Interrupt Enable Register" */
1566 +/** PCM Transmit Crash Interrupt
1567 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1568 +#define ICU0_IM0_IER_PCM_HW2_CRASH 0x80000000
1569 +/* Disable
1570 +#define ICU0_IM0_IER_PCM_HW2_CRASH_DIS 0x00000000 */
1571 +/** Enable */
1572 +#define ICU0_IM0_IER_PCM_HW2_CRASH_EN 0x80000000
1573 +/** PCM Transmit Interrupt
1574 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1575 +#define ICU0_IM0_IER_PCM_TX 0x40000000
1576 +/* Disable
1577 +#define ICU0_IM0_IER_PCM_TX_DIS 0x00000000 */
1578 +/** Enable */
1579 +#define ICU0_IM0_IER_PCM_TX_EN 0x40000000
1580 +/** PCM Receive Interrupt
1581 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1582 +#define ICU0_IM0_IER_PCM_RX 0x20000000
1583 +/* Disable
1584 +#define ICU0_IM0_IER_PCM_RX_DIS 0x00000000 */
1585 +/** Enable */
1586 +#define ICU0_IM0_IER_PCM_RX_EN 0x20000000
1587 +/** Secure Hash Algorithm Interrupt
1588 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1589 +#define ICU0_IM0_IER_SHA1_HASH 0x10000000
1590 +/* Disable
1591 +#define ICU0_IM0_IER_SHA1_HASH_DIS 0x00000000 */
1592 +/** Enable */
1593 +#define ICU0_IM0_IER_SHA1_HASH_EN 0x10000000
1594 +/** Advanced Encryption Standard Interrupt
1595 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1596 +#define ICU0_IM0_IER_AES_AES 0x08000000
1597 +/* Disable
1598 +#define ICU0_IM0_IER_AES_AES_DIS 0x00000000 */
1599 +/** Enable */
1600 +#define ICU0_IM0_IER_AES_AES_EN 0x08000000
1601 +/** SSC Frame Interrupt
1602 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1603 +#define ICU0_IM0_IER_SSC0_F 0x00020000
1604 +/* Disable
1605 +#define ICU0_IM0_IER_SSC0_F_DIS 0x00000000 */
1606 +/** Enable */
1607 +#define ICU0_IM0_IER_SSC0_F_EN 0x00020000
1608 +/** SSC Error Interrupt
1609 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1610 +#define ICU0_IM0_IER_SSC0_E 0x00010000
1611 +/* Disable
1612 +#define ICU0_IM0_IER_SSC0_E_DIS 0x00000000 */
1613 +/** Enable */
1614 +#define ICU0_IM0_IER_SSC0_E_EN 0x00010000
1615 +/** SSC Receive Interrupt
1616 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1617 +#define ICU0_IM0_IER_SSC0_R 0x00008000
1618 +/* Disable
1619 +#define ICU0_IM0_IER_SSC0_R_DIS 0x00000000 */
1620 +/** Enable */
1621 +#define ICU0_IM0_IER_SSC0_R_EN 0x00008000
1622 +/** SSC Transmit Interrupt
1623 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1624 +#define ICU0_IM0_IER_SSC0_T 0x00004000
1625 +/* Disable
1626 +#define ICU0_IM0_IER_SSC0_T_DIS 0x00000000 */
1627 +/** Enable */
1628 +#define ICU0_IM0_IER_SSC0_T_EN 0x00004000
1629 +/** I2C Peripheral Interrupt
1630 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1631 +#define ICU0_IM0_IER_I2C_I2C_P_INT 0x00002000
1632 +/* Disable
1633 +#define ICU0_IM0_IER_I2C_I2C_P_INT_DIS 0x00000000 */
1634 +/** Enable */
1635 +#define ICU0_IM0_IER_I2C_I2C_P_INT_EN 0x00002000
1636 +/** I2C Error Interrupt
1637 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1638 +#define ICU0_IM0_IER_I2C_I2C_ERR_INT 0x00001000
1639 +/* Disable
1640 +#define ICU0_IM0_IER_I2C_I2C_ERR_INT_DIS 0x00000000 */
1641 +/** Enable */
1642 +#define ICU0_IM0_IER_I2C_I2C_ERR_INT_EN 0x00001000
1643 +/** I2C Burst Data Transfer Request
1644 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1645 +#define ICU0_IM0_IER_I2C_BREQ_INT 0x00000800
1646 +/* Disable
1647 +#define ICU0_IM0_IER_I2C_BREQ_INT_DIS 0x00000000 */
1648 +/** Enable */
1649 +#define ICU0_IM0_IER_I2C_BREQ_INT_EN 0x00000800
1650 +/** I2C Last Burst Data Transfer Request
1651 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1652 +#define ICU0_IM0_IER_I2C_LBREQ_INT 0x00000400
1653 +/* Disable
1654 +#define ICU0_IM0_IER_I2C_LBREQ_INT_DIS 0x00000000 */
1655 +/** Enable */
1656 +#define ICU0_IM0_IER_I2C_LBREQ_INT_EN 0x00000400
1657 +/** I2C Single Data Transfer Request
1658 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1659 +#define ICU0_IM0_IER_I2C_SREQ_INT 0x00000200
1660 +/* Disable
1661 +#define ICU0_IM0_IER_I2C_SREQ_INT_DIS 0x00000000 */
1662 +/** Enable */
1663 +#define ICU0_IM0_IER_I2C_SREQ_INT_EN 0x00000200
1664 +/** I2C Last Single Data Transfer Request
1665 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1666 +#define ICU0_IM0_IER_I2C_LSREQ_INT 0x00000100
1667 +/* Disable
1668 +#define ICU0_IM0_IER_I2C_LSREQ_INT_DIS 0x00000000 */
1669 +/** Enable */
1670 +#define ICU0_IM0_IER_I2C_LSREQ_INT_EN 0x00000100
1671 +/** HOST IF Mailbox1 Transmit Interrupt
1672 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1673 +#define ICU0_IM0_IER_HOST_MB1_TIR 0x00000010
1674 +/* Disable
1675 +#define ICU0_IM0_IER_HOST_MB1_TIR_DIS 0x00000000 */
1676 +/** Enable */
1677 +#define ICU0_IM0_IER_HOST_MB1_TIR_EN 0x00000010
1678 +/** HOST IF Mailbox1 Receive Interrupt
1679 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1680 +#define ICU0_IM0_IER_HOST_MB1_RIR 0x00000008
1681 +/* Disable
1682 +#define ICU0_IM0_IER_HOST_MB1_RIR_DIS 0x00000000 */
1683 +/** Enable */
1684 +#define ICU0_IM0_IER_HOST_MB1_RIR_EN 0x00000008
1685 +/** HOST IF Mailbox0 Transmit Interrupt
1686 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1687 +#define ICU0_IM0_IER_HOST_MB0_TIR 0x00000004
1688 +/* Disable
1689 +#define ICU0_IM0_IER_HOST_MB0_TIR_DIS 0x00000000 */
1690 +/** Enable */
1691 +#define ICU0_IM0_IER_HOST_MB0_TIR_EN 0x00000004
1692 +/** HOST IF Mailbox0 Receive Interrupt
1693 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1694 +#define ICU0_IM0_IER_HOST_MB0_RIR 0x00000002
1695 +/* Disable
1696 +#define ICU0_IM0_IER_HOST_MB0_RIR_DIS 0x00000000 */
1697 +/** Enable */
1698 +#define ICU0_IM0_IER_HOST_MB0_RIR_EN 0x00000002
1699 +/** HOST IF Event Interrupt
1700 + Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1701 +#define ICU0_IM0_IER_HOST_EIR 0x00000001
1702 +/* Disable
1703 +#define ICU0_IM0_IER_HOST_EIR_DIS 0x00000000 */
1704 +/** Enable */
1705 +#define ICU0_IM0_IER_HOST_EIR_EN 0x00000001
1706 +
1707 +/* Fields of "IM0 Interrupt Output Status Register" */
1708 +/** PCM Transmit Crash Interrupt
1709 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1710 +#define ICU0_IM0_IOSR_PCM_HW2_CRASH 0x80000000
1711 +/* Nothing
1712 +#define ICU0_IM0_IOSR_PCM_HW2_CRASH_NULL 0x00000000 */
1713 +/** Read: Interrupt occurred. */
1714 +#define ICU0_IM0_IOSR_PCM_HW2_CRASH_INTOCC 0x80000000
1715 +/** PCM Transmit Interrupt
1716 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1717 +#define ICU0_IM0_IOSR_PCM_TX 0x40000000
1718 +/* Nothing
1719 +#define ICU0_IM0_IOSR_PCM_TX_NULL 0x00000000 */
1720 +/** Read: Interrupt occurred. */
1721 +#define ICU0_IM0_IOSR_PCM_TX_INTOCC 0x40000000
1722 +/** PCM Receive Interrupt
1723 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1724 +#define ICU0_IM0_IOSR_PCM_RX 0x20000000
1725 +/* Nothing
1726 +#define ICU0_IM0_IOSR_PCM_RX_NULL 0x00000000 */
1727 +/** Read: Interrupt occurred. */
1728 +#define ICU0_IM0_IOSR_PCM_RX_INTOCC 0x20000000
1729 +/** Secure Hash Algorithm Interrupt
1730 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1731 +#define ICU0_IM0_IOSR_SHA1_HASH 0x10000000
1732 +/* Nothing
1733 +#define ICU0_IM0_IOSR_SHA1_HASH_NULL 0x00000000 */
1734 +/** Read: Interrupt occurred. */
1735 +#define ICU0_IM0_IOSR_SHA1_HASH_INTOCC 0x10000000
1736 +/** Advanced Encryption Standard Interrupt
1737 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1738 +#define ICU0_IM0_IOSR_AES_AES 0x08000000
1739 +/* Nothing
1740 +#define ICU0_IM0_IOSR_AES_AES_NULL 0x00000000 */
1741 +/** Read: Interrupt occurred. */
1742 +#define ICU0_IM0_IOSR_AES_AES_INTOCC 0x08000000
1743 +/** SSC Frame Interrupt
1744 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1745 +#define ICU0_IM0_IOSR_SSC0_F 0x00020000
1746 +/* Nothing
1747 +#define ICU0_IM0_IOSR_SSC0_F_NULL 0x00000000 */
1748 +/** Read: Interrupt occurred. */
1749 +#define ICU0_IM0_IOSR_SSC0_F_INTOCC 0x00020000
1750 +/** SSC Error Interrupt
1751 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1752 +#define ICU0_IM0_IOSR_SSC0_E 0x00010000
1753 +/* Nothing
1754 +#define ICU0_IM0_IOSR_SSC0_E_NULL 0x00000000 */
1755 +/** Read: Interrupt occurred. */
1756 +#define ICU0_IM0_IOSR_SSC0_E_INTOCC 0x00010000
1757 +/** SSC Receive Interrupt
1758 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1759 +#define ICU0_IM0_IOSR_SSC0_R 0x00008000
1760 +/* Nothing
1761 +#define ICU0_IM0_IOSR_SSC0_R_NULL 0x00000000 */
1762 +/** Read: Interrupt occurred. */
1763 +#define ICU0_IM0_IOSR_SSC0_R_INTOCC 0x00008000
1764 +/** SSC Transmit Interrupt
1765 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1766 +#define ICU0_IM0_IOSR_SSC0_T 0x00004000
1767 +/* Nothing
1768 +#define ICU0_IM0_IOSR_SSC0_T_NULL 0x00000000 */
1769 +/** Read: Interrupt occurred. */
1770 +#define ICU0_IM0_IOSR_SSC0_T_INTOCC 0x00004000
1771 +/** I2C Peripheral Interrupt
1772 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1773 +#define ICU0_IM0_IOSR_I2C_I2C_P_INT 0x00002000
1774 +/* Nothing
1775 +#define ICU0_IM0_IOSR_I2C_I2C_P_INT_NULL 0x00000000 */
1776 +/** Read: Interrupt occurred. */
1777 +#define ICU0_IM0_IOSR_I2C_I2C_P_INT_INTOCC 0x00002000
1778 +/** I2C Error Interrupt
1779 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1780 +#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT 0x00001000
1781 +/* Nothing
1782 +#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_NULL 0x00000000 */
1783 +/** Read: Interrupt occurred. */
1784 +#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_INTOCC 0x00001000
1785 +/** I2C Burst Data Transfer Request
1786 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1787 +#define ICU0_IM0_IOSR_I2C_BREQ_INT 0x00000800
1788 +/* Nothing
1789 +#define ICU0_IM0_IOSR_I2C_BREQ_INT_NULL 0x00000000 */
1790 +/** Read: Interrupt occurred. */
1791 +#define ICU0_IM0_IOSR_I2C_BREQ_INT_INTOCC 0x00000800
1792 +/** I2C Last Burst Data Transfer Request
1793 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1794 +#define ICU0_IM0_IOSR_I2C_LBREQ_INT 0x00000400
1795 +/* Nothing
1796 +#define ICU0_IM0_IOSR_I2C_LBREQ_INT_NULL 0x00000000 */
1797 +/** Read: Interrupt occurred. */
1798 +#define ICU0_IM0_IOSR_I2C_LBREQ_INT_INTOCC 0x00000400
1799 +/** I2C Single Data Transfer Request
1800 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1801 +#define ICU0_IM0_IOSR_I2C_SREQ_INT 0x00000200
1802 +/* Nothing
1803 +#define ICU0_IM0_IOSR_I2C_SREQ_INT_NULL 0x00000000 */
1804 +/** Read: Interrupt occurred. */
1805 +#define ICU0_IM0_IOSR_I2C_SREQ_INT_INTOCC 0x00000200
1806 +/** I2C Last Single Data Transfer Request
1807 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1808 +#define ICU0_IM0_IOSR_I2C_LSREQ_INT 0x00000100
1809 +/* Nothing
1810 +#define ICU0_IM0_IOSR_I2C_LSREQ_INT_NULL 0x00000000 */
1811 +/** Read: Interrupt occurred. */
1812 +#define ICU0_IM0_IOSR_I2C_LSREQ_INT_INTOCC 0x00000100
1813 +/** HOST IF Mailbox1 Transmit Interrupt
1814 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1815 +#define ICU0_IM0_IOSR_HOST_MB1_TIR 0x00000010
1816 +/* Nothing
1817 +#define ICU0_IM0_IOSR_HOST_MB1_TIR_NULL 0x00000000 */
1818 +/** Read: Interrupt occurred. */
1819 +#define ICU0_IM0_IOSR_HOST_MB1_TIR_INTOCC 0x00000010
1820 +/** HOST IF Mailbox1 Receive Interrupt
1821 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1822 +#define ICU0_IM0_IOSR_HOST_MB1_RIR 0x00000008
1823 +/* Nothing
1824 +#define ICU0_IM0_IOSR_HOST_MB1_RIR_NULL 0x00000000 */
1825 +/** Read: Interrupt occurred. */
1826 +#define ICU0_IM0_IOSR_HOST_MB1_RIR_INTOCC 0x00000008
1827 +/** HOST IF Mailbox0 Transmit Interrupt
1828 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1829 +#define ICU0_IM0_IOSR_HOST_MB0_TIR 0x00000004
1830 +/* Nothing
1831 +#define ICU0_IM0_IOSR_HOST_MB0_TIR_NULL 0x00000000 */
1832 +/** Read: Interrupt occurred. */
1833 +#define ICU0_IM0_IOSR_HOST_MB0_TIR_INTOCC 0x00000004
1834 +/** HOST IF Mailbox0 Receive Interrupt
1835 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1836 +#define ICU0_IM0_IOSR_HOST_MB0_RIR 0x00000002
1837 +/* Nothing
1838 +#define ICU0_IM0_IOSR_HOST_MB0_RIR_NULL 0x00000000 */
1839 +/** Read: Interrupt occurred. */
1840 +#define ICU0_IM0_IOSR_HOST_MB0_RIR_INTOCC 0x00000002
1841 +/** HOST IF Event Interrupt
1842 + Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1843 +#define ICU0_IM0_IOSR_HOST_EIR 0x00000001
1844 +/* Nothing
1845 +#define ICU0_IM0_IOSR_HOST_EIR_NULL 0x00000000 */
1846 +/** Read: Interrupt occurred. */
1847 +#define ICU0_IM0_IOSR_HOST_EIR_INTOCC 0x00000001
1848 +
1849 +/* Fields of "IM0 Interrupt Request Set Register" */
1850 +/** PCM Transmit Crash Interrupt
1851 + Software control for the corresponding bit in the IM0_ISR register. */
1852 +#define ICU0_IM0_IRSR_PCM_HW2_CRASH 0x80000000
1853 +/** PCM Transmit Interrupt
1854 + Software control for the corresponding bit in the IM0_ISR register. */
1855 +#define ICU0_IM0_IRSR_PCM_TX 0x40000000
1856 +/** PCM Receive Interrupt
1857 + Software control for the corresponding bit in the IM0_ISR register. */
1858 +#define ICU0_IM0_IRSR_PCM_RX 0x20000000
1859 +/** Secure Hash Algorithm Interrupt
1860 + Software control for the corresponding bit in the IM0_ISR register. */
1861 +#define ICU0_IM0_IRSR_SHA1_HASH 0x10000000
1862 +/** Advanced Encryption Standard Interrupt
1863 + Software control for the corresponding bit in the IM0_ISR register. */
1864 +#define ICU0_IM0_IRSR_AES_AES 0x08000000
1865 +/** SSC Frame Interrupt
1866 + Software control for the corresponding bit in the IM0_ISR register. */
1867 +#define ICU0_IM0_IRSR_SSC0_F 0x00020000
1868 +/** SSC Error Interrupt
1869 + Software control for the corresponding bit in the IM0_ISR register. */
1870 +#define ICU0_IM0_IRSR_SSC0_E 0x00010000
1871 +/** SSC Receive Interrupt
1872 + Software control for the corresponding bit in the IM0_ISR register. */
1873 +#define ICU0_IM0_IRSR_SSC0_R 0x00008000
1874 +/** SSC Transmit Interrupt
1875 + Software control for the corresponding bit in the IM0_ISR register. */
1876 +#define ICU0_IM0_IRSR_SSC0_T 0x00004000
1877 +/** I2C Peripheral Interrupt
1878 + Software control for the corresponding bit in the IM0_ISR register. */
1879 +#define ICU0_IM0_IRSR_I2C_I2C_P_INT 0x00002000
1880 +/** I2C Error Interrupt
1881 + Software control for the corresponding bit in the IM0_ISR register. */
1882 +#define ICU0_IM0_IRSR_I2C_I2C_ERR_INT 0x00001000
1883 +/** I2C Burst Data Transfer Request
1884 + Software control for the corresponding bit in the IM0_ISR register. */
1885 +#define ICU0_IM0_IRSR_I2C_BREQ_INT 0x00000800
1886 +/** I2C Last Burst Data Transfer Request
1887 + Software control for the corresponding bit in the IM0_ISR register. */
1888 +#define ICU0_IM0_IRSR_I2C_LBREQ_INT 0x00000400
1889 +/** I2C Single Data Transfer Request
1890 + Software control for the corresponding bit in the IM0_ISR register. */
1891 +#define ICU0_IM0_IRSR_I2C_SREQ_INT 0x00000200
1892 +/** I2C Last Single Data Transfer Request
1893 + Software control for the corresponding bit in the IM0_ISR register. */
1894 +#define ICU0_IM0_IRSR_I2C_LSREQ_INT 0x00000100
1895 +/** HOST IF Mailbox1 Transmit Interrupt
1896 + Software control for the corresponding bit in the IM0_ISR register. */
1897 +#define ICU0_IM0_IRSR_HOST_MB1_TIR 0x00000010
1898 +/** HOST IF Mailbox1 Receive Interrupt
1899 + Software control for the corresponding bit in the IM0_ISR register. */
1900 +#define ICU0_IM0_IRSR_HOST_MB1_RIR 0x00000008
1901 +/** HOST IF Mailbox0 Transmit Interrupt
1902 + Software control for the corresponding bit in the IM0_ISR register. */
1903 +#define ICU0_IM0_IRSR_HOST_MB0_TIR 0x00000004
1904 +/** HOST IF Mailbox0 Receive Interrupt
1905 + Software control for the corresponding bit in the IM0_ISR register. */
1906 +#define ICU0_IM0_IRSR_HOST_MB0_RIR 0x00000002
1907 +/** HOST IF Event Interrupt
1908 + Software control for the corresponding bit in the IM0_ISR register. */
1909 +#define ICU0_IM0_IRSR_HOST_EIR 0x00000001
1910 +
1911 +/* Fields of "IM0 Interrupt Mode Register" */
1912 +/** PCM Transmit Crash Interrupt
1913 + Type of interrupt. */
1914 +#define ICU0_IM0_IMR_PCM_HW2_CRASH 0x80000000
1915 +/* Indirect Interrupt.
1916 +#define ICU0_IM0_IMR_PCM_HW2_CRASH_IND 0x00000000 */
1917 +/** Direct Interrupt. */
1918 +#define ICU0_IM0_IMR_PCM_HW2_CRASH_DIR 0x80000000
1919 +/** PCM Transmit Interrupt
1920 + Type of interrupt. */
1921 +#define ICU0_IM0_IMR_PCM_TX 0x40000000
1922 +/* Indirect Interrupt.
1923 +#define ICU0_IM0_IMR_PCM_TX_IND 0x00000000 */
1924 +/** Direct Interrupt. */
1925 +#define ICU0_IM0_IMR_PCM_TX_DIR 0x40000000
1926 +/** PCM Receive Interrupt
1927 + Type of interrupt. */
1928 +#define ICU0_IM0_IMR_PCM_RX 0x20000000
1929 +/* Indirect Interrupt.
1930 +#define ICU0_IM0_IMR_PCM_RX_IND 0x00000000 */
1931 +/** Direct Interrupt. */
1932 +#define ICU0_IM0_IMR_PCM_RX_DIR 0x20000000
1933 +/** Secure Hash Algorithm Interrupt
1934 + Type of interrupt. */
1935 +#define ICU0_IM0_IMR_SHA1_HASH 0x10000000
1936 +/* Indirect Interrupt.
1937 +#define ICU0_IM0_IMR_SHA1_HASH_IND 0x00000000 */
1938 +/** Direct Interrupt. */
1939 +#define ICU0_IM0_IMR_SHA1_HASH_DIR 0x10000000
1940 +/** Advanced Encryption Standard Interrupt
1941 + Type of interrupt. */
1942 +#define ICU0_IM0_IMR_AES_AES 0x08000000
1943 +/* Indirect Interrupt.
1944 +#define ICU0_IM0_IMR_AES_AES_IND 0x00000000 */
1945 +/** Direct Interrupt. */
1946 +#define ICU0_IM0_IMR_AES_AES_DIR 0x08000000
1947 +/** SSC Frame Interrupt
1948 + Type of interrupt. */
1949 +#define ICU0_IM0_IMR_SSC0_F 0x00020000
1950 +/* Indirect Interrupt.
1951 +#define ICU0_IM0_IMR_SSC0_F_IND 0x00000000 */
1952 +/** Direct Interrupt. */
1953 +#define ICU0_IM0_IMR_SSC0_F_DIR 0x00020000
1954 +/** SSC Error Interrupt
1955 + Type of interrupt. */
1956 +#define ICU0_IM0_IMR_SSC0_E 0x00010000
1957 +/* Indirect Interrupt.
1958 +#define ICU0_IM0_IMR_SSC0_E_IND 0x00000000 */
1959 +/** Direct Interrupt. */
1960 +#define ICU0_IM0_IMR_SSC0_E_DIR 0x00010000
1961 +/** SSC Receive Interrupt
1962 + Type of interrupt. */
1963 +#define ICU0_IM0_IMR_SSC0_R 0x00008000
1964 +/* Indirect Interrupt.
1965 +#define ICU0_IM0_IMR_SSC0_R_IND 0x00000000 */
1966 +/** Direct Interrupt. */
1967 +#define ICU0_IM0_IMR_SSC0_R_DIR 0x00008000
1968 +/** SSC Transmit Interrupt
1969 + Type of interrupt. */
1970 +#define ICU0_IM0_IMR_SSC0_T 0x00004000
1971 +/* Indirect Interrupt.
1972 +#define ICU0_IM0_IMR_SSC0_T_IND 0x00000000 */
1973 +/** Direct Interrupt. */
1974 +#define ICU0_IM0_IMR_SSC0_T_DIR 0x00004000
1975 +/** I2C Peripheral Interrupt
1976 + Type of interrupt. */
1977 +#define ICU0_IM0_IMR_I2C_I2C_P_INT 0x00002000
1978 +/* Indirect Interrupt.
1979 +#define ICU0_IM0_IMR_I2C_I2C_P_INT_IND 0x00000000 */
1980 +/** Direct Interrupt. */
1981 +#define ICU0_IM0_IMR_I2C_I2C_P_INT_DIR 0x00002000
1982 +/** I2C Error Interrupt
1983 + Type of interrupt. */
1984 +#define ICU0_IM0_IMR_I2C_I2C_ERR_INT 0x00001000
1985 +/* Indirect Interrupt.
1986 +#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_IND 0x00000000 */
1987 +/** Direct Interrupt. */
1988 +#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_DIR 0x00001000
1989 +/** I2C Burst Data Transfer Request
1990 + Type of interrupt. */
1991 +#define ICU0_IM0_IMR_I2C_BREQ_INT 0x00000800
1992 +/* Indirect Interrupt.
1993 +#define ICU0_IM0_IMR_I2C_BREQ_INT_IND 0x00000000 */
1994 +/** Direct Interrupt. */
1995 +#define ICU0_IM0_IMR_I2C_BREQ_INT_DIR 0x00000800
1996 +/** I2C Last Burst Data Transfer Request
1997 + Type of interrupt. */
1998 +#define ICU0_IM0_IMR_I2C_LBREQ_INT 0x00000400
1999 +/* Indirect Interrupt.
2000 +#define ICU0_IM0_IMR_I2C_LBREQ_INT_IND 0x00000000 */
2001 +/** Direct Interrupt. */
2002 +#define ICU0_IM0_IMR_I2C_LBREQ_INT_DIR 0x00000400
2003 +/** I2C Single Data Transfer Request
2004 + Type of interrupt. */
2005 +#define ICU0_IM0_IMR_I2C_SREQ_INT 0x00000200
2006 +/* Indirect Interrupt.
2007 +#define ICU0_IM0_IMR_I2C_SREQ_INT_IND 0x00000000 */
2008 +/** Direct Interrupt. */
2009 +#define ICU0_IM0_IMR_I2C_SREQ_INT_DIR 0x00000200
2010 +/** I2C Last Single Data Transfer Request
2011 + Type of interrupt. */
2012 +#define ICU0_IM0_IMR_I2C_LSREQ_INT 0x00000100
2013 +/* Indirect Interrupt.
2014 +#define ICU0_IM0_IMR_I2C_LSREQ_INT_IND 0x00000000 */
2015 +/** Direct Interrupt. */
2016 +#define ICU0_IM0_IMR_I2C_LSREQ_INT_DIR 0x00000100
2017 +/** HOST IF Mailbox1 Transmit Interrupt
2018 + Type of interrupt. */
2019 +#define ICU0_IM0_IMR_HOST_MB1_TIR 0x00000010
2020 +/* Indirect Interrupt.
2021 +#define ICU0_IM0_IMR_HOST_MB1_TIR_IND 0x00000000 */
2022 +/** Direct Interrupt. */
2023 +#define ICU0_IM0_IMR_HOST_MB1_TIR_DIR 0x00000010
2024 +/** HOST IF Mailbox1 Receive Interrupt
2025 + Type of interrupt. */
2026 +#define ICU0_IM0_IMR_HOST_MB1_RIR 0x00000008
2027 +/* Indirect Interrupt.
2028 +#define ICU0_IM0_IMR_HOST_MB1_RIR_IND 0x00000000 */
2029 +/** Direct Interrupt. */
2030 +#define ICU0_IM0_IMR_HOST_MB1_RIR_DIR 0x00000008
2031 +/** HOST IF Mailbox0 Transmit Interrupt
2032 + Type of interrupt. */
2033 +#define ICU0_IM0_IMR_HOST_MB0_TIR 0x00000004
2034 +/* Indirect Interrupt.
2035 +#define ICU0_IM0_IMR_HOST_MB0_TIR_IND 0x00000000 */
2036 +/** Direct Interrupt. */
2037 +#define ICU0_IM0_IMR_HOST_MB0_TIR_DIR 0x00000004
2038 +/** HOST IF Mailbox0 Receive Interrupt
2039 + Type of interrupt. */
2040 +#define ICU0_IM0_IMR_HOST_MB0_RIR 0x00000002
2041 +/* Indirect Interrupt.
2042 +#define ICU0_IM0_IMR_HOST_MB0_RIR_IND 0x00000000 */
2043 +/** Direct Interrupt. */
2044 +#define ICU0_IM0_IMR_HOST_MB0_RIR_DIR 0x00000002
2045 +/** HOST IF Event Interrupt
2046 + Type of interrupt. */
2047 +#define ICU0_IM0_IMR_HOST_EIR 0x00000001
2048 +/* Indirect Interrupt.
2049 +#define ICU0_IM0_IMR_HOST_EIR_IND 0x00000000 */
2050 +/** Direct Interrupt. */
2051 +#define ICU0_IM0_IMR_HOST_EIR_DIR 0x00000001
2052 +
2053 +/* Fields of "IM1 Interrupt Status Register" */
2054 +/** Crossbar Error Interrupt
2055 + This bit is an indirect interrupt. */
2056 +#define ICU0_IM1_ISR_XBAR_ERROR 0x80000000
2057 +/* Nothing
2058 +#define ICU0_IM1_ISR_XBAR_ERROR_NULL 0x00000000 */
2059 +/** Write: Acknowledge the interrupt. */
2060 +#define ICU0_IM1_ISR_XBAR_ERROR_INTACK 0x80000000
2061 +/** Read: Interrupt occurred. */
2062 +#define ICU0_IM1_ISR_XBAR_ERROR_INTOCC 0x80000000
2063 +/** DDR Controller Interrupt
2064 + This bit is an indirect interrupt. */
2065 +#define ICU0_IM1_ISR_DDR 0x40000000
2066 +/* Nothing
2067 +#define ICU0_IM1_ISR_DDR_NULL 0x00000000 */
2068 +/** Write: Acknowledge the interrupt. */
2069 +#define ICU0_IM1_ISR_DDR_INTACK 0x40000000
2070 +/** Read: Interrupt occurred. */
2071 +#define ICU0_IM1_ISR_DDR_INTOCC 0x40000000
2072 +/** FPI Bus Control Unit Interrupt
2073 + This bit is a direct interrupt. */
2074 +#define ICU0_IM1_ISR_BCU0 0x20000000
2075 +/* Nothing
2076 +#define ICU0_IM1_ISR_BCU0_NULL 0x00000000 */
2077 +/** Write: Acknowledge the interrupt. */
2078 +#define ICU0_IM1_ISR_BCU0_INTACK 0x20000000
2079 +/** Read: Interrupt occurred. */
2080 +#define ICU0_IM1_ISR_BCU0_INTOCC 0x20000000
2081 +/** SBIU interrupt
2082 + This bit is an indirect interrupt. */
2083 +#define ICU0_IM1_ISR_SBIU0 0x08000000
2084 +/* Nothing
2085 +#define ICU0_IM1_ISR_SBIU0_NULL 0x00000000 */
2086 +/** Write: Acknowledge the interrupt. */
2087 +#define ICU0_IM1_ISR_SBIU0_INTACK 0x08000000
2088 +/** Read: Interrupt occurred. */
2089 +#define ICU0_IM1_ISR_SBIU0_INTOCC 0x08000000
2090 +/** Watchdog Prewarning Interrupt
2091 + This bit is an indirect interrupt. */
2092 +#define ICU0_IM1_ISR_WDT_PIR 0x02000000
2093 +/* Nothing
2094 +#define ICU0_IM1_ISR_WDT_PIR_NULL 0x00000000 */
2095 +/** Write: Acknowledge the interrupt. */
2096 +#define ICU0_IM1_ISR_WDT_PIR_INTACK 0x02000000
2097 +/** Read: Interrupt occurred. */
2098 +#define ICU0_IM1_ISR_WDT_PIR_INTOCC 0x02000000
2099 +/** Watchdog Access Error Interrupt
2100 + This bit is an indirect interrupt. */
2101 +#define ICU0_IM1_ISR_WDT_AEIR 0x01000000
2102 +/* Nothing
2103 +#define ICU0_IM1_ISR_WDT_AEIR_NULL 0x00000000 */
2104 +/** Write: Acknowledge the interrupt. */
2105 +#define ICU0_IM1_ISR_WDT_AEIR_INTACK 0x01000000
2106 +/** Read: Interrupt occurred. */
2107 +#define ICU0_IM1_ISR_WDT_AEIR_INTOCC 0x01000000
2108 +/** SYS GPE Interrupt
2109 + This bit is an indirect interrupt. */
2110 +#define ICU0_IM1_ISR_SYS_GPE 0x00200000
2111 +/* Nothing
2112 +#define ICU0_IM1_ISR_SYS_GPE_NULL 0x00000000 */
2113 +/** Write: Acknowledge the interrupt. */
2114 +#define ICU0_IM1_ISR_SYS_GPE_INTACK 0x00200000
2115 +/** Read: Interrupt occurred. */
2116 +#define ICU0_IM1_ISR_SYS_GPE_INTOCC 0x00200000
2117 +/** SYS1 Interrupt
2118 + This bit is an indirect interrupt. */
2119 +#define ICU0_IM1_ISR_SYS1 0x00100000
2120 +/* Nothing
2121 +#define ICU0_IM1_ISR_SYS1_NULL 0x00000000 */
2122 +/** Write: Acknowledge the interrupt. */
2123 +#define ICU0_IM1_ISR_SYS1_INTACK 0x00100000
2124 +/** Read: Interrupt occurred. */
2125 +#define ICU0_IM1_ISR_SYS1_INTOCC 0x00100000
2126 +/** PMA Interrupt from IntNode of the RX Clk Domain
2127 + This bit is an indirect interrupt. */
2128 +#define ICU0_IM1_ISR_PMA_RX 0x00020000
2129 +/* Nothing
2130 +#define ICU0_IM1_ISR_PMA_RX_NULL 0x00000000 */
2131 +/** Write: Acknowledge the interrupt. */
2132 +#define ICU0_IM1_ISR_PMA_RX_INTACK 0x00020000
2133 +/** Read: Interrupt occurred. */
2134 +#define ICU0_IM1_ISR_PMA_RX_INTOCC 0x00020000
2135 +/** PMA Interrupt from IntNode of the TX Clk Domain
2136 + This bit is an indirect interrupt. */
2137 +#define ICU0_IM1_ISR_PMA_TX 0x00010000
2138 +/* Nothing
2139 +#define ICU0_IM1_ISR_PMA_TX_NULL 0x00000000 */
2140 +/** Write: Acknowledge the interrupt. */
2141 +#define ICU0_IM1_ISR_PMA_TX_INTACK 0x00010000
2142 +/** Read: Interrupt occurred. */
2143 +#define ICU0_IM1_ISR_PMA_TX_INTOCC 0x00010000
2144 +/** PMA Interrupt from IntNode of the 200MHz Domain
2145 + This bit is an indirect interrupt. */
2146 +#define ICU0_IM1_ISR_PMA_200M 0x00008000
2147 +/* Nothing
2148 +#define ICU0_IM1_ISR_PMA_200M_NULL 0x00000000 */
2149 +/** Write: Acknowledge the interrupt. */
2150 +#define ICU0_IM1_ISR_PMA_200M_INTACK 0x00008000
2151 +/** Read: Interrupt occurred. */
2152 +#define ICU0_IM1_ISR_PMA_200M_INTOCC 0x00008000
2153 +/** Time of Day
2154 + This bit is an indirect interrupt. */
2155 +#define ICU0_IM1_ISR_TOD 0x00004000
2156 +/* Nothing
2157 +#define ICU0_IM1_ISR_TOD_NULL 0x00000000 */
2158 +/** Write: Acknowledge the interrupt. */
2159 +#define ICU0_IM1_ISR_TOD_INTACK 0x00004000
2160 +/** Read: Interrupt occurred. */
2161 +#define ICU0_IM1_ISR_TOD_INTOCC 0x00004000
2162 +/** 8kHz root interrupt derived from GPON interface
2163 + This bit is a direct interrupt. */
2164 +#define ICU0_IM1_ISR_FSC_ROOT 0x00002000
2165 +/* Nothing
2166 +#define ICU0_IM1_ISR_FSC_ROOT_NULL 0x00000000 */
2167 +/** Write: Acknowledge the interrupt. */
2168 +#define ICU0_IM1_ISR_FSC_ROOT_INTACK 0x00002000
2169 +/** Read: Interrupt occurred. */
2170 +#define ICU0_IM1_ISR_FSC_ROOT_INTOCC 0x00002000
2171 +/** FSC Timer Interrupt 1
2172 + Delayed version of FSCROOT. This bit is a direct interrupt. */
2173 +#define ICU0_IM1_ISR_FSCT_CMP1 0x00001000
2174 +/* Nothing
2175 +#define ICU0_IM1_ISR_FSCT_CMP1_NULL 0x00000000 */
2176 +/** Write: Acknowledge the interrupt. */
2177 +#define ICU0_IM1_ISR_FSCT_CMP1_INTACK 0x00001000
2178 +/** Read: Interrupt occurred. */
2179 +#define ICU0_IM1_ISR_FSCT_CMP1_INTOCC 0x00001000
2180 +/** FSC Timer Interrupt 0
2181 + Delayed version of FSCROOT. This bit is a direct interrupt. */
2182 +#define ICU0_IM1_ISR_FSCT_CMP0 0x00000800
2183 +/* Nothing
2184 +#define ICU0_IM1_ISR_FSCT_CMP0_NULL 0x00000000 */
2185 +/** Write: Acknowledge the interrupt. */
2186 +#define ICU0_IM1_ISR_FSCT_CMP0_INTACK 0x00000800
2187 +/** Read: Interrupt occurred. */
2188 +#define ICU0_IM1_ISR_FSCT_CMP0_INTOCC 0x00000800
2189 +/** 8kHz backup interrupt derived from core-PLL
2190 + This bit is an indirect interrupt. */
2191 +#define ICU0_IM1_ISR_FSC_BKP 0x00000400
2192 +/* Nothing
2193 +#define ICU0_IM1_ISR_FSC_BKP_NULL 0x00000000 */
2194 +/** Write: Acknowledge the interrupt. */
2195 +#define ICU0_IM1_ISR_FSC_BKP_INTACK 0x00000400
2196 +/** Read: Interrupt occurred. */
2197 +#define ICU0_IM1_ISR_FSC_BKP_INTOCC 0x00000400
2198 +/** External Interrupt from GPIO P4
2199 + This bit is an indirect interrupt. */
2200 +#define ICU0_IM1_ISR_P4 0x00000100
2201 +/* Nothing
2202 +#define ICU0_IM1_ISR_P4_NULL 0x00000000 */
2203 +/** Write: Acknowledge the interrupt. */
2204 +#define ICU0_IM1_ISR_P4_INTACK 0x00000100
2205 +/** Read: Interrupt occurred. */
2206 +#define ICU0_IM1_ISR_P4_INTOCC 0x00000100
2207 +/** External Interrupt from GPIO P3
2208 + This bit is an indirect interrupt. */
2209 +#define ICU0_IM1_ISR_P3 0x00000080
2210 +/* Nothing
2211 +#define ICU0_IM1_ISR_P3_NULL 0x00000000 */
2212 +/** Write: Acknowledge the interrupt. */
2213 +#define ICU0_IM1_ISR_P3_INTACK 0x00000080
2214 +/** Read: Interrupt occurred. */
2215 +#define ICU0_IM1_ISR_P3_INTOCC 0x00000080
2216 +/** External Interrupt from GPIO P2
2217 + This bit is an indirect interrupt. */
2218 +#define ICU0_IM1_ISR_P2 0x00000040
2219 +/* Nothing
2220 +#define ICU0_IM1_ISR_P2_NULL 0x00000000 */
2221 +/** Write: Acknowledge the interrupt. */
2222 +#define ICU0_IM1_ISR_P2_INTACK 0x00000040
2223 +/** Read: Interrupt occurred. */
2224 +#define ICU0_IM1_ISR_P2_INTOCC 0x00000040
2225 +/** External Interrupt from GPIO P1
2226 + This bit is an indirect interrupt. */
2227 +#define ICU0_IM1_ISR_P1 0x00000020
2228 +/* Nothing
2229 +#define ICU0_IM1_ISR_P1_NULL 0x00000000 */
2230 +/** Write: Acknowledge the interrupt. */
2231 +#define ICU0_IM1_ISR_P1_INTACK 0x00000020
2232 +/** Read: Interrupt occurred. */
2233 +#define ICU0_IM1_ISR_P1_INTOCC 0x00000020
2234 +/** External Interrupt from GPIO P0
2235 + This bit is an indirect interrupt. */
2236 +#define ICU0_IM1_ISR_P0 0x00000010
2237 +/* Nothing
2238 +#define ICU0_IM1_ISR_P0_NULL 0x00000000 */
2239 +/** Write: Acknowledge the interrupt. */
2240 +#define ICU0_IM1_ISR_P0_INTACK 0x00000010
2241 +/** Read: Interrupt occurred. */
2242 +#define ICU0_IM1_ISR_P0_INTOCC 0x00000010
2243 +/** EBU Serial Flash Busy
2244 + This bit is an indirect interrupt. */
2245 +#define ICU0_IM1_ISR_EBU_SF_BUSY 0x00000004
2246 +/* Nothing
2247 +#define ICU0_IM1_ISR_EBU_SF_BUSY_NULL 0x00000000 */
2248 +/** Write: Acknowledge the interrupt. */
2249 +#define ICU0_IM1_ISR_EBU_SF_BUSY_INTACK 0x00000004
2250 +/** Read: Interrupt occurred. */
2251 +#define ICU0_IM1_ISR_EBU_SF_BUSY_INTOCC 0x00000004
2252 +/** EBU Serial Flash Command Overwrite Error
2253 + This bit is an indirect interrupt. */
2254 +#define ICU0_IM1_ISR_EBU_SF_COVERR 0x00000002
2255 +/* Nothing
2256 +#define ICU0_IM1_ISR_EBU_SF_COVERR_NULL 0x00000000 */
2257 +/** Write: Acknowledge the interrupt. */
2258 +#define ICU0_IM1_ISR_EBU_SF_COVERR_INTACK 0x00000002
2259 +/** Read: Interrupt occurred. */
2260 +#define ICU0_IM1_ISR_EBU_SF_COVERR_INTOCC 0x00000002
2261 +/** EBU Serial Flash Command Error
2262 + This bit is an indirect interrupt. */
2263 +#define ICU0_IM1_ISR_EBU_SF_CMDERR 0x00000001
2264 +/* Nothing
2265 +#define ICU0_IM1_ISR_EBU_SF_CMDERR_NULL 0x00000000 */
2266 +/** Write: Acknowledge the interrupt. */
2267 +#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTACK 0x00000001
2268 +/** Read: Interrupt occurred. */
2269 +#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTOCC 0x00000001
2270 +
2271 +/* Fields of "IM1 Interrupt Enable Register" */
2272 +/** Crossbar Error Interrupt
2273 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2274 +#define ICU0_IM1_IER_XBAR_ERROR 0x80000000
2275 +/* Disable
2276 +#define ICU0_IM1_IER_XBAR_ERROR_DIS 0x00000000 */
2277 +/** Enable */
2278 +#define ICU0_IM1_IER_XBAR_ERROR_EN 0x80000000
2279 +/** DDR Controller Interrupt
2280 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2281 +#define ICU0_IM1_IER_DDR 0x40000000
2282 +/* Disable
2283 +#define ICU0_IM1_IER_DDR_DIS 0x00000000 */
2284 +/** Enable */
2285 +#define ICU0_IM1_IER_DDR_EN 0x40000000
2286 +/** FPI Bus Control Unit Interrupt
2287 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2288 +#define ICU0_IM1_IER_BCU0 0x20000000
2289 +/* Disable
2290 +#define ICU0_IM1_IER_BCU0_DIS 0x00000000 */
2291 +/** Enable */
2292 +#define ICU0_IM1_IER_BCU0_EN 0x20000000
2293 +/** SBIU interrupt
2294 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2295 +#define ICU0_IM1_IER_SBIU0 0x08000000
2296 +/* Disable
2297 +#define ICU0_IM1_IER_SBIU0_DIS 0x00000000 */
2298 +/** Enable */
2299 +#define ICU0_IM1_IER_SBIU0_EN 0x08000000
2300 +/** Watchdog Prewarning Interrupt
2301 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2302 +#define ICU0_IM1_IER_WDT_PIR 0x02000000
2303 +/* Disable
2304 +#define ICU0_IM1_IER_WDT_PIR_DIS 0x00000000 */
2305 +/** Enable */
2306 +#define ICU0_IM1_IER_WDT_PIR_EN 0x02000000
2307 +/** Watchdog Access Error Interrupt
2308 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2309 +#define ICU0_IM1_IER_WDT_AEIR 0x01000000
2310 +/* Disable
2311 +#define ICU0_IM1_IER_WDT_AEIR_DIS 0x00000000 */
2312 +/** Enable */
2313 +#define ICU0_IM1_IER_WDT_AEIR_EN 0x01000000
2314 +/** SYS GPE Interrupt
2315 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2316 +#define ICU0_IM1_IER_SYS_GPE 0x00200000
2317 +/* Disable
2318 +#define ICU0_IM1_IER_SYS_GPE_DIS 0x00000000 */
2319 +/** Enable */
2320 +#define ICU0_IM1_IER_SYS_GPE_EN 0x00200000
2321 +/** SYS1 Interrupt
2322 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2323 +#define ICU0_IM1_IER_SYS1 0x00100000
2324 +/* Disable
2325 +#define ICU0_IM1_IER_SYS1_DIS 0x00000000 */
2326 +/** Enable */
2327 +#define ICU0_IM1_IER_SYS1_EN 0x00100000
2328 +/** PMA Interrupt from IntNode of the RX Clk Domain
2329 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2330 +#define ICU0_IM1_IER_PMA_RX 0x00020000
2331 +/* Disable
2332 +#define ICU0_IM1_IER_PMA_RX_DIS 0x00000000 */
2333 +/** Enable */
2334 +#define ICU0_IM1_IER_PMA_RX_EN 0x00020000
2335 +/** PMA Interrupt from IntNode of the TX Clk Domain
2336 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2337 +#define ICU0_IM1_IER_PMA_TX 0x00010000
2338 +/* Disable
2339 +#define ICU0_IM1_IER_PMA_TX_DIS 0x00000000 */
2340 +/** Enable */
2341 +#define ICU0_IM1_IER_PMA_TX_EN 0x00010000
2342 +/** PMA Interrupt from IntNode of the 200MHz Domain
2343 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2344 +#define ICU0_IM1_IER_PMA_200M 0x00008000
2345 +/* Disable
2346 +#define ICU0_IM1_IER_PMA_200M_DIS 0x00000000 */
2347 +/** Enable */
2348 +#define ICU0_IM1_IER_PMA_200M_EN 0x00008000
2349 +/** Time of Day
2350 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2351 +#define ICU0_IM1_IER_TOD 0x00004000
2352 +/* Disable
2353 +#define ICU0_IM1_IER_TOD_DIS 0x00000000 */
2354 +/** Enable */
2355 +#define ICU0_IM1_IER_TOD_EN 0x00004000
2356 +/** 8kHz root interrupt derived from GPON interface
2357 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2358 +#define ICU0_IM1_IER_FSC_ROOT 0x00002000
2359 +/* Disable
2360 +#define ICU0_IM1_IER_FSC_ROOT_DIS 0x00000000 */
2361 +/** Enable */
2362 +#define ICU0_IM1_IER_FSC_ROOT_EN 0x00002000
2363 +/** FSC Timer Interrupt 1
2364 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2365 +#define ICU0_IM1_IER_FSCT_CMP1 0x00001000
2366 +/* Disable
2367 +#define ICU0_IM1_IER_FSCT_CMP1_DIS 0x00000000 */
2368 +/** Enable */
2369 +#define ICU0_IM1_IER_FSCT_CMP1_EN 0x00001000
2370 +/** FSC Timer Interrupt 0
2371 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2372 +#define ICU0_IM1_IER_FSCT_CMP0 0x00000800
2373 +/* Disable
2374 +#define ICU0_IM1_IER_FSCT_CMP0_DIS 0x00000000 */
2375 +/** Enable */
2376 +#define ICU0_IM1_IER_FSCT_CMP0_EN 0x00000800
2377 +/** 8kHz backup interrupt derived from core-PLL
2378 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2379 +#define ICU0_IM1_IER_FSC_BKP 0x00000400
2380 +/* Disable
2381 +#define ICU0_IM1_IER_FSC_BKP_DIS 0x00000000 */
2382 +/** Enable */
2383 +#define ICU0_IM1_IER_FSC_BKP_EN 0x00000400
2384 +/** External Interrupt from GPIO P4
2385 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2386 +#define ICU0_IM1_IER_P4 0x00000100
2387 +/* Disable
2388 +#define ICU0_IM1_IER_P4_DIS 0x00000000 */
2389 +/** Enable */
2390 +#define ICU0_IM1_IER_P4_EN 0x00000100
2391 +/** External Interrupt from GPIO P3
2392 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2393 +#define ICU0_IM1_IER_P3 0x00000080
2394 +/* Disable
2395 +#define ICU0_IM1_IER_P3_DIS 0x00000000 */
2396 +/** Enable */
2397 +#define ICU0_IM1_IER_P3_EN 0x00000080
2398 +/** External Interrupt from GPIO P2
2399 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2400 +#define ICU0_IM1_IER_P2 0x00000040
2401 +/* Disable
2402 +#define ICU0_IM1_IER_P2_DIS 0x00000000 */
2403 +/** Enable */
2404 +#define ICU0_IM1_IER_P2_EN 0x00000040
2405 +/** External Interrupt from GPIO P1
2406 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2407 +#define ICU0_IM1_IER_P1 0x00000020
2408 +/* Disable
2409 +#define ICU0_IM1_IER_P1_DIS 0x00000000 */
2410 +/** Enable */
2411 +#define ICU0_IM1_IER_P1_EN 0x00000020
2412 +/** External Interrupt from GPIO P0
2413 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2414 +#define ICU0_IM1_IER_P0 0x00000010
2415 +/* Disable
2416 +#define ICU0_IM1_IER_P0_DIS 0x00000000 */
2417 +/** Enable */
2418 +#define ICU0_IM1_IER_P0_EN 0x00000010
2419 +/** EBU Serial Flash Busy
2420 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2421 +#define ICU0_IM1_IER_EBU_SF_BUSY 0x00000004
2422 +/* Disable
2423 +#define ICU0_IM1_IER_EBU_SF_BUSY_DIS 0x00000000 */
2424 +/** Enable */
2425 +#define ICU0_IM1_IER_EBU_SF_BUSY_EN 0x00000004
2426 +/** EBU Serial Flash Command Overwrite Error
2427 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2428 +#define ICU0_IM1_IER_EBU_SF_COVERR 0x00000002
2429 +/* Disable
2430 +#define ICU0_IM1_IER_EBU_SF_COVERR_DIS 0x00000000 */
2431 +/** Enable */
2432 +#define ICU0_IM1_IER_EBU_SF_COVERR_EN 0x00000002
2433 +/** EBU Serial Flash Command Error
2434 + Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2435 +#define ICU0_IM1_IER_EBU_SF_CMDERR 0x00000001
2436 +/* Disable
2437 +#define ICU0_IM1_IER_EBU_SF_CMDERR_DIS 0x00000000 */
2438 +/** Enable */
2439 +#define ICU0_IM1_IER_EBU_SF_CMDERR_EN 0x00000001
2440 +
2441 +/* Fields of "IM1 Interrupt Output Status Register" */
2442 +/** Crossbar Error Interrupt
2443 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2444 +#define ICU0_IM1_IOSR_XBAR_ERROR 0x80000000
2445 +/* Nothing
2446 +#define ICU0_IM1_IOSR_XBAR_ERROR_NULL 0x00000000 */
2447 +/** Read: Interrupt occurred. */
2448 +#define ICU0_IM1_IOSR_XBAR_ERROR_INTOCC 0x80000000
2449 +/** DDR Controller Interrupt
2450 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2451 +#define ICU0_IM1_IOSR_DDR 0x40000000
2452 +/* Nothing
2453 +#define ICU0_IM1_IOSR_DDR_NULL 0x00000000 */
2454 +/** Read: Interrupt occurred. */
2455 +#define ICU0_IM1_IOSR_DDR_INTOCC 0x40000000
2456 +/** FPI Bus Control Unit Interrupt
2457 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2458 +#define ICU0_IM1_IOSR_BCU0 0x20000000
2459 +/* Nothing
2460 +#define ICU0_IM1_IOSR_BCU0_NULL 0x00000000 */
2461 +/** Read: Interrupt occurred. */
2462 +#define ICU0_IM1_IOSR_BCU0_INTOCC 0x20000000
2463 +/** SBIU interrupt
2464 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2465 +#define ICU0_IM1_IOSR_SBIU0 0x08000000
2466 +/* Nothing
2467 +#define ICU0_IM1_IOSR_SBIU0_NULL 0x00000000 */
2468 +/** Read: Interrupt occurred. */
2469 +#define ICU0_IM1_IOSR_SBIU0_INTOCC 0x08000000
2470 +/** Watchdog Prewarning Interrupt
2471 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2472 +#define ICU0_IM1_IOSR_WDT_PIR 0x02000000
2473 +/* Nothing
2474 +#define ICU0_IM1_IOSR_WDT_PIR_NULL 0x00000000 */
2475 +/** Read: Interrupt occurred. */
2476 +#define ICU0_IM1_IOSR_WDT_PIR_INTOCC 0x02000000
2477 +/** Watchdog Access Error Interrupt
2478 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2479 +#define ICU0_IM1_IOSR_WDT_AEIR 0x01000000
2480 +/* Nothing
2481 +#define ICU0_IM1_IOSR_WDT_AEIR_NULL 0x00000000 */
2482 +/** Read: Interrupt occurred. */
2483 +#define ICU0_IM1_IOSR_WDT_AEIR_INTOCC 0x01000000
2484 +/** SYS GPE Interrupt
2485 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2486 +#define ICU0_IM1_IOSR_SYS_GPE 0x00200000
2487 +/* Nothing
2488 +#define ICU0_IM1_IOSR_SYS_GPE_NULL 0x00000000 */
2489 +/** Read: Interrupt occurred. */
2490 +#define ICU0_IM1_IOSR_SYS_GPE_INTOCC 0x00200000
2491 +/** SYS1 Interrupt
2492 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2493 +#define ICU0_IM1_IOSR_SYS1 0x00100000
2494 +/* Nothing
2495 +#define ICU0_IM1_IOSR_SYS1_NULL 0x00000000 */
2496 +/** Read: Interrupt occurred. */
2497 +#define ICU0_IM1_IOSR_SYS1_INTOCC 0x00100000
2498 +/** PMA Interrupt from IntNode of the RX Clk Domain
2499 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2500 +#define ICU0_IM1_IOSR_PMA_RX 0x00020000
2501 +/* Nothing
2502 +#define ICU0_IM1_IOSR_PMA_RX_NULL 0x00000000 */
2503 +/** Read: Interrupt occurred. */
2504 +#define ICU0_IM1_IOSR_PMA_RX_INTOCC 0x00020000
2505 +/** PMA Interrupt from IntNode of the TX Clk Domain
2506 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2507 +#define ICU0_IM1_IOSR_PMA_TX 0x00010000
2508 +/* Nothing
2509 +#define ICU0_IM1_IOSR_PMA_TX_NULL 0x00000000 */
2510 +/** Read: Interrupt occurred. */
2511 +#define ICU0_IM1_IOSR_PMA_TX_INTOCC 0x00010000
2512 +/** PMA Interrupt from IntNode of the 200MHz Domain
2513 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2514 +#define ICU0_IM1_IOSR_PMA_200M 0x00008000
2515 +/* Nothing
2516 +#define ICU0_IM1_IOSR_PMA_200M_NULL 0x00000000 */
2517 +/** Read: Interrupt occurred. */
2518 +#define ICU0_IM1_IOSR_PMA_200M_INTOCC 0x00008000
2519 +/** Time of Day
2520 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2521 +#define ICU0_IM1_IOSR_TOD 0x00004000
2522 +/* Nothing
2523 +#define ICU0_IM1_IOSR_TOD_NULL 0x00000000 */
2524 +/** Read: Interrupt occurred. */
2525 +#define ICU0_IM1_IOSR_TOD_INTOCC 0x00004000
2526 +/** 8kHz root interrupt derived from GPON interface
2527 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2528 +#define ICU0_IM1_IOSR_FSC_ROOT 0x00002000
2529 +/* Nothing
2530 +#define ICU0_IM1_IOSR_FSC_ROOT_NULL 0x00000000 */
2531 +/** Read: Interrupt occurred. */
2532 +#define ICU0_IM1_IOSR_FSC_ROOT_INTOCC 0x00002000
2533 +/** FSC Timer Interrupt 1
2534 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2535 +#define ICU0_IM1_IOSR_FSCT_CMP1 0x00001000
2536 +/* Nothing
2537 +#define ICU0_IM1_IOSR_FSCT_CMP1_NULL 0x00000000 */
2538 +/** Read: Interrupt occurred. */
2539 +#define ICU0_IM1_IOSR_FSCT_CMP1_INTOCC 0x00001000
2540 +/** FSC Timer Interrupt 0
2541 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2542 +#define ICU0_IM1_IOSR_FSCT_CMP0 0x00000800
2543 +/* Nothing
2544 +#define ICU0_IM1_IOSR_FSCT_CMP0_NULL 0x00000000 */
2545 +/** Read: Interrupt occurred. */
2546 +#define ICU0_IM1_IOSR_FSCT_CMP0_INTOCC 0x00000800
2547 +/** 8kHz backup interrupt derived from core-PLL
2548 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2549 +#define ICU0_IM1_IOSR_FSC_BKP 0x00000400
2550 +/* Nothing
2551 +#define ICU0_IM1_IOSR_FSC_BKP_NULL 0x00000000 */
2552 +/** Read: Interrupt occurred. */
2553 +#define ICU0_IM1_IOSR_FSC_BKP_INTOCC 0x00000400
2554 +/** External Interrupt from GPIO P4
2555 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2556 +#define ICU0_IM1_IOSR_P4 0x00000100
2557 +/* Nothing
2558 +#define ICU0_IM1_IOSR_P4_NULL 0x00000000 */
2559 +/** Read: Interrupt occurred. */
2560 +#define ICU0_IM1_IOSR_P4_INTOCC 0x00000100
2561 +/** External Interrupt from GPIO P3
2562 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2563 +#define ICU0_IM1_IOSR_P3 0x00000080
2564 +/* Nothing
2565 +#define ICU0_IM1_IOSR_P3_NULL 0x00000000 */
2566 +/** Read: Interrupt occurred. */
2567 +#define ICU0_IM1_IOSR_P3_INTOCC 0x00000080
2568 +/** External Interrupt from GPIO P2
2569 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2570 +#define ICU0_IM1_IOSR_P2 0x00000040
2571 +/* Nothing
2572 +#define ICU0_IM1_IOSR_P2_NULL 0x00000000 */
2573 +/** Read: Interrupt occurred. */
2574 +#define ICU0_IM1_IOSR_P2_INTOCC 0x00000040
2575 +/** External Interrupt from GPIO P1
2576 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2577 +#define ICU0_IM1_IOSR_P1 0x00000020
2578 +/* Nothing
2579 +#define ICU0_IM1_IOSR_P1_NULL 0x00000000 */
2580 +/** Read: Interrupt occurred. */
2581 +#define ICU0_IM1_IOSR_P1_INTOCC 0x00000020
2582 +/** External Interrupt from GPIO P0
2583 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2584 +#define ICU0_IM1_IOSR_P0 0x00000010
2585 +/* Nothing
2586 +#define ICU0_IM1_IOSR_P0_NULL 0x00000000 */
2587 +/** Read: Interrupt occurred. */
2588 +#define ICU0_IM1_IOSR_P0_INTOCC 0x00000010
2589 +/** EBU Serial Flash Busy
2590 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2591 +#define ICU0_IM1_IOSR_EBU_SF_BUSY 0x00000004
2592 +/* Nothing
2593 +#define ICU0_IM1_IOSR_EBU_SF_BUSY_NULL 0x00000000 */
2594 +/** Read: Interrupt occurred. */
2595 +#define ICU0_IM1_IOSR_EBU_SF_BUSY_INTOCC 0x00000004
2596 +/** EBU Serial Flash Command Overwrite Error
2597 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2598 +#define ICU0_IM1_IOSR_EBU_SF_COVERR 0x00000002
2599 +/* Nothing
2600 +#define ICU0_IM1_IOSR_EBU_SF_COVERR_NULL 0x00000000 */
2601 +/** Read: Interrupt occurred. */
2602 +#define ICU0_IM1_IOSR_EBU_SF_COVERR_INTOCC 0x00000002
2603 +/** EBU Serial Flash Command Error
2604 + Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2605 +#define ICU0_IM1_IOSR_EBU_SF_CMDERR 0x00000001
2606 +/* Nothing
2607 +#define ICU0_IM1_IOSR_EBU_SF_CMDERR_NULL 0x00000000 */
2608 +/** Read: Interrupt occurred. */
2609 +#define ICU0_IM1_IOSR_EBU_SF_CMDERR_INTOCC 0x00000001
2610 +
2611 +/* Fields of "IM1 Interrupt Request Set Register" */
2612 +/** Crossbar Error Interrupt
2613 + Software control for the corresponding bit in the IM1_ISR register. */
2614 +#define ICU0_IM1_IRSR_XBAR_ERROR 0x80000000
2615 +/** DDR Controller Interrupt
2616 + Software control for the corresponding bit in the IM1_ISR register. */
2617 +#define ICU0_IM1_IRSR_DDR 0x40000000
2618 +/** FPI Bus Control Unit Interrupt
2619 + Software control for the corresponding bit in the IM1_ISR register. */
2620 +#define ICU0_IM1_IRSR_BCU0 0x20000000
2621 +/** SBIU interrupt
2622 + Software control for the corresponding bit in the IM1_ISR register. */
2623 +#define ICU0_IM1_IRSR_SBIU0 0x08000000
2624 +/** Watchdog Prewarning Interrupt
2625 + Software control for the corresponding bit in the IM1_ISR register. */
2626 +#define ICU0_IM1_IRSR_WDT_PIR 0x02000000
2627 +/** Watchdog Access Error Interrupt
2628 + Software control for the corresponding bit in the IM1_ISR register. */
2629 +#define ICU0_IM1_IRSR_WDT_AEIR 0x01000000
2630 +/** SYS GPE Interrupt
2631 + Software control for the corresponding bit in the IM1_ISR register. */
2632 +#define ICU0_IM1_IRSR_SYS_GPE 0x00200000
2633 +/** SYS1 Interrupt
2634 + Software control for the corresponding bit in the IM1_ISR register. */
2635 +#define ICU0_IM1_IRSR_SYS1 0x00100000
2636 +/** PMA Interrupt from IntNode of the RX Clk Domain
2637 + Software control for the corresponding bit in the IM1_ISR register. */
2638 +#define ICU0_IM1_IRSR_PMA_RX 0x00020000
2639 +/** PMA Interrupt from IntNode of the TX Clk Domain
2640 + Software control for the corresponding bit in the IM1_ISR register. */
2641 +#define ICU0_IM1_IRSR_PMA_TX 0x00010000
2642 +/** PMA Interrupt from IntNode of the 200MHz Domain
2643 + Software control for the corresponding bit in the IM1_ISR register. */
2644 +#define ICU0_IM1_IRSR_PMA_200M 0x00008000
2645 +/** Time of Day
2646 + Software control for the corresponding bit in the IM1_ISR register. */
2647 +#define ICU0_IM1_IRSR_TOD 0x00004000
2648 +/** 8kHz root interrupt derived from GPON interface
2649 + Software control for the corresponding bit in the IM1_ISR register. */
2650 +#define ICU0_IM1_IRSR_FSC_ROOT 0x00002000
2651 +/** FSC Timer Interrupt 1
2652 + Software control for the corresponding bit in the IM1_ISR register. */
2653 +#define ICU0_IM1_IRSR_FSCT_CMP1 0x00001000
2654 +/** FSC Timer Interrupt 0
2655 + Software control for the corresponding bit in the IM1_ISR register. */
2656 +#define ICU0_IM1_IRSR_FSCT_CMP0 0x00000800
2657 +/** 8kHz backup interrupt derived from core-PLL
2658 + Software control for the corresponding bit in the IM1_ISR register. */
2659 +#define ICU0_IM1_IRSR_FSC_BKP 0x00000400
2660 +/** External Interrupt from GPIO P4
2661 + Software control for the corresponding bit in the IM1_ISR register. */
2662 +#define ICU0_IM1_IRSR_P4 0x00000100
2663 +/** External Interrupt from GPIO P3
2664 + Software control for the corresponding bit in the IM1_ISR register. */
2665 +#define ICU0_IM1_IRSR_P3 0x00000080
2666 +/** External Interrupt from GPIO P2
2667 + Software control for the corresponding bit in the IM1_ISR register. */
2668 +#define ICU0_IM1_IRSR_P2 0x00000040
2669 +/** External Interrupt from GPIO P1
2670 + Software control for the corresponding bit in the IM1_ISR register. */
2671 +#define ICU0_IM1_IRSR_P1 0x00000020
2672 +/** External Interrupt from GPIO P0
2673 + Software control for the corresponding bit in the IM1_ISR register. */
2674 +#define ICU0_IM1_IRSR_P0 0x00000010
2675 +/** EBU Serial Flash Busy
2676 + Software control for the corresponding bit in the IM1_ISR register. */
2677 +#define ICU0_IM1_IRSR_EBU_SF_BUSY 0x00000004
2678 +/** EBU Serial Flash Command Overwrite Error
2679 + Software control for the corresponding bit in the IM1_ISR register. */
2680 +#define ICU0_IM1_IRSR_EBU_SF_COVERR 0x00000002
2681 +/** EBU Serial Flash Command Error
2682 + Software control for the corresponding bit in the IM1_ISR register. */
2683 +#define ICU0_IM1_IRSR_EBU_SF_CMDERR 0x00000001
2684 +
2685 +/* Fields of "IM1 Interrupt Mode Register" */
2686 +/** Crossbar Error Interrupt
2687 + Type of interrupt. */
2688 +#define ICU0_IM1_IMR_XBAR_ERROR 0x80000000
2689 +/* Indirect Interrupt.
2690 +#define ICU0_IM1_IMR_XBAR_ERROR_IND 0x00000000 */
2691 +/** Direct Interrupt. */
2692 +#define ICU0_IM1_IMR_XBAR_ERROR_DIR 0x80000000
2693 +/** DDR Controller Interrupt
2694 + Type of interrupt. */
2695 +#define ICU0_IM1_IMR_DDR 0x40000000
2696 +/* Indirect Interrupt.
2697 +#define ICU0_IM1_IMR_DDR_IND 0x00000000 */
2698 +/** Direct Interrupt. */
2699 +#define ICU0_IM1_IMR_DDR_DIR 0x40000000
2700 +/** FPI Bus Control Unit Interrupt
2701 + Type of interrupt. */
2702 +#define ICU0_IM1_IMR_BCU0 0x20000000
2703 +/* Indirect Interrupt.
2704 +#define ICU0_IM1_IMR_BCU0_IND 0x00000000 */
2705 +/** Direct Interrupt. */
2706 +#define ICU0_IM1_IMR_BCU0_DIR 0x20000000
2707 +/** SBIU interrupt
2708 + Type of interrupt. */
2709 +#define ICU0_IM1_IMR_SBIU0 0x08000000
2710 +/* Indirect Interrupt.
2711 +#define ICU0_IM1_IMR_SBIU0_IND 0x00000000 */
2712 +/** Direct Interrupt. */
2713 +#define ICU0_IM1_IMR_SBIU0_DIR 0x08000000
2714 +/** Watchdog Prewarning Interrupt
2715 + Type of interrupt. */
2716 +#define ICU0_IM1_IMR_WDT_PIR 0x02000000
2717 +/* Indirect Interrupt.
2718 +#define ICU0_IM1_IMR_WDT_PIR_IND 0x00000000 */
2719 +/** Direct Interrupt. */
2720 +#define ICU0_IM1_IMR_WDT_PIR_DIR 0x02000000
2721 +/** Watchdog Access Error Interrupt
2722 + Type of interrupt. */
2723 +#define ICU0_IM1_IMR_WDT_AEIR 0x01000000
2724 +/* Indirect Interrupt.
2725 +#define ICU0_IM1_IMR_WDT_AEIR_IND 0x00000000 */
2726 +/** Direct Interrupt. */
2727 +#define ICU0_IM1_IMR_WDT_AEIR_DIR 0x01000000
2728 +/** SYS GPE Interrupt
2729 + Type of interrupt. */
2730 +#define ICU0_IM1_IMR_SYS_GPE 0x00200000
2731 +/* Indirect Interrupt.
2732 +#define ICU0_IM1_IMR_SYS_GPE_IND 0x00000000 */
2733 +/** Direct Interrupt. */
2734 +#define ICU0_IM1_IMR_SYS_GPE_DIR 0x00200000
2735 +/** SYS1 Interrupt
2736 + Type of interrupt. */
2737 +#define ICU0_IM1_IMR_SYS1 0x00100000
2738 +/* Indirect Interrupt.
2739 +#define ICU0_IM1_IMR_SYS1_IND 0x00000000 */
2740 +/** Direct Interrupt. */
2741 +#define ICU0_IM1_IMR_SYS1_DIR 0x00100000
2742 +/** PMA Interrupt from IntNode of the RX Clk Domain
2743 + Type of interrupt. */
2744 +#define ICU0_IM1_IMR_PMA_RX 0x00020000
2745 +/* Indirect Interrupt.
2746 +#define ICU0_IM1_IMR_PMA_RX_IND 0x00000000 */
2747 +/** Direct Interrupt. */
2748 +#define ICU0_IM1_IMR_PMA_RX_DIR 0x00020000
2749 +/** PMA Interrupt from IntNode of the TX Clk Domain
2750 + Type of interrupt. */
2751 +#define ICU0_IM1_IMR_PMA_TX 0x00010000
2752 +/* Indirect Interrupt.
2753 +#define ICU0_IM1_IMR_PMA_TX_IND 0x00000000 */
2754 +/** Direct Interrupt. */
2755 +#define ICU0_IM1_IMR_PMA_TX_DIR 0x00010000
2756 +/** PMA Interrupt from IntNode of the 200MHz Domain
2757 + Type of interrupt. */
2758 +#define ICU0_IM1_IMR_PMA_200M 0x00008000
2759 +/* Indirect Interrupt.
2760 +#define ICU0_IM1_IMR_PMA_200M_IND 0x00000000 */
2761 +/** Direct Interrupt. */
2762 +#define ICU0_IM1_IMR_PMA_200M_DIR 0x00008000
2763 +/** Time of Day
2764 + Type of interrupt. */
2765 +#define ICU0_IM1_IMR_TOD 0x00004000
2766 +/* Indirect Interrupt.
2767 +#define ICU0_IM1_IMR_TOD_IND 0x00000000 */
2768 +/** Direct Interrupt. */
2769 +#define ICU0_IM1_IMR_TOD_DIR 0x00004000
2770 +/** 8kHz root interrupt derived from GPON interface
2771 + Type of interrupt. */
2772 +#define ICU0_IM1_IMR_FSC_ROOT 0x00002000
2773 +/* Indirect Interrupt.
2774 +#define ICU0_IM1_IMR_FSC_ROOT_IND 0x00000000 */
2775 +/** Direct Interrupt. */
2776 +#define ICU0_IM1_IMR_FSC_ROOT_DIR 0x00002000
2777 +/** FSC Timer Interrupt 1
2778 + Type of interrupt. */
2779 +#define ICU0_IM1_IMR_FSCT_CMP1 0x00001000
2780 +/* Indirect Interrupt.
2781 +#define ICU0_IM1_IMR_FSCT_CMP1_IND 0x00000000 */
2782 +/** Direct Interrupt. */
2783 +#define ICU0_IM1_IMR_FSCT_CMP1_DIR 0x00001000
2784 +/** FSC Timer Interrupt 0
2785 + Type of interrupt. */
2786 +#define ICU0_IM1_IMR_FSCT_CMP0 0x00000800
2787 +/* Indirect Interrupt.
2788 +#define ICU0_IM1_IMR_FSCT_CMP0_IND 0x00000000 */
2789 +/** Direct Interrupt. */
2790 +#define ICU0_IM1_IMR_FSCT_CMP0_DIR 0x00000800
2791 +/** 8kHz backup interrupt derived from core-PLL
2792 + Type of interrupt. */
2793 +#define ICU0_IM1_IMR_FSC_BKP 0x00000400
2794 +/* Indirect Interrupt.
2795 +#define ICU0_IM1_IMR_FSC_BKP_IND 0x00000000 */
2796 +/** Direct Interrupt. */
2797 +#define ICU0_IM1_IMR_FSC_BKP_DIR 0x00000400
2798 +/** External Interrupt from GPIO P4
2799 + Type of interrupt. */
2800 +#define ICU0_IM1_IMR_P4 0x00000100
2801 +/* Indirect Interrupt.
2802 +#define ICU0_IM1_IMR_P4_IND 0x00000000 */
2803 +/** Direct Interrupt. */
2804 +#define ICU0_IM1_IMR_P4_DIR 0x00000100
2805 +/** External Interrupt from GPIO P3
2806 + Type of interrupt. */
2807 +#define ICU0_IM1_IMR_P3 0x00000080
2808 +/* Indirect Interrupt.
2809 +#define ICU0_IM1_IMR_P3_IND 0x00000000 */
2810 +/** Direct Interrupt. */
2811 +#define ICU0_IM1_IMR_P3_DIR 0x00000080
2812 +/** External Interrupt from GPIO P2
2813 + Type of interrupt. */
2814 +#define ICU0_IM1_IMR_P2 0x00000040
2815 +/* Indirect Interrupt.
2816 +#define ICU0_IM1_IMR_P2_IND 0x00000000 */
2817 +/** Direct Interrupt. */
2818 +#define ICU0_IM1_IMR_P2_DIR 0x00000040
2819 +/** External Interrupt from GPIO P1
2820 + Type of interrupt. */
2821 +#define ICU0_IM1_IMR_P1 0x00000020
2822 +/* Indirect Interrupt.
2823 +#define ICU0_IM1_IMR_P1_IND 0x00000000 */
2824 +/** Direct Interrupt. */
2825 +#define ICU0_IM1_IMR_P1_DIR 0x00000020
2826 +/** External Interrupt from GPIO P0
2827 + Type of interrupt. */
2828 +#define ICU0_IM1_IMR_P0 0x00000010
2829 +/* Indirect Interrupt.
2830 +#define ICU0_IM1_IMR_P0_IND 0x00000000 */
2831 +/** Direct Interrupt. */
2832 +#define ICU0_IM1_IMR_P0_DIR 0x00000010
2833 +/** EBU Serial Flash Busy
2834 + Type of interrupt. */
2835 +#define ICU0_IM1_IMR_EBU_SF_BUSY 0x00000004
2836 +/* Indirect Interrupt.
2837 +#define ICU0_IM1_IMR_EBU_SF_BUSY_IND 0x00000000 */
2838 +/** Direct Interrupt. */
2839 +#define ICU0_IM1_IMR_EBU_SF_BUSY_DIR 0x00000004
2840 +/** EBU Serial Flash Command Overwrite Error
2841 + Type of interrupt. */
2842 +#define ICU0_IM1_IMR_EBU_SF_COVERR 0x00000002
2843 +/* Indirect Interrupt.
2844 +#define ICU0_IM1_IMR_EBU_SF_COVERR_IND 0x00000000 */
2845 +/** Direct Interrupt. */
2846 +#define ICU0_IM1_IMR_EBU_SF_COVERR_DIR 0x00000002
2847 +/** EBU Serial Flash Command Error
2848 + Type of interrupt. */
2849 +#define ICU0_IM1_IMR_EBU_SF_CMDERR 0x00000001
2850 +/* Indirect Interrupt.
2851 +#define ICU0_IM1_IMR_EBU_SF_CMDERR_IND 0x00000000 */
2852 +/** Direct Interrupt. */
2853 +#define ICU0_IM1_IMR_EBU_SF_CMDERR_DIR 0x00000001
2854 +
2855 +/* Fields of "IM2 Interrupt Status Register" */
2856 +/** EIM Interrupt
2857 + This bit is an indirect interrupt. */
2858 +#define ICU0_IM2_ISR_EIM 0x80000000
2859 +/* Nothing
2860 +#define ICU0_IM2_ISR_EIM_NULL 0x00000000 */
2861 +/** Write: Acknowledge the interrupt. */
2862 +#define ICU0_IM2_ISR_EIM_INTACK 0x80000000
2863 +/** Read: Interrupt occurred. */
2864 +#define ICU0_IM2_ISR_EIM_INTOCC 0x80000000
2865 +/** GTC Upstream Interrupt
2866 + This bit is an indirect interrupt. */
2867 +#define ICU0_IM2_ISR_GTC_US 0x40000000
2868 +/* Nothing
2869 +#define ICU0_IM2_ISR_GTC_US_NULL 0x00000000 */
2870 +/** Write: Acknowledge the interrupt. */
2871 +#define ICU0_IM2_ISR_GTC_US_INTACK 0x40000000
2872 +/** Read: Interrupt occurred. */
2873 +#define ICU0_IM2_ISR_GTC_US_INTOCC 0x40000000
2874 +/** GTC Downstream Interrupt
2875 + This bit is an indirect interrupt. */
2876 +#define ICU0_IM2_ISR_GTC_DS 0x20000000
2877 +/* Nothing
2878 +#define ICU0_IM2_ISR_GTC_DS_NULL 0x00000000 */
2879 +/** Write: Acknowledge the interrupt. */
2880 +#define ICU0_IM2_ISR_GTC_DS_INTACK 0x20000000
2881 +/** Read: Interrupt occurred. */
2882 +#define ICU0_IM2_ISR_GTC_DS_INTOCC 0x20000000
2883 +/** TBM Interrupt
2884 + This bit is an indirect interrupt. */
2885 +#define ICU0_IM2_ISR_TBM 0x00400000
2886 +/* Nothing
2887 +#define ICU0_IM2_ISR_TBM_NULL 0x00000000 */
2888 +/** Write: Acknowledge the interrupt. */
2889 +#define ICU0_IM2_ISR_TBM_INTACK 0x00400000
2890 +/** Read: Interrupt occurred. */
2891 +#define ICU0_IM2_ISR_TBM_INTOCC 0x00400000
2892 +/** Dispatcher Interrupt
2893 + This bit is an indirect interrupt. */
2894 +#define ICU0_IM2_ISR_DISP 0x00200000
2895 +/* Nothing
2896 +#define ICU0_IM2_ISR_DISP_NULL 0x00000000 */
2897 +/** Write: Acknowledge the interrupt. */
2898 +#define ICU0_IM2_ISR_DISP_INTACK 0x00200000
2899 +/** Read: Interrupt occurred. */
2900 +#define ICU0_IM2_ISR_DISP_INTOCC 0x00200000
2901 +/** CONFIG Interrupt
2902 + This bit is an indirect interrupt. */
2903 +#define ICU0_IM2_ISR_CONFIG 0x00100000
2904 +/* Nothing
2905 +#define ICU0_IM2_ISR_CONFIG_NULL 0x00000000 */
2906 +/** Write: Acknowledge the interrupt. */
2907 +#define ICU0_IM2_ISR_CONFIG_INTACK 0x00100000
2908 +/** Read: Interrupt occurred. */
2909 +#define ICU0_IM2_ISR_CONFIG_INTOCC 0x00100000
2910 +/** CONFIG Break Interrupt
2911 + This bit is an indirect interrupt. */
2912 +#define ICU0_IM2_ISR_CONFIG_BREAK 0x00080000
2913 +/* Nothing
2914 +#define ICU0_IM2_ISR_CONFIG_BREAK_NULL 0x00000000 */
2915 +/** Write: Acknowledge the interrupt. */
2916 +#define ICU0_IM2_ISR_CONFIG_BREAK_INTACK 0x00080000
2917 +/** Read: Interrupt occurred. */
2918 +#define ICU0_IM2_ISR_CONFIG_BREAK_INTOCC 0x00080000
2919 +/** OCTRLC Interrupt
2920 + This bit is an indirect interrupt. */
2921 +#define ICU0_IM2_ISR_OCTRLC 0x00040000
2922 +/* Nothing
2923 +#define ICU0_IM2_ISR_OCTRLC_NULL 0x00000000 */
2924 +/** Write: Acknowledge the interrupt. */
2925 +#define ICU0_IM2_ISR_OCTRLC_INTACK 0x00040000
2926 +/** Read: Interrupt occurred. */
2927 +#define ICU0_IM2_ISR_OCTRLC_INTOCC 0x00040000
2928 +/** ICTRLC 1 Interrupt
2929 + This bit is an indirect interrupt. */
2930 +#define ICU0_IM2_ISR_ICTRLC1 0x00020000
2931 +/* Nothing
2932 +#define ICU0_IM2_ISR_ICTRLC1_NULL 0x00000000 */
2933 +/** Write: Acknowledge the interrupt. */
2934 +#define ICU0_IM2_ISR_ICTRLC1_INTACK 0x00020000
2935 +/** Read: Interrupt occurred. */
2936 +#define ICU0_IM2_ISR_ICTRLC1_INTOCC 0x00020000
2937 +/** ICTRLC 0 Interrupt
2938 + This bit is an indirect interrupt. */
2939 +#define ICU0_IM2_ISR_ICTRLC0 0x00010000
2940 +/* Nothing
2941 +#define ICU0_IM2_ISR_ICTRLC0_NULL 0x00000000 */
2942 +/** Write: Acknowledge the interrupt. */
2943 +#define ICU0_IM2_ISR_ICTRLC0_INTACK 0x00010000
2944 +/** Read: Interrupt occurred. */
2945 +#define ICU0_IM2_ISR_ICTRLC0_INTOCC 0x00010000
2946 +/** LINK 1 Interrupt
2947 + This bit is an indirect interrupt. */
2948 +#define ICU0_IM2_ISR_LINK1 0x00004000
2949 +/* Nothing
2950 +#define ICU0_IM2_ISR_LINK1_NULL 0x00000000 */
2951 +/** Write: Acknowledge the interrupt. */
2952 +#define ICU0_IM2_ISR_LINK1_INTACK 0x00004000
2953 +/** Read: Interrupt occurred. */
2954 +#define ICU0_IM2_ISR_LINK1_INTOCC 0x00004000
2955 +/** TMU Interrupt
2956 + This bit is an indirect interrupt. */
2957 +#define ICU0_IM2_ISR_TMU 0x00001000
2958 +/* Nothing
2959 +#define ICU0_IM2_ISR_TMU_NULL 0x00000000 */
2960 +/** Write: Acknowledge the interrupt. */
2961 +#define ICU0_IM2_ISR_TMU_INTACK 0x00001000
2962 +/** Read: Interrupt occurred. */
2963 +#define ICU0_IM2_ISR_TMU_INTOCC 0x00001000
2964 +/** FSQM Interrupt
2965 + This bit is an indirect interrupt. */
2966 +#define ICU0_IM2_ISR_FSQM 0x00000800
2967 +/* Nothing
2968 +#define ICU0_IM2_ISR_FSQM_NULL 0x00000000 */
2969 +/** Write: Acknowledge the interrupt. */
2970 +#define ICU0_IM2_ISR_FSQM_INTACK 0x00000800
2971 +/** Read: Interrupt occurred. */
2972 +#define ICU0_IM2_ISR_FSQM_INTOCC 0x00000800
2973 +/** IQM Interrupt
2974 + This bit is an indirect interrupt. */
2975 +#define ICU0_IM2_ISR_IQM 0x00000400
2976 +/* Nothing
2977 +#define ICU0_IM2_ISR_IQM_NULL 0x00000000 */
2978 +/** Write: Acknowledge the interrupt. */
2979 +#define ICU0_IM2_ISR_IQM_INTACK 0x00000400
2980 +/** Read: Interrupt occurred. */
2981 +#define ICU0_IM2_ISR_IQM_INTOCC 0x00000400
2982 +/** OCTRLG Interrupt
2983 + This bit is an indirect interrupt. */
2984 +#define ICU0_IM2_ISR_OCTRLG 0x00000200
2985 +/* Nothing
2986 +#define ICU0_IM2_ISR_OCTRLG_NULL 0x00000000 */
2987 +/** Write: Acknowledge the interrupt. */
2988 +#define ICU0_IM2_ISR_OCTRLG_INTACK 0x00000200
2989 +/** Read: Interrupt occurred. */
2990 +#define ICU0_IM2_ISR_OCTRLG_INTOCC 0x00000200
2991 +/** OCTRLL 3 Interrupt
2992 + This bit is an indirect interrupt. */
2993 +#define ICU0_IM2_ISR_OCTRLL3 0x00000080
2994 +/* Nothing
2995 +#define ICU0_IM2_ISR_OCTRLL3_NULL 0x00000000 */
2996 +/** Write: Acknowledge the interrupt. */
2997 +#define ICU0_IM2_ISR_OCTRLL3_INTACK 0x00000080
2998 +/** Read: Interrupt occurred. */
2999 +#define ICU0_IM2_ISR_OCTRLL3_INTOCC 0x00000080
3000 +/** OCTRLL 2 Interrupt
3001 + This bit is an indirect interrupt. */
3002 +#define ICU0_IM2_ISR_OCTRLL2 0x00000040
3003 +/* Nothing
3004 +#define ICU0_IM2_ISR_OCTRLL2_NULL 0x00000000 */
3005 +/** Write: Acknowledge the interrupt. */
3006 +#define ICU0_IM2_ISR_OCTRLL2_INTACK 0x00000040
3007 +/** Read: Interrupt occurred. */
3008 +#define ICU0_IM2_ISR_OCTRLL2_INTOCC 0x00000040
3009 +/** OCTRLL 1 Interrupt
3010 + This bit is an indirect interrupt. */
3011 +#define ICU0_IM2_ISR_OCTRLL1 0x00000020
3012 +/* Nothing
3013 +#define ICU0_IM2_ISR_OCTRLL1_NULL 0x00000000 */
3014 +/** Write: Acknowledge the interrupt. */
3015 +#define ICU0_IM2_ISR_OCTRLL1_INTACK 0x00000020
3016 +/** Read: Interrupt occurred. */
3017 +#define ICU0_IM2_ISR_OCTRLL1_INTOCC 0x00000020
3018 +/** OCTRLL 0 Interrupt
3019 + This bit is an indirect interrupt. */
3020 +#define ICU0_IM2_ISR_OCTRLL0 0x00000010
3021 +/* Nothing
3022 +#define ICU0_IM2_ISR_OCTRLL0_NULL 0x00000000 */
3023 +/** Write: Acknowledge the interrupt. */
3024 +#define ICU0_IM2_ISR_OCTRLL0_INTACK 0x00000010
3025 +/** Read: Interrupt occurred. */
3026 +#define ICU0_IM2_ISR_OCTRLL0_INTOCC 0x00000010
3027 +/** ICTRLL 3 Interrupt
3028 + This bit is an indirect interrupt. */
3029 +#define ICU0_IM2_ISR_ICTRLL3 0x00000008
3030 +/* Nothing
3031 +#define ICU0_IM2_ISR_ICTRLL3_NULL 0x00000000 */
3032 +/** Write: Acknowledge the interrupt. */
3033 +#define ICU0_IM2_ISR_ICTRLL3_INTACK 0x00000008
3034 +/** Read: Interrupt occurred. */
3035 +#define ICU0_IM2_ISR_ICTRLL3_INTOCC 0x00000008
3036 +/** ICTRLL 2 Interrupt
3037 + This bit is an indirect interrupt. */
3038 +#define ICU0_IM2_ISR_ICTRLL2 0x00000004
3039 +/* Nothing
3040 +#define ICU0_IM2_ISR_ICTRLL2_NULL 0x00000000 */
3041 +/** Write: Acknowledge the interrupt. */
3042 +#define ICU0_IM2_ISR_ICTRLL2_INTACK 0x00000004
3043 +/** Read: Interrupt occurred. */
3044 +#define ICU0_IM2_ISR_ICTRLL2_INTOCC 0x00000004
3045 +/** ICTRLL 1 Interrupt
3046 + This bit is an indirect interrupt. */
3047 +#define ICU0_IM2_ISR_ICTRLL1 0x00000002
3048 +/* Nothing
3049 +#define ICU0_IM2_ISR_ICTRLL1_NULL 0x00000000 */
3050 +/** Write: Acknowledge the interrupt. */
3051 +#define ICU0_IM2_ISR_ICTRLL1_INTACK 0x00000002
3052 +/** Read: Interrupt occurred. */
3053 +#define ICU0_IM2_ISR_ICTRLL1_INTOCC 0x00000002
3054 +/** ICTRLL 0 Interrupt
3055 + This bit is an indirect interrupt. */
3056 +#define ICU0_IM2_ISR_ICTRLL0 0x00000001
3057 +/* Nothing
3058 +#define ICU0_IM2_ISR_ICTRLL0_NULL 0x00000000 */
3059 +/** Write: Acknowledge the interrupt. */
3060 +#define ICU0_IM2_ISR_ICTRLL0_INTACK 0x00000001
3061 +/** Read: Interrupt occurred. */
3062 +#define ICU0_IM2_ISR_ICTRLL0_INTOCC 0x00000001
3063 +
3064 +/* Fields of "IM2 Interrupt Enable Register" */
3065 +/** EIM Interrupt
3066 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3067 +#define ICU0_IM2_IER_EIM 0x80000000
3068 +/* Disable
3069 +#define ICU0_IM2_IER_EIM_DIS 0x00000000 */
3070 +/** Enable */
3071 +#define ICU0_IM2_IER_EIM_EN 0x80000000
3072 +/** GTC Upstream Interrupt
3073 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3074 +#define ICU0_IM2_IER_GTC_US 0x40000000
3075 +/* Disable
3076 +#define ICU0_IM2_IER_GTC_US_DIS 0x00000000 */
3077 +/** Enable */
3078 +#define ICU0_IM2_IER_GTC_US_EN 0x40000000
3079 +/** GTC Downstream Interrupt
3080 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3081 +#define ICU0_IM2_IER_GTC_DS 0x20000000
3082 +/* Disable
3083 +#define ICU0_IM2_IER_GTC_DS_DIS 0x00000000 */
3084 +/** Enable */
3085 +#define ICU0_IM2_IER_GTC_DS_EN 0x20000000
3086 +/** TBM Interrupt
3087 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3088 +#define ICU0_IM2_IER_TBM 0x00400000
3089 +/* Disable
3090 +#define ICU0_IM2_IER_TBM_DIS 0x00000000 */
3091 +/** Enable */
3092 +#define ICU0_IM2_IER_TBM_EN 0x00400000
3093 +/** Dispatcher Interrupt
3094 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3095 +#define ICU0_IM2_IER_DISP 0x00200000
3096 +/* Disable
3097 +#define ICU0_IM2_IER_DISP_DIS 0x00000000 */
3098 +/** Enable */
3099 +#define ICU0_IM2_IER_DISP_EN 0x00200000
3100 +/** CONFIG Interrupt
3101 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3102 +#define ICU0_IM2_IER_CONFIG 0x00100000
3103 +/* Disable
3104 +#define ICU0_IM2_IER_CONFIG_DIS 0x00000000 */
3105 +/** Enable */
3106 +#define ICU0_IM2_IER_CONFIG_EN 0x00100000
3107 +/** CONFIG Break Interrupt
3108 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3109 +#define ICU0_IM2_IER_CONFIG_BREAK 0x00080000
3110 +/* Disable
3111 +#define ICU0_IM2_IER_CONFIG_BREAK_DIS 0x00000000 */
3112 +/** Enable */
3113 +#define ICU0_IM2_IER_CONFIG_BREAK_EN 0x00080000
3114 +/** OCTRLC Interrupt
3115 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3116 +#define ICU0_IM2_IER_OCTRLC 0x00040000
3117 +/* Disable
3118 +#define ICU0_IM2_IER_OCTRLC_DIS 0x00000000 */
3119 +/** Enable */
3120 +#define ICU0_IM2_IER_OCTRLC_EN 0x00040000
3121 +/** ICTRLC 1 Interrupt
3122 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3123 +#define ICU0_IM2_IER_ICTRLC1 0x00020000
3124 +/* Disable
3125 +#define ICU0_IM2_IER_ICTRLC1_DIS 0x00000000 */
3126 +/** Enable */
3127 +#define ICU0_IM2_IER_ICTRLC1_EN 0x00020000
3128 +/** ICTRLC 0 Interrupt
3129 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3130 +#define ICU0_IM2_IER_ICTRLC0 0x00010000
3131 +/* Disable
3132 +#define ICU0_IM2_IER_ICTRLC0_DIS 0x00000000 */
3133 +/** Enable */
3134 +#define ICU0_IM2_IER_ICTRLC0_EN 0x00010000
3135 +/** LINK 1 Interrupt
3136 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3137 +#define ICU0_IM2_IER_LINK1 0x00004000
3138 +/* Disable
3139 +#define ICU0_IM2_IER_LINK1_DIS 0x00000000 */
3140 +/** Enable */
3141 +#define ICU0_IM2_IER_LINK1_EN 0x00004000
3142 +/** TMU Interrupt
3143 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3144 +#define ICU0_IM2_IER_TMU 0x00001000
3145 +/* Disable
3146 +#define ICU0_IM2_IER_TMU_DIS 0x00000000 */
3147 +/** Enable */
3148 +#define ICU0_IM2_IER_TMU_EN 0x00001000
3149 +/** FSQM Interrupt
3150 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3151 +#define ICU0_IM2_IER_FSQM 0x00000800
3152 +/* Disable
3153 +#define ICU0_IM2_IER_FSQM_DIS 0x00000000 */
3154 +/** Enable */
3155 +#define ICU0_IM2_IER_FSQM_EN 0x00000800
3156 +/** IQM Interrupt
3157 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3158 +#define ICU0_IM2_IER_IQM 0x00000400
3159 +/* Disable
3160 +#define ICU0_IM2_IER_IQM_DIS 0x00000000 */
3161 +/** Enable */
3162 +#define ICU0_IM2_IER_IQM_EN 0x00000400
3163 +/** OCTRLG Interrupt
3164 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3165 +#define ICU0_IM2_IER_OCTRLG 0x00000200
3166 +/* Disable
3167 +#define ICU0_IM2_IER_OCTRLG_DIS 0x00000000 */
3168 +/** Enable */
3169 +#define ICU0_IM2_IER_OCTRLG_EN 0x00000200
3170 +/** OCTRLL 3 Interrupt
3171 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3172 +#define ICU0_IM2_IER_OCTRLL3 0x00000080
3173 +/* Disable
3174 +#define ICU0_IM2_IER_OCTRLL3_DIS 0x00000000 */
3175 +/** Enable */
3176 +#define ICU0_IM2_IER_OCTRLL3_EN 0x00000080
3177 +/** OCTRLL 2 Interrupt
3178 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3179 +#define ICU0_IM2_IER_OCTRLL2 0x00000040
3180 +/* Disable
3181 +#define ICU0_IM2_IER_OCTRLL2_DIS 0x00000000 */
3182 +/** Enable */
3183 +#define ICU0_IM2_IER_OCTRLL2_EN 0x00000040
3184 +/** OCTRLL 1 Interrupt
3185 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3186 +#define ICU0_IM2_IER_OCTRLL1 0x00000020
3187 +/* Disable
3188 +#define ICU0_IM2_IER_OCTRLL1_DIS 0x00000000 */
3189 +/** Enable */
3190 +#define ICU0_IM2_IER_OCTRLL1_EN 0x00000020
3191 +/** OCTRLL 0 Interrupt
3192 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3193 +#define ICU0_IM2_IER_OCTRLL0 0x00000010
3194 +/* Disable
3195 +#define ICU0_IM2_IER_OCTRLL0_DIS 0x00000000 */
3196 +/** Enable */
3197 +#define ICU0_IM2_IER_OCTRLL0_EN 0x00000010
3198 +/** ICTRLL 3 Interrupt
3199 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3200 +#define ICU0_IM2_IER_ICTRLL3 0x00000008
3201 +/* Disable
3202 +#define ICU0_IM2_IER_ICTRLL3_DIS 0x00000000 */
3203 +/** Enable */
3204 +#define ICU0_IM2_IER_ICTRLL3_EN 0x00000008
3205 +/** ICTRLL 2 Interrupt
3206 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3207 +#define ICU0_IM2_IER_ICTRLL2 0x00000004
3208 +/* Disable
3209 +#define ICU0_IM2_IER_ICTRLL2_DIS 0x00000000 */
3210 +/** Enable */
3211 +#define ICU0_IM2_IER_ICTRLL2_EN 0x00000004
3212 +/** ICTRLL 1 Interrupt
3213 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3214 +#define ICU0_IM2_IER_ICTRLL1 0x00000002
3215 +/* Disable
3216 +#define ICU0_IM2_IER_ICTRLL1_DIS 0x00000000 */
3217 +/** Enable */
3218 +#define ICU0_IM2_IER_ICTRLL1_EN 0x00000002
3219 +/** ICTRLL 0 Interrupt
3220 + Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3221 +#define ICU0_IM2_IER_ICTRLL0 0x00000001
3222 +/* Disable
3223 +#define ICU0_IM2_IER_ICTRLL0_DIS 0x00000000 */
3224 +/** Enable */
3225 +#define ICU0_IM2_IER_ICTRLL0_EN 0x00000001
3226 +
3227 +/* Fields of "IM2 Interrupt Output Status Register" */
3228 +/** EIM Interrupt
3229 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3230 +#define ICU0_IM2_IOSR_EIM 0x80000000
3231 +/* Nothing
3232 +#define ICU0_IM2_IOSR_EIM_NULL 0x00000000 */
3233 +/** Read: Interrupt occurred. */
3234 +#define ICU0_IM2_IOSR_EIM_INTOCC 0x80000000
3235 +/** GTC Upstream Interrupt
3236 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3237 +#define ICU0_IM2_IOSR_GTC_US 0x40000000
3238 +/* Nothing
3239 +#define ICU0_IM2_IOSR_GTC_US_NULL 0x00000000 */
3240 +/** Read: Interrupt occurred. */
3241 +#define ICU0_IM2_IOSR_GTC_US_INTOCC 0x40000000
3242 +/** GTC Downstream Interrupt
3243 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3244 +#define ICU0_IM2_IOSR_GTC_DS 0x20000000
3245 +/* Nothing
3246 +#define ICU0_IM2_IOSR_GTC_DS_NULL 0x00000000 */
3247 +/** Read: Interrupt occurred. */
3248 +#define ICU0_IM2_IOSR_GTC_DS_INTOCC 0x20000000
3249 +/** TBM Interrupt
3250 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3251 +#define ICU0_IM2_IOSR_TBM 0x00400000
3252 +/* Nothing
3253 +#define ICU0_IM2_IOSR_TBM_NULL 0x00000000 */
3254 +/** Read: Interrupt occurred. */
3255 +#define ICU0_IM2_IOSR_TBM_INTOCC 0x00400000
3256 +/** Dispatcher Interrupt
3257 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3258 +#define ICU0_IM2_IOSR_DISP 0x00200000
3259 +/* Nothing
3260 +#define ICU0_IM2_IOSR_DISP_NULL 0x00000000 */
3261 +/** Read: Interrupt occurred. */
3262 +#define ICU0_IM2_IOSR_DISP_INTOCC 0x00200000
3263 +/** CONFIG Interrupt
3264 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3265 +#define ICU0_IM2_IOSR_CONFIG 0x00100000
3266 +/* Nothing
3267 +#define ICU0_IM2_IOSR_CONFIG_NULL 0x00000000 */
3268 +/** Read: Interrupt occurred. */
3269 +#define ICU0_IM2_IOSR_CONFIG_INTOCC 0x00100000
3270 +/** CONFIG Break Interrupt
3271 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3272 +#define ICU0_IM2_IOSR_CONFIG_BREAK 0x00080000
3273 +/* Nothing
3274 +#define ICU0_IM2_IOSR_CONFIG_BREAK_NULL 0x00000000 */
3275 +/** Read: Interrupt occurred. */
3276 +#define ICU0_IM2_IOSR_CONFIG_BREAK_INTOCC 0x00080000
3277 +/** OCTRLC Interrupt
3278 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3279 +#define ICU0_IM2_IOSR_OCTRLC 0x00040000
3280 +/* Nothing
3281 +#define ICU0_IM2_IOSR_OCTRLC_NULL 0x00000000 */
3282 +/** Read: Interrupt occurred. */
3283 +#define ICU0_IM2_IOSR_OCTRLC_INTOCC 0x00040000
3284 +/** ICTRLC 1 Interrupt
3285 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3286 +#define ICU0_IM2_IOSR_ICTRLC1 0x00020000
3287 +/* Nothing
3288 +#define ICU0_IM2_IOSR_ICTRLC1_NULL 0x00000000 */
3289 +/** Read: Interrupt occurred. */
3290 +#define ICU0_IM2_IOSR_ICTRLC1_INTOCC 0x00020000
3291 +/** ICTRLC 0 Interrupt
3292 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3293 +#define ICU0_IM2_IOSR_ICTRLC0 0x00010000
3294 +/* Nothing
3295 +#define ICU0_IM2_IOSR_ICTRLC0_NULL 0x00000000 */
3296 +/** Read: Interrupt occurred. */
3297 +#define ICU0_IM2_IOSR_ICTRLC0_INTOCC 0x00010000
3298 +/** LINK 1 Interrupt
3299 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3300 +#define ICU0_IM2_IOSR_LINK1 0x00004000
3301 +/* Nothing
3302 +#define ICU0_IM2_IOSR_LINK1_NULL 0x00000000 */
3303 +/** Read: Interrupt occurred. */
3304 +#define ICU0_IM2_IOSR_LINK1_INTOCC 0x00004000
3305 +/** TMU Interrupt
3306 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3307 +#define ICU0_IM2_IOSR_TMU 0x00001000
3308 +/* Nothing
3309 +#define ICU0_IM2_IOSR_TMU_NULL 0x00000000 */
3310 +/** Read: Interrupt occurred. */
3311 +#define ICU0_IM2_IOSR_TMU_INTOCC 0x00001000
3312 +/** FSQM Interrupt
3313 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3314 +#define ICU0_IM2_IOSR_FSQM 0x00000800
3315 +/* Nothing
3316 +#define ICU0_IM2_IOSR_FSQM_NULL 0x00000000 */
3317 +/** Read: Interrupt occurred. */
3318 +#define ICU0_IM2_IOSR_FSQM_INTOCC 0x00000800
3319 +/** IQM Interrupt
3320 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3321 +#define ICU0_IM2_IOSR_IQM 0x00000400
3322 +/* Nothing
3323 +#define ICU0_IM2_IOSR_IQM_NULL 0x00000000 */
3324 +/** Read: Interrupt occurred. */
3325 +#define ICU0_IM2_IOSR_IQM_INTOCC 0x00000400
3326 +/** OCTRLG Interrupt
3327 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3328 +#define ICU0_IM2_IOSR_OCTRLG 0x00000200
3329 +/* Nothing
3330 +#define ICU0_IM2_IOSR_OCTRLG_NULL 0x00000000 */
3331 +/** Read: Interrupt occurred. */
3332 +#define ICU0_IM2_IOSR_OCTRLG_INTOCC 0x00000200
3333 +/** OCTRLL 3 Interrupt
3334 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3335 +#define ICU0_IM2_IOSR_OCTRLL3 0x00000080
3336 +/* Nothing
3337 +#define ICU0_IM2_IOSR_OCTRLL3_NULL 0x00000000 */
3338 +/** Read: Interrupt occurred. */
3339 +#define ICU0_IM2_IOSR_OCTRLL3_INTOCC 0x00000080
3340 +/** OCTRLL 2 Interrupt
3341 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3342 +#define ICU0_IM2_IOSR_OCTRLL2 0x00000040
3343 +/* Nothing
3344 +#define ICU0_IM2_IOSR_OCTRLL2_NULL 0x00000000 */
3345 +/** Read: Interrupt occurred. */
3346 +#define ICU0_IM2_IOSR_OCTRLL2_INTOCC 0x00000040
3347 +/** OCTRLL 1 Interrupt
3348 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3349 +#define ICU0_IM2_IOSR_OCTRLL1 0x00000020
3350 +/* Nothing
3351 +#define ICU0_IM2_IOSR_OCTRLL1_NULL 0x00000000 */
3352 +/** Read: Interrupt occurred. */
3353 +#define ICU0_IM2_IOSR_OCTRLL1_INTOCC 0x00000020
3354 +/** OCTRLL 0 Interrupt
3355 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3356 +#define ICU0_IM2_IOSR_OCTRLL0 0x00000010
3357 +/* Nothing
3358 +#define ICU0_IM2_IOSR_OCTRLL0_NULL 0x00000000 */
3359 +/** Read: Interrupt occurred. */
3360 +#define ICU0_IM2_IOSR_OCTRLL0_INTOCC 0x00000010
3361 +/** ICTRLL 3 Interrupt
3362 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3363 +#define ICU0_IM2_IOSR_ICTRLL3 0x00000008
3364 +/* Nothing
3365 +#define ICU0_IM2_IOSR_ICTRLL3_NULL 0x00000000 */
3366 +/** Read: Interrupt occurred. */
3367 +#define ICU0_IM2_IOSR_ICTRLL3_INTOCC 0x00000008
3368 +/** ICTRLL 2 Interrupt
3369 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3370 +#define ICU0_IM2_IOSR_ICTRLL2 0x00000004
3371 +/* Nothing
3372 +#define ICU0_IM2_IOSR_ICTRLL2_NULL 0x00000000 */
3373 +/** Read: Interrupt occurred. */
3374 +#define ICU0_IM2_IOSR_ICTRLL2_INTOCC 0x00000004
3375 +/** ICTRLL 1 Interrupt
3376 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3377 +#define ICU0_IM2_IOSR_ICTRLL1 0x00000002
3378 +/* Nothing
3379 +#define ICU0_IM2_IOSR_ICTRLL1_NULL 0x00000000 */
3380 +/** Read: Interrupt occurred. */
3381 +#define ICU0_IM2_IOSR_ICTRLL1_INTOCC 0x00000002
3382 +/** ICTRLL 0 Interrupt
3383 + Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3384 +#define ICU0_IM2_IOSR_ICTRLL0 0x00000001
3385 +/* Nothing
3386 +#define ICU0_IM2_IOSR_ICTRLL0_NULL 0x00000000 */
3387 +/** Read: Interrupt occurred. */
3388 +#define ICU0_IM2_IOSR_ICTRLL0_INTOCC 0x00000001
3389 +
3390 +/* Fields of "IM2 Interrupt Request Set Register" */
3391 +/** EIM Interrupt
3392 + Software control for the corresponding bit in the IM2_ISR register. */
3393 +#define ICU0_IM2_IRSR_EIM 0x80000000
3394 +/** GTC Upstream Interrupt
3395 + Software control for the corresponding bit in the IM2_ISR register. */
3396 +#define ICU0_IM2_IRSR_GTC_US 0x40000000
3397 +/** GTC Downstream Interrupt
3398 + Software control for the corresponding bit in the IM2_ISR register. */
3399 +#define ICU0_IM2_IRSR_GTC_DS 0x20000000
3400 +/** TBM Interrupt
3401 + Software control for the corresponding bit in the IM2_ISR register. */
3402 +#define ICU0_IM2_IRSR_TBM 0x00400000
3403 +/** Dispatcher Interrupt
3404 + Software control for the corresponding bit in the IM2_ISR register. */
3405 +#define ICU0_IM2_IRSR_DISP 0x00200000
3406 +/** CONFIG Interrupt
3407 + Software control for the corresponding bit in the IM2_ISR register. */
3408 +#define ICU0_IM2_IRSR_CONFIG 0x00100000
3409 +/** CONFIG Break Interrupt
3410 + Software control for the corresponding bit in the IM2_ISR register. */
3411 +#define ICU0_IM2_IRSR_CONFIG_BREAK 0x00080000
3412 +/** OCTRLC Interrupt
3413 + Software control for the corresponding bit in the IM2_ISR register. */
3414 +#define ICU0_IM2_IRSR_OCTRLC 0x00040000
3415 +/** ICTRLC 1 Interrupt
3416 + Software control for the corresponding bit in the IM2_ISR register. */
3417 +#define ICU0_IM2_IRSR_ICTRLC1 0x00020000
3418 +/** ICTRLC 0 Interrupt
3419 + Software control for the corresponding bit in the IM2_ISR register. */
3420 +#define ICU0_IM2_IRSR_ICTRLC0 0x00010000