[lantiq] add lantiq svip support
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.3 / 300-svip_header.patch
1 Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/irq.h
2 ===================================================================
3 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4 +++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/irq.h 2012-07-31 15:46:02.464476159 +0200
5 @@ -0,0 +1,36 @@
6 +/*
7 + * arch/mips/include/asm/mach-lantiq/svip/irq.h
8 + *
9 + * This program is free software; you can redistribute it and/or modify
10 + * it under the terms of the GNU General Public License as published by
11 + * the Free Software Foundation; either version 2 of the License, or
12 + * (at your option) any later version.
13 + *
14 + * This program is distributed in the hope that it will be useful,
15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 + * GNU General Public License for more details.
18 + *
19 + * You should have received a copy of the GNU General Public License
20 + * along with this program; if not, write to the Free Software
21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
22 + *
23 + * Copyright (C) 2010 Lantiq
24 + *
25 + */
26 +
27 +#ifndef __IRQ_H
28 +#define __IRQ_H
29 +
30 +#include <svip_irq.h>
31 +
32 +#define NR_IRQS 264
33 +
34 +#include_next <irq.h>
35 +
36 +/* Functions for EXINT handling */
37 +extern int ifx_enable_external_int(u32 exint, u32 mode);
38 +extern int ifx_disable_external_int(u32 exint);
39 +extern int ifx_external_int_level(u32 exint);
40 +
41 +#endif
42 Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h
43 ===================================================================
44 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
45 +++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h 2012-07-31 15:58:41.312508597 +0200
46 @@ -0,0 +1,71 @@
47 +/*
48 + * This program is free software; you can redistribute it and/or modify it
49 + * under the terms of the GNU General Public License version 2 as published
50 + * by the Free Software Foundation.
51 + *
52 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
53 + */
54 +
55 +#ifndef _LTQ_SVIP_H__
56 +#define _LTQ_SVIP_H__
57 +
58 +#ifdef CONFIG_SOC_SVIP
59 +
60 +#include <lantiq.h>
61 +
62 +/* Chip IDs */
63 +#define SOC_ID_SVIP 0x169
64 +
65 +/* SoC Types */
66 +#define SOC_TYPE_SVIP 0x01
67 +
68 +/* ASC0/1 - serial port */
69 +#define LTQ_ASC0_BASE_ADDR 0x14100100
70 +#define LTQ_ASC1_BASE_ADDR 0x14100200
71 +#define LTQ_ASC_SIZE 0x100
72 +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
73 +
74 +#define LTQ_ASC_TIR(x) (INT_NUM_IM0_IRL0 + (x * 8))
75 +#define LTQ_ASC_RIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 2)
76 +#define LTQ_ASC_EIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 3)
77 +
78 +/* ICU - interrupt control unit */
79 +#define LTQ_ICU_BASE_ADDR 0x14106000
80 +#define LTQ_ICU_BASE_ADDR1 0x14106028
81 +#define LTQ_ICU_BASE_ADDR2 0x1E016000
82 +#define LTQ_ICU_BASE_ADDR3 0x1E016028
83 +#define LTQ_ICU_BASE_ADDR4 0x14106050
84 +#define LTQ_ICU_BASE_ADDR5 0x14106078
85 +#define LTQ_ICU_SIZE 0x100
86 +
87 +/* WDT */
88 +#define LTQ_WDT_BASE_ADDR 0x1F8803F0
89 +#define LTQ_WDT_SIZE 0x10
90 +
91 +/* Status */
92 +#define LTQ_STATUS_BASE_ADDR (KSEG1 + 0x1E000500)
93 +#define LTQ_STATUS_CHIPID ((u32 *)(LTQ_STATUS_BASE_ADDR + 0x000C))
94 +
95 +#define LTQ_EIU_BASE_ADDR 0
96 +
97 +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
98 +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
99 +
100 +extern __iomem void *ltq_ebu_membase;
101 +
102 +extern void ltq_gpio_configure(int port, int pin, bool dirin, bool puen,
103 + bool altsel0, bool altsel1);
104 +extern int ltq_port_get_dir(unsigned int port, unsigned int pin);
105 +extern int ltq_port_get_puden(unsigned int port, unsigned int pin);
106 +extern int ltq_port_get_altsel0(unsigned int port, unsigned int pin);
107 +extern int ltq_port_get_altsel1(unsigned int port, unsigned int pin);
108 +
109 +#define ltq_is_ar9() 0
110 +#define ltq_is_vr9() 0
111 +#define ltq_is_falcon() 0
112 +
113 +#define BS_FLASH 0
114 +#define LTQ_RST_CAUSE_WDTRST 0x2
115 +
116 +#endif /* CONFIG_SOC_SVIP */
117 +#endif /* _LTQ_SVIP_H__ */
118 Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h
119 ===================================================================
120 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
121 +++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h 2012-07-31 15:46:02.468476160 +0200
122 @@ -0,0 +1,35 @@
123 +/*
124 + * This program is free software; you can redistribute it and/or modify
125 + * it under the terms of the GNU General Public License as published by
126 + * the Free Software Foundation; either version 2 of the License, or
127 + * (at your option) any later version.
128 + *
129 + * This program is distributed in the hope that it will be useful,
130 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
131 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
132 + * GNU General Public License for more details.
133 + *
134 + * You should have received a copy of the GNU General Public License
135 + * along with this program; if not, write to the Free Software
136 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
137 + *
138 + * Copyright (C) 2010 Lantiq
139 + */
140 +#ifndef __SVIP_IRQ_H
141 +#define __SVIP_IRQ_H
142 +
143 +#define IM_NUM 6
144 +
145 +#define INT_NUM_IRQ0 8
146 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
147 +#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
148 +#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
149 +#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
150 +#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
151 +#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
152 +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
153 +
154 +#define INT_NUM_IM5_IRL0 (INT_NUM_IRQ0 + 160)
155 +#define MIPS_CPU_TIMER_IRQ (INT_NUM_IM5_IRL0 + 2)
156 +
157 +#endif
158 Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/base_reg.h
159 ===================================================================
160 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
161 +++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/base_reg.h 2012-07-31 15:46:02.468476160 +0200
162 @@ -0,0 +1,56 @@
163 +/******************************************************************************
164 +
165 + Copyright (c) 2007
166 + Infineon Technologies AG
167 + St. Martin Strasse 53; 81669 Munich, Germany
168 +
169 + Any use of this Software is subject to the conclusion of a respective
170 + License Agreement. Without such a License Agreement no rights to the
171 + Software are granted.
172 +
173 + ******************************************************************************/
174 +
175 +#ifndef __BASE_REG_H
176 +#define __BASE_REG_H
177 +
178 +#ifndef KSEG1
179 +#define KSEG1 0xA0000000
180 +#endif
181 +
182 +#define LTQ_EBU_SEG1_BASE (KSEG1 + 0x10000000)
183 +#define LTQ_EBU_SEG2_BASE (KSEG1 + 0x11000000)
184 +#define LTQ_EBU_SEG3_BASE (KSEG1 + 0x12000000)
185 +#define LTQ_EBU_SEG4_BASE (KSEG1 + 0x13000000)
186 +
187 +#define LTQ_ASC0_BASE (KSEG1 + 0x14100100)
188 +#define LTQ_ASC1_BASE (KSEG1 + 0x14100200)
189 +
190 +#define LTQ_SSC0_BASE (0x14100300)
191 +#define LTQ_SSC1_BASE (0x14100400)
192 +
193 +#define LTQ_PORT_P0_BASE (KSEG1 + 0x14100600)
194 +#define LTQ_PORT_P1_BASE (KSEG1 + 0x14108100)
195 +#define LTQ_PORT_P2_BASE (KSEG1 + 0x14100800)
196 +#define LTQ_PORT_P3_BASE (KSEG1 + 0x14100900)
197 +#define LTQ_PORT_P4_BASE (KSEG1 + 0x1E000400)
198 +
199 +#define LTQ_EBU_BASE (KSEG1 + 0x14102000)
200 +#define LTQ_DMA_BASE (KSEG1 + 0x14104000)
201 +
202 +#define LTQ_ICU0_IM3_IM2_BASE (KSEG1 + 0x1E016000)
203 +#define LTQ_ICU0_IM5_IM4_IM1_IM0_BASE (KSEG1 + 0x14106000)
204 +
205 +#define LTQ_ES_BASE (KSEG1 + 0x18000000)
206 +
207 +#define LTQ_SYS0_BASE (KSEG1 + 0x1C000000)
208 +#define LTQ_SYS1_BASE (KSEG1 + 0x1C000800)
209 +#define LTQ_SYS2_BASE (KSEG1 + 0x1E400000)
210 +
211 +#define LTQ_L2_SPRAM_BASE (KSEG1 + 0x1F1E8000)
212 +
213 +#define LTQ_SWINT_BASE (KSEG1 + 0x1E000100)
214 +#define LTQ_MBS_BASE (KSEG1 + 0x1E000200)
215 +
216 +#define LTQ_STATUS_BASE (KSEG1 + 0x1E000500)
217 +
218 +#endif
219 Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h
220 ===================================================================
221 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
222 +++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h 2012-07-31 15:46:02.468476160 +0200
223 @@ -0,0 +1,370 @@
224 +/******************************************************************************
225 +
226 + Copyright (c) 2007
227 + Infineon Technologies AG
228 + St. Martin Strasse 53; 81669 Munich, Germany
229 +
230 + Any use of this Software is subject to the conclusion of a respective
231 + License Agreement. Without such a License Agreement no rights to the
232 + Software are granted.
233 +
234 + ******************************************************************************/
235 +
236 +#ifndef __SYS1_REG_H
237 +#define __SYS1_REG_H
238 +
239 +#define sys1_r32(reg) ltq_r32(&sys1->reg)
240 +#define sys1_w32(val, reg) ltq_w32(val, &sys1->reg)
241 +#define sys1_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys1->reg)
242 +
243 +/** SYS1 register structure */
244 +struct svip_reg_sys1 {
245 + unsigned long clksr; /* 0x0000 */
246 + unsigned long clkenr; /* 0x0004 */
247 + unsigned long clkclr; /* 0x0008 */
248 + unsigned long reserved0[1];
249 + unsigned long l2ccr; /* 0x0010 */
250 + unsigned long fpicr; /* 0x0014 */
251 + unsigned long wdtcr; /* 0x0018 */
252 + unsigned long reserved1[1];
253 + unsigned long cpucr[6]; /* 0x0020 */
254 + unsigned long reserved2[2];
255 + unsigned long rsr; /* 0x0040 */
256 + unsigned long rreqr; /* 0x0044 */
257 + unsigned long rrlsr; /* 0x0048 */
258 + unsigned long rbtr; /* 0x004c */
259 + unsigned long irncr; /* 0x0050 */
260 + unsigned long irnicr; /* 0x0054 */
261 + unsigned long irnen; /* 0x0058 */
262 + unsigned long reserved3[1];
263 + unsigned long cpursr[6]; /* 0x0060 */
264 + unsigned long reserved4[2];
265 + unsigned long cpusrssr[6]; /* 0x0080 */
266 + unsigned long reserved5[2];
267 + unsigned long cpuwrssr[6]; /* 0x00a0 */
268 +};
269 +
270 +/*******************************************************************************
271 + * SYS1 Clock Status Register
272 + ******************************************************************************/
273 +/* (r) Clock Enable for L2C */
274 +#define SYS1_CLKSR_L2C (0x1 << 31)
275 +/* (r) Clock Enable for DDR2 */
276 +#define SYS1_CLKSR_DDR2 (0x1 << 30)
277 +/* (r) Clock Enable for SMI2 */
278 +#define SYS1_CLKSR_SMI2 (0x1 << 29)
279 +/* (r) Clock Enable for SMI1 */
280 +#define SYS1_CLKSR_SMI1 (0x1 << 28)
281 +/* (r) Clock Enable for SMI0 */
282 +#define SYS1_CLKSR_SMI0 (0x1 << 27)
283 +/* (r) Clock Enable for FMI0 */
284 +#define SYS1_CLKSR_FMI0 (0x1 << 26)
285 +/* (r) Clock Enable for PORT0 */
286 +#define SYS1_CLKSR_PORT0 (0x1 << 0)
287 +/* (r) Clock Enable for PCM3 */
288 +#define SYS1_CLKSR_PCM3 (0x1 << 19)
289 +/* (r) Clock Enable for PCM2 */
290 +#define SYS1_CLKSR_PCM2 (0x1 << 18)
291 +/* (r) Clock Enable for PCM1 */
292 +#define SYS1_CLKSR_PCM1 (0x1 << 17)
293 +/* (r) Clock Enable for PCM0 */
294 +#define SYS1_CLKSR_PCM0 (0x1 << 16)
295 +/* (r) Clock Enable for ASC1 */
296 +#define SYS1_CLKSR_ASC1 (0x1 << 15)
297 +/* (r) Clock Enable for ASC0 */
298 +#define SYS1_CLKSR_ASC0 (0x1 << 14)
299 +/* (r) Clock Enable for SSC2 */
300 +#define SYS1_CLKSR_SSC2 (0x1 << 13)
301 +/* (r) Clock Enable for SSC1 */
302 +#define SYS1_CLKSR_SSC1 (0x1 << 12)
303 +/* (r) Clock Enable for SSC0 */
304 +#define SYS1_CLKSR_SSC0 (0x1 << 11)
305 +/* (r) Clock Enable for GPTC */
306 +#define SYS1_CLKSR_GPTC (0x1 << 10)
307 +/* (r) Clock Enable for DMA */
308 +#define SYS1_CLKSR_DMA (0x1 << 9)
309 +/* (r) Clock Enable for FSCT */
310 +#define SYS1_CLKSR_FSCT (0x1 << 8)
311 +/* (r) Clock Enable for ETHSW */
312 +#define SYS1_CLKSR_ETHSW (0x1 << 7)
313 +/* (r) Clock Enable for EBU */
314 +#define SYS1_CLKSR_EBU (0x1 << 6)
315 +/* (r) Clock Enable for TRNG */
316 +#define SYS1_CLKSR_TRNG (0x1 << 5)
317 +/* (r) Clock Enable for DEU */
318 +#define SYS1_CLKSR_DEU (0x1 << 4)
319 +/* (r) Clock Enable for PORT3 */
320 +#define SYS1_CLKSR_PORT3 (0x1 << 3)
321 +/* (r) Clock Enable for PORT2 */
322 +#define SYS1_CLKSR_PORT2 (0x1 << 2)
323 +/* (r) Clock Enable for PORT1 */
324 +#define SYS1_CLKSR_PORT1 (0x1 << 1)
325 +
326 +/*******************************************************************************
327 + * SYS1 Clock Enable Register
328 + ******************************************************************************/
329 +/* (w) Clock Enable Request for L2C */
330 +#define SYS1_CLKENR_L2C (0x1 << 31)
331 +/* (w) Clock Enable Request for DDR2 */
332 +#define SYS1_CLKENR_DDR2 (0x1 << 30)
333 +/* (w) Clock Enable Request for SMI2 */
334 +#define SYS1_CLKENR_SMI2 (0x1 << 29)
335 +/* (w) Clock Enable Request for SMI1 */
336 +#define SYS1_CLKENR_SMI1 (0x1 << 28)
337 +/* (w) Clock Enable Request for SMI0 */
338 +#define SYS1_CLKENR_SMI0 (0x1 << 27)
339 +/* (w) Clock Enable Request for FMI0 */
340 +#define SYS1_CLKENR_FMI0 (0x1 << 26)
341 +/* (w) Clock Enable Request for PORT0 */
342 +#define SYS1_CLKENR_PORT0 (0x1 << 0)
343 +/* (w) Clock Enable Request for PCM3 */
344 +#define SYS1_CLKENR_PCM3 (0x1 << 19)
345 +/* (w) Clock Enable Request for PCM2 */
346 +#define SYS1_CLKENR_PCM2 (0x1 << 18)
347 +/* (w) Clock Enable Request for PCM1 */
348 +#define SYS1_CLKENR_PCM1 (0x1 << 17)
349 +/* (w) Clock Enable Request for PCM0 */
350 +#define SYS1_CLKENR_PCM0 (0x1 << 16)
351 +/* (w) Clock Enable Request for ASC1 */
352 +#define SYS1_CLKENR_ASC1 (0x1 << 15)
353 +/* (w) Clock Enable Request for ASC0 */
354 +#define SYS1_CLKENR_ASC0 (0x1 << 14)
355 +/* (w) Clock Enable Request for SSC2 */
356 +#define SYS1_CLKENR_SSC2 (0x1 << 13)
357 +/* (w) Clock Enable Request for SSC1 */
358 +#define SYS1_CLKENR_SSC1 (0x1 << 12)
359 +/* (w) Clock Enable Request for SSC0 */
360 +#define SYS1_CLKENR_SSC0 (0x1 << 11)
361 +/* (w) Clock Enable Request for GPTC */
362 +#define SYS1_CLKENR_GPTC (0x1 << 10)
363 +/* (w) Clock Enable Request for DMA */
364 +#define SYS1_CLKENR_DMA (0x1 << 9)
365 +/* (w) Clock Enable Request for FSCT */
366 +#define SYS1_CLKENR_FSCT (0x1 << 8)
367 +/* (w) Clock Enable Request for ETHSW */
368 +#define SYS1_CLKENR_ETHSW (0x1 << 7)
369 +/* (w) Clock Enable Request for EBU */
370 +#define SYS1_CLKENR_EBU (0x1 << 6)
371 +/* (w) Clock Enable Request for TRNG */
372 +#define SYS1_CLKENR_TRNG (0x1 << 5)
373 +/* (w) Clock Enable Request for DEU */
374 +#define SYS1_CLKENR_DEU (0x1 << 4)
375 +/* (w) Clock Enable Request for PORT3 */
376 +#define SYS1_CLKENR_PORT3 (0x1 << 3)
377 +/* (w) Clock Enable Request for PORT2 */
378 +#define SYS1_CLKENR_PORT2 (0x1 << 2)
379 +/* (w) Clock Enable Request for PORT1 */
380 +#define SYS1_CLKENR_PORT1 (0x1 << 1)
381 +
382 +/*******************************************************************************
383 + * SYS1 Clock Clear Register
384 + ******************************************************************************/
385 +/* (w) Clock Disable Request for L2C */
386 +#define SYS1_CLKCLR_L2C (0x1 << 31)
387 +/* (w) Clock Disable Request for DDR2 */
388 +#define SYS1_CLKCLR_DDR2 (0x1 << 30)
389 +/* (w) Clock Disable Request for SMI2 */
390 +#define SYS1_CLKCLR_SMI2 (0x1 << 29)
391 +/* (w) Clock Disable Request for SMI1 */
392 +#define SYS1_CLKCLR_SMI1 (0x1 << 28)
393 +/* (w) Clock Disable Request for SMI0 */
394 +#define SYS1_CLKCLR_SMI0 (0x1 << 27)
395 +/* (w) Clock Disable Request for FMI0 */
396 +#define SYS1_CLKCLR_FMI0 (0x1 << 26)
397 +/* (w) Clock Disable Request for PORT0 */
398 +#define SYS1_CLKCLR_PORT0 (0x1 << 0)
399 +/* (w) Clock Disable Request for PCM3 */
400 +#define SYS1_CLKCLR_PCM3 (0x1 << 19)
401 +/* (w) Clock Disable Request for PCM2 */
402 +#define SYS1_CLKCLR_PCM2 (0x1 << 18)
403 +/* (w) Clock Disable Request for PCM1 */
404 +#define SYS1_CLKCLR_PCM1 (0x1 << 17)
405 +/* (w) Clock Disable Request for PCM0 */
406 +#define SYS1_CLKCLR_PCM0 (0x1 << 16)
407 +/* (w) Clock Disable Request for ASC1 */
408 +#define SYS1_CLKCLR_ASC1 (0x1 << 15)
409 +/* (w) Clock Disable Request for ASC0 */
410 +#define SYS1_CLKCLR_ASC0 (0x1 << 14)
411 +/* (w) Clock Disable Request for SSC2 */
412 +#define SYS1_CLKCLR_SSC2 (0x1 << 13)
413 +/* (w) Clock Disable Request for SSC1 */
414 +#define SYS1_CLKCLR_SSC1 (0x1 << 12)
415 +/* (w) Clock Disable Request for SSC0 */
416 +#define SYS1_CLKCLR_SSC0 (0x1 << 11)
417 +/* (w) Clock Disable Request for GPTC */
418 +#define SYS1_CLKCLR_GPTC (0x1 << 10)
419 +/* (w) Clock Disable Request for DMA */
420 +#define SYS1_CLKCLR_DMA (0x1 << 9)
421 +/* (w) Clock Disable Request for FSCT */
422 +#define SYS1_CLKCLR_FSCT (0x1 << 8)
423 +/* (w) Clock Disable Request for ETHSW */
424 +#define SYS1_CLKCLR_ETHSW (0x1 << 7)
425 +/* (w) Clock Disable Request for EBU */
426 +#define SYS1_CLKCLR_EBU (0x1 << 6)
427 +/* (w) Clock Disable Request for TRNG */
428 +#define SYS1_CLKCLR_TRNG (0x1 << 5)
429 +/* (w) Clock Disable Request for DEU */
430 +#define SYS1_CLKCLR_DEU (0x1 << 4)
431 +/* (w) Clock Disable Request for PORT3 */
432 +#define SYS1_CLKCLR_PORT3 (0x1 << 3)
433 +/* (w) Clock Disable Request for PORT2 */
434 +#define SYS1_CLKCLR_PORT2 (0x1 << 2)
435 +/* (w) Clock Disable Request for PORT1 */
436 +#define SYS1_CLKCLR_PORT1 (0x1 << 1)
437 +
438 +/*******************************************************************************
439 + * SYS1 FPI Control Register
440 + ******************************************************************************/
441 +
442 +/* FPI Bus Clock divider (0) */
443 +#define SYS1_FPICR_FPIDIV (0x1)
444 +#define SYS1_FPICR_FPIDIV_VAL(val) (((val) & 0x1) << 0)
445 +#define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1)
446 +#define SYS1_FPICR_FPIDIV_SET(reg,val) (reg) = ((reg & ~SYS1_FPICR_FPIDIV) | (((val) & 0x1) << 0))
447 +
448 +/*******************************************************************************
449 + * SYS1 Clock Control Register for CPUn
450 + ******************************************************************************/
451 +
452 +/* Enable bit for clock of CPUn (1) */
453 +#define SYS1_CPUCR_CPUCLKEN (0x1 << 1)
454 +#define SYS1_CPUCR_CPUCLKEN_VAL(val) (((val) & 0x1) << 1)
455 +#define SYS1_CPUCR_CPUCLKEN_GET(val) ((((val) & SYS1_CPUCR_CPUCLKEN) >> 1) & 0x1)
456 +#define SYS1_CPUCR_CPUCLKEN_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUCLKEN) | (((val) & 0x1) << 1))
457 +/* Divider factor for clock of CPUn (0) */
458 +#define SYS1_CPUCR_CPUDIV (0x1)
459 +#define SYS1_CPUCR_CPUDIV_VAL(val) (((val) & 0x1) << 0)
460 +#define SYS1_CPUCR_CPUDIV_GET(val) ((((val) & SYS1_CPUCR_CPUDIV) >> 0) & 0x1)
461 +#define SYS1_CPUCR_CPUDIV_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUDIV) | (((val) & 0x1) << 0))
462 +
463 +/*******************************************************************************
464 + * SYS1 Reset Request Register
465 + ******************************************************************************/
466 +
467 +/* HRSTOUT Reset Request (18) */
468 +#define SYS1_RREQ_HRSTOUT (0x1 << 18)
469 +#define SYS1_RREQ_HRSTOUT_VAL(val) (((val) & 0x1) << 18)
470 +#define SYS1_RREQ_HRSTOUT_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_HRSTOUT) | (((val) & 1) << 18))
471 + /* FBS0 Reset Request (17) */
472 +#define SYS1_RREQ_FBS0 (0x1 << 17)
473 +#define SYS1_RREQ_FBS0_VAL(val) (((val) & 0x1) << 17)
474 +#define SYS1_RREQ_FBS0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_FBS0) | (((val) & 1) << 17))
475 + /* SUBSYS Reset Request (16) */
476 +#define SYS1_RREQ_SUBSYS (0x1 << 16)
477 +#define SYS1_RREQ_SUBSYS_VAL(val) (((val) & 0x1) << 16)
478 +#define SYS1_RREQ_SUBSYS_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_SUBSYS) | (((val) & 1) << 16))
479 + /* Watchdog5 Reset Request (13) */
480 +#define SYS1_RREQ_WDT5 (0x1 << 13)
481 +#define SYS1_RREQ_WDT5_VAL(val) (((val) & 0x1) << 13)
482 +#define SYS1_RREQ_WDT5_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT5) | (((val) & 1) << 13))
483 + /* Watchdog4 Reset Request (12) */
484 +#define SYS1_RREQ_WDT4 (0x1 << 12)
485 +#define SYS1_RREQ_WDT4_VAL(val) (((val) & 0x1) << 12)
486 +#define SYS1_RREQ_WDT4_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT4) | (((val) & 1) << 12))
487 + /* Watchdog3 Reset Request (11) */
488 +#define SYS1_RREQ_WDT3 (0x1 << 11)
489 +#define SYS1_RREQ_WDT3_VAL(val) (((val) & 0x1) << 11)
490 +#define SYS1_RREQ_WDT3_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT3) | (((val) & 1) << 11))
491 + /* Watchdog2 Reset Request (10) */
492 +#define SYS1_RREQ_WDT2 (0x1 << 10)
493 +#define SYS1_RREQ_WDT2_VAL(val) (((val) & 0x1) << 10)
494 +#define SYS1_RREQ_WDT2_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT2) | (((val) & 1) << 10))
495 + /* Watchdog1 Reset Request (9) */
496 +#define SYS1_RREQ_WDT1 (0x1 << 9)
497 +#define SYS1_RREQ_WDT1_VAL(val) (((val) & 0x1) << 9)
498 +#define SYS1_RREQ_WDT1_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT1) | (((val) & 1) << 9))
499 + /* Watchdog0 Reset Request (8) */
500 +#define SYS1_RREQ_WDT0 (0x1 << 8)
501 +#define SYS1_RREQ_WDT0_VAL(val) (((val) & 0x1) << 8)
502 +#define SYS1_RREQ_WDT0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT0) | (((val) & 1) << 8))
503 + /* CPU5 Reset Request (5) */
504 +#define SYS1_RREQ_CPU5 (0x1 << 5)
505 +#define SYS1_RREQ_CPU5_VAL(val) (((val) & 0x1) << 5)
506 +#define SYS1_RREQ_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU5) | (((val) & 1) << 5))
507 + /* CPU4 Reset Request (4) */
508 +#define SYS1_RREQ_CPU4 (0x1 << 4)
509 +#define SYS1_RREQ_CPU4_VAL(val) (((val) & 0x1) << 4)
510 +#define SYS1_RREQ_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU4) | (((val) & 1) << 4))
511 + /* CPU3 Reset Request (3) */
512 +#define SYS1_RREQ_CPU3 (0x1 << 3)
513 +#define SYS1_RREQ_CPU3_VAL(val) (((val) & 0x1) << 3)
514 +#define SYS1_RREQ_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU3) | (((val) & 1) << 3))
515 + /* CPU2 Reset Request (2) */
516 +#define SYS1_RREQ_CPU2 (0x1 << 2)
517 +#define SYS1_RREQ_CPU2_VAL(val) (((val) & 0x1) << 2)
518 +#define SYS1_RREQ_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU2) | (((val) & 1) << 2))
519 + /* CPU1 Reset Request (1) */
520 +#define SYS1_RREQ_CPU1 (0x1 << 1)
521 +#define SYS1_RREQ_CPU1_VAL(val) (((val) & 0x1) << 1)
522 +#define SYS1_RREQ_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU1) | (((val) & 1) << 1))
523 +/* CPU0 Reset Request (0) */
524 +#define SYS1_RREQ_CPU0 (0x1)
525 +#define SYS1_RREQ_CPU0_VAL(val) (((val) & 0x1) << 0)
526 +#define SYS1_RREQ_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU0) | (((val) & 1) << 0))
527 +
528 +/*******************************************************************************
529 + * SYS1 Reset Release Register
530 + ******************************************************************************/
531 +
532 +/* HRSTOUT Reset Release (18) */
533 +#define SYS1_RRLSR_HRSTOUT (0x1 << 18)
534 +#define SYS1_RRLSR_HRSTOUT_VAL(val) (((val) & 0x1) << 18)
535 +#define SYS1_RRLSR_HRSTOUT_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_HRSTOUT) | (((val) & 1) << 18))
536 +/* FBS0 Reset Release (17) */
537 +#define SYS1_RRLSR_FBS0 (0x1 << 17)
538 +#define SYS1_RRLSR_FBS0_VAL(val) (((val) & 0x1) << 17)
539 +#define SYS1_RRLSR_FBS0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_FBS0) | (((val) & 1) << 17))
540 +/* SUBSYS Reset Release (16) */
541 +#define SYS1_RRLSR_SUBSYS (0x1 << 16)
542 +#define SYS1_RRLSR_SUBSYS_VAL(val) (((val) & 0x1) << 16)
543 +#define SYS1_RRLSR_SUBSYS_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_SUBSYS) | (((val) & 1) << 16))
544 +/* Watchdog5 Reset Release (13) */
545 +#define SYS1_RRLSR_WDT5 (0x1 << 13)
546 +#define SYS1_RRLSR_WDT5_VAL(val) (((val) & 0x1) << 13)
547 +#define SYS1_RRLSR_WDT5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT5) | (((val) & 1) << 13))
548 +/* Watchdog4 Reset Release (12) */
549 +#define SYS1_RRLSR_WDT4 (0x1 << 12)
550 +#define SYS1_RRLSR_WDT4_VAL(val) (((val) & 0x1) << 12)
551 +#define SYS1_RRLSR_WDT4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT4) | (((val) & 1) << 12))
552 +/* Watchdog3 Reset Release (11) */
553 +#define SYS1_RRLSR_WDT3 (0x1 << 11)
554 +#define SYS1_RRLSR_WDT3_VAL(val) (((val) & 0x1) << 11)
555 +#define SYS1_RRLSR_WDT3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT3) | (((val) & 1) << 11))
556 +/* Watchdog2 Reset Release (10) */
557 +#define SYS1_RRLSR_WDT2 (0x1 << 10)
558 +#define SYS1_RRLSR_WDT2_VAL(val) (((val) & 0x1) << 10)
559 +#define SYS1_RRLSR_WDT2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT2) | (((val) & 1) << 10))
560 +/* Watchdog1 Reset Release (9) */
561 +#define SYS1_RRLSR_WDT1 (0x1 << 9)
562 +#define SYS1_RRLSR_WDT1_VAL(val) (((val) & 0x1) << 9)
563 +#define SYS1_RRLSR_WDT1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT1) | (((val) & 1) << 9))
564 +/* Watchdog0 Reset Release (8) */
565 +#define SYS1_RRLSR_WDT0 (0x1 << 8)
566 +#define SYS1_RRLSR_WDT0_VAL(val) (((val) & 0x1) << 8)
567 +#define SYS1_RRLSR_WDT0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT0) | (((val) & 1) << 8))
568 +/* CPU5 Reset Release (5) */
569 +#define SYS1_RRLSR_CPU5 (0x1 << 5)
570 +#define SYS1_RRLSR_CPU5_VAL(val) (((val) & 0x1) << 5)
571 +#define SYS1_RRLSR_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU5) | (((val) & 1) << 5))
572 +/* CPU4 Reset Release (4) */
573 +#define SYS1_RRLSR_CPU4 (0x1 << 4)
574 +#define SYS1_RRLSR_CPU4_VAL(val) (((val) & 0x1) << 4)
575 +#define SYS1_RRLSR_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU4) | (((val) & 1) << 4))
576 +/* CPU3 Reset Release (3) */
577 +#define SYS1_RRLSR_CPU3 (0x1 << 3)
578 +#define SYS1_RRLSR_CPU3_VAL(val) (((val) & 0x1) << 3)
579 +#define SYS1_RRLSR_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU3) | (((val) & 1) << 3))
580 +/* CPU2 Reset Release (2) */
581 +#define SYS1_RRLSR_CPU2 (0x1 << 2)
582 +#define SYS1_RRLSR_CPU2_VAL(val) (((val) & 0x1) << 2)
583 +#define SYS1_RRLSR_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU2) | (((val) & 1) << 2))
584 +/* CPU1 Reset Release (1) */
585 +#define SYS1_RRLSR_CPU1 (0x1 << 1)
586 +#define SYS1_RRLSR_CPU1_VAL(val) (((val) & 0x1) << 1)
587 +#define SYS1_RRLSR_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU1) | (((val) & 1) << 1))
588 +/* CPU0 Reset Release (0) */
589 +#define SYS1_RRLSR_CPU0 (0x1)
590 +#define SYS1_RRLSR_CPU0_VAL(val) (((val) & 0x1) << 0)
591 +#define SYS1_RRLSR_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU0) | (((val) & 1) << 0))
592 +
593 +#endif
594 Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/es_reg.h
595 ===================================================================
596 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
597 +++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/es_reg.h 2012-07-31 15:46:02.476476158 +0200
598 @@ -0,0 +1,2098 @@
599 +/******************************************************************************
600 +
601 + Copyright (c) 2007
602 + Infineon Technologies AG
603 + St. Martin Strasse 53; 81669 Munich, Germany
604 +
605 + Any use of this Software is subject to the conclusion of a respective
606 + License Agreement. Without such a License Agreement no rights to the
607 + Software are granted.
608 +
609 + ******************************************************************************/
610 +
611 +#ifndef __ES_REG_H
612 +#define __ES_REG_H
613 +
614 +#define es_r32(reg) ltq_r32(&es->reg)
615 +#define es_w32(val, reg) ltq_w32(val, &es->reg)
616 +#define es_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &es->reg)
617 +
618 +/** ES register structure */
619 +struct svip_reg_es {
620 + volatile unsigned long ps; /* 0x0000 */
621 + volatile unsigned long p0_ctl; /* 0x0004 */
622 + volatile unsigned long p1_ctl; /* 0x0008 */
623 + volatile unsigned long p2_ctl; /* 0x000C */
624 + volatile unsigned long p0_vlan; /* 0x0010 */
625 + volatile unsigned long p1_vlan; /* 0x0014 */
626 + volatile unsigned long p2_vlan; /* 0x0018 */
627 + volatile unsigned long reserved1[1]; /* 0x001C */
628 + volatile unsigned long p0_inctl; /* 0x0020 */
629 + volatile unsigned long p1_inctl; /* 0x0024 */
630 + volatile unsigned long p2_inctl; /* 0x0028 */
631 + volatile unsigned long reserved2[1]; /* 0x002C */
632 + volatile unsigned long p0_ecs_q32; /* 0x0030 */
633 + volatile unsigned long p0_ecs_q10; /* 0x0034 */
634 + volatile unsigned long p0_ecw_q32; /* 0x0038 */
635 + volatile unsigned long p0_ecw_q10; /* 0x003C */
636 + volatile unsigned long p1_ecs_q32; /* 0x0040 */
637 + volatile unsigned long p1_ecs_q10; /* 0x0044 */
638 + volatile unsigned long p1_ecw_q32; /* 0x0048 */
639 + volatile unsigned long p1_ecw_q10; /* 0x004C */
640 + volatile unsigned long p2_ecs_q32; /* 0x0050 */
641 + volatile unsigned long p2_ecs_q10; /* 0x0054 */
642 + volatile unsigned long p2_ecw_q32; /* 0x0058 */
643 + volatile unsigned long p2_ecw_q10; /* 0x005C */
644 + volatile unsigned long int_ena; /* 0x0060 */
645 + volatile unsigned long int_st; /* 0x0064 */
646 + volatile unsigned long sw_gctl0; /* 0x0068 */
647 + volatile unsigned long sw_gctl1; /* 0x006C */
648 + volatile unsigned long arp; /* 0x0070 */
649 + volatile unsigned long strm_ctl; /* 0x0074 */
650 + volatile unsigned long rgmii_ctl; /* 0x0078 */
651 + volatile unsigned long prt_1p; /* 0x007C */
652 + volatile unsigned long gbkt_szbs; /* 0x0080 */
653 + volatile unsigned long gbkt_szebs; /* 0x0084 */
654 + volatile unsigned long bf_th; /* 0x0088 */
655 + volatile unsigned long pmac_hd_ctl; /* 0x008C */
656 + volatile unsigned long pmac_sa1; /* 0x0090 */
657 + volatile unsigned long pmac_sa2; /* 0x0094 */
658 + volatile unsigned long pmac_da1; /* 0x0098 */
659 + volatile unsigned long pmac_da2; /* 0x009C */
660 + volatile unsigned long pmac_vlan; /* 0x00A0 */
661 + volatile unsigned long pmac_tx_ipg; /* 0x00A4 */
662 + volatile unsigned long pmac_rx_ipg; /* 0x00A8 */
663 + volatile unsigned long adr_tb_ctl0; /* 0x00AC */
664 + volatile unsigned long adr_tb_ctl1; /* 0x00B0 */
665 + volatile unsigned long adr_tb_ctl2; /* 0x00B4 */
666 + volatile unsigned long adr_tb_st0; /* 0x00B8 */
667 + volatile unsigned long adr_tb_st1; /* 0x00BC */
668 + volatile unsigned long adr_tb_st2; /* 0x00C0 */
669 + volatile unsigned long rmon_ctl; /* 0x00C4 */
670 + volatile unsigned long rmon_st; /* 0x00C8 */
671 + volatile unsigned long mdio_ctl; /* 0x00CC */
672 + volatile unsigned long mdio_data; /* 0x00D0 */
673 + volatile unsigned long tp_flt_act; /* 0x00D4 */
674 + volatile unsigned long prtcl_flt_act; /* 0x00D8 */
675 + volatile unsigned long reserved4[9]; /* 0xdc */
676 + volatile unsigned long vlan_flt0; /* 0x0100 */
677 + volatile unsigned long vlan_flt1; /* 0x0104 */
678 + volatile unsigned long vlan_flt2; /* 0x0108 */
679 + volatile unsigned long vlan_flt3; /* 0x010C */
680 + volatile unsigned long vlan_flt4; /* 0x0110 */
681 + volatile unsigned long vlan_flt5; /* 0x0114 */
682 + volatile unsigned long vlan_flt6; /* 0x0118 */
683 + volatile unsigned long vlan_flt7; /* 0x011C */
684 + volatile unsigned long vlan_flt8; /* 0x0120 */
685 + volatile unsigned long vlan_flt9; /* 0x0124 */
686 + volatile unsigned long vlan_flt10; /* 0x0128 */
687 + volatile unsigned long vlan_flt11; /* 0x012C */
688 + volatile unsigned long vlan_flt12; /* 0x0130 */
689 + volatile unsigned long vlan_flt13; /* 0x0134 */
690 + volatile unsigned long vlan_flt14; /* 0x0138 */
691 + volatile unsigned long vlan_flt15; /* 0x013C */
692 + volatile unsigned long tp_flt10; /* 0x0140 */
693 + volatile unsigned long tp_flt32; /* 0x0144 */
694 + volatile unsigned long tp_flt54; /* 0x0148 */
695 + volatile unsigned long tp_flt76; /* 0x014C */
696 + volatile unsigned long dfsrv_map0; /* 0x0150 */
697 + volatile unsigned long dfsrv_map1; /* 0x0154 */
698 + volatile unsigned long dfsrv_map2; /* 0x0158 */
699 + volatile unsigned long dfsrv_map3; /* 0x015C */
700 + volatile unsigned long tcp_pf0; /* 0x0160 */
701 + volatile unsigned long tcp_pf1; /* 0x0164 */
702 + volatile unsigned long tcp_pf2; /* 0x0168 */
703 + volatile unsigned long tcp_pf3; /* 0x016C */
704 + volatile unsigned long tcp_pf4; /* 0x0170 */
705 + volatile unsigned long tcp_pf5; /* 0x0174 */
706 + volatile unsigned long tcp_pf6; /* 0x0178 */
707 + volatile unsigned long tcp_pf7; /* 0x017C */
708 + volatile unsigned long ra_03_00; /* 0x0180 */
709 + volatile unsigned long ra_07_04; /* 0x0184 */
710 + volatile unsigned long ra_0b_08; /* 0x0188 */
711 + volatile unsigned long ra_0f_0c; /* 0x018C */
712 + volatile unsigned long ra_13_10; /* 0x0190 */
713 + volatile unsigned long ra_17_14; /* 0x0194 */
714 + volatile unsigned long ra_1b_18; /* 0x0198 */
715 + volatile unsigned long ra_1f_1c; /* 0x019C */
716 + volatile unsigned long ra_23_20; /* 0x01A0 */
717 + volatile unsigned long ra_27_24; /* 0x01A4 */
718 + volatile unsigned long ra_2b_28; /* 0x01A8 */
719 + volatile unsigned long ra_2f_2c; /* 0x01AC */
720 + volatile unsigned long prtcl_f0; /* 0x01B0 */
721 + volatile unsigned long prtcl_f1; /* 0x01B4 */
722 +};
723 +
724 +/*******************************************************************************
725 + * ES
726 + ******************************************************************************/
727 +#define LTQ_ES_PS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0000))
728 +#define LTQ_ES_P0_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0004))
729 +#define LTQ_ES_P1_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0008))
730 +#define LTQ_ES_P2_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x000C))
731 +#define LTQ_ES_P0_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010))
732 +#define LTQ_ES_P1_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0014))
733 +#define LTQ_ES_P2_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010))
734 +#define LTQ_ES_P0_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0020))
735 +#define LTQ_ES_P1_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0024))
736 +#define LTQ_ES_P2_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0028))
737 +#define LTQ_ES_P0_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030))
738 +#define LTQ_ES_P0_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034))
739 +#define LTQ_ES_P0_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038))
740 +#define LTQ_ES_P0_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C))
741 +#define LTQ_ES_P1_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030))
742 +#define LTQ_ES_P1_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034))
743 +#define LTQ_ES_P1_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038))
744 +#define LTQ_ES_P1_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C))
745 +#define LTQ_ES_P2_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030))
746 +#define LTQ_ES_P2_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034))
747 +#define LTQ_ES_P2_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038))
748 +#define LTQ_ES_P2_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C))
749 +#define LTQ_ES_INT_ENA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0060))
750 +#define LTQ_ES_INT_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0064))
751 +#define LTQ_ES_SW_GCTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0068))
752 +#define LTQ_ES_SW_GCTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x006C))
753 +#define LTQ_ES_ARP_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0070))
754 +#define LTQ_ES_STRM_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0074))
755 +#define LTQ_ES_RGMII_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0078))
756 +#define LTQ_ES_PRT_1P_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x007C))
757 +#define LTQ_ES_GBKT_SZBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0080))
758 +#define LTQ_ES_GBKT_SZEBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0084))
759 +#define LTQ_ES_BF_TH_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0088))
760 +#define LTQ_ES_PMAC_HD_CTL ((volatile unsigned int*)(LTQ_ES_BASE + 0x008C))
761 +#define LTQ_ES_PMAC_SA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0090))
762 +#define LTQ_ES_PMAC_SA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0094))
763 +#define LTQ_ES_PMAC_DA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0098))
764 +#define LTQ_ES_PMAC_DA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x009C))
765 +#define LTQ_ES_PMAC_VLAN ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A0))
766 +#define LTQ_ES_PMAC_TX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A4))
767 +#define LTQ_ES_PMAC_RX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A8))
768 +#define LTQ_ES_ADR_TB_CTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00AC))
769 +#define LTQ_ES_ADR_TB_CTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B0))
770 +#define LTQ_ES_ADR_TB_CTL2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B4))
771 +#define LTQ_ES_ADR_TB_ST0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B8))
772 +#define LTQ_ES_ADR_TB_ST1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00BC))
773 +#define LTQ_ES_ADR_TB_ST2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C0))
774 +#define LTQ_ES_RMON_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C4))
775 +#define LTQ_ES_RMON_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C8))
776 +#define LTQ_ES_MDIO_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00CC))
777 +#define LTQ_ES_MDIO_DATA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D0))
778 +#define LTQ_ES_TP_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D4))
779 +#define LTQ_ES_PRTCL_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D8))
780 +#define LTQ_ES_VLAN_FLT0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0100))
781 +#define LTQ_ES_VLAN_FLT1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0104))
782 +#define LTQ_ES_VLAN_FLT2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0108))
783 +#define LTQ_ES_VLAN_FLT3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x010C))
784 +#define LTQ_ES_VLAN_FLT4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0110))
785 +#define LTQ_ES_VLAN_FLT5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0114))
786 +#define LTQ_ES_VLAN_FLT6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0118))
787 +#define LTQ_ES_VLAN_FLT7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x011C))
788 +#define LTQ_ES_VLAN_FLT8_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0120))
789 +#define LTQ_ES_VLAN_FLT9_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0124))
790 +#define LTQ_ES_VLAN_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0128))
791 +#define LTQ_ES_VLAN_FLT11_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x012C))
792 +#define LTQ_ES_VLAN_FLT12_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0130))
793 +#define LTQ_ES_VLAN_FLT13_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0134))
794 +#define LTQ_ES_VLAN_FLT14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0138))
795 +#define LTQ_ES_VLAN_FLT15_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x013C))
796 +#define LTQ_ES_TP_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0140))
797 +#define LTQ_ES_TP_FLT32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0144))
798 +#define LTQ_ES_TP_FLT54_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0148))
799 +#define LTQ_ES_TP_FLT76_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x014C))
800 +#define LTQ_ES_DFSRV_MAP0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0150))
801 +#define LTQ_ES_DFSRV_MAP1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0154))
802 +#define LTQ_ES_DFSRV_MAP2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0158))
803 +#define LTQ_ES_DFSRV_MAP3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x015C))
804 +#define LTQ_ES_TCP_PF0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0160))
805 +#define LTQ_ES_TCP_PF1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0164))
806 +#define LTQ_ES_TCP_PF2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0168))
807 +#define LTQ_ES_TCP_PF3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x016C))
808 +#define LTQ_ES_TCP_PF4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0170))
809 +#define LTQ_ES_TCP_PF5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0174))
810 +#define LTQ_ES_TCP_PF6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0178))
811 +#define LTQ_ES_TCP_PF7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x017C))
812 +#define LTQ_ES_RA_03_00_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0180))
813 +#define LTQ_ES_RA_07_04_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0184))
814 +#define LTQ_ES_RA_0B_08_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0188))
815 +#define LTQ_ES_RA_0F_0C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x018C))
816 +#define LTQ_ES_RA_13_10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0190))
817 +#define LTQ_ES_RA_17_14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0194))
818 +#define LTQ_ES_RA_1B_18_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0198))
819 +#define LTQ_ES_RA_1F_1C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x019C))
820 +#define LTQ_ES_RA_23_20_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A0))
821 +#define LTQ_ES_RA_27_24_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A4))
822 +#define LTQ_ES_RA_2B_28_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A8))
823 +#define LTQ_ES_RA_2F_2C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01AC))
824 +#define LTQ_ES_PRTCL_F0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B0))
825 +#define LTQ_ES_PRTCL_F1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B4))
826 +
827 +/*******************************************************************************
828 + * Port Status Register
829 + ******************************************************************************/
830 +
831 +/* Port 1 Flow Control Status (12) */
832 +#define LTQ_ES_PS_REG_P1FCS (0x1 << 12)
833 +#define LTQ_ES_PS_REG_P1FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P1FCS) >> 12) & 0x1)
834 +/* Port 1 Duplex Status (11) */
835 +#define LTQ_ES_PS_REG_P1DS (0x1 << 11)
836 +#define LTQ_ES_PS_REG_P1DS_GET(val) ((((val) & LTQ_ES_PS_REG_P1DS) >> 11) & 0x1)
837 +/* Port 1 Speed High Status (10) */
838 +#define LTQ_ES_PS_REG_P1SHS (0x1 << 10)
839 +#define LTQ_ES_PS_REG_P1SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SHS) >> 10) & 0x1)
840 +/* Port 1 Speed Status (9) */
841 +#define LTQ_ES_PS_REG_P1SS (0x1 << 9)
842 +#define LTQ_ES_PS_REG_P1SS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SS) >> 9) & 0x1)
843 +/* Port 1 Link Status (8) */
844 +#define LTQ_ES_PS_REG_P1LS (0x1 << 8)
845 +#define LTQ_ES_PS_REG_P1LS_GET(val) ((((val) & LTQ_ES_PS_REG_P1LS) >> 8) & 0x1)
846 +/* Port 0 Flow Control Status (4) */
847 +#define LTQ_ES_PS_REG_P0FCS (0x1 << 4)
848 +#define LTQ_ES_PS_REG_P0FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P0FCS) >> 4) & 0x1)
849 +/* Port 0 Duplex Status (3) */
850 +#define LTQ_ES_PS_REG_P0DS (0x1 << 3)
851 +#define LTQ_ES_PS_REG_P0DS_GET(val) ((((val) & LTQ_ES_PS_REG_P0DS) >> 3) & 0x1)
852 +/* Port 0 Speed High Status (2) */
853 +#define LTQ_ES_PS_REG_P0SHS (0x1 << 2)
854 +#define LTQ_ES_PS_REG_P0SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SHS) >> 2) & 0x1)
855 +/* Port 0 Speed Status (1) */
856 +#define LTQ_ES_PS_REG_P0SS (0x1 << 1)
857 +#define LTQ_ES_PS_REG_P0SS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SS) >> 1) & 0x1)
858 +/* Port 0 Link Status (0) */
859 +#define LTQ_ES_PS_REG_P0LS (0x1)
860 +#define LTQ_ES_PS_REG_P0LS_GET(val) ((((val) & LTQ_ES_PS_REG_P0LS) >> 0) & 0x1)
861 +
862 +/*******************************************************************************
863 + * P0 Control Register
864 + ******************************************************************************/
865 +
866 +/* STP/RSTP port state (31:30) */
867 +#define LTQ_ES_P0_CTL_REG_SPS (0x3 << 30)
868 +#define LTQ_ES_P0_CTL_REG_SPS_VAL(val) (((val) & 0x3) << 30)
869 +#define LTQ_ES_P0_CTL_REG_SPS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPS) >> 30) & 0x3)
870 +#define LTQ_ES_P0_CTL_REG_SPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPS) | (((val) & 0x3) << 30))
871 +/* TCP/UDP PRIEN (29) */
872 +#define LTQ_ES_P0_CTL_REG_TCPE (0x1 << 29)
873 +#define LTQ_ES_P0_CTL_REG_TCPE_VAL(val) (((val) & 0x1) << 29)
874 +#define LTQ_ES_P0_CTL_REG_TCPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TCPE) >> 29) & 0x1)
875 +#define LTQ_ES_P0_CTL_REG_TCPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TCPE) | (((val) & 0x1) << 29))
876 +/* IP over TCP/UDP (28) */
877 +#define LTQ_ES_P0_CTL_REG_IPOVTU (0x1 << 28)
878 +#define LTQ_ES_P0_CTL_REG_IPOVTU_VAL(val) (((val) & 0x1) << 28)
879 +#define LTQ_ES_P0_CTL_REG_IPOVTU_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPOVTU) >> 28) & 0x1)
880 +#define LTQ_ES_P0_CTL_REG_IPOVTU_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPOVTU) | (((val) & 0x1) << 28))
881 +/* VLAN Priority Enable (27) */
882 +#define LTQ_ES_P0_CTL_REG_VPE (0x1 << 27)
883 +#define LTQ_ES_P0_CTL_REG_VPE_VAL(val) (((val) & 0x1) << 27)
884 +#define LTQ_ES_P0_CTL_REG_VPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_VPE) >> 27) & 0x1)
885 +#define LTQ_ES_P0_CTL_REG_VPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_VPE) | (((val) & 0x1) << 27))
886 +/* Service Priority Enable (26) */
887 +#define LTQ_ES_P0_CTL_REG_SPE (0x1 << 26)
888 +#define LTQ_ES_P0_CTL_REG_SPE_VAL(val) (((val) & 0x1) << 26)
889 +#define LTQ_ES_P0_CTL_REG_SPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPE) >> 26) & 0x1)
890 +#define LTQ_ES_P0_CTL_REG_SPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPE) | (((val) & 0x1) << 26))
891 +/* IP over VLAN PRI (25) */
892 +#define LTQ_ES_P0_CTL_REG_IPVLAN (0x1 << 25)
893 +#define LTQ_ES_P0_CTL_REG_IPVLAN_VAL(val) (((val) & 0x1) << 25)
894 +#define LTQ_ES_P0_CTL_REG_IPVLAN_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPVLAN) >> 25) & 0x1)
895 +#define LTQ_ES_P0_CTL_REG_IPVLAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPVLAN) | (((val) & 0x1) << 25))
896 +/* Ether Type Priority Enable (24) */
897 +#define LTQ_ES_P0_CTL_REG_TPE (0x1 << 24)
898 +#define LTQ_ES_P0_CTL_REG_TPE_VAL(val) (((val) & 0x1) << 24)
899 +#define LTQ_ES_P0_CTL_REG_TPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TPE) >> 24) & 0x1)
900 +#define LTQ_ES_P0_CTL_REG_TPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TPE) | (((val) & 0x1) << 24))
901 +/* Force Link Up (18) */
902 +#define LTQ_ES_P0_CTL_REG_FLP (0x1 << 18)
903 +#define LTQ_ES_P0_CTL_REG_FLP_VAL(val) (((val) & 0x1) << 18)
904 +#define LTQ_ES_P0_CTL_REG_FLP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLP) >> 18) & 0x1)
905 +#define LTQ_ES_P0_CTL_REG_FLP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLP) | (((val) & 0x1) << 18))
906 +/* Force Link Down (17) */
907 +#define LTQ_ES_P0_CTL_REG_FLD (0x1 << 17)
908 +#define LTQ_ES_P0_CTL_REG_FLD_VAL(val) (((val) & 0x1) << 17)
909 +#define LTQ_ES_P0_CTL_REG_FLD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLD) >> 17) & 0x1)
910 +#define LTQ_ES_P0_CTL_REG_FLD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLD) | (((val) & 0x1) << 17))
911 +/* Ratio Mode for WFQ (16) */
912 +#define LTQ_ES_P0_CTL_REG_RMWFQ (0x1 << 16)
913 +#define LTQ_ES_P0_CTL_REG_RMWFQ_VAL(val) (((val) & 0x1) << 16)
914 +#define LTQ_ES_P0_CTL_REG_RMWFQ_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_RMWFQ) >> 16) & 0x1)
915 +#define LTQ_ES_P0_CTL_REG_RMWFQ_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_RMWFQ) | (((val) & 0x1) << 16))
916 +/* Aging Disable (15) */
917 +#define LTQ_ES_P0_CTL_REG_AD (0x1 << 15)
918 +#define LTQ_ES_P0_CTL_REG_AD_VAL(val) (((val) & 0x1) << 15)
919 +#define LTQ_ES_P0_CTL_REG_AD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_AD) >> 15) & 0x1)
920 +#define LTQ_ES_P0_CTL_REG_AD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_AD) | (((val) & 0x1) << 15))
921 +/* Learning Disable (14) */
922 +#define LTQ_ES_P0_CTL_REG_LD (0x1 << 14)
923 +#define LTQ_ES_P0_CTL_REG_LD_VAL(val) (((val) & 0x1) << 14)
924 +#define LTQ_ES_P0_CTL_REG_LD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_LD) >> 14) & 0x1)
925 +#define LTQ_ES_P0_CTL_REG_LD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_LD) | (((val) & 0x1) << 14))
926 +/* Maximum Number of Addresses (12:8) */
927 +#define LTQ_ES_P0_CTL_REG_MNA024 (0x1f << 8)
928 +#define LTQ_ES_P0_CTL_REG_MNA024_VAL(val) (((val) & 0x1f) << 8)
929 +#define LTQ_ES_P0_CTL_REG_MNA024_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_MNA024) >> 8) & 0x1f)
930 +#define LTQ_ES_P0_CTL_REG_MNA024_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_MNA024) | (((val) & 0x1f) << 8))
931 +/* PPPOE Port Only (7) */
932 +#define LTQ_ES_P0_CTL_REG_PPPOEP (0x1 << 7)
933 +#define LTQ_ES_P0_CTL_REG_PPPOEP_VAL(val) (((val) & 0x1) << 7)
934 +#define LTQ_ES_P0_CTL_REG_PPPOEP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PPPOEP) >> 7) & 0x1)
935 +#define LTQ_ES_P0_CTL_REG_PPPOEP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PPPOEP) | (((val) & 0x1) << 7))
936 +/* PPPOE Manage (6) */
937 +#define LTQ_ES_P0_CTL_REG_PM (0x1 << 6)
938 +#define LTQ_ES_P0_CTL_REG_PM_VAL(val) (((val) & 0x1) << 6)
939 +#define LTQ_ES_P0_CTL_REG_PM_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PM) >> 6) & 0x1)
940 +#define LTQ_ES_P0_CTL_REG_PM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PM) | (((val) & 0x1) << 6))
941 +/* Port Mirror Option (5:4) */
942 +#define LTQ_ES_P0_CTL_REG_IPMO (0x3 << 4)
943 +#define LTQ_ES_P0_CTL_REG_IPMO_VAL(val) (((val) & 0x3) << 4)
944 +#define LTQ_ES_P0_CTL_REG_IPMO_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPMO) >> 4) & 0x3)
945 +#define LTQ_ES_P0_CTL_REG_IPMO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPMO) | (((val) & 0x3) << 4))
946 +/* 802.1x Port Authorized state (3:2) */
947 +#define LTQ_ES_P0_CTL_REG_PAS (0x3 << 2)
948 +#define LTQ_ES_P0_CTL_REG_PAS_VAL(val) (((val) & 0x3) << 2)
949 +#define LTQ_ES_P0_CTL_REG_PAS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PAS) >> 2) & 0x3)
950 +#define LTQ_ES_P0_CTL_REG_PAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PAS) | (((val) & 0x3) << 2))
951 +/* Drop Scheme for voilation 802.1x (1) */
952 +#define LTQ_ES_P0_CTL_REG_DSV8021X (0x1 << 1)
953 +#define LTQ_ES_P0_CTL_REG_DSV8021X_VAL(val) (((val) & 0x1) << 1)
954 +#define LTQ_ES_P0_CTL_REG_DSV8021X_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_DSV8021X) >> 1) & 0x1)
955 +#define LTQ_ES_P0_CTL_REG_DSV8021X_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_DSV8021X) | (((val) & 0x1) << 1))
956 +/* ByPass Mode for Output (0) */
957 +#define LTQ_ES_P0_CTL_REG_BYPASS (0x1)
958 +#define LTQ_ES_P0_CTL_REG_BYPASS_VAL(val) (((val) & 0x1) << 0)
959 +#define LTQ_ES_P0_CTL_REG_BYPASS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_BYPASS) >> 0) & 0x1)
960 +#define LTQ_ES_P0_CTL_REG_BYPASS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_BYPASS) | (((val) & 0x1) << 0))
961 +
962 +/*******************************************************************************
963 + * Port 0 VLAN Control Register
964 + ******************************************************************************/
965 +
966 +/* Default FID (31:30) */
967 +#define LTQ_ES_P0_VLAN_REG_DFID (0x3 << 30)
968 +#define LTQ_ES_P0_VLAN_REG_DFID_VAL(val) (((val) & 0x3) << 30)
969 +#define LTQ_ES_P0_VLAN_REG_DFID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DFID) >> 30) & 0x3)
970 +#define LTQ_ES_P0_VLAN_REG_DFID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DFID) | (((val) & 0x3) << 30))
971 +/* Tagged Base VLAN Enable (29) */
972 +#define LTQ_ES_P0_VLAN_REG_TBVE (0x1 << 29)
973 +#define LTQ_ES_P0_VLAN_REG_TBVE_VAL(val) (((val) & 0x1) << 29)
974 +#define LTQ_ES_P0_VLAN_REG_TBVE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_TBVE) >> 29) & 0x1)
975 +#define LTQ_ES_P0_VLAN_REG_TBVE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_TBVE) | (((val) & 0x1) << 29))
976 +/* Input Force No TAG Enable (28) */
977 +#define LTQ_ES_P0_VLAN_REG_IFNTE (0x1 << 28)
978 +#define LTQ_ES_P0_VLAN_REG_IFNTE_VAL(val) (((val) & 0x1) << 28)
979 +#define LTQ_ES_P0_VLAN_REG_IFNTE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_IFNTE) >> 28) & 0x1)
980 +#define LTQ_ES_P0_VLAN_REG_IFNTE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_IFNTE) | (((val) & 0x1) << 28))
981 +/* VID Check with the VID table (27) */
982 +#define LTQ_ES_P0_VLAN_REG_VC (0x1 << 27)
983 +#define LTQ_ES_P0_VLAN_REG_VC_VAL(val) (((val) & 0x1) << 27)
984 +#define LTQ_ES_P0_VLAN_REG_VC_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VC) >> 27) & 0x1)
985 +#define LTQ_ES_P0_VLAN_REG_VC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VC) | (((val) & 0x1) << 27))
986 +/* VLAN Security Disable (26) */
987 +#define LTQ_ES_P0_VLAN_REG_VSD (0x1 << 26)
988 +#define LTQ_ES_P0_VLAN_REG_VSD_VAL(val) (((val) & 0x1) << 26)
989 +#define LTQ_ES_P0_VLAN_REG_VSD_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VSD) >> 26) & 0x1)
990 +#define LTQ_ES_P0_VLAN_REG_VSD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VSD) | (((val) & 0x1) << 26))
991 +/* Admit Only VLAN_Tagged Packet (25) */
992 +#define LTQ_ES_P0_VLAN_REG_AOVTP (0x1 << 25)
993 +#define LTQ_ES_P0_VLAN_REG_AOVTP_VAL(val) (((val) & 0x1) << 25)
994 +#define LTQ_ES_P0_VLAN_REG_AOVTP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_AOVTP) >> 25) & 0x1)
995 +#define LTQ_ES_P0_VLAN_REG_AOVTP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_AOVTP) | (((val) & 0x1) << 25))
996 +/* VLAN Member Check Enable (24) */
997 +#define LTQ_ES_P0_VLAN_REG_VMCE (0x1 << 24)
998 +#define LTQ_ES_P0_VLAN_REG_VMCE_VAL(val) (((val) & 0x1) << 24)
999 +#define LTQ_ES_P0_VLAN_REG_VMCE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VMCE) >> 24) & 0x1)
1000 +#define LTQ_ES_P0_VLAN_REG_VMCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VMCE) | (((val) & 0x1) << 24))
1001 +/* Reserved (23:19) */
1002 +#define LTQ_ES_P0_VLAN_REG_RES (0x1f << 19)
1003 +#define LTQ_ES_P0_VLAN_REG_RES_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_RES) >> 19) & 0x1f)
1004 +/* Default VLAN Port Map (18:16) */
1005 +#define LTQ_ES_P0_VLAN_REG_DVPM (0x7 << 16)
1006 +#define LTQ_ES_P0_VLAN_REG_DVPM_VAL(val) (((val) & 0x7) << 16)
1007 +#define LTQ_ES_P0_VLAN_REG_DVPM_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DVPM) >> 16) & 0x7)
1008 +#define LTQ_ES_P0_VLAN_REG_DVPM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DVPM) | (((val) & 0x7) << 16))
1009 +/* Port Priority (15:14) */
1010 +#define LTQ_ES_P0_VLAN_REG_PP (0x3 << 14)
1011 +#define LTQ_ES_P0_VLAN_REG_PP_VAL(val) (((val) & 0x3) << 14)
1012 +#define LTQ_ES_P0_VLAN_REG_PP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PP) >> 14) & 0x3)
1013 +#define LTQ_ES_P0_VLAN_REG_PP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PP) | (((val) & 0x3) << 14))
1014 +/* Port Priority Enable (13) */
1015 +#define LTQ_ES_P0_VLAN_REG_PPE (0x1 << 13)
1016 +#define LTQ_ES_P0_VLAN_REG_PPE_VAL(val) (((val) & 0x1) << 13)
1017 +#define LTQ_ES_P0_VLAN_REG_PPE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PPE) >> 13) & 0x1)
1018 +#define LTQ_ES_P0_VLAN_REG_PPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PPE) | (((val) & 0x1) << 13))
1019 +/* Portbase VLAN tag member for Port 0 (12) */
1020 +#define LTQ_ES_P0_VLAN_REG_PVTAGMP (0x1 << 12)
1021 +#define LTQ_ES_P0_VLAN_REG_PVTAGMP_VAL(val) (((val) & 0x1) << 12)
1022 +#define LTQ_ES_P0_VLAN_REG_PVTAGMP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVTAGMP) >> 12) & 0x1)
1023 +#define LTQ_ES_P0_VLAN_REG_PVTAGMP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVTAGMP) | (((val) & 0x1) << 12))
1024 +/* PVID (11:0) */
1025 +#define LTQ_ES_P0_VLAN_REG_PVID (0xfff)
1026 +#define LTQ_ES_P0_VLAN_REG_PVID_VAL(val) (((val) & 0xfff) << 0)
1027 +#define LTQ_ES_P0_VLAN_REG_PVID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVID) >> 0) & 0xfff)
1028 +#define LTQ_ES_P0_VLAN_REG_PVID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVID) | (((val) & 0xfff) << 0))
1029 +
1030 +/*******************************************************************************
1031 + * Port 0 Ingress Control Register
1032 + ******************************************************************************/
1033 +
1034 +/* Reserved (31:13) */
1035 +#define LTQ_ES_P0_INCTL_REG_RES (0x7ffff << 13)
1036 +#define LTQ_ES_P0_INCTL_REG_RES_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_RES) >> 13) & 0x7ffff)
1037 +/* Port 0 Ingress/Egress Timer Tick T selection (12:11) */
1038 +#define LTQ_ES_P0_INCTL_REG_P0ITT (0x3 << 11)
1039 +#define LTQ_ES_P0_INCTL_REG_P0ITT_VAL(val) (((val) & 0x3) << 11)
1040 +#define LTQ_ES_P0_INCTL_REG_P0ITT_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITT) >> 11) & 0x3)
1041 +#define LTQ_ES_P0_INCTL_REG_P0ITT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITT) | (((val) & 0x3) << 11))
1042 +/* Port 0 Igress Token R (10:0) */
1043 +#define LTQ_ES_P0_INCTL_REG_P0ITR (0x7ff)
1044 +#define LTQ_ES_P0_INCTL_REG_P0ITR_VAL(val) (((val) & 0x7ff) << 0)
1045 +#define LTQ_ES_P0_INCTL_REG_P0ITR_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITR) >> 0) & 0x7ff)
1046 +#define LTQ_ES_P0_INCTL_REG_P0ITR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITR) | (((val) & 0x7ff) << 0))
1047 +
1048 +/*******************************************************************************
1049 + * Port 0 Egress Control for Strict Q32 Register
1050 + ******************************************************************************/
1051 +
1052 +/* Port 0 Egress Token R for Strict Priority Q3 (26:16) */
1053 +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR (0x7ff << 16)
1054 +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_VAL(val) (((val) & 0x7ff) << 16)
1055 +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) >> 16) & 0x7ff)
1056 +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) | (((val) & 0x7ff) << 16))
1057 +/* Port 0 Egress Token R for Strict Priority Q2 (10:0) */
1058 +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR (0x7ff)
1059 +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_VAL(val) (((val) & 0x7ff) << 0)
1060 +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) >> 0) & 0x7ff)
1061 +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) | (((val) & 0x7ff) << 0))
1062 +
1063 +/*******************************************************************************
1064 + * Port 0 Egress Control for Strict Q10 Register
1065 + ******************************************************************************/
1066 +
1067 +/* Reserved (31:27) */
1068 +#define LTQ_ES_P0_ECS_Q10_REG_RES (0x1f << 27)
1069 +#define LTQ_ES_P0_ECS_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_RES) >> 27) & 0x1f)
1070 +/* Port 0 Egress Token R for Strict Priority Q1 (26:16) */
1071 +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR (0x7ff << 16)
1072 +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_VAL(val) (((val) & 0x7ff) << 16)
1073 +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) >> 16) & 0x7ff)
1074 +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) | (((val) & 0x7ff) << 16))
1075 +/* Port 0 Egress Token R for Strict Priority Q0 (10:0) */
1076 +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR (0x7ff)
1077 +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_VAL(val) (((val) & 0x7ff) << 0)
1078 +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) >> 0) & 0x7ff)
1079 +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) | (((val) & 0x7ff) << 0))
1080 +
1081 +/*******************************************************************************
1082 + * Port 0 Egress Control for WFQ Q32 Register
1083 + ******************************************************************************/
1084 +
1085 +/* Reserved (31:27) */
1086 +#define LTQ_ES_P0_ECW_Q32_REG_RES (0x1f << 27)
1087 +#define LTQ_ES_P0_ECW_Q32_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_RES) >> 27) & 0x1f)
1088 +/* Port 0 Egress Token R for WFQ Q3 (26:16) */
1089 +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR (0x7ff << 16)
1090 +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_VAL(val) (((val) & 0x7ff) << 16)
1091 +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) >> 16) & 0x7ff)
1092 +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) | (((val) & 0x7ff) << 16))
1093 +/* Port 0 Egress Token R for WFQ Q2 (10:0) */
1094 +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR (0x7ff)
1095 +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_VAL(val) (((val) & 0x7ff) << 0)
1096 +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) >> 0) & 0x7ff)
1097 +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) | (((val) & 0x7ff) << 0))
1098 +
1099 +/*******************************************************************************
1100 + * Port 0 Egress Control for WFQ Q10 Register
1101 + ******************************************************************************/
1102 +
1103 +/* Reserved (31:27) */
1104 +#define LTQ_ES_P0_ECW_Q10_REG_RES (0x1f << 27)
1105 +#define LTQ_ES_P0_ECW_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_RES) >> 27) & 0x1f)
1106 +/* Port 0 Egress Token R for WFQ Q1 (26:16) */
1107 +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR (0x7ff << 16)
1108 +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_VAL(val) (((val) & 0x7ff) << 16)
1109 +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) >> 16) & 0x7ff)
1110 +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) | (((val) & 0x7ff) << 16))
1111 +/* Port 0 Egress Token R for WFQ Q0 (10:0) */
1112 +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR (0x7ff)
1113 +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_VAL(val) (((val) & 0x7ff) << 0)
1114 +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) >> 0) & 0x7ff)
1115 +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) | (((val) & 0x7ff) << 0))
1116 +
1117 +/*******************************************************************************
1118 + * Interrupt Enable Register
1119 + ******************************************************************************/
1120 +
1121 +/* Reserved (31:8) */
1122 +#define LTQ_ES_INT_ENA_REG_RES (0xffffff << 8)
1123 +#define LTQ_ES_INT_ENA_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_RES) >> 8) & 0xffffff)
1124 +/* Data Buffer is Full Interrupt Enable (7) */
1125 +#define LTQ_ES_INT_ENA_REG_DBFIE (0x1 << 7)
1126 +#define LTQ_ES_INT_ENA_REG_DBFIE_VAL(val) (((val) & 0x1) << 7)
1127 +#define LTQ_ES_INT_ENA_REG_DBFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBFIE) >> 7) & 0x1)
1128 +#define LTQ_ES_INT_ENA_REG_DBFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBFIE) | (((val) & 0x1) << 7))
1129 +/* Data Buffer is nearly Full Interrupt Enable (6) */
1130 +#define LTQ_ES_INT_ENA_REG_DBNFIE (0x1 << 6)
1131 +#define LTQ_ES_INT_ENA_REG_DBNFIE_VAL(val) (((val) & 0x1) << 6)
1132 +#define LTQ_ES_INT_ENA_REG_DBNFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBNFIE) >> 6) & 0x1)
1133 +#define LTQ_ES_INT_ENA_REG_DBNFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBNFIE) | (((val) & 0x1) << 6))
1134 +/* Learning Table Full Interrupt Enable (5) */
1135 +#define LTQ_ES_INT_ENA_REG_LTFIE (0x1 << 5)
1136 +#define LTQ_ES_INT_ENA_REG_LTFIE_VAL(val) (((val) & 0x1) << 5)
1137 +#define LTQ_ES_INT_ENA_REG_LTFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTFIE) >> 5) & 0x1)
1138 +#define LTQ_ES_INT_ENA_REG_LTFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTFIE) | (((val) & 0x1) << 5))
1139 +/* Leaning Table Access Done Interrupt Enable (4) */
1140 +#define LTQ_ES_INT_ENA_REG_LTADIE (0x1 << 4)
1141 +#define LTQ_ES_INT_ENA_REG_LTADIE_VAL(val) (((val) & 0x1) << 4)
1142 +#define LTQ_ES_INT_ENA_REG_LTADIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTADIE) >> 4) & 0x1)
1143 +#define LTQ_ES_INT_ENA_REG_LTADIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTADIE) | (((val) & 0x1) << 4))
1144 +/* Port Security Violation Interrupt Enable (3:1) */
1145 +#define LTQ_ES_INT_ENA_REG_PSVIE (0x7 << 1)
1146 +#define LTQ_ES_INT_ENA_REG_PSVIE_VAL(val) (((val) & 0x7) << 1)
1147 +#define LTQ_ES_INT_ENA_REG_PSVIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSVIE) >> 1) & 0x7)
1148 +#define LTQ_ES_INT_ENA_REG_PSVIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSVIE) | (((val) & 0x7) << 1))
1149 +/* Port Status Change Interrupt Enable (0) */
1150 +#define LTQ_ES_INT_ENA_REG_PSCIE (0x1)
1151 +#define LTQ_ES_INT_ENA_REG_PSCIE_VAL(val) (((val) & 0x1) << 0)
1152 +#define LTQ_ES_INT_ENA_REG_PSCIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSCIE) >> 0) & 0x1)
1153 +#define LTQ_ES_INT_ENA_REG_PSCIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSCIE) | (((val) & 0x1) << 0))
1154 +
1155 +/*******************************************************************************
1156 + * Interrupt Status Register
1157 + ******************************************************************************/
1158 +
1159 +/* Reserved (31:8) */
1160 +#define LTQ_ES_INT_ST_REG_RES (0xffffff << 8)
1161 +#define LTQ_ES_INT_ST_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ST_REG_RES) >> 8) & 0xffffff)
1162 +/* Data Buffer is Full (7) */
1163 +#define LTQ_ES_INT_ST_REG_DBF (0x1 << 7)
1164 +#define LTQ_ES_INT_ST_REG_DBF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBF) >> 7) & 0x1)
1165 +/* Data Buffer is nearly Full (6) */
1166 +#define LTQ_ES_INT_ST_REG_DBNF (0x1 << 6)
1167 +#define LTQ_ES_INT_ST_REG_DBNF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBNF) >> 6) & 0x1)
1168 +/* Learning Table Full (5) */
1169 +#define LTQ_ES_INT_ST_REG_LTF (0x1 << 5)
1170 +#define LTQ_ES_INT_ST_REG_LTF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTF) >> 5) & 0x1)
1171 +/* Leaning Table Access Done (4) */
1172 +#define LTQ_ES_INT_ST_REG_LTAD (0x1 << 4)
1173 +#define LTQ_ES_INT_ST_REG_LTAD_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTAD) >> 4) & 0x1)
1174 +/* Port Security Violation (3:1) */
1175 +#define LTQ_ES_INT_ST_REG_PSV (0x7 << 1)
1176 +#define LTQ_ES_INT_ST_REG_PSV_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSV) >> 1) & 0x7)
1177 +/* Port Status Change (0) */
1178 +#define LTQ_ES_INT_ST_REG_PSC (0x1)
1179 +#define LTQ_ES_INT_ST_REG_PSC_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSC) >> 0) & 0x1)
1180 +
1181 +/*******************************************************************************
1182 + * Switch Global Control Register 0
1183 + ******************************************************************************/
1184 +
1185 +/* Switch Enable (31) */
1186 +#define LTQ_ES_SW_GCTL0_REG_SE (0x1 << 31)
1187 +#define LTQ_ES_SW_GCTL0_REG_SE_VAL(val) (((val) & 0x1) << 31)
1188 +#define LTQ_ES_SW_GCTL0_REG_SE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SE) >> 31) & 0x1)
1189 +#define LTQ_ES_SW_GCTL0_REG_SE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SE) | (((val) & 0x1) << 31))
1190 +/* CRC Check Disable (30) */
1191 +#define LTQ_ES_SW_GCTL0_REG_ICRCCD (0x1 << 30)
1192 +#define LTQ_ES_SW_GCTL0_REG_ICRCCD_VAL(val) (((val) & 0x1) << 30)
1193 +#define LTQ_ES_SW_GCTL0_REG_ICRCCD_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ICRCCD) >> 30) & 0x1)
1194 +#define LTQ_ES_SW_GCTL0_REG_ICRCCD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ICRCCD) | (((val) & 0x1) << 30))
1195 +/* Replace VID0 (28) */
1196 +#define LTQ_ES_SW_GCTL0_REG_RVID0 (0x1 << 28)
1197 +#define LTQ_ES_SW_GCTL0_REG_RVID0_VAL(val) (((val) & 0x1) << 28)
1198 +#define LTQ_ES_SW_GCTL0_REG_RVID0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID0) >> 28) & 0x1)
1199 +#define LTQ_ES_SW_GCTL0_REG_RVID0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID0) | (((val) & 0x1) << 28))
1200 +/* Replace VID1 (27) */
1201 +#define LTQ_ES_SW_GCTL0_REG_RVID1 (0x1 << 27)
1202 +#define LTQ_ES_SW_GCTL0_REG_RVID1_VAL(val) (((val) & 0x1) << 27)
1203 +#define LTQ_ES_SW_GCTL0_REG_RVID1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID1) >> 27) & 0x1)
1204 +#define LTQ_ES_SW_GCTL0_REG_RVID1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID1) | (((val) & 0x1) << 27))
1205 +/* Replace VIDFFF (26) */
1206 +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF (0x1 << 26)
1207 +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_VAL(val) (((val) & 0x1) << 26)
1208 +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVIDFFF) >> 26) & 0x1)
1209 +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVIDFFF) | (((val) & 0x1) << 26))
1210 +/* Priority Change Rule (25) */
1211 +#define LTQ_ES_SW_GCTL0_REG_PCR (0x1 << 25)
1212 +#define LTQ_ES_SW_GCTL0_REG_PCR_VAL(val) (((val) & 0x1) << 25)
1213 +#define LTQ_ES_SW_GCTL0_REG_PCR_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCR) >> 25) & 0x1)
1214 +#define LTQ_ES_SW_GCTL0_REG_PCR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCR) | (((val) & 0x1) << 25))
1215 +/* Priority Change Enable (24) */
1216 +#define LTQ_ES_SW_GCTL0_REG_PCE (0x1 << 24)
1217 +#define LTQ_ES_SW_GCTL0_REG_PCE_VAL(val) (((val) & 0x1) << 24)
1218 +#define LTQ_ES_SW_GCTL0_REG_PCE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCE) >> 24) & 0x1)
1219 +#define LTQ_ES_SW_GCTL0_REG_PCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCE) | (((val) & 0x1) << 24))
1220 +/* Transmit Short IPG Enable (23) */
1221 +#define LTQ_ES_SW_GCTL0_REG_TSIPGE (0x1 << 23)
1222 +#define LTQ_ES_SW_GCTL0_REG_TSIPGE_VAL(val) (((val) & 0x1) << 23)
1223 +#define LTQ_ES_SW_GCTL0_REG_TSIPGE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_TSIPGE) >> 23) & 0x1)
1224 +#define LTQ_ES_SW_GCTL0_REG_TSIPGE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_TSIPGE) | (((val) & 0x1) << 23))
1225 +/* PHY Base Address (22) */
1226 +#define LTQ_ES_SW_GCTL0_REG_PHYBA (0x1 << 22)
1227 +#define LTQ_ES_SW_GCTL0_REG_PHYBA_VAL(val) (((val) & 0x1) << 22)
1228 +#define LTQ_ES_SW_GCTL0_REG_PHYBA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PHYBA) >> 22) & 0x1)
1229 +#define LTQ_ES_SW_GCTL0_REG_PHYBA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PHYBA) | (((val) & 0x1) << 22))
1230 +/* Drop Packet When Excessive Collision Happen (21) */
1231 +#define LTQ_ES_SW_GCTL0_REG_DPWECH (0x1 << 21)
1232 +#define LTQ_ES_SW_GCTL0_REG_DPWECH_VAL(val) (((val) & 0x1) << 21)
1233 +#define LTQ_ES_SW_GCTL0_REG_DPWECH_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DPWECH) >> 21) & 0x1)
1234 +#define LTQ_ES_SW_GCTL0_REG_DPWECH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DPWECH) | (((val) & 0x1) << 21))
1235 +/* Aging Timer Select (20:18) */
1236 +#define LTQ_ES_SW_GCTL0_REG_ATS (0x7 << 18)
1237 +#define LTQ_ES_SW_GCTL0_REG_ATS_VAL(val) (((val) & 0x7) << 18)
1238 +#define LTQ_ES_SW_GCTL0_REG_ATS_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ATS) >> 18) & 0x7)
1239 +#define LTQ_ES_SW_GCTL0_REG_ATS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ATS) | (((val) & 0x7) << 18))
1240 +/* Mirror CRC Also (17) */
1241 +#define LTQ_ES_SW_GCTL0_REG_MCA (0x1 << 17)
1242 +#define LTQ_ES_SW_GCTL0_REG_MCA_VAL(val) (((val) & 0x1) << 17)
1243 +#define LTQ_ES_SW_GCTL0_REG_MCA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MCA) >> 17) & 0x1)
1244 +#define LTQ_ES_SW_GCTL0_REG_MCA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MCA) | (((val) & 0x1) << 17))
1245 +/* Mirror RXER Also (16) */
1246 +#define LTQ_ES_SW_GCTL0_REG_MRA (0x1 << 16)
1247 +#define LTQ_ES_SW_GCTL0_REG_MRA_VAL(val) (((val) & 0x1) << 16)
1248 +#define LTQ_ES_SW_GCTL0_REG_MRA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MRA) >> 16) & 0x1)
1249 +#define LTQ_ES_SW_GCTL0_REG_MRA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MRA) | (((val) & 0x1) << 16))
1250 +/* Mirror PAUSE Also (15) */
1251 +#define LTQ_ES_SW_GCTL0_REG_MPA (0x1 << 15)
1252 +#define LTQ_ES_SW_GCTL0_REG_MPA_VAL(val) (((val) & 0x1) << 15)
1253 +#define LTQ_ES_SW_GCTL0_REG_MPA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPA) >> 15) & 0x1)
1254 +#define LTQ_ES_SW_GCTL0_REG_MPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPA) | (((val) & 0x1) << 15))
1255 +/* Mirror Long Also (14) */
1256 +#define LTQ_ES_SW_GCTL0_REG_MLA (0x1 << 14)
1257 +#define LTQ_ES_SW_GCTL0_REG_MLA_VAL(val) (((val) & 0x1) << 14)
1258 +#define LTQ_ES_SW_GCTL0_REG_MLA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MLA) >> 14) & 0x1)
1259 +#define LTQ_ES_SW_GCTL0_REG_MLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MLA) | (((val) & 0x1) << 14))
1260 +/* Mirror Short Also (13) */
1261 +#define LTQ_ES_SW_GCTL0_REG_MSA (0x1 << 13)
1262 +#define LTQ_ES_SW_GCTL0_REG_MSA_VAL(val) (((val) & 0x1) << 13)
1263 +#define LTQ_ES_SW_GCTL0_REG_MSA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MSA) >> 13) & 0x1)
1264 +#define LTQ_ES_SW_GCTL0_REG_MSA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MSA) | (((val) & 0x1) << 13))
1265 +/* Sniffer port number (12:11) */
1266 +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN (0x3 << 11)
1267 +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(val) (((val) & 0x3) << 11)
1268 +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SNIFFPN) >> 11) & 0x3)
1269 +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SNIFFPN) | (((val) & 0x3) << 11))
1270 +/* Max Packet Length (MAXPKTLEN) (9:8) */
1271 +#define LTQ_ES_SW_GCTL0_REG_MPL (0x3 << 8)
1272 +#define LTQ_ES_SW_GCTL0_REG_MPL_VAL(val) (((val) & 0x3) << 8)
1273 +#define LTQ_ES_SW_GCTL0_REG_MPL_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPL) >> 8) & 0x3)
1274 +#define LTQ_ES_SW_GCTL0_REG_MPL_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPL) | (((val) & 0x3) << 8))
1275 +/* Discard Mode (Drop scheme for Packets Classified as Q3) (7:6) */
1276 +#define LTQ_ES_SW_GCTL0_REG_DMQ3 (0x3 << 6)
1277 +#define LTQ_ES_SW_GCTL0_REG_DMQ3_VAL(val) (((val) & 0x3) << 6)
1278 +#define LTQ_ES_SW_GCTL0_REG_DMQ3_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ3) >> 6) & 0x3)
1279 +#define LTQ_ES_SW_GCTL0_REG_DMQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ3) | (((val) & 0x3) << 6))
1280 +/* Discard Mode (Drop scheme for Packets Classified as Q2) (5:4) */
1281 +#define LTQ_ES_SW_GCTL0_REG_DMQ2 (0x3 << 4)
1282 +#define LTQ_ES_SW_GCTL0_REG_DMQ2_VAL(val) (((val) & 0x3) << 4)
1283 +#define LTQ_ES_SW_GCTL0_REG_DMQ2_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ2) >> 4) & 0x3)
1284 +#define LTQ_ES_SW_GCTL0_REG_DMQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ2) | (((val) & 0x3) << 4))
1285 +/* Discard Mode (Drop scheme for Packets Classified as Q1) (3:2) */
1286 +#define LTQ_ES_SW_GCTL0_REG_DMQ1 (0x3 << 2)
1287 +#define LTQ_ES_SW_GCTL0_REG_DMQ1_VAL(val) (((val) & 0x3) << 2)
1288 +#define LTQ_ES_SW_GCTL0_REG_DMQ1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ1) >> 2) & 0x3)
1289 +#define LTQ_ES_SW_GCTL0_REG_DMQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ1) | (((val) & 0x3) << 2))
1290 +/* Discard Mode (Drop scheme for Packets Classified as Q0) (1:0) */
1291 +#define LTQ_ES_SW_GCTL0_REG_DMQ0 (0x3)
1292 +#define LTQ_ES_SW_GCTL0_REG_DMQ0_VAL(val) (((val) & 0x3) << 0)
1293 +#define LTQ_ES_SW_GCTL0_REG_DMQ0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ0) >> 0) & 0x3)
1294 +#define LTQ_ES_SW_GCTL0_REG_DMQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ0) | (((val) & 0x3) << 0))
1295 +
1296 +/*******************************************************************************
1297 + * Switch Global Control Register 1
1298 + ******************************************************************************/
1299 +
1300 +/* BIST Done (27) */
1301 +#define LTQ_ES_SW_GCTL1_REG_BISTDN (0x1 << 27)
1302 +#define LTQ_ES_SW_GCTL1_REG_BISTDN_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BISTDN) >> 27) & 0x1)
1303 +/* Enable drop scheme of TX and RX (26) */
1304 +#define LTQ_ES_SW_GCTL1_REG_EDSTX (0x1 << 26)
1305 +#define LTQ_ES_SW_GCTL1_REG_EDSTX_VAL(val) (((val) & 0x1) << 26)
1306 +#define LTQ_ES_SW_GCTL1_REG_EDSTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_EDSTX) >> 26) & 0x1)
1307 +#define LTQ_ES_SW_GCTL1_REG_EDSTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_EDSTX) | (((val) & 0x1) << 26))
1308 +/* Congestion threshold for TX queue (25:24) */
1309 +#define LTQ_ES_SW_GCTL1_REG_CTTX (0x3 << 24)
1310 +#define LTQ_ES_SW_GCTL1_REG_CTTX_VAL(val) (((val) & 0x3) << 24)
1311 +#define LTQ_ES_SW_GCTL1_REG_CTTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_CTTX) >> 24) & 0x3)
1312 +#define LTQ_ES_SW_GCTL1_REG_CTTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_CTTX) | (((val) & 0x3) << 24))
1313 +/* Input Jam Threshold (23:21) */
1314 +#define LTQ_ES_SW_GCTL1_REG_IJT (0x7 << 21)
1315 +#define LTQ_ES_SW_GCTL1_REG_IJT_VAL(val) (((val) & 0x7) << 21)
1316 +#define LTQ_ES_SW_GCTL1_REG_IJT_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_IJT) >> 21) & 0x7)
1317 +#define LTQ_ES_SW_GCTL1_REG_IJT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_IJT) | (((val) & 0x7) << 21))
1318 +/* Do not Identify VLAN after SNAP (20) */
1319 +#define LTQ_ES_SW_GCTL1_REG_DIVS (0x1 << 20)
1320 +#define LTQ_ES_SW_GCTL1_REG_DIVS_VAL(val) (((val) & 0x1) << 20)
1321 +#define LTQ_ES_SW_GCTL1_REG_DIVS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIVS) >> 20) & 0x1)
1322 +#define LTQ_ES_SW_GCTL1_REG_DIVS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIVS) | (((val) & 0x1) << 20))
1323 +/* Do not Identify IPV6 in PPPOE (19) */
1324 +#define LTQ_ES_SW_GCTL1_REG_DII6P (0x1 << 19)
1325 +#define LTQ_ES_SW_GCTL1_REG_DII6P_VAL(val) (((val) & 0x1) << 19)
1326 +#define LTQ_ES_SW_GCTL1_REG_DII6P_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DII6P) >> 19) & 0x1)
1327 +#define LTQ_ES_SW_GCTL1_REG_DII6P_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DII6P) | (((val) & 0x1) << 19))
1328 +/* Do not Identify IP in PPPOE after SNAP (18) */
1329 +#define LTQ_ES_SW_GCTL1_REG_DIIPS (0x1 << 18)
1330 +#define LTQ_ES_SW_GCTL1_REG_DIIPS_VAL(val) (((val) & 0x1) << 18)
1331 +#define LTQ_ES_SW_GCTL1_REG_DIIPS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIPS) >> 18) & 0x1)
1332 +#define LTQ_ES_SW_GCTL1_REG_DIIPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIPS) | (((val) & 0x1) << 18))
1333 +/* Do not Identify Ether-Type = 0x0800, IP VER = 6 as IPV6 packets (17) */
1334 +#define LTQ_ES_SW_GCTL1_REG_DIE (0x1 << 17)
1335 +#define LTQ_ES_SW_GCTL1_REG_DIE_VAL(val) (((val) & 0x1) << 17)
1336 +#define LTQ_ES_SW_GCTL1_REG_DIE_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIE) >> 17) & 0x1)
1337 +#define LTQ_ES_SW_GCTL1_REG_DIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIE) | (((val) & 0x1) << 17))
1338 +/* Do not Identify IP in PPPOE (16) */
1339 +#define LTQ_ES_SW_GCTL1_REG_DIIP (0x1 << 16)
1340 +#define LTQ_ES_SW_GCTL1_REG_DIIP_VAL(val) (((val) & 0x1) << 16)
1341 +#define LTQ_ES_SW_GCTL1_REG_DIIP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIP) >> 16) & 0x1)
1342 +#define LTQ_ES_SW_GCTL1_REG_DIIP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIP) | (((val) & 0x1) << 16))
1343 +/* Do not Identify SNAP (15) */
1344 +#define LTQ_ES_SW_GCTL1_REG_DIS (0x1 << 15)
1345 +#define LTQ_ES_SW_GCTL1_REG_DIS_VAL(val) (((val) & 0x1) << 15)
1346 +#define LTQ_ES_SW_GCTL1_REG_DIS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIS) >> 15) & 0x1)
1347 +#define LTQ_ES_SW_GCTL1_REG_DIS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIS) | (((val) & 0x1) << 15))
1348 +/* Unicast Portmap (14:12) */
1349 +#define LTQ_ES_SW_GCTL1_REG_UP (0x7 << 12)
1350 +#define LTQ_ES_SW_GCTL1_REG_UP_VAL(val) (((val) & 0x7) << 12)
1351 +#define LTQ_ES_SW_GCTL1_REG_UP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_UP) >> 12) & 0x7)
1352 +#define LTQ_ES_SW_GCTL1_REG_UP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_UP) | (((val) & 0x7) << 12))
1353 +/* Broadcast Portmap (10:8) */
1354 +#define LTQ_ES_SW_GCTL1_REG_BP (0x7 << 8)
1355 +#define LTQ_ES_SW_GCTL1_REG_BP_VAL(val) (((val) & 0x7) << 8)
1356 +#define LTQ_ES_SW_GCTL1_REG_BP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BP) >> 8) & 0x7)
1357 +#define LTQ_ES_SW_GCTL1_REG_BP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_BP) | (((val) & 0x7) << 8))
1358 +/* Multicast Portmap (6:4) */
1359 +#define LTQ_ES_SW_GCTL1_REG_MP (0x7 << 4)
1360 +#define LTQ_ES_SW_GCTL1_REG_MP_VAL(val) (((val) & 0x7) << 4)
1361 +#define LTQ_ES_SW_GCTL1_REG_MP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_MP) >> 4) & 0x7)
1362 +#define LTQ_ES_SW_GCTL1_REG_MP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_MP) | (((val) & 0x7) << 4))
1363 +/* Reserve Portmap (2:0) */
1364 +#define LTQ_ES_SW_GCTL1_REG_RP (0x7)
1365 +#define LTQ_ES_SW_GCTL1_REG_RP_VAL(val) (((val) & 0x7) << 0)
1366 +#define LTQ_ES_SW_GCTL1_REG_RP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_RP) >> 0) & 0x7)
1367 +#define LTQ_ES_SW_GCTL1_REG_RP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_RP) | (((val) & 0x7) << 0))
1368 +
1369 +/*******************************************************************************
1370 + * ARP/RARP Register
1371 + ******************************************************************************/
1372 +
1373 +/* MAC Control Action (15:14) */
1374 +#define LTQ_ES_ARP_REG_MACA (0x3 << 14)
1375 +#define LTQ_ES_ARP_REG_MACA_VAL(val) (((val) & 0x3) << 14)
1376 +#define LTQ_ES_ARP_REG_MACA_GET(val) ((((val) & LTQ_ES_ARP_REG_MACA) >> 14) & 0x3)
1377 +#define LTQ_ES_ARP_REG_MACA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_MACA) | (((val) & 0x3) << 14))
1378 +/* Unicast packet Treated as Cross_VLAN packet (13) */
1379 +#define LTQ_ES_ARP_REG_UPT (0x1 << 13)
1380 +#define LTQ_ES_ARP_REG_UPT_VAL(val) (((val) & 0x1) << 13)
1381 +#define LTQ_ES_ARP_REG_UPT_GET(val) ((((val) & LTQ_ES_ARP_REG_UPT) >> 13) & 0x1)
1382 +#define LTQ_ES_ARP_REG_UPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_UPT) | (((val) & 0x1) << 13))
1383 +/* RARP Packet Treated as Cross_VLAN Packet (12) */
1384 +#define LTQ_ES_ARP_REG_RPT (0x1 << 12)
1385 +#define LTQ_ES_ARP_REG_RPT_VAL(val) (((val) & 0x1) << 12)
1386 +#define LTQ_ES_ARP_REG_RPT_GET(val) ((((val) & LTQ_ES_ARP_REG_RPT) >> 12) & 0x1)
1387 +#define LTQ_ES_ARP_REG_RPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RPT) | (((val) & 0x1) << 12))
1388 +/* RARP/ARP Packet Action (11:10) */
1389 +#define LTQ_ES_ARP_REG_RAPA (0x3 << 10)
1390 +#define LTQ_ES_ARP_REG_RAPA_VAL(val) (((val) & 0x3) << 10)
1391 +#define LTQ_ES_ARP_REG_RAPA_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPA) >> 10) & 0x3)
1392 +#define LTQ_ES_ARP_REG_RAPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPA) | (((val) & 0x3) << 10))
1393 +/* RARP/ARP Packet Priority Enable (9) */
1394 +#define LTQ_ES_ARP_REG_RAPPE (0x1 << 9)
1395 +#define LTQ_ES_ARP_REG_RAPPE_VAL(val) (((val) & 0x1) << 9)
1396 +#define LTQ_ES_ARP_REG_RAPPE_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPPE) >> 9) & 0x1)
1397 +#define LTQ_ES_ARP_REG_RAPPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPPE) | (((val) & 0x1) << 9))
1398 +/* RARP/ARP Packet Priority (8:7) */
1399 +#define LTQ_ES_ARP_REG_RAPP (0x3 << 7)
1400 +#define LTQ_ES_ARP_REG_RAPP_VAL(val) (((val) & 0x3) << 7)
1401 +#define LTQ_ES_ARP_REG_RAPP_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPP) >> 7) & 0x3)
1402 +#define LTQ_ES_ARP_REG_RAPP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPP) | (((val) & 0x3) << 7))
1403 +/* RARP/ARP Packet Output Tag Handle (6:5) */
1404 +#define LTQ_ES_ARP_REG_RAPOTH (0x3 << 5)
1405 +#define LTQ_ES_ARP_REG_RAPOTH_VAL(val) (((val) & 0x3) << 5)
1406 +#define LTQ_ES_ARP_REG_RAPOTH_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPOTH) >> 5) & 0x3)
1407 +#define LTQ_ES_ARP_REG_RAPOTH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPOTH) | (((val) & 0x3) << 5))
1408 +/* ARP Packet Treated as Cross _ VLAN Packet (4) */
1409 +#define LTQ_ES_ARP_REG_APT (0x1 << 4)
1410 +#define LTQ_ES_ARP_REG_APT_VAL(val) (((val) & 0x1) << 4)
1411 +#define LTQ_ES_ARP_REG_APT_GET(val) ((((val) & LTQ_ES_ARP_REG_APT) >> 4) & 0x1)
1412 +#define LTQ_ES_ARP_REG_APT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_APT) | (((val) & 0x1) << 4))
1413 +/* RARP/ARP Packet Treated as Management Packet (3) */
1414 +#define LTQ_ES_ARP_REG_RAPTM (0x1 << 3)
1415 +#define LTQ_ES_ARP_REG_RAPTM_VAL(val) (((val) & 0x1) << 3)
1416 +#define LTQ_ES_ARP_REG_RAPTM_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPTM) >> 3) & 0x1)
1417 +#define LTQ_ES_ARP_REG_RAPTM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPTM) | (((val) & 0x1) << 3))
1418 +/* RARP/ARP Packet Treated as Span Packet (2) */
1419 +#define LTQ_ES_ARP_REG_TAPTS (0x1 << 2)
1420 +#define LTQ_ES_ARP_REG_TAPTS_VAL(val) (((val) & 0x1) << 2)
1421 +#define LTQ_ES_ARP_REG_TAPTS_GET(val) ((((val) & LTQ_ES_ARP_REG_TAPTS) >> 2) & 0x1)
1422 +#define LTQ_ES_ARP_REG_TAPTS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAPTS) | (((val) & 0x1) << 2))
1423 +/* Trap ARP Packet (1) */
1424 +#define LTQ_ES_ARP_REG_TAP (0x1 << 1)
1425 +#define LTQ_ES_ARP_REG_TAP_VAL(val) (((val) & 0x1) << 1)
1426 +#define LTQ_ES_ARP_REG_TAP_GET(val) ((((val) & LTQ_ES_ARP_REG_TAP) >> 1) & 0x1)
1427 +#define LTQ_ES_ARP_REG_TAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAP) | (((val) & 0x1) << 1))
1428 +/* Trap RARP Packet (0) */
1429 +#define LTQ_ES_ARP_REG_TRP (0x1)
1430 +#define LTQ_ES_ARP_REG_TRP_VAL(val) (((val) & 0x1) << 0)
1431 +#define LTQ_ES_ARP_REG_TRP_GET(val) ((((val) & LTQ_ES_ARP_REG_TRP) >> 0) & 0x1)
1432 +#define LTQ_ES_ARP_REG_TRP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TRP) | (((val) & 0x1) << 0))
1433 +
1434 +/*******************************************************************************
1435 + * Storm control Register
1436 + ******************************************************************************/
1437 +
1438 +/* Reserved (31:29) */
1439 +#define LTQ_ES_STRM_CTL_REG_RES (0x7 << 29)
1440 +#define LTQ_ES_STRM_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_RES) >> 29) & 0x7)
1441 +/* 10M Threshold (28:16) */
1442 +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH (0x1fff << 16)
1443 +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_VAL(val) (((val) & 0x1fff) << 16)
1444 +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_10_TH) >> 16) & 0x1fff)
1445 +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_10_TH) | (((val) & 0x1fff) << 16))
1446 +/* Storm Enable for Broadcast Packets (15) */
1447 +#define LTQ_ES_STRM_CTL_REG_STORM_B (0x1 << 15)
1448 +#define LTQ_ES_STRM_CTL_REG_STORM_B_VAL(val) (((val) & 0x1) << 15)
1449 +#define LTQ_ES_STRM_CTL_REG_STORM_B_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_B) >> 15) & 0x1)
1450 +#define LTQ_ES_STRM_CTL_REG_STORM_B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_B) | (((val) & 0x1) << 15))
1451 +/* Storm Enable for Multicast Packets (14) */
1452 +#define LTQ_ES_STRM_CTL_REG_STORM_M (0x1 << 14)
1453 +#define LTQ_ES_STRM_CTL_REG_STORM_M_VAL(val) (((val) & 0x1) << 14)
1454 +#define LTQ_ES_STRM_CTL_REG_STORM_M_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_M) >> 14) & 0x1)
1455 +#define LTQ_ES_STRM_CTL_REG_STORM_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_M) | (((val) & 0x1) << 14))
1456 +/* Storm Enable for Un-learned Unicast Packets (13) */
1457 +#define LTQ_ES_STRM_CTL_REG_STORM_U (0x1 << 13)
1458 +#define LTQ_ES_STRM_CTL_REG_STORM_U_VAL(val) (((val) & 0x1) << 13)
1459 +#define LTQ_ES_STRM_CTL_REG_STORM_U_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_U) >> 13) & 0x1)
1460 +#define LTQ_ES_STRM_CTL_REG_STORM_U_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_U) | (((val) & 0x1) << 13))
1461 +/* 100M Threshold (12:0) */
1462 +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH (0x1fff)
1463 +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_VAL(val) (((val) & 0x1fff) << 0)
1464 +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_100_TH) >> 0) & 0x1fff)
1465 +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_100_TH) | (((val) & 0x1fff) << 0))
1466 +
1467 +/*******************************************************************************
1468 + * RGMII/GMII Port Control Register
1469 + ******************************************************************************/
1470 +
1471 +/* Management Clock Select (31:24) */
1472 +#define LTQ_ES_RGMII_CTL_REG_MCS (0xff << 24)
1473 +#define LTQ_ES_RGMII_CTL_REG_MCS_VAL(val) (((val) & 0xff) << 24)
1474 +#define LTQ_ES_RGMII_CTL_REG_MCS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_MCS) >> 24) & 0xff)
1475 +#define LTQ_ES_RGMII_CTL_REG_MCS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_MCS) | (((val) & 0xff) << 24))
1476 +/* Interface Selection (19:18) */
1477 +#define LTQ_ES_RGMII_CTL_REG_IS (0x3 << 18)
1478 +#define LTQ_ES_RGMII_CTL_REG_IS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_IS) >> 18) & 0x3)
1479 +/* Port 1 RGMII Rx Clock Delay (17:16) */
1480 +#define LTQ_ES_RGMII_CTL_REG_P1RDLY (0x3 << 16)
1481 +#define LTQ_ES_RGMII_CTL_REG_P1RDLY_VAL(val) (((val) & 0x3) << 16)
1482 +#define LTQ_ES_RGMII_CTL_REG_P1RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1RDLY) >> 16) & 0x3)
1483 +#define LTQ_ES_RGMII_CTL_REG_P1RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1RDLY) | (((val) & 0x3) << 16))
1484 +/* Port 1 RGMII Tx Clock Delay (15:14) */
1485 +#define LTQ_ES_RGMII_CTL_REG_P1TDLY (0x3 << 14)
1486 +#define LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(val) (((val) & 0x3) << 14)
1487 +#define LTQ_ES_RGMII_CTL_REG_P1TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1TDLY) >> 14) & 0x3)
1488 +#define LTQ_ES_RGMII_CTL_REG_P1TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1TDLY) | (((val) & 0x3) << 14))
1489 +/* Port 1 Speed (13:12) */
1490 +#define LTQ_ES_RGMII_CTL_REG_P1SPD (0x3 << 12)
1491 +#define LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(val) (((val) & 0x3) << 12)
1492 +#define LTQ_ES_RGMII_CTL_REG_P1SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1SPD) >> 12) & 0x3)
1493 +#define LTQ_ES_RGMII_CTL_REG_P1SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1SPD) | (((val) & 0x3) << 12))
1494 +/* Port 1 Duplex mode (11) */
1495 +#define LTQ_ES_RGMII_CTL_REG_P1DUP (0x1 << 11)
1496 +#define LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(val) (((val) & 0x1) << 11)
1497 +#define LTQ_ES_RGMII_CTL_REG_P1DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1DUP) >> 11) & 0x1)
1498 +#define LTQ_ES_RGMII_CTL_REG_P1DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1DUP) | (((val) & 0x1) << 11))
1499 +/* Port 1 Flow Control Enable (10) */
1500 +#define LTQ_ES_RGMII_CTL_REG_P1FCE (0x1 << 10)
1501 +#define LTQ_ES_RGMII_CTL_REG_P1FCE_VAL(val) (((val) & 0x1) << 10)
1502 +#define LTQ_ES_RGMII_CTL_REG_P1FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1FCE) >> 10) & 0x1)
1503 +#define LTQ_ES_RGMII_CTL_REG_P1FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1FCE) | (((val) & 0x1) << 10))
1504 +/* Port 0 RGMII Rx Clock Delay (7:6) */
1505 +#define LTQ_ES_RGMII_CTL_REG_P0RDLY (0x3 << 6)
1506 +#define LTQ_ES_RGMII_CTL_REG_P0RDLY_VAL(val) (((val) & 0x3) << 6)
1507 +#define LTQ_ES_RGMII_CTL_REG_P0RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0RDLY) >> 6) & 0x3)
1508 +#define LTQ_ES_RGMII_CTL_REG_P0RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0RDLY) | (((val) & 0x3) << 6))
1509 +/* Port 0 RGMII Tx Clock Delay (5:4) */
1510 +#define LTQ_ES_RGMII_CTL_REG_P0TDLY (0x3 << 4)
1511 +#define LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(val) (((val) & 0x3) << 4)
1512 +#define LTQ_ES_RGMII_CTL_REG_P0TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0TDLY) >> 4) & 0x3)
1513 +#define LTQ_ES_RGMII_CTL_REG_P0TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0TDLY) | (((val) & 0x3) << 4))
1514 +/* Port 0 Speed (3:2) */
1515 +#define LTQ_ES_RGMII_CTL_REG_P0SPD (0x3 << 2)
1516 +#define LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(val) (((val) & 0x3) << 2)
1517 +#define LTQ_ES_RGMII_CTL_REG_P0SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0SPD) >> 2) & 0x3)
1518 +#define LTQ_ES_RGMII_CTL_REG_P0SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0SPD) | (((val) & 0x3) << 2))
1519 +/* Port 0 Duplex mode (1) */
1520 +#define LTQ_ES_RGMII_CTL_REG_P0DUP (0x1 << 1)
1521 +#define LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(val) (((val) & 0x1) << 1)
1522 +#define LTQ_ES_RGMII_CTL_REG_P0DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0DUP) >> 1) & 0x1)
1523 +#define LTQ_ES_RGMII_CTL_REG_P0DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0DUP) | (((val) & 0x1) << 1))
1524 +/* Port 0 Flow Control Enable (0) */
1525 +#define LTQ_ES_RGMII_CTL_REG_P0FCE (0x1)
1526 +#define LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(val) (((val) & 0x1) << 0)
1527 +#define LTQ_ES_RGMII_CTL_REG_P0FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0FCE) >> 0) & 0x1)
1528 +#define LTQ_ES_RGMII_CTL_REG_P0FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0FCE) | (((val) & 0x1) << 0))
1529 +
1530 +/*******************************************************************************
1531 + * 802.1p Priority Map Register
1532 + ******************************************************************************/
1533 +
1534 +/* Priority Queue 7 (15:14) */
1535 +#define LTQ_ES_PRT_1P_REG_1PPQ7 (0x3 << 14)
1536 +#define LTQ_ES_PRT_1P_REG_1PPQ7_VAL(val) (((val) & 0x3) << 14)
1537 +#define LTQ_ES_PRT_1P_REG_1PPQ7_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ7) >> 14) & 0x3)
1538 +#define LTQ_ES_PRT_1P_REG_1PPQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ7) | (((val) & 0x3) << 14))
1539 +/* Priority Queue 6 (13:12) */
1540 +#define LTQ_ES_PRT_1P_REG_1PPQ6 (0x3 << 12)
1541 +#define LTQ_ES_PRT_1P_REG_1PPQ6_VAL(val) (((val) & 0x3) << 12)
1542 +#define LTQ_ES_PRT_1P_REG_1PPQ6_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ6) >> 12) & 0x3)
1543 +#define LTQ_ES_PRT_1P_REG_1PPQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ6) | (((val) & 0x3) << 12))
1544 +/* Priority Queue 5 (11:10) */
1545 +#define LTQ_ES_PRT_1P_REG_1PPQ5 (0x3 << 10)
1546 +#define LTQ_ES_PRT_1P_REG_1PPQ5_VAL(val) (((val) & 0x3) << 10)
1547 +#define LTQ_ES_PRT_1P_REG_1PPQ5_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ5) >> 10) & 0x3)
1548 +#define LTQ_ES_PRT_1P_REG_1PPQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ5) | (((val) & 0x3) << 10))
1549 +/* Priority Queue 4 (9:8) */
1550 +#define LTQ_ES_PRT_1P_REG_1PPQ4 (0x3 << 8)
1551 +#define LTQ_ES_PRT_1P_REG_1PPQ4_VAL(val) (((val) & 0x3) << 8)
1552 +#define LTQ_ES_PRT_1P_REG_1PPQ4_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ4) >> 8) & 0x3)
1553 +#define LTQ_ES_PRT_1P_REG_1PPQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ4) | (((val) & 0x3) << 8))
1554 +/* Priority Queue 3 (7:6) */
1555 +#define LTQ_ES_PRT_1P_REG_1PPQ3 (0x3 << 6)
1556 +#define LTQ_ES_PRT_1P_REG_1PPQ3_VAL(val) (((val) & 0x3) << 6)
1557 +#define LTQ_ES_PRT_1P_REG_1PPQ3_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ3) >> 6) & 0x3)
1558 +#define LTQ_ES_PRT_1P_REG_1PPQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ3) | (((val) & 0x3) << 6))
1559 +/* Priority Queue 2 (5:4) */
1560 +#define LTQ_ES_PRT_1P_REG_1PPQ2 (0x3 << 4)
1561 +#define LTQ_ES_PRT_1P_REG_1PPQ2_VAL(val) (((val) & 0x3) << 4)
1562 +#define LTQ_ES_PRT_1P_REG_1PPQ2_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ2) >> 4) & 0x3)
1563 +#define LTQ_ES_PRT_1P_REG_1PPQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ2) | (((val) & 0x3) << 4))
1564 +/* Priority Queue 1 (3:2) */
1565 +#define LTQ_ES_PRT_1P_REG_1PPQ1 (0x3 << 2)
1566 +#define LTQ_ES_PRT_1P_REG_1PPQ1_VAL(val) (((val) & 0x3) << 2)
1567 +#define LTQ_ES_PRT_1P_REG_1PPQ1_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ1) >> 2) & 0x3)
1568 +#define LTQ_ES_PRT_1P_REG_1PPQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ1) | (((val) & 0x3) << 2))
1569 +/* Priority Queue 0 (1:0) */
1570 +#define LTQ_ES_PRT_1P_REG_1PPQ0 (0x3)
1571 +#define LTQ_ES_PRT_1P_REG_1PPQ0_VAL(val) (((val) & 0x3) << 0)
1572 +#define LTQ_ES_PRT_1P_REG_1PPQ0_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ0) >> 0) & 0x3)
1573 +#define LTQ_ES_PRT_1P_REG_1PPQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ0) | (((val) & 0x3) << 0))
1574 +
1575 +/*******************************************************************************
1576 + * Global Bucket Size Base counter
1577 + ******************************************************************************/
1578 +
1579 +/* Reserved (31:18) */
1580 +#define LTQ_ES_GBKT_SZBS_REG_REV (0x3fff << 18)
1581 +#define LTQ_ES_GBKT_SZBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_REV) >> 18) & 0x3fff)
1582 +/* Base[17:0] (17:0) */
1583 +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0 (0x3ffff)
1584 +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_VAL(val) (((val) & 0x3ffff) << 0)
1585 +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_BASE17_0) >> 0) & 0x3ffff)
1586 +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZBS_REG_BASE17_0) | (((val) & 0x3ffff) << 0))
1587 +
1588 +/*******************************************************************************
1589 + * Global Bucket Size Extend Base Counter
1590 + ******************************************************************************/
1591 +
1592 +/* Reserved (31:18) */
1593 +#define LTQ_ES_GBKT_SZEBS_REG_REV (0x3fff << 18)
1594 +#define LTQ_ES_GBKT_SZEBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_REV) >> 18) & 0x3fff)
1595 +/* Extend Base[17:0] (17:0) */
1596 +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0 (0x3ffff)
1597 +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_VAL(val) (((val) & 0x3ffff) << 0)
1598 +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) >> 0) & 0x3ffff)
1599 +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) | (((val) & 0x3ffff) << 0))
1600 +
1601 +/*******************************************************************************
1602 + * Buffer Threshold Register
1603 + ******************************************************************************/
1604 +
1605 +/* Port Unfull Offset 3 (31:30) */
1606 +#define LTQ_ES_BF_TH_REG_PUO3 (0x3 << 30)
1607 +#define LTQ_ES_BF_TH_REG_PUO3_VAL(val) (((val) & 0x3) << 30)
1608 +#define LTQ_ES_BF_TH_REG_PUO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO3) >> 30) & 0x3)
1609 +#define LTQ_ES_BF_TH_REG_PUO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO3) | (((val) & 0x3) << 30))
1610 +/* Port Unfull Offset 2 (29:28) */
1611 +#define LTQ_ES_BF_TH_REG_PUO2 (0x3 << 28)
1612 +#define LTQ_ES_BF_TH_REG_PUO2_VAL(val) (((val) & 0x3) << 28)
1613 +#define LTQ_ES_BF_TH_REG_PUO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO2) >> 28) & 0x3)
1614 +#define LTQ_ES_BF_TH_REG_PUO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO2) | (((val) & 0x3) << 28))
1615 +/* Port Unfull Offset 1 (27:26) */
1616 +#define LTQ_ES_BF_TH_REG_PUO1 (0x3 << 26)
1617 +#define LTQ_ES_BF_TH_REG_PUO1_VAL(val) (((val) & 0x3) << 26)
1618 +#define LTQ_ES_BF_TH_REG_PUO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO1) >> 26) & 0x3)
1619 +#define LTQ_ES_BF_TH_REG_PUO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO1) | (((val) & 0x3) << 26))
1620 +/* Port Unfull Offset 0 (25:24) */
1621 +#define LTQ_ES_BF_TH_REG_PUO0 (0x3 << 24)
1622 +#define LTQ_ES_BF_TH_REG_PUO0_VAL(val) (((val) & 0x3) << 24)
1623 +#define LTQ_ES_BF_TH_REG_PUO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO0) >> 24) & 0x3)
1624 +#define LTQ_ES_BF_TH_REG_PUO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO0) | (((val) & 0x3) << 24))
1625 +/* Port Full Offset 3 (23:22) */
1626 +#define LTQ_ES_BF_TH_REG_PFO3 (0x3 << 22)
1627 +#define LTQ_ES_BF_TH_REG_PFO3_VAL(val) (((val) & 0x3) << 22)
1628 +#define LTQ_ES_BF_TH_REG_PFO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO3) >> 22) & 0x3)
1629 +#define LTQ_ES_BF_TH_REG_PFO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO3) | (((val) & 0x3) << 22))
1630 +/* Port Full Offset 2 (21:20) */
1631 +#define LTQ_ES_BF_TH_REG_PFO2 (0x3 << 20)
1632 +#define LTQ_ES_BF_TH_REG_PFO2_VAL(val) (((val) & 0x3) << 20)
1633 +#define LTQ_ES_BF_TH_REG_PFO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO2) >> 20) & 0x3)
1634 +#define LTQ_ES_BF_TH_REG_PFO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO2) | (((val) & 0x3) << 20))
1635 +/* Port Full Offset 1 (19:18) */
1636 +#define LTQ_ES_BF_TH_REG_PFO1 (0x3 << 18)
1637 +#define LTQ_ES_BF_TH_REG_PFO1_VAL(val) (((val) & 0x3) << 18)
1638 +#define LTQ_ES_BF_TH_REG_PFO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO1) >> 18) & 0x3)
1639 +#define LTQ_ES_BF_TH_REG_PFO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO1) | (((val) & 0x3) << 18))
1640 +/* Port Full Offset 0 (17:16) */
1641 +#define LTQ_ES_BF_TH_REG_PFO0 (0x3 << 16)
1642 +#define LTQ_ES_BF_TH_REG_PFO0_VAL(val) (((val) & 0x3) << 16)
1643 +#define LTQ_ES_BF_TH_REG_PFO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO0) >> 16) & 0x3)
1644 +#define LTQ_ES_BF_TH_REG_PFO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO0) | (((val) & 0x3) << 16))
1645 +/* Reserved (15:14) */
1646 +#define LTQ_ES_BF_TH_REG_RES (0x3 << 14)
1647 +#define LTQ_ES_BF_TH_REG_RES_GET(val) ((((val) & LTQ_ES_BF_TH_REG_RES) >> 14) & 0x3)
1648 +/* Total Low Add (13) */
1649 +#define LTQ_ES_BF_TH_REG_TLA (0x1 << 13)
1650 +#define LTQ_ES_BF_TH_REG_TLA_VAL(val) (((val) & 0x1) << 13)
1651 +#define LTQ_ES_BF_TH_REG_TLA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLA) >> 13) & 0x1)
1652 +#define LTQ_ES_BF_TH_REG_TLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLA) | (((val) & 0x1) << 13))
1653 +/* Total High Add (12) */
1654 +#define LTQ_ES_BF_TH_REG_THA (0x1 << 12)
1655 +#define LTQ_ES_BF_TH_REG_THA_VAL(val) (((val) & 0x1) << 12)
1656 +#define LTQ_ES_BF_TH_REG_THA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THA) >> 12) & 0x1)
1657 +#define LTQ_ES_BF_TH_REG_THA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THA) | (((val) & 0x1) << 12))
1658 +/* Total Low Offset (11:10) */
1659 +#define LTQ_ES_BF_TH_REG_TLO (0x3 << 10)
1660 +#define LTQ_ES_BF_TH_REG_TLO_VAL(val) (((val) & 0x3) << 10)
1661 +#define LTQ_ES_BF_TH_REG_TLO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLO) >> 10) & 0x3)
1662 +#define LTQ_ES_BF_TH_REG_TLO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLO) | (((val) & 0x3) << 10))
1663 +/* Total High Offset (9:8) */
1664 +#define LTQ_ES_BF_TH_REG_THO (0x3 << 8)
1665 +#define LTQ_ES_BF_TH_REG_THO_VAL(val) (((val) & 0x3) << 8)
1666 +#define LTQ_ES_BF_TH_REG_THO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THO) >> 8) & 0x3)
1667 +#define LTQ_ES_BF_TH_REG_THO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THO) | (((val) & 0x3) << 8))
1668 +/* Port Unfull Add (7:4) */
1669 +#define LTQ_ES_BF_TH_REG_PUA (0xf << 4)
1670 +#define LTQ_ES_BF_TH_REG_PUA_VAL(val) (((val) & 0xf) << 4)
1671 +#define LTQ_ES_BF_TH_REG_PUA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUA) >> 4) & 0xf)
1672 +#define LTQ_ES_BF_TH_REG_PUA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUA) | (((val) & 0xf) << 4))
1673 +/* Port Full Add (3:0) */
1674 +#define LTQ_ES_BF_TH_REG_PFA (0xf)
1675 +#define LTQ_ES_BF_TH_REG_PFA_VAL(val) (((val) & 0xf) << 0)
1676 +#define LTQ_ES_BF_TH_REG_PFA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFA) >> 0) & 0xf)
1677 +#define LTQ_ES_BF_TH_REG_PFA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFA) | (((val) & 0xf) << 0))
1678 +
1679 +/*******************************************************************************
1680 + * PMAC Header Control Register
1681 + ******************************************************************************/
1682 +
1683 +/* Reserved (31:22) */
1684 +#define LTQ_ES_PMAC_HD_CTL_RES (0x3ff << 22)
1685 +#define LTQ_ES_PMAC_HD_CTL_RES_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RES) >> 22) & 0x3ff)
1686 +/* Remove Layer-2 Header from Packets Going from PMAC to DMA (21) */
1687 +#define LTQ_ES_PMAC_HD_CTL_RL2 (0x1 << 21)
1688 +#define LTQ_ES_PMAC_HD_CTL_RL2_VAL(val) (((val) & 0x1) << 21)
1689 +#define LTQ_ES_PMAC_HD_CTL_RL2_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RL2) >> 21) & 0x1)
1690 +#define LTQ_ES_PMAC_HD_CTL_RL2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RL2) | (((val) & 0x1) << 21))
1691 +/* Remove CRC from Packets Going from PMAC to DMA (20) */
1692 +#define LTQ_ES_PMAC_HD_CTL_RC (0x1 << 20)
1693 +#define LTQ_ES_PMAC_HD_CTL_RC_VAL(val) (((val) & 0x1) << 20)
1694 +#define LTQ_ES_PMAC_HD_CTL_RC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RC) >> 20) & 0x1)
1695 +#define LTQ_ES_PMAC_HD_CTL_RC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RC) | (((val) & 0x1) << 20))
1696 +/* Status Header for Packets from PMAC to DMA (19) */
1697 +#define LTQ_ES_PMAC_HD_CTL_AS (0x1 << 19)
1698 +#define LTQ_ES_PMAC_HD_CTL_AS_VAL(val) (((val) & 0x1) << 19)
1699 +#define LTQ_ES_PMAC_HD_CTL_AS_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AS) >> 19) & 0x1)
1700 +#define LTQ_ES_PMAC_HD_CTL_AS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AS) | (((val) & 0x1) << 19))
1701 +/* Add CRC for packets from DMA to PMAC (18) */
1702 +#define LTQ_ES_PMAC_HD_CTL_AC (0x1 << 18)
1703 +#define LTQ_ES_PMAC_HD_CTL_AC_VAL(val) (((val) & 0x1) << 18)
1704 +#define LTQ_ES_PMAC_HD_CTL_AC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AC) >> 18) & 0x1)
1705 +#define LTQ_ES_PMAC_HD_CTL_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AC) | (((val) & 0x1) << 18))
1706 +/* Contains the length/type value to the added to packets from DMA to PMAC (17:2) */
1707 +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN (0xffff << 2)
1708 +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_VAL(val) (((val) & 0xffff) << 2)
1709 +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TYPE_LEN) >> 2) & 0xffff)
1710 +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TYPE_LEN) | (((val) & 0xffff) << 2))
1711 +/* Add TAG to Packets from DMA to PMAC (1) */
1712 +#define LTQ_ES_PMAC_HD_CTL_TAG (0x1 << 1)
1713 +#define LTQ_ES_PMAC_HD_CTL_TAG_VAL(val) (((val) & 0x1) << 1)
1714 +#define LTQ_ES_PMAC_HD_CTL_TAG_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TAG) >> 1) & 0x1)
1715 +#define LTQ_ES_PMAC_HD_CTL_TAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TAG) | (((val) & 0x1) << 1))
1716 +/* ADD Header to Packets from DMA to PMAC (0) */
1717 +#define LTQ_ES_PMAC_HD_CTL_ADD (0x1)
1718 +#define LTQ_ES_PMAC_HD_CTL_ADD_VAL(val) (((val) & 0x1) << 0)
1719 +#define LTQ_ES_PMAC_HD_CTL_ADD_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_ADD) >> 0) & 0x1)
1720 +#define LTQ_ES_PMAC_HD_CTL_ADD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_ADD) | (((val) & 0x1) << 0))
1721 +
1722 +/*******************************************************************************
1723 + * PMAC Source Address Register 1
1724 + ******************************************************************************/
1725 +
1726 +/* Source Address to be inserted as a part of the Ethernet header. (15:0) */
1727 +#define LTQ_ES_PMAC_SA1_SA_47_32 (0xffff)
1728 +#define LTQ_ES_PMAC_SA1_SA_47_32_VAL(val) (((val) & 0xffff) << 0)
1729 +#define LTQ_ES_PMAC_SA1_SA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_SA1_SA_47_32) >> 0) & 0xffff)
1730 +#define LTQ_ES_PMAC_SA1_SA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA1_SA_47_32) | (((val) & 0xffff) << 0))
1731 +
1732 +/*******************************************************************************
1733 + * PMAC Source Address Register 2
1734 + ******************************************************************************/
1735 +
1736 +/* Source Address (31:0) */
1737 +#define LTQ_ES_PMAC_SA2_SA_31_0 (0xFFFFFFFFL)
1738 +#define LTQ_ES_PMAC_SA2_SA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0)
1739 +#define LTQ_ES_PMAC_SA2_SA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_SA2_SA_31_0) >> 0) & 0xFFFFFFFFL)
1740 +#define LTQ_ES_PMAC_SA2_SA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA2_SA_31_0) | (((val) & 0xFFFFFFFFL) << 0))
1741 +
1742 +/*******************************************************************************
1743 + * PMAC Destination Address Register 1
1744 + ******************************************************************************/
1745 +
1746 +/* Destination Address (15:0) */
1747 +#define LTQ_ES_PMAC_DA1_DA_47_32 (0xffff)
1748 +#define LTQ_ES_PMAC_DA1_DA_47_32_VAL(val) (((val) & 0xffff) << 0)
1749 +#define LTQ_ES_PMAC_DA1_DA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_DA1_DA_47_32) >> 0) & 0xffff)
1750 +#define LTQ_ES_PMAC_DA1_DA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA1_DA_47_32) | (((val) & 0xffff) << 0))
1751 +
1752 +/*******************************************************************************
1753 + * PMAC Destination Address Register 2
1754 + ******************************************************************************/
1755 +
1756 +/* Destination Address to be inserted as a part of the Ethernet header. (31:0) */
1757 +#define LTQ_ES_PMAC_DA2_DA_31_0 (0xFFFFFFFFL)
1758 +#define LTQ_ES_PMAC_DA2_DA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0)
1759 +#define LTQ_ES_PMAC_DA2_DA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_DA2_DA_31_0) >> 0) & 0xFFFFFFFFL)
1760 +#define LTQ_ES_PMAC_DA2_DA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA2_DA_31_0) | (((val) & 0xFFFFFFFFL) << 0))
1761 +
1762 +/*******************************************************************************
1763 + * PMAC VLAN Register
1764 + ******************************************************************************/
1765 +
1766 +/* Priority to be inserted as a part of VLAN tag (15:13) */
1767 +#define LTQ_ES_PMAC_VLAN_PRI (0x7 << 13)
1768 +#define LTQ_ES_PMAC_VLAN_PRI_VAL(val) (((val) & 0x7) << 13)
1769 +#define LTQ_ES_PMAC_VLAN_PRI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_PRI) >> 13) & 0x7)
1770 +#define LTQ_ES_PMAC_VLAN_PRI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_PRI) | (((val) & 0x7) << 13))
1771 +/* CFI bit to be inserted as a part of VLAN tag (12) */
1772 +#define LTQ_ES_PMAC_VLAN_CFI (0x1 << 12)
1773 +#define LTQ_ES_PMAC_VLAN_CFI_VAL(val) (((val) & 0x1) << 12)
1774 +#define LTQ_ES_PMAC_VLAN_CFI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_CFI) >> 12) & 0x1)
1775 +#define LTQ_ES_PMAC_VLAN_CFI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_CFI) | (((val) & 0x1) << 12))
1776 +/* VLAN ID to be inserted as a part of VLAN tag (11:0) */
1777 +#define LTQ_ES_PMAC_VLAN_VLAN_ID (0xfff)
1778 +#define LTQ_ES_PMAC_VLAN_VLAN_ID_VAL(val) (((val) & 0xfff) << 0)
1779 +#define LTQ_ES_PMAC_VLAN_VLAN_ID_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_VLAN_ID) >> 0) & 0xfff)
1780 +#define LTQ_ES_PMAC_VLAN_VLAN_ID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_VLAN ID) | (((val) & 0xfff) << 0))
1781 +
1782 +/*******************************************************************************
1783 + * PMAC TX IPG Counter Register
1784 + ******************************************************************************/
1785 +
1786 +/* IPG Counter (7:0) */
1787 +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT (0xff)
1788 +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0)
1789 +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_TX_IPG_IPG_CNT) >> 0) & 0xff)
1790 +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_TX_IPG_IPG_CNT) | (((val) & 0xff) << 0))
1791 +
1792 +/*******************************************************************************
1793 + * PMAC RX IPG Counter Register
1794 + ******************************************************************************/
1795 +
1796 +/* IPG Counter (7:0) */
1797 +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT (0xff)
1798 +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0)
1799 +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_RX_IPG_IPG_CNT) >> 0) & 0xff)
1800 +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_RX_IPG_IPG_CNT) | (((val) & 0xff) << 0))
1801 +
1802 +/*******************************************************************************
1803 + * Address Table Control 0 Register
1804 + ******************************************************************************/
1805 +
1806 +/* Address [31:0] (31:0) */
1807 +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0 (0xFFFFFFFFL)
1808 +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0)
1809 +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) >> 0) & 0xFFFFFFFFL)
1810 +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) | (((val) & 0xFFFFFFFFL) << 0))
1811 +
1812 +/*******************************************************************************
1813 + * Address Table Control 1 Register
1814 + ******************************************************************************/
1815 +
1816 +/* Port Map (22:20) */
1817 +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP (0x7 << 20)
1818 +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(val) (((val) & 0x7) << 20)
1819 +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_PMAP) >> 20) & 0x7)
1820 +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_PMAP) | (((val) & 0x7) << 20))
1821 +/* FID group (17:16) */
1822 +#define LTQ_ES_ADR_TB_CTL1_REG_FID (0x3 << 16)
1823 +#define LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(val) (((val) & 0x3) << 16)
1824 +#define LTQ_ES_ADR_TB_CTL1_REG_FID_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_FID) >> 16) & 0x3)
1825 +#define LTQ_ES_ADR_TB_CTL1_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_FID) | (((val) & 0x3) << 16))
1826 +/* Address [47:32] (15:0) */
1827 +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32 (0xffff)
1828 +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_VAL(val) (((val) & 0xffff) << 0)
1829 +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) >> 0) & 0xffff)
1830 +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) | (((val) & 0xffff) << 0))
1831 +
1832 +/*******************************************************************************
1833 + * Address Table Control 2 Register
1834 + ******************************************************************************/
1835 +
1836 +/* Command (22:20) */
1837 +#define LTQ_ES_ADR_TB_CTL2_REG_CMD (0x7 << 20)
1838 +#define LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(val) (((val) & 0x7) << 20)
1839 +#define LTQ_ES_ADR_TB_CTL2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_CMD) >> 20) & 0x7)
1840 +#define LTQ_ES_ADR_TB_CTL2_REG_CMD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_CMD) | (((val) & 0x7) << 20))
1841 +/* Access Control (19:16) */
1842 +#define LTQ_ES_ADR_TB_CTL2_REG_AC (0xf << 16)
1843 +#define LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(val) (((val) & 0xf) << 16)
1844 +#define LTQ_ES_ADR_TB_CTL2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_AC) >> 16) & 0xf)
1845 +#define LTQ_ES_ADR_TB_CTL2_REG_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_AC) | (((val) & 0xf) << 16))
1846 +/* Info Type: Static address (12) */
1847 +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT (0x1 << 12)
1848 +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_VAL(val) (((val) & 0x1) << 12)
1849 +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_INFOT) >> 12) & 0x1)
1850 +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_INFOT) | (((val) & 0x1) << 12))
1851 +/* Info_Ctrl/Age Timer (10:0) */
1852 +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT (0x7ff)
1853 +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_VAL(val) (((val) & 0x7ff) << 0)
1854 +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_ITAT) >> 0) & 0x7ff)
1855 +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_ITAT) | (((val) & 0x7ff) << 0))
1856 +
1857 +/*******************************************************************************
1858 + * Address Table Status 0 Register
1859 + ******************************************************************************/
1860 +
1861 +/* Address [31:0] (31:0) */
1862 +#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0 (0xFFFFFFFFL)
1863 +#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0) >> 0) & 0xFFFFFFFFL)
1864 +
1865 +/*******************************************************************************
1866 + * Address Table Status 1 Register
1867 + ******************************************************************************/
1868 +
1869 +/* Port Map (22:20) */
1870 +#define LTQ_ES_ADR_TB_ST1_REG_PMAPS (0x7 << 20)
1871 +#define LTQ_ES_ADR_TB_ST1_REG_PMAPS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_PMAPS) >> 20) & 0x7)
1872 +/* FID group (17:16) */
1873 +#define LTQ_ES_ADR_TB_ST1_REG_FIDS (0x3 << 16)
1874 +#define LTQ_ES_ADR_TB_ST1_REG_FIDS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_FIDS) >> 16) & 0x3)
1875 +/* Address [47:32] (15:0) */
1876 +#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32 (0xffff)
1877 +#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32) >> 0) & 0xffff)
1878 +
1879 +/*******************************************************************************
1880 + * Address Table Status 2 Register
1881 + ******************************************************************************/
1882 +
1883 +/* Busy (31) */
1884 +#define LTQ_ES_ADR_TB_ST2_REG_BUSY (0x1 << 31)
1885 +#define LTQ_ES_ADR_TB_ST2_REG_BUSY_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BUSY) >> 31) & 0x1)
1886 +/* Result (30:28) */
1887 +#define LTQ_ES_ADR_TB_ST2_REG_RSLT (0x7 << 28)
1888 +#define LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_RSLT) >> 28) & 0x7)
1889 +/* Command (22:20) */
1890 +#define LTQ_ES_ADR_TB_ST2_REG_CMD (0x7 << 20)
1891 +#define LTQ_ES_ADR_TB_ST2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_CMD) >> 20) & 0x7)
1892 +/* Access Control (19:16) */
1893 +#define LTQ_ES_ADR_TB_ST2_REG_AC (0xf << 16)
1894 +#define LTQ_ES_ADR_TB_ST2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_AC) >> 16) & 0xf)
1895 +/* Bad Status (14) */
1896 +#define LTQ_ES_ADR_TB_ST2_REG_BAD (0x1 << 14)
1897 +#define LTQ_ES_ADR_TB_ST2_REG_BAD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BAD) >> 14) & 0x1)
1898 +/* Occupy (13) */
1899 +#define LTQ_ES_ADR_TB_ST2_REG_OCP (0x1 << 13)
1900 +#define LTQ_ES_ADR_TB_ST2_REG_OCP_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_OCP) >> 13) & 0x1)
1901 +/* Info Type: Static address (12) */
1902 +#define LTQ_ES_ADR_TB_ST2_REG_INFOTS (0x1 << 12)
1903 +#define LTQ_ES_ADR_TB_ST2_REG_INFOTS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_INFOTS) >> 12) & 0x1)
1904 +/* Info_Ctrl/Age Timer Status (10:0) */
1905 +#define LTQ_ES_ADR_TB_ST2_REG_ITATS (0x7ff)
1906 +#define LTQ_ES_ADR_TB_ST2_REG_ITATS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_ITATS) >> 0) & 0x7ff)
1907 +
1908 +/*******************************************************************************
1909 + * RMON Counter Control Register
1910 + ******************************************************************************/
1911 +
1912 +/* Reserved (31:12) */
1913 +#define LTQ_ES_RMON_CTL_REG_RES (0xfffff << 12)
1914 +#define LTQ_ES_RMON_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_RES) >> 12) & 0xfffff)
1915 +/* Busy/Access Start (11) */
1916 +#define LTQ_ES_RMON_CTL_REG_BAS (0x1 << 11)
1917 +#define LTQ_ES_RMON_CTL_REG_BAS_VAL(val) (((val) & 0x1) << 11)
1918 +#define LTQ_ES_RMON_CTL_REG_BAS_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_BAS) >> 11) & 0x1)
1919 +#define LTQ_ES_RMON_CTL_REG_BAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_BAS) | (((val) & 0x1) << 11))
1920 +/* Command for access counter (10:9) */
1921 +#define LTQ_ES_RMON_CTL_REG_CAC (0x3 << 9)
1922 +#define LTQ_ES_RMON_CTL_REG_CAC_VAL(val) (((val) & 0x3) << 9)
1923 +#define LTQ_ES_RMON_CTL_REG_CAC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_CAC) >> 9) & 0x3)
1924 +#define LTQ_ES_RMON_CTL_REG_CAC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_CAC) | (((val) & 0x3) << 9))
1925 +/* Port (8:6) */
1926 +#define LTQ_ES_RMON_CTL_REG_PORTC (0x7 << 6)
1927 +#define LTQ_ES_RMON_CTL_REG_PORTC_VAL(val) (((val) & 0x7) << 6)
1928 +#define LTQ_ES_RMON_CTL_REG_PORTC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_PORTC) >> 6) & 0x7)
1929 +#define LTQ_ES_RMON_CTL_REG_PORTC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_PORTC) | (((val) & 0x7) << 6))
1930 +/* Counter Offset (5:0) */
1931 +#define LTQ_ES_RMON_CTL_REG_OFFSET (0x3f)
1932 +#define LTQ_ES_RMON_CTL_REG_OFFSET_VAL(val) (((val) & 0x3f) << 0)
1933 +#define LTQ_ES_RMON_CTL_REG_OFFSET_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_OFFSET) >> 0) & 0x3f)
1934 +#define LTQ_ES_RMON_CTL_REG_OFFSET_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_OFFSET) | (((val) & 0x3f) << 0))
1935 +
1936 +/*******************************************************************************
1937 + * RMON Counter Status Register
1938 + ******************************************************************************/
1939 +
1940 +/* Counter [31:0] or Counter[63:32] for byte count (31:0) */
1941 +#define LTQ_ES_RMON_ST_REG_COUNTER (0xFFFFFFFFL)
1942 +#define LTQ_ES_RMON_ST_REG_COUNTER_GET(val) ((((val) & LTQ_ES_RMON_ST_REG_COUNTER) >> 0) & 0xFFFFFFFFL)
1943 +
1944 +/*******************************************************************************
1945 + * MDIO Indirect Access Control
1946 + ******************************************************************************/
1947 +
1948 +/* The Write Data to the MDIO register (31:16) */
1949 +#define LTQ_ES_MDIO_CTL_REG_WD (0xffff << 16)
1950 +#define LTQ_ES_MDIO_CTL_REG_WD_VAL(val) (((val) & 0xffff) << 16)
1951 +#define LTQ_ES_MDIO_CTL_REG_WD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_WD) >> 16) & 0xffff)
1952 +#define LTQ_ES_MDIO_CTL_REG_WD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_WD) | (((val) & 0xffff) << 16))
1953 +/* Busy state (15) */
1954 +#define LTQ_ES_MDIO_CTL_REG_MBUSY (0x1 << 15)
1955 +#define LTQ_ES_MDIO_CTL_REG_MBUSY_VAL(val) (((val) & 0x1) << 15)
1956 +#define LTQ_ES_MDIO_CTL_REG_MBUSY_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_MBUSY) >> 15) & 0x1)
1957 +#define LTQ_ES_MDIO_CTL_REG_MBUSY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_MBUSY) | (((val) & 0x1) << 15))
1958 +/* Reserved (14:12) */
1959 +#define LTQ_ES_MDIO_CTL_REG_RES (0x7 << 12)
1960 +#define LTQ_ES_MDIO_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_RES) >> 12) & 0x7)
1961 +/* Operation Code (11:10) */
1962 +#define LTQ_ES_MDIO_CTL_REG_OP (0x3 << 10)
1963 +#define LTQ_ES_MDIO_CTL_REG_OP_VAL(val) (((val) & 0x3) << 10)
1964 +#define LTQ_ES_MDIO_CTL_REG_OP_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_OP) >> 10) & 0x3)
1965 +#define LTQ_ES_MDIO_CTL_REG_OP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_OP) | (((val) & 0x3) << 10))
1966 +/* PHY Address (9:5) */
1967 +#define LTQ_ES_MDIO_CTL_REG_PHYAD (0x1f << 5)
1968 +#define LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(val) (((val) & 0x1f) << 5)
1969 +#define LTQ_ES_MDIO_CTL_REG_PHYAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_PHYAD) >> 5) & 0x1f)
1970 +#define LTQ_ES_MDIO_CTL_REG_PHYAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_PHYAD) | (((val) & 0x1f) << 5))
1971 +/* Register Address (4:0) */
1972 +#define LTQ_ES_MDIO_CTL_REG_REGAD (0x1f)
1973 +#define LTQ_ES_MDIO_CTL_REG_REGAD_VAL(val) (((val) & 0x1f) << 0)
1974 +#define LTQ_ES_MDIO_CTL_REG_REGAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_REGAD) >> 0) & 0x1f)
1975 +#define LTQ_ES_MDIO_CTL_REG_REGAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_REGAD) | (((val) & 0x1f) << 0))
1976 +
1977 +/*******************************************************************************
1978 + * MDIO Indirect Read Data
1979 + ******************************************************************************/
1980 +
1981 +/* Reserved (31:16) */
1982 +#define LTQ_ES_MDIO_DATA_REG_RES (0xffff << 16)
1983 +#define LTQ_ES_MDIO_DATA_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RES) >> 16) & 0xffff)
1984 +/* The Read Data (15:0) */
1985 +#define LTQ_ES_MDIO_DATA_REG_RD (0xffff)
1986 +#define LTQ_ES_MDIO_DATA_REG_RD_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RD) >> 0) & 0xffff)
1987 +
1988 +/*******************************************************************************
1989 + * Type Filter Action
1990 + ******************************************************************************/
1991 +
1992 +/* Destination Queue for Type Filter 7 (31:30) */
1993 +#define LTQ_ES_TP_FLT_ACT_REG_QATF7 (0x3 << 30)
1994 +#define LTQ_ES_TP_FLT_ACT_REG_QATF7_VAL(val) (((val) & 0x3) << 30)
1995 +#define LTQ_ES_TP_FLT_ACT_REG_QATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF7) >> 30) & 0x3)
1996 +#define LTQ_ES_TP_FLT_ACT_REG_QATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF7) | (((val) & 0x3) << 30))
1997 +/* Destination Queue for Type Filter 6 (29:28) */
1998 +#define LTQ_ES_TP_FLT_ACT_REG_QATF6 (0x3 << 28)
1999 +#define LTQ_ES_TP_FLT_ACT_REG_QATF6_VAL(val) (((val) & 0x3) << 28)
2000 +#define LTQ_ES_TP_FLT_ACT_REG_QATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF6) >> 28) & 0x3)
2001 +#define LTQ_ES_TP_FLT_ACT_REG_QATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF6) | (((val) & 0x3) << 28))
2002 +/* Destination Queue for Type Filter 5 (27:26) */
2003 +#define LTQ_ES_TP_FLT_ACT_REG_QTF5 (0x3 << 26)
2004 +#define LTQ_ES_TP_FLT_ACT_REG_QTF5_VAL(val) (((val) & 0x3) << 26)
2005 +#define LTQ_ES_TP_FLT_ACT_REG_QTF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF5) >> 26) & 0x3)
2006 +#define LTQ_ES_TP_FLT_ACT_REG_QTF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF5) | (((val) & 0x3) << 26))
2007 +/* Destination Queue for Type Filter 4 (25:24) */
2008 +#define LTQ_ES_TP_FLT_ACT_REG_QTF4 (0x3 << 24)
2009 +#define LTQ_ES_TP_FLT_ACT_REG_QTF4_VAL(val) (((val) & 0x3) << 24)
2010 +#define LTQ_ES_TP_FLT_ACT_REG_QTF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF4) >> 24) & 0x3)
2011 +#define LTQ_ES_TP_FLT_ACT_REG_QTF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF4) | (((val) & 0x3) << 24))
2012 +/* Destination Queue for Type Filter 3 (23:22) */
2013 +#define LTQ_ES_TP_FLT_ACT_REG_QTF3 (0x3 << 22)
2014 +#define LTQ_ES_TP_FLT_ACT_REG_QTF3_VAL(val) (((val) & 0x3) << 22)
2015 +#define LTQ_ES_TP_FLT_ACT_REG_QTF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF3) >> 22) & 0x3)
2016 +#define LTQ_ES_TP_FLT_ACT_REG_QTF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF3) | (((val) & 0x3) << 22))
2017 +/* Destination Queue for Type Filter 2 (21:20) */
2018 +#define LTQ_ES_TP_FLT_ACT_REG_QTF2 (0x3 << 20)
2019 +#define LTQ_ES_TP_FLT_ACT_REG_QTF2_VAL(val) (((val) & 0x3) << 20)
2020 +#define LTQ_ES_TP_FLT_ACT_REG_QTF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF2) >> 20) & 0x3)
2021 +#define LTQ_ES_TP_FLT_ACT_REG_QTF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF2) | (((val) & 0x3) << 20))
2022 +/* Destination Queue for Type Filter 1 (19:18) */
2023 +#define LTQ_ES_TP_FLT_ACT_REG_QTF1 (0x3 << 18)
2024 +#define LTQ_ES_TP_FLT_ACT_REG_QTF1_VAL(val) (((val) & 0x3) << 18)
2025 +#define LTQ_ES_TP_FLT_ACT_REG_QTF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF1) >> 18) & 0x3)
2026 +#define LTQ_ES_TP_FLT_ACT_REG_QTF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF1) | (((val) & 0x3) << 18))
2027 +/* Destination Queue for Type Filter 0 (17:16) */
2028 +#define LTQ_ES_TP_FLT_ACT_REG_QTF0 (0x3 << 16)
2029 +#define LTQ_ES_TP_FLT_ACT_REG_QTF0_VAL(val) (((val) & 0x3) << 16)
2030 +#define LTQ_ES_TP_FLT_ACT_REG_QTF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF0) >> 16) & 0x3)
2031 +#define LTQ_ES_TP_FLT_ACT_REG_QTF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF0) | (((val) & 0x3) << 16))
2032 +/* Action for Type Filter 7 (15:14) */
2033 +#define LTQ_ES_TP_FLT_ACT_REG_ATF7 (0x3 << 14)
2034 +#define LTQ_ES_TP_FLT_ACT_REG_ATF7_VAL(val) (((val) & 0x3) << 14)
2035 +#define LTQ_ES_TP_FLT_ACT_REG_ATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF7) >> 14) & 0x3)
2036 +#define LTQ_ES_TP_FLT_ACT_REG_ATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF7) | (((val) & 0x3) << 14))
2037 +/* Action for Type Filter 6 (13:12) */
2038 +#define LTQ_ES_TP_FLT_ACT_REG_ATF6 (0x3 << 12)
2039 +#define LTQ_ES_TP_FLT_ACT_REG_ATF6_VAL(val) (((val) & 0x3) << 12)
2040 +#define LTQ_ES_TP_FLT_ACT_REG_ATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF6) >> 12) & 0x3)
2041 +#define LTQ_ES_TP_FLT_ACT_REG_ATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF6) | (((val) & 0x3) << 12))
2042 +/* Action for Type Filter 5 (11:10) */
2043 +#define LTQ_ES_TP_FLT_ACT_REG_ATF5 (0x3 << 10)
2044 +#define LTQ_ES_TP_FLT_ACT_REG_ATF5_VAL(val) (((val) & 0x3) << 10)
2045 +#define LTQ_ES_TP_FLT_ACT_REG_ATF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF5) >> 10) & 0x3)
2046 +#define LTQ_ES_TP_FLT_ACT_REG_ATF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF5) | (((val) & 0x3) << 10))
2047 +/* Action for Type Filter 4 (9:8) */
2048 +#define LTQ_ES_TP_FLT_ACT_REG_ATF4 (0x3 << 8)
2049 +#define LTQ_ES_TP_FLT_ACT_REG_ATF4_VAL(val) (((val) & 0x3) << 8)
2050 +#define LTQ_ES_TP_FLT_ACT_REG_ATF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF4) >> 8) & 0x3)
2051 +#define LTQ_ES_TP_FLT_ACT_REG_ATF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF4) | (((val) & 0x3) << 8))
2052 +/* Action for Type Filter 3 (7:6) */
2053 +#define LTQ_ES_TP_FLT_ACT_REG_ATF3 (0x3 << 6)
2054 +#define LTQ_ES_TP_FLT_ACT_REG_ATF3_VAL(val) (((val) & 0x3) << 6)
2055 +#define LTQ_ES_TP_FLT_ACT_REG_ATF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF3) >> 6) & 0x3)
2056 +#define LTQ_ES_TP_FLT_ACT_REG_ATF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF3) | (((val) & 0x3) << 6))
2057 +/* Action for Type Filter 2 (5:4) */
2058 +#define LTQ_ES_TP_FLT_ACT_REG_ATF2 (0x3 << 4)
2059 +#define LTQ_ES_TP_FLT_ACT_REG_ATF2_VAL(val) (((val) & 0x3) << 4)
2060 +#define LTQ_ES_TP_FLT_ACT_REG_ATF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF2) >> 4) & 0x3)
2061 +#define LTQ_ES_TP_FLT_ACT_REG_ATF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF2) | (((val) & 0x3) << 4))
2062 +/* Action for Type Filter 1 (3:2) */
2063 +#define LTQ_ES_TP_FLT_ACT_REG_ATF1 (0x3 << 2)
2064 +#define LTQ_ES_TP_FLT_ACT_REG_ATF1_VAL(val) (((val) & 0x3) << 2)
2065 +#define LTQ_ES_TP_FLT_ACT_REG_ATF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF1) >> 2) & 0x3)
2066 +#define LTQ_ES_TP_FLT_ACT_REG_ATF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF1) | (((val) & 0x3) << 2))
2067 +/* Action for Type Filter 0 (1:0) */
2068 +#define LTQ_ES_TP_FLT_ACT_REG_ATF0 (0x3)
2069 +#define LTQ_ES_TP_FLT_ACT_REG_ATF0_VAL(val) (((val) & 0x3) << 0)
2070 +#define LTQ_ES_TP_FLT_ACT_REG_ATF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF0) >> 0) & 0x3)
2071 +#define LTQ_ES_TP_FLT_ACT_REG_ATF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF0) | (((val) & 0x3) << 0))
2072 +
2073 +/*******************************************************************************
2074 + * Protocol Filter Action
2075 + ******************************************************************************/
2076 +
2077 +/* Action for Protocol Filter 7 (15:14) */
2078 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7 (0x3 << 14)
2079 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_VAL(val) (((val) & 0x3) << 14)
2080 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF7) >> 14) & 0x3)
2081 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF7) | (((val) & 0x3) << 14))
2082 +/* Action for Protocol Filter 6 (13:12) */
2083 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6 (0x3 << 12)
2084 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_VAL(val) (((val) & 0x3) << 12)
2085 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF6) >> 12) & 0x3)
2086 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF6) | (((val) & 0x3) << 12))
2087 +/* Action for Protocol Filter 5 (11:10) */
2088 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5 (0x3 << 10)
2089 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_VAL(val) (((val) & 0x3) << 10)
2090 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF5) >> 10) & 0x3)
2091 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF5) | (((val) & 0x3) << 10))
2092 +/* Action for Protocol Filter 4 (9:8) */
2093 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4 (0x3 << 8)
2094 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_VAL(val) (((val) & 0x3) << 8)
2095 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF4) >> 8) & 0x3)
2096 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF4) | (((val) & 0x3) << 8))
2097 +/* Action for Protocol Filter 3 (7:6) */
2098 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3 (0x3 << 6)
2099 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_VAL(val) (((val) & 0x3) << 6)
2100 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF3) >> 6) & 0x3)
2101 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF3) | (((val) & 0x3) << 6))
2102 +/* Action for Protocol Filter 2 (5:4) */
2103 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2 (0x3 << 4)
2104 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_VAL(val) (((val) & 0x3) << 4)
2105 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF2) >> 4) & 0x3)
2106 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF2) | (((val) & 0x3) << 4))
2107 +/* Action for Protocol Filter 1 (3:2) */
2108 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1 (0x3 << 2)
2109 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_VAL(val) (((val) & 0x3) << 2)
2110 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF1) >> 2) & 0x3)
2111 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF1) | (((val) & 0x3) << 2))
2112 +/* Action for Protocol Filter 0 (1:0) */
2113 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0 (0x3)
2114 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_VAL(val) (((val) & 0x3) << 0)
2115 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF0) >> 0) & 0x3)
2116 +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF0) | (((val) & 0x3) << 0))
2117 +
2118 +/*******************************************************************************
2119 + * VLAN Filter 0
2120 + ******************************************************************************/
2121 +
2122 +/* Res (31:24) */
2123 +#define LTQ_ES_VLAN_FLT0_REG_RES (0xff << 24)
2124 +#define LTQ_ES_VLAN_FLT0_REG_RES_VAL(val) (((val) & 0xff) << 24)
2125 +#define LTQ_ES_VLAN_FLT0_REG_RES_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_RES) >> 24) & 0xff)
2126 +#define LTQ_ES_VLAN_FLT0_REG_RES_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_RES) | (((val) & 0xff) << 24))
2127 +/* FID (23:22) */
2128 +#define LTQ_ES_VLAN_FLT0_REG_FID (0x3 << 22)
2129 +#define LTQ_ES_VLAN_FLT0_REG_FID_VAL(val) (((val) & 0x3) << 22)
2130 +#define LTQ_ES_VLAN_FLT0_REG_FID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_FID) >> 22) & 0x3)
2131 +#define LTQ_ES_VLAN_FLT0_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_FID) | (((val) & 0x3) << 22))
2132 +/* Tagged Member (21:19) */
2133 +#define LTQ_ES_VLAN_FLT0_REG_TM (0x7 << 19)
2134 +#define LTQ_ES_VLAN_FLT0_REG_TM_VAL(val) (((val) & 0x7) << 19)
2135 +#define LTQ_ES_VLAN_FLT0_REG_TM_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_TM) >> 19) & 0x7)
2136 +#define LTQ_ES_VLAN_FLT0_REG_TM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_TM) | (((val) & 0x7) << 19))
2137 +/* Member (18:16) */
2138 +#define LTQ_ES_VLAN_FLT0_REG_M (0x7 << 16)
2139 +#define LTQ_ES_VLAN_FLT0_REG_M_VAL(val) (((val) & 0x7) << 16)
2140 +#define LTQ_ES_VLAN_FLT0_REG_M_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_M) >> 16) & 0x7)
2141 +#define LTQ_ES_VLAN_FLT0_REG_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_M) | (((val) & 0x7) << 16))
2142 +/* VLAN_Valid (15) */
2143 +#define LTQ_ES_VLAN_FLT0_REG_VV (0x1 << 15)
2144 +#define LTQ_ES_VLAN_FLT0_REG_VV_VAL(val) (((val) & 0x1) << 15)
2145 +#define LTQ_ES_VLAN_FLT0_REG_VV_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VV) >> 15) & 0x1)
2146 +#define LTQ_ES_VLAN_FLT0_REG_VV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VV) | (((val) & 0x1) << 15))
2147 +/* VLAN PRI (14:12) */
2148 +#define LTQ_ES_VLAN_FLT0_REG_VP (0x7 << 12)
2149 +#define LTQ_ES_VLAN_FLT0_REG_VP_VAL(val) (((val) & 0x7) << 12)
2150 +#define LTQ_ES_VLAN_FLT0_REG_VP_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VP) >> 12) & 0x7)
2151 +#define LTQ_ES_VLAN_FLT0_REG_VP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VP) | (((val) & 0x7) << 12))
2152 +/* VID (11:0) */
2153 +#define LTQ_ES_VLAN_FLT0_REG_VID (0xfff)
2154 +#define LTQ_ES_VLAN_FLT0_REG_VID_VAL(val) (((val) & 0xfff) << 0)
2155 +#define LTQ_ES_VLAN_FLT0_REG_VID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VID) >> 0) & 0xfff)
2156 +#define LTQ_ES_VLAN_FLT0_REG_VID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VID) | (((val) & 0xfff) << 0))
2157 +
2158 +/*******************************************************************************
2159 + * Type Filter 10
2160 + ******************************************************************************/
2161 +
2162 +/* Value 1 Compared with Ether-Type (31:16) */
2163 +#define LTQ_ES_TP_FLT10_REG_VCET1 (0xffff << 16)
2164 +#define LTQ_ES_TP_FLT10_REG_VCET1_VAL(val) (((val) & 0xffff) << 16)
2165 +#define LTQ_ES_TP_FLT10_REG_VCET1_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET1) >> 16) & 0xffff)
2166 +#define LTQ_ES_TP_FLT10_REG_VCET1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET1) | (((val) & 0xffff) << 16))
2167 +/* Value 0 Compared with Ether-Type (15:0) */
2168 +#define LTQ_ES_TP_FLT10_REG_VCET0 (0xffff)
2169 +#define LTQ_ES_TP_FLT10_REG_VCET0_VAL(val) (((val) & 0xffff) << 0)
2170 +#define LTQ_ES_TP_FLT10_REG_VCET0_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET0) >> 0) & 0xffff)
2171 +#define LTQ_ES_TP_FLT10_REG_VCET0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET0) | (((val) & 0xffff) << 0))
2172 +
2173 +/*******************************************************************************
2174 + * DiffServMapping 0
2175 + ******************************************************************************/
2176 +
2177 +/* Priority Queue F (31:30) */
2178 +#define LTQ_ES_DFSRV_MAP0_REG_PQF (0x3 << 30)
2179 +#define LTQ_ES_DFSRV_MAP0_REG_PQF_VAL(val) (((val) & 0x3) << 30)
2180 +#define LTQ_ES_DFSRV_MAP0_REG_PQF_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQF) >> 30) & 0x3)
2181 +#define LTQ_ES_DFSRV_MAP0_REG_PQF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQF) | (((val) & 0x3) << 30))
2182 +/* Priority Queue E (29:28) */
2183 +#define LTQ_ES_DFSRV_MAP0_REG_PQE (0x3 << 28)
2184 +#define LTQ_ES_DFSRV_MAP0_REG_PQE_VAL(val) (((val) & 0x3) << 28)
2185 +#define LTQ_ES_DFSRV_MAP0_REG_PQE_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQE) >> 28) & 0x3)
2186 +#define LTQ_ES_DFSRV_MAP0_REG_PQE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQE) | (((val) & 0x3) << 28))
2187 +/* Priority Queue D (27:26) */
2188 +#define LTQ_ES_DFSRV_MAP0_REG_PQD (0x3 << 26)
2189 +#define LTQ_ES_DFSRV_MAP0_REG_PQD_VAL(val) (((val) & 0x3) << 26)
2190 +#define LTQ_ES_DFSRV_MAP0_REG_PQD_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQD) >> 26) & 0x3)
2191 +#define LTQ_ES_DFSRV_MAP0_REG_PQD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQD) | (((val) & 0x3) << 26))
2192 +/* Priority Queue C (25:24) */
2193 +#define LTQ_ES_DFSRV_MAP0_REG_PQC (0x3 << 24)
2194 +#define LTQ_ES_DFSRV_MAP0_REG_PQC_VAL(val) (((val) & 0x3) << 24)
2195 +#define LTQ_ES_DFSRV_MAP0_REG_PQC_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQC) >> 24) & 0x3)
2196 +#define LTQ_ES_DFSRV_MAP0_REG_PQC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQC) | (((val) & 0x3) << 24))
2197 +/* Priority Queue B (23:22) */
2198 +#define LTQ_ES_DFSRV_MAP0_REG_PQB (0x3 << 22)
2199 +#define LTQ_ES_DFSRV_MAP0_REG_PQB_VAL(val) (((val) & 0x3) << 22)
2200 +#define LTQ_ES_DFSRV_MAP0_REG_PQB_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQB) >> 22) & 0x3)
2201 +#define LTQ_ES_DFSRV_MAP0_REG_PQB_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQB) | (((val) & 0x3) << 22))
2202 +/* Priority Queue A (21:20) */
2203 +#define LTQ_ES_DFSRV_MAP0_REG_PQA (0x3 << 20)
2204 +#define LTQ_ES_DFSRV_MAP0_REG_PQA_VAL(val) (((val) & 0x3) << 20)
2205 +#define LTQ_ES_DFSRV_MAP0_REG_PQA_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQA) >> 20) & 0x3)
2206 +#define LTQ_ES_DFSRV_MAP0_REG_PQA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQA) | (((val) & 0x3) << 20))
2207 +/* Priority Queue 9 (19:18) */
2208 +#define LTQ_ES_DFSRV_MAP0_REG_PQ9 (0x3 << 18)
2209 +#define LTQ_ES_DFSRV_MAP0_REG_PQ9_VAL(val) (((val) & 0x3) << 18)
2210 +#define LTQ_ES_DFSRV_MAP0_REG_PQ9_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ9) >> 18) & 0x3)
2211 +#define LTQ_ES_DFSRV_MAP0_REG_PQ9_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ9) | (((val) & 0x3) << 18))
2212 +/* Priority Queue 8 (17:16) */
2213 +#define LTQ_ES_DFSRV_MAP0_REG_PQ8 (0x3 << 16)
2214 +#define LTQ_ES_DFSRV_MAP0_REG_PQ8_VAL(val) (((val) & 0x3) << 16)
2215 +#define LTQ_ES_DFSRV_MAP0_REG_PQ8_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ8) >> 16) & 0x3)
2216 +#define LTQ_ES_DFSRV_MAP0_REG_PQ8_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ8) | (((val) & 0x3) << 16))
2217 +/* Priority Queue 7 (15:14) */
2218 +#define LTQ_ES_DFSRV_MAP0_REG_PQ7 (0x3 << 14)
2219 +#define LTQ_ES_DFSRV_MAP0_REG_PQ7_VAL(val) (((val) & 0x3) << 14)
2220 +#define LTQ_ES_DFSRV_MAP0_REG_PQ7_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ7) >> 14) & 0x3)
2221 +#define LTQ_ES_DFSRV_MAP0_REG_PQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ7) | (((val) & 0x3) << 14))
2222 +/* Priority Queue 6 (13:12) */
2223 +#define LTQ_ES_DFSRV_MAP0_REG_PQ6 (0x3 << 12)
2224 +#define LTQ_ES_DFSRV_MAP0_REG_PQ6_VAL(val) (((val) & 0x3) << 12)
2225 +#define LTQ_ES_DFSRV_MAP0_REG_PQ6_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ6) >> 12) & 0x3)
2226 +#define LTQ_ES_DFSRV_MAP0_REG_PQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ6) | (((val) & 0x3) << 12))
2227 +/* Priority Queue 5 (11:10) */
2228 +#define LTQ_ES_DFSRV_MAP0_REG_PQ5 (0x3 << 10)
2229 +#define LTQ_ES_DFSRV_MAP0_REG_PQ5_VAL(val) (((val) & 0x3) << 10)
2230 +#define LTQ_ES_DFSRV_MAP0_REG_PQ5_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ5) >> 10) & 0x3)
2231 +#define LTQ_ES_DFSRV_MAP0_REG_PQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ5) | (((val) & 0x3) << 10))
2232 +/* Priority Queue 4 (9:8) */
2233 +#define LTQ_ES_DFSRV_MAP0_REG_PQ4 (0x3 << 8)
2234 +#define LTQ_ES_DFSRV_MAP0_REG_PQ4_VAL(val) (((val) & 0x3) << 8)
2235 +#define LTQ_ES_DFSRV_MAP0_REG_PQ4_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ4) >> 8) & 0x3)
2236 +#define LTQ_ES_DFSRV_MAP0_REG_PQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ4) | (((val) & 0x3) << 8))
2237 +/* Priority Queue 3 (7:6) */
2238 +#define LTQ_ES_DFSRV_MAP0_REG_PQ3 (0x3 << 6)
2239 +#define LTQ_ES_DFSRV_MAP0_REG_PQ3_VAL(val) (((val) & 0x3) << 6)
2240 +#define LTQ_ES_DFSRV_MAP0_REG_PQ3_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ3) >> 6) & 0x3)
2241 +#define LTQ_ES_DFSRV_MAP0_REG_PQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ3) | (((val) & 0x3) << 6))
2242 +/* Priority Queue 2 (5:4) */
2243 +#define LTQ_ES_DFSRV_MAP0_REG_PQ2 (0x3 << 4)
2244 +#define LTQ_ES_DFSRV_MAP0_REG_PQ2_VAL(val) (((val) & 0x3) << 4)
2245 +#define LTQ_ES_DFSRV_MAP0_REG_PQ2_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ2) >> 4) & 0x3)
2246 +#define LTQ_ES_DFSRV_MAP0_REG_PQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ2) | (((val) & 0x3) << 4))
2247 +/* Priority Queue 1 (3:2) */
2248 +#define LTQ_ES_DFSRV_MAP0_REG_PQ1 (0x3 << 2)
2249 +#define LTQ_ES_DFSRV_MAP0_REG_PQ1_VAL(val) (((val) & 0x3) << 2)
2250 +#define LTQ_ES_DFSRV_MAP0_REG_PQ1_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ1) >> 2) & 0x3)
2251 +#define LTQ_ES_DFSRV_MAP0_REG_PQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ1) | (((val) & 0x3) << 2))
2252 +/* Priority Queue 0 (1:0) */
2253 +#define LTQ_ES_DFSRV_MAP0_REG_PQ0 (0x3)
2254 +#define LTQ_ES_DFSRV_MAP0_REG_PQ0_VAL(val) (((val) & 0x3) << 0)
2255 +#define LTQ_ES_DFSRV_MAP0_REG_PQ0_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ0) >> 0) & 0x3)
2256 +#define LTQ_ES_DFSRV_MAP0_REG_PQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ0) | (((val) & 0x3) << 0))
2257 +
2258 +/*******************************************************************************
2259 + * DiffServMapping 1
2260 + ******************************************************************************/
2261 +
2262 +/* Priority Queue 1F (31:30) */
2263 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F (0x3 << 30)
2264 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_VAL(val) (((val) & 0x3) << 30)
2265 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1F) >> 30) & 0x3)
2266 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1F) | (((val) & 0x3) << 30))
2267 +/* Priority Queue 1E (29:28) */
2268 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E (0x3 << 28)
2269 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_VAL(val) (((val) & 0x3) << 28)
2270 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1E) >> 28) & 0x3)
2271 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1E) | (((val) & 0x3) << 28))
2272 +/* Priority Queue 1D (27:26) */
2273 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D (0x3 << 26)
2274 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_VAL(val) (((val) & 0x3) << 26)
2275 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1D) >> 26) & 0x3)
2276 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1D) | (((val) & 0x3) << 26))
2277 +/* Priority Queue 1C (25:24) */
2278 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C (0x3 << 24)
2279 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_VAL(val) (((val) & 0x3) << 24)
2280 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1C) >> 24) & 0x3)
2281 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1C) | (((val) & 0x3) << 24))
2282 +/* Priority Queue 1B (23:22) */
2283 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B (0x3 << 22)
2284 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_VAL(val) (((val) & 0x3) << 22)
2285 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1B) >> 22) & 0x3)
2286 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1B) | (((val) & 0x3) << 22))
2287 +/* Priority Queue 1A (21:20) */
2288 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A (0x3 << 20)
2289 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_VAL(val) (((val) & 0x3) << 20)
2290 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1A) >> 20) & 0x3)
2291 +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1A) | (((val) & 0x3) << 20))
2292 +/* Priority Queue 19 (19:18) */
2293 +#define LTQ_ES_DFSRV_MAP1_REG_PQ19 (0x3 << 18)
2294 +#define LTQ_ES_DFSRV_MAP1_REG_PQ19_VAL(val) (((val) & 0x3) << 18)
2295 +#define LTQ_ES_DFSRV_MAP1_REG_PQ19_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ19) >> 18) & 0x3)
2296 +#define LTQ_ES_DFSRV_MAP1_REG_PQ19_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ19) | (((val) & 0x3) << 18))
2297 +/* Priority Queue 18 (17:16) */
2298 +#define LTQ_ES_DFSRV_MAP1_REG_PQ18 (0x3 << 16)
2299 +#define LTQ_ES_DFSRV_MAP1_REG_PQ18_VAL(val) (((val) & 0x3) << 16)
2300 +#define LTQ_ES_DFSRV_MAP1_REG_PQ18_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ18) >> 16) & 0x3)
2301 +#define LTQ_ES_DFSRV_MAP1_REG_PQ18_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ18) | (((val) & 0x3) << 16))
2302 +/* Priority Queue 17 (15:14) */
2303 +#define LTQ_ES_DFSRV_MAP1_REG_PQ17 (0x3 << 14)
2304 +#define LTQ_ES_DFSRV_MAP1_REG_PQ17_VAL(val) (((val) & 0x3) << 14)
2305 +#define LTQ_ES_DFSRV_MAP1_REG_PQ17_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ17) >> 14) & 0x3)
2306 +#define LTQ_ES_DFSRV_MAP1_REG_PQ17_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ17) | (((val) & 0x3) << 14))
2307 +/* Priority Queue 16 (13:12) */
2308 +#define LTQ_ES_DFSRV_MAP1_REG_PQ16 (0x3 << 12)
2309 +#define LTQ_ES_DFSRV_MAP1_REG_PQ16_VAL(val) (((val) & 0x3) << 12)
2310 +#define LTQ_ES_DFSRV_MAP1_REG_PQ16_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ16) >> 12) & 0x3)
2311 +#define LTQ_ES_DFSRV_MAP1_REG_PQ16_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ16) | (((val) & 0x3) << 12))
2312 +/* Priority Queue 15 (11:10) */
2313 +#define LTQ_ES_DFSRV_MAP1_REG_PQ15 (0x3 << 10)
2314 +#define LTQ_ES_DFSRV_MAP1_REG_PQ15_VAL(val) (((val) & 0x3) << 10)
2315 +#define LTQ_ES_DFSRV_MAP1_REG_PQ15_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ15) >> 10) & 0x3)
2316 +#define LTQ_ES_DFSRV_MAP1_REG_PQ15_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ15) | (((val) & 0x3) << 10))
2317 +/* Priority Queue 14 (9:8) */
2318 +#define LTQ_ES_DFSRV_MAP1_REG_PQ14 (0x3 << 8)
2319 +#define LTQ_ES_DFSRV_MAP1_REG_PQ14_VAL(val) (((val) & 0x3) << 8)
2320 +#define LTQ_ES_DFSRV_MAP1_REG_PQ14_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ14) >> 8) & 0x3)
2321 +#define LTQ_ES_DFSRV_MAP1_REG_PQ14_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ14) | (((val) & 0x3) << 8))
2322 +/* Priority Queue 13 (7:6) */
2323 +#define LTQ_ES_DFSRV_MAP1_REG_PQ13 (0x3 << 6)
2324 +#define LTQ_ES_DFSRV_MAP1_REG_PQ13_VAL(val) (((val) & 0x3) << 6)
2325 +#define LTQ_ES_DFSRV_MAP1_REG_PQ13_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ13) >> 6) & 0x3)
2326 +#define LTQ_ES_DFSRV_MAP1_REG_PQ13_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ13) | (((val) & 0x3) << 6))
2327 +/* Priority Queue 12 (5:4) */
2328 +#define LTQ_ES_DFSRV_MAP1_REG_PQ12 (0x3 << 4)
2329 +#define LTQ_ES_DFSRV_MAP1_REG_PQ12_VAL(val) (((val) & 0x3) << 4)
2330 +#define LTQ_ES_DFSRV_MAP1_REG_PQ12_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ12) >> 4) & 0x3)
2331 +#define LTQ_ES_DFSRV_MAP1_REG_PQ12_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ12) | (((val) & 0x3) << 4))
2332 +/* Priority Queue 11 (3:2) */
2333 +#define LTQ_ES_DFSRV_MAP1_REG_PQ11 (0x3 << 2)
2334 +#define LTQ_ES_DFSRV_MAP1_REG_PQ11_VAL(val) (((val) & 0x3) << 2)
2335 +#define LTQ_ES_DFSRV_MAP1_REG_PQ11_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ11) >> 2) & 0x3)
2336 +#define LTQ_ES_DFSRV_MAP1_REG_PQ11_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ11) | (((val) & 0x3) << 2))
2337 +/* Priority Queue 10 (1:0) */
2338 +#define LTQ_ES_DFSRV_MAP1_REG_PQ10 (0x3)
2339 +#define LTQ_ES_DFSRV_MAP1_REG_PQ10_VAL(val) (((val) & 0x3) << 0)
2340 +#define LTQ_ES_DFSRV_MAP1_REG_PQ10_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ10) >> 0) & 0x3)
2341 +#define LTQ_ES_DFSRV_MAP1_REG_PQ10_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ10) | (((val) & 0x3) << 0))
2342 +
2343 +/*******************************************************************************
2344 + * DiffServMapping 2
2345 + ******************************************************************************/
2346 +
2347 +/* Priority Queue 2F (31:30) */
2348 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F (0x3 << 30)
2349 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_VAL(val) (((val) & 0x3) << 30)
2350 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2F) >> 30) & 0x3)
2351 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2F) | (((val) & 0x3) << 30))
2352 +/* Priority Queue 2E (29:28) */
2353 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E (0x3 << 28)
2354 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_VAL(val) (((val) & 0x3) << 28)
2355 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2E) >> 28) & 0x3)
2356 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2E) | (((val) & 0x3) << 28))
2357 +/* Priority Queue 2D (27:26) */
2358 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D (0x3 << 26)
2359 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_VAL(val) (((val) & 0x3) << 26)
2360 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2D) >> 26) & 0x3)
2361 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2D) | (((val) & 0x3) << 26))
2362 +/* Priority Queue 2C (25:24) */
2363 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C (0x3 << 24)
2364 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_VAL(val) (((val) & 0x3) << 24)
2365 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2C) >> 24) & 0x3)
2366 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2C) | (((val) & 0x3) << 24))
2367 +/* Priority Queue 2B (23:22) */
2368 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B (0x3 << 22)
2369 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_VAL(val) (((val) & 0x3) << 22)
2370 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2B) >> 22) & 0x3)
2371 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2B) | (((val) & 0x3) << 22))
2372 +/* Priority Queue 2A (21:20) */
2373 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A (0x3 << 20)
2374 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_VAL(val) (((val) & 0x3) << 20)
2375 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2A) >> 20) & 0x3)
2376 +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2A) | (((val) & 0x3) << 20))
2377 +/* Priority Queue 29 (19:18) */
2378 +#define LTQ_ES_DFSRV_MAP2_REG_PQ29 (0x3 << 18)
2379 +#define LTQ_ES_DFSRV_MAP2_REG_PQ29_VAL(val) (((val) & 0x3) << 18)
2380 +#define LTQ_ES_DFSRV_MAP2_REG_PQ29_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ29) >> 18) & 0x3)
2381 +#define LTQ_ES_DFSRV_MAP2_REG_PQ29_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ29) | (((val) & 0x3) << 18))
2382 +/* Priority Queue 28 (17:16) */
2383 +#define LTQ_ES_DFSRV_MAP2_REG_PQ28 (0x3 << 16)
2384 +#define LTQ_ES_DFSRV_MAP2_REG_PQ28_VAL(val) (((val) & 0x3) << 16)
2385 +#define LTQ_ES_DFSRV_MAP2_REG_PQ28_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ28) >> 16) & 0x3)
2386 +#define LTQ_ES_DFSRV_MAP2_REG_PQ28_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ28) | (((val) & 0x3) << 16))
2387 +/* Priority Queue 27 (15:14) */
2388 +#define LTQ_ES_DFSRV_MAP2_REG_PQ27 (0x3 << 14)
2389 +#define LTQ_ES_DFSRV_MAP2_REG_PQ27_VAL(val) (((val) & 0x3) << 14)
2390 +#define LTQ_ES_DFSRV_MAP2_REG_PQ27_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ27) >> 14) & 0x3)
2391 +#define LTQ_ES_DFSRV_MAP2_REG_PQ27_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ27) | (((val) & 0x3) << 14))
2392 +/* Priority Queue 26 (13:12) */
2393 +#define LTQ_ES_DFSRV_MAP2_REG_PQ26 (0x3 << 12)
2394 +#define LTQ_ES_DFSRV_MAP2_REG_PQ26_VAL(val) (((val) & 0x3) << 12)
2395 +#define LTQ_ES_DFSRV_MAP2_REG_PQ26_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ26) >> 12) & 0x3)
2396 +#define LTQ_ES_DFSRV_MAP2_REG_PQ26_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ26) | (((val) & 0x3) << 12))
2397 +/* Priority Queue 25 (11:10) */
2398 +#define LTQ_ES_DFSRV_MAP2_REG_PQ25 (0x3 << 10)
2399 +#define LTQ_ES_DFSRV_MAP2_REG_PQ25_VAL(val) (((val) & 0x3) << 10)
2400 +#define LTQ_ES_DFSRV_MAP2_REG_PQ25_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ25) >> 10) & 0x3)
2401 +#define LTQ_ES_DFSRV_MAP2_REG_PQ25_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ25) | (((val) & 0x3) << 10))
2402 +/* Priority Queue 24 (9:8) */
2403 +#define LTQ_ES_DFSRV_MAP2_REG_PQ24 (0x3 << 8)
2404 +#define LTQ_ES_DFSRV_MAP2_REG_PQ24_VAL(val) (((val) & 0x3) << 8)
2405 +#define LTQ_ES_DFSRV_MAP2_REG_PQ24_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ24) >> 8) & 0x3)
2406 +#define LTQ_ES_DFSRV_MAP2_REG_PQ24_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ24) | (((val) & 0x3) << 8))
2407 +/* Priority Queue 23 (7:6) */
2408 +#define LTQ_ES_DFSRV_MAP2_REG_PQ23 (0x3 << 6)
2409 +#define LTQ_ES_DFSRV_MAP2_REG_PQ23_VAL(val) (((val) & 0x3) << 6)
2410 +#define LTQ_ES_DFSRV_MAP2_REG_PQ23_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ23) >> 6) & 0x3)
2411 +#define LTQ_ES_DFSRV_MAP2_REG_PQ23_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ23) | (((val) & 0x3) << 6))
2412 +/* Priority Queue 22 (5:4) */
2413 +#define LTQ_ES_DFSRV_MAP2_REG_PQ22 (0x3 << 4)
2414 +#define LTQ_ES_DFSRV_MAP2_REG_PQ22_VAL(val) (((val) & 0x3) << 4)
2415 +#define LTQ_ES_DFSRV_MAP2_REG_PQ22_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ22) >> 4) & 0x3)
2416 +#define LTQ_ES_DFSRV_MAP2_REG_PQ22_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ22) | (((val) & 0x3) << 4))
2417 +/* Priority Queue 21 (3:2) */
2418 +#define LTQ_ES_DFSRV_MAP2_REG_PQ21 (0x3 << 2)
2419 +#define LTQ_ES_DFSRV_MAP2_REG_PQ21_VAL(val) (((val) & 0x3) << 2)
2420 +#define LTQ_ES_DFSRV_MAP2_REG_PQ21_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ21) >> 2) & 0x3)
2421 +#define LTQ_ES_DFSRV_MAP2_REG_PQ21_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ21) | (((val) & 0x3) << 2))
2422 +/* Priority Queue 20 (1:0) */
2423 +#define LTQ_ES_DFSRV_MAP2_REG_PQ20 (0x3)
2424 +#define LTQ_ES_DFSRV_MAP2_REG_PQ20_VAL(val) (((val) & 0x3) << 0)
2425 +#define LTQ_ES_DFSRV_MAP2_REG_PQ20_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ20) >> 0) & 0x3)
2426 +#define LTQ_ES_DFSRV_MAP2_REG_PQ20_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ20) | (((val) & 0x3) << 0))
2427 +
2428 +/*******************************************************************************
2429 + * DiffServMapping 3
2430 + ******************************************************************************/
2431 +
2432 +/* Priority Queue 3F (31:30) */
2433 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F (0x3 << 30)
2434 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_VAL(val) (((val) & 0x3) << 30)
2435 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3F) >> 30) & 0x3)
2436 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3F) | (((val) & 0x3) << 30))
2437 +/* Priority Queue 3E (29:28) */
2438 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E (0x3 << 28)
2439 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_VAL(val) (((val) & 0x3) << 28)
2440 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3E) >> 28) & 0x3)
2441 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3E) | (((val) & 0x3) << 28))
2442 +/* Priority Queue 3D (27:26) */
2443 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D (0x3 << 26)
2444 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_VAL(val) (((val) & 0x3) << 26)
2445 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3D) >> 26) & 0x3)
2446 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3D) | (((val) & 0x3) << 26))
2447 +/* Priority Queue 3C (25:24) */
2448 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C (0x3 << 24)
2449 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_VAL(val) (((val) & 0x3) << 24)
2450 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3C) >> 24) & 0x3)
2451 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3C) | (((val) & 0x3) << 24))
2452 +/* Priority Queue 3B (23:22) */
2453 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B (0x3 << 22)
2454 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_VAL(val) (((val) & 0x3) << 22)
2455 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3B) >> 22) & 0x3)
2456 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3B) | (((val) & 0x3) << 22))
2457 +/* Priority Queue 3A (21:20) */
2458 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A (0x3 << 20)
2459 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_VAL(val) (((val) & 0x3) << 20)
2460 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3A) >> 20) & 0x3)
2461 +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3A) | (((val) & 0x3) << 20))
2462 +/* Priority Queue 39 (19:18) */
2463 +#define LTQ_ES_DFSRV_MAP3_REG_PQ39 (0x3 << 18)
2464 +#define LTQ_ES_DFSRV_MAP3_REG_PQ39_VAL(val) (((val) & 0x3) << 18)
2465 +#define LTQ_ES_DFSRV_MAP3_REG_PQ39_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ39) >> 18) & 0x3)
2466 +#define LTQ_ES_DFSRV_MAP3_REG_PQ39_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ39) | (((val) & 0x3) << 18))
2467 +/* Priority Queue 38 (17:16) */
2468 +#define LTQ_ES_DFSRV_MAP3_REG_PQ38 (0x3 << 16)
2469 +#define LTQ_ES_DFSRV_MAP3_REG_PQ38_VAL(val) (((val) & 0x3) << 16)
2470 +#define LTQ_ES_DFSRV_MAP3_REG_PQ38_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ38) >> 16) & 0x3)
2471 +#define LTQ_ES_DFSRV_MAP3_REG_PQ38_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ38) | (((val) & 0x3) << 16))
2472 +/* Priority Queue 37 (15:14) */
2473 +#define LTQ_ES_DFSRV_MAP3_REG_PQ37 (0x3 << 14)
2474 +#define LTQ_ES_DFSRV_MAP3_REG_PQ37_VAL(val) (((val) & 0x3) << 14)
2475 +#define LTQ_ES_DFSRV_MAP3_REG_PQ37_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ37) >> 14) & 0x3)
2476 +#define LTQ_ES_DFSRV_MAP3_REG_PQ37_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ37) | (((val) & 0x3) << 14))
2477 +/* Priority Queue 36 (13:12) */
2478 +#define LTQ_ES_DFSRV_MAP3_REG_PQ36 (0x3 << 12)
2479 +#define LTQ_ES_DFSRV_MAP3_REG_PQ36_VAL(val) (((val) & 0x3) << 12)
2480 +#define LTQ_ES_DFSRV_MAP3_REG_PQ36_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ36) >> 12) & 0x3)
2481 +#define LTQ_ES_DFSRV_MAP3_REG_PQ36_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ36) | (((val) & 0x3) << 12))
2482 +/* Priority Queue 35 (11:10) */
2483 +#define LTQ_ES_DFSRV_MAP3_REG_PQ35 (0x3 << 10)
2484 +#define LTQ_ES_DFSRV_MAP3_REG_PQ35_VAL(val) (((val) & 0x3) << 10)
2485 +#define LTQ_ES_DFSRV_MAP3_REG_PQ35_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ35) >> 10) & 0x3)
2486 +#define LTQ_ES_DFSRV_MAP3_REG_PQ35_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ35) | (((val) & 0x3) << 10))
2487 +/* Priority Queue 34 (9:8) */
2488 +#define LTQ_ES_DFSRV_MAP3_REG_PQ34 (0x3 << 8)
2489 +#define LTQ_ES_DFSRV_MAP3_REG_PQ34_VAL(val) (((val) & 0x3) << 8)
2490 +#define LTQ_ES_DFSRV_MAP3_REG_PQ34_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ34) >> 8) & 0x3)
2491 +#define LTQ_ES_DFSRV_MAP3_REG_PQ34_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ34) | (((val) & 0x3) << 8))
2492 +/* Priority Queue 33 (7:6) */
2493 +#define LTQ_ES_DFSRV_MAP3_REG_PQ33 (0x3 << 6)
2494 +#define LTQ_ES_DFSRV_MAP3_REG_PQ33_VAL(val) (((val) & 0x3) << 6)
2495 +#define LTQ_ES_DFSRV_MAP3_REG_PQ33_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ33) >> 6) & 0x3)
2496 +#define LTQ_ES_DFSRV_MAP3_REG_PQ33_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ33) | (((val) & 0x3) << 6))
2497 +/* Priority Queue 32 (5:4) */
2498 +#define LTQ_ES_DFSRV_MAP3_REG_PQ32 (0x3 << 4)
2499 +#define LTQ_ES_DFSRV_MAP3_REG_PQ32_VAL(val) (((val) & 0x3) << 4)
2500 +#define LTQ_ES_DFSRV_MAP3_REG_PQ32_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ32) >> 4) & 0x3)
2501 +#define LTQ_ES_DFSRV_MAP3_REG_PQ32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ32) | (((val) & 0x3) << 4))
2502 +/* Priority Queue 31 (3:2) */
2503 +#define LTQ_ES_DFSRV_MAP3_REG_PQ31 (0x3 << 2)
2504 +#define LTQ_ES_DFSRV_MAP3_REG_PQ31_VAL(val) (((val) & 0x3) << 2)
2505 +#define LTQ_ES_DFSRV_MAP3_REG_PQ31_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ31) >> 2) & 0x3)
2506 +#define LTQ_ES_DFSRV_MAP3_REG_PQ31_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ31) | (((val) & 0x3) << 2))
2507 +/* Priority Queue 30 (1:0) */
2508 +#define LTQ_ES_DFSRV_MAP3_REG_PQ30 (0x3)
2509 +#define LTQ_ES_DFSRV_MAP3_REG_PQ30_VAL(val) (((val) & 0x3) << 0)
2510 +#define LTQ_ES_DFSRV_MAP3_REG_PQ30_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ30) >> 0) & 0x3)
2511 +#define LTQ_ES_DFSRV_MAP3_REG_PQ30_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ30) | (((val) & 0x3) << 0))
2512 +
2513 +/*******************************************************************************
2514 + * TCP/UDP Port Filter 0
2515 + ******************************************************************************/
2516 +
2517 +/* Reserved (31:30) */
2518 +#define LTQ_ES_TCP_PF0_REG_RES (0x3 << 30)
2519 +#define LTQ_ES_TCP_PF0_REG_RES_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_RES) >> 30) & 0x3)
2520 +/* Action for TCP/UDP Port Filter 0 (29:28) */
2521 +#define LTQ_ES_TCP_PF0_REG_ATUF0 (0x3 << 28)
2522 +#define LTQ_ES_TCP_PF0_REG_ATUF0_VAL(val) (((val) & 0x3) << 28)
2523 +#define LTQ_ES_TCP_PF0_REG_ATUF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_ATUF0) >> 28) & 0x3)
2524 +#define LTQ_ES_TCP_PF0_REG_ATUF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_ATUF0) | (((val) & 0x3) << 28))
2525 +/* TCP/UDP PRI for TCP/UDP Port Filter 0 (27:26) */
2526 +#define LTQ_ES_TCP_PF0_REG_TUPF0 (0x3 << 26)
2527 +#define LTQ_ES_TCP_PF0_REG_TUPF0_VAL(val) (((val) & 0x3) << 26)
2528 +#define LTQ_ES_TCP_PF0_REG_TUPF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_TUPF0) >> 26) & 0x3)
2529 +#define LTQ_ES_TCP_PF0_REG_TUPF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_TUPF0) | (((val) & 0x3) << 26))
2530 +/* Compare TCP/UDP Source Port or Destination Port (25:24) */
2531 +#define LTQ_ES_TCP_PF0_REG_COMP0 (0x3 << 24)
2532 +#define LTQ_ES_TCP_PF0_REG_COMP0_VAL(val) (((val) & 0x3) << 24)
2533 +#define LTQ_ES_TCP_PF0_REG_COMP0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_COMP0) >> 24) & 0x3)
2534 +#define LTQ_ES_TCP_PF0_REG_COMP0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_COMP0) | (((val) & 0x3) << 24))
2535 +/* Port Range in TCP/UDP (23:16) */
2536 +#define LTQ_ES_TCP_PF0_REG_PRANGE0 (0xff << 16)
2537 +#define LTQ_ES_TCP_PF0_REG_PRANGE0_VAL(val) (((val) & 0xff) << 16)
2538 +#define LTQ_ES_TCP_PF0_REG_PRANGE0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_PRANGE0) >> 16) & 0xff)
2539 +#define LTQ_ES_TCP_PF0_REG_PRANGE0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_PRANGE0) | (((val) & 0xff) << 16))
2540 +/* Base Port number 0 (15:0) */
2541 +#define LTQ_ES_TCP_PF0_REG_BASEPT0 (0xffff)
2542 +#define LTQ_ES_TCP_PF0_REG_BASEPT0_VAL(val) (((val) & 0xffff) << 0)
2543 +#define LTQ_ES_TCP_PF0_REG_BASEPT0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_BASEPT0) >> 0) & 0xffff)
2544 +#define LTQ_ES_TCP_PF0_REG_BASEPT0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_BASEPT0) | (((val) & 0xffff) << 0))
2545 +
2546 +/*******************************************************************************
2547 + * Reserved DA(0180C2000003~0180C2000000) control register
2548 + ******************************************************************************/
2549 +
2550 +/* Valid bit for 0180C2000003 (31) */
2551 +#define LTQ_ES_RA_03_00_REG_RA03_VALID (0x1 << 31)
2552 +#define LTQ_ES_RA_03_00_REG_RA03_VALID_VAL(val) (((val) & 0x1) << 31)
2553 +#define LTQ_ES_RA_03_00_REG_RA03_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_VALID) >> 31) & 0x1)
2554 +#define LTQ_ES_RA_03_00_REG_RA03_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_VALID) | (((val) & 0x1) << 31))
2555 +/* Span bit for 0180C2000003 (30) */
2556 +#define LTQ_ES_RA_03_00_REG_RA03_SPAN (0x1 << 30)
2557 +#define LTQ_ES_RA_03_00_REG_RA03_SPAN_VAL(val) (((val) & 0x1) << 30)
2558 +#define LTQ_ES_RA_03_00_REG_RA03_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_SPAN) >> 30) & 0x1)
2559 +#define LTQ_ES_RA_03_00_REG_RA03_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_SPAN) | (((val) & 0x1) << 30))
2560 +/* Management bit for 0180C2000003 (29) */
2561 +#define LTQ_ES_RA_03_00_REG_RA03_MG (0x1 << 29)
2562 +#define LTQ_ES_RA_03_00_REG_RA03_MG_VAL(val) (((val) & 0x1) << 29)
2563 +#define LTQ_ES_RA_03_00_REG_RA03_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_MG) >> 29) & 0x1)
2564 +#define LTQ_ES_RA_03_00_REG_RA03_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_MG) | (((val) & 0x1) << 29))
2565 +/* Cross_VLAN bit for 0180C2000003 (28) */
2566 +#define LTQ_ES_RA_03_00_REG_RA03_CV (0x1 << 28)
2567 +#define LTQ_ES_RA_03_00_REG_RA03_CV_VAL(val) (((val) & 0x1) << 28)
2568 +#define LTQ_ES_RA_03_00_REG_RA03_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_CV) >> 28) & 0x1)
2569 +#define LTQ_ES_RA_03_00_REG_RA03_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_CV) | (((val) & 0x1) << 28))
2570 +/* TXTAG bit for 0180C2000003 (27:26) */
2571 +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG (0x3 << 26)
2572 +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_VAL(val) (((val) & 0x3) << 26)
2573 +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_TXTAG) >> 26) & 0x3)
2574 +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_TXTAG) | (((val) & 0x3) << 26))
2575 +/* Action bit for 0180C2000003 (25:24) */
2576 +#define LTQ_ES_RA_03_00_REG_RA03_ACT (0x3 << 24)
2577 +#define LTQ_ES_RA_03_00_REG_RA03_ACT_VAL(val) (((val) & 0x3) << 24)
2578 +#define LTQ_ES_RA_03_00_REG_RA03_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_ACT) >> 24) & 0x3)
2579 +#define LTQ_ES_RA_03_00_REG_RA03_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_ACT) | (((val) & 0x3) << 24))
2580 +/* Valid bit for 0180C2000002 (23) */
2581 +#define LTQ_ES_RA_03_00_REG_RA02_VALID (0x1 << 23)
2582 +#define LTQ_ES_RA_03_00_REG_RA02_VALID_VAL(val) (((val) & 0x1) << 23)
2583 +#define LTQ_ES_RA_03_00_REG_RA02_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_VALID) >> 23) & 0x1)
2584 +#define LTQ_ES_RA_03_00_REG_RA02_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_VALID) | (((val) & 0x1) << 23))
2585 +/* Span bit for 0180C2000002 (22) */
2586 +#define LTQ_ES_RA_03_00_REG_RA02_SPAN (0x1 << 22)
2587 +#define LTQ_ES_RA_03_00_REG_RA02_SPAN_VAL(val) (((val) & 0x1) << 22)
2588 +#define LTQ_ES_RA_03_00_REG_RA02_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_SPAN) >> 22) & 0x1)
2589 +#define LTQ_ES_RA_03_00_REG_RA02_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_SPAN) | (((val) & 0x1) << 22))
2590 +/* Management bit for 0180C2000002 (21) */
2591 +#define LTQ_ES_RA_03_00_REG_RA02_MG (0x1 << 21)
2592 +#define LTQ_ES_RA_03_00_REG_RA02_MG_VAL(val) (((val) & 0x1) << 21)
2593 +#define LTQ_ES_RA_03_00_REG_RA02_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_MG) >> 21) & 0x1)
2594 +#define LTQ_ES_RA_03_00_REG_RA02_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_MG) | (((val) & 0x1) << 21))
2595 +/* Cross_VLAN bit for 0180C2000002 (20) */
2596 +#define LTQ_ES_RA_03_00_REG_RA02_CV (0x1 << 20)
2597 +#define LTQ_ES_RA_03_00_REG_RA02_CV_VAL(val) (((val) & 0x1) << 20)
2598 +#define LTQ_ES_RA_03_00_REG_RA02_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_CV) >> 20) & 0x1)
2599 +#define LTQ_ES_RA_03_00_REG_RA02_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_CV) | (((val) & 0x1) << 20))
2600 +/* TXTAG bit for 0180C2000002 (19:18) */
2601 +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG (0x3 << 18)
2602 +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_VAL(val) (((val) & 0x3) << 18)
2603 +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_TXTAG) >> 18) & 0x3)
2604 +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_TXTAG) | (((val) & 0x3) << 18))
2605 +/* Action bit for 0180C2000002 (17:16) */
2606 +#define LTQ_ES_RA_03_00_REG_RA02_ACT (0x3 << 16)
2607 +#define LTQ_ES_RA_03_00_REG_RA02_ACT_VAL(val) (((val) & 0x3) << 16)
2608 +#define LTQ_ES_RA_03_00_REG_RA02_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_ACT) >> 16) & 0x3)
2609 +#define LTQ_ES_RA_03_00_REG_RA02_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_ACT) | (((val) & 0x3) << 16))
2610 +/* Valid bit for 0180C2000001 (15) */
2611 +#define LTQ_ES_RA_03_00_REG_RA01_VALID (0x1 << 15)
2612 +#define LTQ_ES_RA_03_00_REG_RA01_VALID_VAL(val) (((val) & 0x1) << 15)
2613 +#define LTQ_ES_RA_03_00_REG_RA01_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_VALID) >> 15) & 0x1)
2614 +#define LTQ_ES_RA_03_00_REG_RA01_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_VALID) | (((val) & 0x1) << 15))
2615 +/* Span bit for 0180C2000001 (14) */
2616 +#define LTQ_ES_RA_03_00_REG_RA01_SPAN (0x1 << 14)
2617 +#define LTQ_ES_RA_03_00_REG_RA01_SPAN_VAL(val) (((val) & 0x1) << 14)
2618 +#define LTQ_ES_RA_03_00_REG_RA01_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_SPAN) >> 14) & 0x1)
2619 +#define LTQ_ES_RA_03_00_REG_RA01_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_SPAN) | (((val) & 0x1) << 14))
2620 +/* Management bit for 0180C2000001 (13) */
2621 +#define LTQ_ES_RA_03_00_REG_RA01_MG (0x1 << 13)
2622 +#define LTQ_ES_RA_03_00_REG_RA01_MG_VAL(val) (((val) & 0x1) << 13)
2623 +#define LTQ_ES_RA_03_00_REG_RA01_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_MG) >> 13) & 0x1)
2624 +#define LTQ_ES_RA_03_00_REG_RA01_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_MG) | (((val) & 0x1) << 13))
2625 +/* Cross_VLAN bit for 0180C2000001 (12) */
2626 +#define LTQ_ES_RA_03_00_REG_RA01_CV (0x1 << 12)
2627 +#define LTQ_ES_RA_03_00_REG_RA01_CV_VAL(val) (((val) & 0x1) << 12)
2628 +#define LTQ_ES_RA_03_00_REG_RA01_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_CV) >> 12) & 0x1)
2629 +#define LTQ_ES_RA_03_00_REG_RA01_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_CV) | (((val) & 0x1) << 12))
2630 +/* TXTAG bit for 0180C2000001 (11:10) */
2631 +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG (0x3 << 10)
2632 +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_VAL(val) (((val) & 0x3) << 10)
2633 +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_TXTAG) >> 10) & 0x3)
2634 +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_TXTAG) | (((val) & 0x3) << 10))
2635 +/* Action bit for 0180C2000001 (9:8) */
2636 +#define LTQ_ES_RA_03_00_REG_RA01_ACT (0x3 << 8)
2637 +#define LTQ_ES_RA_03_00_REG_RA01_ACT_VAL(val) (((val) & 0x3) << 8)
2638 +#define LTQ_ES_RA_03_00_REG_RA01_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_ACT) >> 8) & 0x3)
2639 +#define LTQ_ES_RA_03_00_REG_RA01_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_ACT) | (((val) & 0x3) << 8))
2640 +/* Valid bit for 0180C2000000 (7) */
2641 +#define LTQ_ES_RA_03_00_REG_RA00_VALID (0x1 << 7)
2642 +#define LTQ_ES_RA_03_00_REG_RA00_VALID_VAL(val) (((val) & 0x1) << 7)
2643 +#define LTQ_ES_RA_03_00_REG_RA00_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_VALID) >> 7) & 0x1)
2644 +#define LTQ_ES_RA_03_00_REG_RA00_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_VALID) | (((val) & 0x1) << 7))
2645 +/* Span bit for 0180C2000000 (6) */
2646 +#define LTQ_ES_RA_03_00_REG_RA00_SPAN (0x1 << 6)
2647 +#define LTQ_ES_RA_03_00_REG_RA00_SPAN_VAL(val) (((val) & 0x1) << 6)
2648 +#define LTQ_ES_RA_03_00_REG_RA00_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_SPAN) >> 6) & 0x1)
2649 +#define LTQ_ES_RA_03_00_REG_RA00_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_SPAN) | (((val) & 0x1) << 6))
2650 +/* Management bit for 0180C2000000 (5) */
2651 +#define LTQ_ES_RA_03_00_REG_RA00_MG (0x1 << 5)
2652 +#define LTQ_ES_RA_03_00_REG_RA00_MG_VAL(val) (((val) & 0x1) << 5)
2653 +#define LTQ_ES_RA_03_00_REG_RA00_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_MG) >> 5) & 0x1)
2654 +#define LTQ_ES_RA_03_00_REG_RA00_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_MG) | (((val) & 0x1) << 5))
2655 +/* Cross_VLAN bit for 0180C2000000 (4) */
2656 +#define LTQ_ES_RA_03_00_REG_RA00_CV (0x1 << 4)
2657 +#define LTQ_ES_RA_03_00_REG_RA00_CV_VAL(val) (((val) & 0x1) << 4)
2658 +#define LTQ_ES_RA_03_00_REG_RA00_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_CV) >> 4) & 0x1)
2659 +#define LTQ_ES_RA_03_00_REG_RA00_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_CV) | (((val) & 0x1) << 4))
2660 +/* TXTAG bit for 0180C2000000 (3:2) */
2661 +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG (0x3 << 2)
2662 +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_VAL(val) (((val) & 0x3) << 2)
2663 +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_TXTAG) >> 2) & 0x3)
2664 +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_TXTAG) | (((val) & 0x3) << 2))
2665 +/* Action bit for 0180C2000000 (1:0) */
2666 +#define LTQ_ES_RA_03_00_REG_RA00_ACT (0x3)
2667 +#define LTQ_ES_RA_03_00_REG_RA00_ACT_VAL(val) (((val) & 0x3) << 0)
2668 +#define LTQ_ES_RA_03_00_REG_RA00_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_ACT) >> 0) & 0x3)
2669 +#define LTQ_ES_RA_03_00_REG_RA00_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_ACT) | (((val) & 0x3) << 0))
2670 +
2671 +/*******************************************************************************
2672 + * Protocol Filter 0
2673 + ******************************************************************************/
2674 +
2675 +/* Value Compared with Protocol in IP Header (31:24) */
2676 +#define LTQ_ES_PRTCL_F0_REG_PFR3 (0xff << 24)
2677 +#define LTQ_ES_PRTCL_F0_REG_PFR3_VAL(val) (((val) & 0xff) << 24)
2678 +#define LTQ_ES_PRTCL_F0_REG_PFR3_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR3) >> 24) & 0xff)
2679 +#define LTQ_ES_PRTCL_F0_REG_PFR3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR3) | (((val) & 0xff) << 24))
2680 +/* Value Compared with Protocol in IP Header (23:16) */
2681 +#define LTQ_ES_PRTCL_F0_REG_PFR2 (0xff << 16)
2682 +#define LTQ_ES_PRTCL_F0_REG_PFR2_VAL(val) (((val) & 0xff) << 16)
2683 +#define LTQ_ES_PRTCL_F0_REG_PFR2_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR2) >> 16) & 0xff)
2684 +#define LTQ_ES_PRTCL_F0_REG_PFR2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR2) | (((val) & 0xff) << 16))
2685 +/* Value Compared with Protocol in IP Header (15:8) */
2686 +#define LTQ_ES_PRTCL_F0_REG_PFR1 (0xff << 8)
2687 +#define LTQ_ES_PRTCL_F0_REG_PFR1_VAL(val) (((val) & 0xff) << 8)
2688 +#define LTQ_ES_PRTCL_F0_REG_PFR1_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR1) >> 8) & 0xff)
2689 +#define LTQ_ES_PRTCL_F0_REG_PFR1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR1) | (((val) & 0xff) << 8))
2690 +/* Value Compared with Protocol in IP Header (7:0) */
2691 +#define LTQ_ES_PRTCL_F0_REG_PFR0 (0xff)
2692 +#define LTQ_ES_PRTCL_F0_REG_PFR0_VAL(val) (((val) & 0xff) << 0)
2693 +#define LTQ_ES_PRTCL_F0_REG_PFR0_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR0) >> 0) & 0xff)
2694 +#define LTQ_ES_PRTCL_F0_REG_PFR0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR0) | (((val) & 0xff) << 0))
2695 +
2696 +#endif
2697 Index: linux-3.3.8/include/linux/svip_nat.h
2698 ===================================================================
2699 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2700 +++ linux-3.3.8/include/linux/svip_nat.h 2012-07-31 15:46:02.476476158 +0200
2701 @@ -0,0 +1,37 @@
2702 +/******************************************************************************
2703 +
2704 + Copyright (c) 2007
2705 + Infineon Technologies AG
2706 + Am Campeon 1-12; 81726 Munich, Germany
2707 +
2708 + THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE,
2709 + WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS
2710 + SOFTWARE IS FREE OF CHARGE.
2711 +
2712 + THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS
2713 + ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING
2714 + WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP,
2715 + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE
2716 + OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD
2717 + PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL
2718 + PROPERTY INFRINGEMENT.
2719 +
2720 + EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT
2721 + FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM
2722 + OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2723 + ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
2724 + DEALINGS IN THE SOFTWARE.
2725 +*******************************************************************************/
2726 +#ifndef _SVIP_NAT_H
2727 +#define _SVIP_NAT_H
2728 +
2729 +/* The declarations here have to be in a header file, because
2730 + * they need to be known both to the kernel module
2731 + * (in chardev.c) and the process calling ioctl (ioctl.c)
2732 + */
2733 +#include <linux/svip_nat_io.h>
2734 +
2735 +#define SVIP_NAT_VERSION "3.1"
2736 +extern int do_SVIP_NAT(struct sk_buff *);
2737 +
2738 +#endif
2739 Index: linux-3.3.8/include/linux/svip_nat_io.h
2740 ===================================================================
2741 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2742 +++ linux-3.3.8/include/linux/svip_nat_io.h 2012-07-31 15:46:02.476476158 +0200
2743 @@ -0,0 +1,103 @@
2744 +/******************************************************************************
2745 +
2746 + Copyright (c) 2007
2747 + Infineon Technologies AG
2748 + Am Campeon 1-12; 81726 Munich, Germany
2749 +
2750 + THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE,
2751 + WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS
2752 + SOFTWARE IS FREE OF CHARGE.
2753 +
2754 + THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS
2755 + ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING
2756 + WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP,
2757 + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE
2758 + OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD
2759 + PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL
2760 + PROPERTY INFRINGEMENT.
2761 +
2762 + EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT
2763 + FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM
2764 + OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2765 + ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
2766 + DEALINGS IN THE SOFTWARE.
2767 + *******************************************************************************/
2768 +#ifndef _SVIP_NAT_IO_H_
2769 +#define _SVIP_NAT_IO_H_
2770 +
2771 +#include <asm/ioctl.h>
2772 +
2773 +#define SVIP_NAT_DEVICE_NAME "svip_nat"
2774 +#define PATH_SVIP_NAT_DEVICE_NAME "/dev/"SVIP_NAT_DEVICE_NAME
2775 +
2776 +#define MAJOR_NUM_SVIP_NAT 10
2777 +#define MINOR_NUM_SVIP_NAT 120
2778 +
2779 +/** maximum SVIP devices supported on a Line card system */
2780 +#define SVIP_SYS_NUM 12
2781 +
2782 +/** maximum voice packet channels possible per SVIP device */
2783 +#define SVIP_CODEC_NUM 16
2784 +
2785 +/** start UDP port number of the SVIP Linecard System */
2786 +#define SVIP_UDP_FROM 50000
2787 +
2788 +/** @defgroup SVIP_NATAPI SVIP Custom NAT ioctl interface.
2789 + An ioctl interface is provided to add a rule into the SVIP NAT table and
2790 + to respectively remove the rule form it. The ioctl interface is accessible
2791 + using the fd issued upon opening the special device node /dev/svip_nat.
2792 + @{ */
2793 +
2794 +/** Used to add a new rule to the SVIP Custom NAT table. If a rule already
2795 + exists for the target UDP port, that rule shall be overwritten.
2796 +
2797 + \param SVIP_NAT_IO_Rule_t* The parameter points to a
2798 + \ref SVIP_NAT_IO_Rule_t structure.
2799 + */
2800 +#define FIO_SVIP_NAT_RULE_ADD \
2801 + _IOW(MAJOR_NUM_SVIP_NAT, 1, SVIP_NAT_IO_Rule_t)
2802 +
2803 +/** Used to remove a rule from the SVIP Custom NAT table. No check is
2804 + performed whether the rule already exists or not. The remove operation is
2805 + performed as long as the target UDP port is within the defined port range.
2806 +
2807 + \param SVIP_NAT_IO_Rule_t* The parameter points to a
2808 + \ref SVIP_NAT_IO_Rule_t structure.
2809 + */
2810 +#define FIO_SVIP_NAT_RULE_REMOVE \
2811 + _IOW(MAJOR_NUM_SVIP_NAT, 2, SVIP_NAT_IO_Rule_t)
2812 +
2813 +/** Used to list all rules in the SVIP Custom NAT table.
2814 +
2815 + \param <none>
2816 + */
2817 +#define FIO_SVIP_NAT_RULE_LIST \
2818 + _IO(MAJOR_NUM_SVIP_NAT, 3)
2819 +
2820 +/** IP address in network-byte order */
2821 +typedef u32 SVIP_IP_ADDR_t;
2822 +/** UDP port in network-byte order */
2823 +typedef u16 SVIP_UDP_PORT_t;
2824 +
2825 +#ifndef ETH_ALEN
2826 +#define ETH_ALEN 6 /* Octets in one ethernet address */
2827 +#endif
2828 +
2829 +/** NAT parameters part of the NAT table.
2830 + These paramters are configurable through the NAT API. */
2831 +typedef struct SVIP_NAT_IO_Rule
2832 +{
2833 + /** Remote peer, IP address */
2834 + SVIP_IP_ADDR_t remIP;
2835 + /** Remote peer, MAC address */
2836 + u8 remMAC[ETH_ALEN];
2837 + /** Target SVIP, IP address (local peer) */
2838 + SVIP_IP_ADDR_t locIP;
2839 + /** Target SVIP, MAC address */
2840 + u8 locMAC[ETH_ALEN];
2841 + /** Target SVIP, UDP port number */
2842 + SVIP_UDP_PORT_t locUDP;
2843 +} SVIP_NAT_IO_Rule_t;
2844 +
2845 +/** @} */
2846 +#endif
2847 Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h
2848 ===================================================================
2849 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2850 +++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h 2012-07-31 15:46:02.476476158 +0200
2851 @@ -0,0 +1,242 @@
2852 +/******************************************************************************
2853 +
2854 + Copyright (c) 2007
2855 + Infineon Technologies AG
2856 + St. Martin Strasse 53; 81669 Munich, Germany
2857 +
2858 + Any use of this Software is subject to the conclusion of a respective
2859 + License Agreement. Without such a License Agreement no rights to the
2860 + Software are granted.
2861 +
2862 + ******************************************************************************/
2863 +
2864 +#ifndef __MPS_REG_H
2865 +#define __MPS_REG_H
2866 +
2867 +#define mbs_r32(reg) ltq_r32(&mbs->reg)
2868 +#define mbs_w32(val, reg) ltq_w32(val, &mbs->reg)
2869 +#define mbs_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &mbs->reg)
2870 +
2871 +/** MBS register structure */
2872 +struct svip_reg_mbs {
2873 + unsigned long reserved0[4];
2874 + unsigned long mbsr0; /* 0x0010 */
2875 + unsigned long mbsr1; /* 0x0014 */
2876 + unsigned long mbsr2; /* 0x0018 */
2877 + unsigned long mbsr3; /* 0x001c */
2878 + unsigned long mbsr4; /* 0x0020 */
2879 + unsigned long mbsr5; /* 0x0024 */
2880 + unsigned long mbsr6; /* 0x0028 */
2881 + unsigned long mbsr7; /* 0x002c */
2882 + unsigned long mbsr8; /* 0x0030 */
2883 + unsigned long mbsr9; /* 0x0034 */
2884 + unsigned long mbsr10; /* 0x0038 */
2885 + unsigned long mbsr11; /* 0x003c */
2886 + unsigned long mbsr12; /* 0x0040 */
2887 + unsigned long mbsr13; /* 0x0044 */
2888 + unsigned long mbsr14; /* 0x0048 */
2889 + unsigned long mbsr15; /* 0x004c */
2890 + unsigned long mbsr16; /* 0x0050 */
2891 + unsigned long mbsr17; /* 0x0054 */
2892 + unsigned long mbsr18; /* 0x0058 */
2893 + unsigned long mbsr19; /* 0x005c */
2894 + unsigned long mbsr20; /* 0x0060 */
2895 + unsigned long mbsr21; /* 0x0064 */
2896 + unsigned long mbsr22; /* 0x0068 */
2897 + unsigned long mbsr23; /* 0x006c */
2898 + unsigned long mbsr24; /* 0x0070 */
2899 + unsigned long mbsr25; /* 0x0074 */
2900 + unsigned long mbsr26; /* 0x0078 */
2901 + unsigned long mbsr27; /* 0x007c */
2902 + unsigned long mbsr28; /* 0x0080 */
2903 +};
2904 +
2905 +/** MPS register structure */
2906 +struct svip_reg_mps {
2907 + volatile unsigned long mps_swirn0set; /* 0x0000 */
2908 + volatile unsigned long mps_swirn0en; /* 0x0004 */
2909 + volatile unsigned long mps_swirn0cr; /* 0x0008 */
2910 + volatile unsigned long mps_swirn0icr; /* 0x000C */
2911 + volatile unsigned long mps_swirn1set; /* 0x0010 */
2912 + volatile unsigned long mps_swirn1en; /* 0x0014 */
2913 + volatile unsigned long mps_swirn1cr; /* 0x0018 */
2914 + volatile unsigned long mps_swirn1icr; /* 0x001C */
2915 + volatile unsigned long mps_swirn2set; /* 0x0020 */
2916 + volatile unsigned long mps_swirn2en; /* 0x0024 */
2917 + volatile unsigned long mps_swirn2cr; /* 0x0028 */
2918 + volatile unsigned long mps_swirn2icr; /* 0x002C */
2919 + volatile unsigned long mps_swirn3set; /* 0x0030 */
2920 + volatile unsigned long mps_swirn3en; /* 0x0034 */
2921 + volatile unsigned long mps_swirn3cr; /* 0x0038 */
2922 + volatile unsigned long mps_swirn3icr; /* 0x003C */
2923 + volatile unsigned long mps_swirn4set; /* 0x0040 */
2924 + volatile unsigned long mps_swirn4en; /* 0x0044 */
2925 + volatile unsigned long mps_swirn4cr; /* 0x0048 */
2926 + volatile unsigned long mps_swirn4icr; /* 0x004C */
2927 + volatile unsigned long mps_swirn5set; /* 0x0050 */
2928 + volatile unsigned long mps_swirn5en; /* 0x0054 */
2929 + volatile unsigned long mps_swirn5cr; /* 0x0058 */
2930 + volatile unsigned long mps_swirn5icr; /* 0x005C */
2931 + volatile unsigned long mps_swirn6set; /* 0x0060 */
2932 + volatile unsigned long mps_swirn6en; /* 0x0064 */
2933 + volatile unsigned long mps_swirn6cr; /* 0x0068 */
2934 + volatile unsigned long mps_swirn6icr; /* 0x006C */
2935 + volatile unsigned long mps_swirn7set; /* 0x0070 */
2936 + volatile unsigned long mps_swirn7en; /* 0x0074 */
2937 + volatile unsigned long mps_swirn7cr; /* 0x0078 */
2938 + volatile unsigned long mps_swirn7icr; /* 0x007C */
2939 + volatile unsigned long mps_swirn8set; /* 0x0080 */
2940 + volatile unsigned long mps_swirn8en; /* 0x0084 */
2941 + volatile unsigned long mps_swirn8cr; /* 0x0088 */
2942 + volatile unsigned long mps_swirn8icr; /* 0x008C */
2943 +};
2944 +
2945 +/* Software Interrupt */
2946 +#define IFX_MPS_SWIRN0SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0000))
2947 +#define IFX_MPS_SWIRN0EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0004))
2948 +#define IFX_MPS_SWIRN0CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0008))
2949 +#define IFX_MPS_SWIRN0ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x000C))
2950 +#define IFX_MPS_SWIRN1SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0010))
2951 +#define IFX_MPS_SWIRN1EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0014))
2952 +#define IFX_MPS_SWIRN1CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0018))
2953 +#define IFX_MPS_SWIRN1ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x001C))
2954 +#define IFX_MPS_SWIRN2SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0020))
2955 +#define IFX_MPS_SWIRN2EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0024))
2956 +#define IFX_MPS_SWIRN2CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0028))
2957 +#define IFX_MPS_SWIRN2ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x002C))
2958 +#define IFX_MPS_SWIRN3SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0030))
2959 +#define IFX_MPS_SWIRN3EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0034))
2960 +#define IFX_MPS_SWIRN3CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0038))
2961 +#define IFX_MPS_SWIRN3ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x003C))
2962 +#define IFX_MPS_SWIRN4SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0040))
2963 +#define IFX_MPS_SWIRN4EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0044))
2964 +#define IFX_MPS_SWIRN4CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0048))
2965 +#define IFX_MPS_SWIRN4ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x004C))
2966 +#define IFX_MPS_SWIRN5SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0050))
2967 +#define IFX_MPS_SWIRN5EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0054))
2968 +#define IFX_MPS_SWIRN5CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0058))
2969 +#define IFX_MPS_SWIRN5ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x005C))
2970 +#define IFX_MPS_SWIRN6SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0060))
2971 +#define IFX_MPS_SWIRN6EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0064))
2972 +#define IFX_MPS_SWIRN6CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0068))
2973 +#define IFX_MPS_SWIRN6ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x006C))
2974 +#define IFX_MPS_SWIRN7SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0070))
2975 +#define IFX_MPS_SWIRN7EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0074))
2976 +#define IFX_MPS_SWIRN7CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0078))
2977 +#define IFX_MPS_SWIRN7ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x007C))
2978 +#define IFX_MPS_SWIRN8SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0080))
2979 +#define IFX_MPS_SWIRN8EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0084))
2980 +#define IFX_MPS_SWIRN8ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x008C))
2981 +#define IFX_MPS_SWIRN8CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0088))
2982 +
2983 +/*******************************************************************************
2984 + * MPS_SWIRNSET Register
2985 + ******************************************************************************/
2986 +
2987 +/* Software Interrupt Request IR5 (5) */
2988 +#define IFX_MPS_SWIRNSET_IR5 (0x1 << 5)
2989 +#define IFX_MPS_SWIRNSET_IR5_VAL(val) (((val) & 0x1) << 5)
2990 +#define IFX_MPS_SWIRNSET_IR5_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR5) | (val) & 1) << 5)
2991 +/* Software Interrupt Request IR4 (4) */
2992 +#define IFX_MPS_SWIRNSET_IR4 (0x1 << 4)
2993 +#define IFX_MPS_SWIRNSET_IR4_VAL(val) (((val) & 0x1) << 4)
2994 +#define IFX_MPS_SWIRNSET_IR4_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR4) | (val) & 1) << 4)
2995 +/* Software Interrupt Request IR3 (3) */
2996 +#define IFX_MPS_SWIRNSET_IR3 (0x1 << 3)
2997 +#define IFX_MPS_SWIRNSET_IR3_VAL(val) (((val) & 0x1) << 3)
2998 +#define IFX_MPS_SWIRNSET_IR3_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR3) | (val) & 1) << 3)
2999 +/* Software Interrupt Request IR2 (2) */
3000 +#define IFX_MPS_SWIRNSET_IR2 (0x1 << 2)
3001 +#define IFX_MPS_SWIRNSET_IR2_VAL(val) (((val) & 0x1) << 2)
3002 +#define IFX_MPS_SWIRNSET_IR2_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR2) | (val) & 1) << 2)
3003 +/* Software Interrupt Request IR1 (1) */
3004 +#define IFX_MPS_SWIRNSET_IR1 (0x1 << 1)
3005 +#define IFX_MPS_SWIRNSET_IR1_VAL(val) (((val) & 0x1) << 1)
3006 +#define IFX_MPS_SWIRNSET_IR1_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR1) | (val) & 1) << 1)
3007 +/* Software Interrupt Request IR0 (0) */
3008 +#define IFX_MPS_SWIRNSET_IR0 (0x1)
3009 +#define IFX_MPS_SWIRNSET_IR0_VAL(val) (((val) & 0x1) << 0)
3010 +#define IFX_MPS_SWIRNSET_IR0_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR0) | (val) & 1) << 0)
3011 +
3012 +/*******************************************************************************
3013 + * MPS_SWIRNEN Register
3014 + ******************************************************************************/
3015 +
3016 +/* Software Interrupt Request IR5 (5) */
3017 +#define IFX_MPS_SWIRNEN_IR5 (0x1 << 5)
3018 +#define IFX_MPS_SWIRNEN_IR5_VAL(val) (((val) & 0x1) << 5)
3019 +#define IFX_MPS_SWIRNEN_IR5_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR5) >> 5) & 0x1)
3020 +#define IFX_MPS_SWIRNEN_IR5_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR5) | (((val) & 0x1) << 5))
3021 +/* Software Interrupt Request IR4 (4) */
3022 +#define IFX_MPS_SWIRNEN_IR4 (0x1 << 4)
3023 +#define IFX_MPS_SWIRNEN_IR4_VAL(val) (((val) & 0x1) << 4)
3024 +#define IFX_MPS_SWIRNEN_IR4_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR4) >> 4) & 0x1)
3025 +#define IFX_MPS_SWIRNEN_IR4_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR4) | (((val) & 0x1) << 4))
3026 +/* Software Interrupt Request IR3 (3) */
3027 +#define IFX_MPS_SWIRNEN_IR3 (0x1 << 3)
3028 +#define IFX_MPS_SWIRNEN_IR3_VAL(val) (((val) & 0x1) << 3)
3029 +#define IFX_MPS_SWIRNEN_IR3_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR3) >> 3) & 0x1)
3030 +#define IFX_MPS_SWIRNEN_IR3_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR3) | (((val) & 0x1) << 3))
3031 +/* Software Interrupt Request IR2 (2) */
3032 +#define IFX_MPS_SWIRNEN_IR2 (0x1 << 2)
3033 +#define IFX_MPS_SWIRNEN_IR2_VAL(val) (((val) & 0x1) << 2)
3034 +#define IFX_MPS_SWIRNEN_IR2_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR2) >> 2) & 0x1)
3035 +#define IFX_MPS_SWIRNEN_IR2_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR2) | (((val) & 0x1) << 2))
3036 +/* Software Interrupt Request IR1 (1) */
3037 +#define IFX_MPS_SWIRNEN_IR1 (0x1 << 1)
3038 +#define IFX_MPS_SWIRNEN_IR1_VAL(val) (((val) & 0x1) << 1)
3039 +#define IFX_MPS_SWIRNEN_IR1_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR1) >> 1) & 0x1)
3040 +#define IFX_MPS_SWIRNEN_IR1_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR1) | (((val) & 0x1) << 1))
3041 +/* Software Interrupt Request IR0 (0) */
3042 +#define IFX_MPS_SWIRNEN_IR0 (0x1)
3043 +#define IFX_MPS_SWIRNEN_IR0_VAL(val) (((val) & 0x1) << 0)
3044 +#define IFX_MPS_SWIRNEN_IR0_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR0) >> 0) & 0x1)
3045 +#define IFX_MPS_SWIRNEN_IR0_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR0) | (((val) & 0x1) << 0))
3046 +
3047 +/*******************************************************************************
3048 + * MPS_SWIRNICR Register
3049 + ******************************************************************************/
3050 +
3051 +/* Software Interrupt Request IR5 (5) */
3052 +#define IFX_MPS_SWIRNICR_IR5 (0x1 << 5)
3053 +#define IFX_MPS_SWIRNICR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR5) >> 5) & 0x1)
3054 +/* Software Interrupt Request IR4 (4) */
3055 +#define IFX_MPS_SWIRNICR_IR4 (0x1 << 4)
3056 +#define IFX_MPS_SWIRNICR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR4) >> 4) & 0x1)
3057 +/* Software Interrupt Request IR3 (3) */
3058 +#define IFX_MPS_SWIRNICR_IR3 (0x1 << 3)
3059 +#define IFX_MPS_SWIRNICR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR3) >> 3) & 0x1)
3060 +/* Software Interrupt Request IR2 (2) */
3061 +#define IFX_MPS_SWIRNICR_IR2 (0x1 << 2)
3062 +#define IFX_MPS_SWIRNICR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR2) >> 2) & 0x1)
3063 +/* Software Interrupt Request IR1 (1) */
3064 +#define IFX_MPS_SWIRNICR_IR1 (0x1 << 1)
3065 +#define IFX_MPS_SWIRNICR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR1) >> 1) & 0x1)
3066 +/* Software Interrupt Request IR0 (0) */
3067 +#define IFX_MPS_SWIRNICR_IR0 (0x1)
3068 +#define IFX_MPS_SWIRNICR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR0) >> 0) & 0x1)
3069 +
3070 +/*******************************************************************************
3071 + * MPS_SWIRNCR Register
3072 + ******************************************************************************/
3073 +
3074 +/* Software Interrupt Request IR5 (5) */
3075 +#define IFX_MPS_SWIRNCR_IR5 (0x1 << 5)
3076 +#define IFX_MPS_SWIRNCR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR5) >> 5) & 0x1)
3077 +/* Software Interrupt Request IR4 (4) */
3078 +#define IFX_MPS_SWIRNCR_IR4 (0x1 << 4)
3079 +#define IFX_MPS_SWIRNCR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR4) >> 4) & 0x1)
3080 +/* Software Interrupt Request IR3 (3) */
3081 +#define IFX_MPS_SWIRNCR_IR3 (0x1 << 3)
3082 +#define IFX_MPS_SWIRNCR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR3) >> 3) & 0x1)
3083 +/* Software Interrupt Request IR2 (2) */
3084 +#define IFX_MPS_SWIRNCR_IR2 (0x1 << 2)
3085 +#define IFX_MPS_SWIRNCR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR2) >> 2) & 0x1)
3086 +/* Software Interrupt Request IR1 (1) */
3087 +#define IFX_MPS_SWIRNCR_IR1 (0x1 << 1)
3088 +#define IFX_MPS_SWIRNCR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR1) >> 1) & 0x1)
3089 +/* Software Interrupt Request IR0 (0) */
3090 +#define IFX_MPS_SWIRNCR_IR0 (0x1)
3091 +#define IFX_MPS_SWIRNCR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR0) >> 0) & 0x1)
3092 +
3093 +#endif
3094 Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/status_reg.h
3095 ===================================================================
3096 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3097 +++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/status_reg.h 2012-07-31 15:46:02.476476158 +0200
3098 @@ -0,0 +1,130 @@
3099 +/******************************************************************************
3100 +
3101 + Copyright (c) 2007
3102 + Infineon Technologies AG
3103 + St. Martin Strasse 53; 81669 Munich, Germany
3104 +
3105 + Any use of this Software is subject to the conclusion of a respective
3106 + License Agreement. Without such a License Agreement no rights to the
3107 + Software are granted.
3108 +
3109 + ******************************************************************************/
3110 +
3111 +#ifndef __STATUS_REG_H
3112 +#define __STATUS_REG_H
3113 +
3114 +#define status_r32(reg) ltq_r32(&status->reg)
3115 +#define status_w32(val, reg) ltq_w32(val, &status->reg)
3116 +#define status_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &status->reg)
3117 +
3118 +/** STATUS register structure */
3119 +struct svip_reg_status {
3120 + unsigned long fuse_deu; /* 0x0000 */
3121 + unsigned long fuse_cpu; /* 0x0004 */
3122 + unsigned long fuse_pll; /* 0x0008 */
3123 + unsigned long chipid; /* 0x000C */
3124 + unsigned long config; /* 0x0010 */
3125 + unsigned long chip_loc; /* 0x0014 */
3126 + unsigned long fuse_spare; /* 0x0018 */
3127 +};
3128 +
3129 +/*******************************************************************************
3130 + * Fuse for DEU Settings
3131 + ******************************************************************************/
3132 +
3133 +/* Fuse for Enabling the TRNG (6) */
3134 +#define STATUS_FUSE_DEU_TRNG (0x1 << 6)
3135 +#define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1)
3136 +/* Fuse for Enabling the DES Submodule (5) */
3137 +#define STATUS_FUSE_DEU_DES (0x1 << 5)
3138 +#define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1)
3139 +/* Fuse for Enabling the 3DES Submodule (4) */
3140 +#define STATUS_FUSE_DEU_3DES (0x1 << 4)
3141 +#define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1)
3142 +/* Fuse for Enabling the AES Submodule (3) */
3143 +#define STATUS_FUSE_DEU_AES (0x1 << 3)
3144 +#define STATUS_FUSE_DEU_AES_GET(val) ((((val) & STATUS_FUSE_DEU_AES) >> 3) & 0x1)
3145 +/* Fuse for Enabling the HASH Submodule (2) */
3146 +#define STATUS_FUSE_DEU_HASH (0x1 << 2)
3147 +#define STATUS_FUSE_DEU_HASH_GET(val) ((((val) & STATUS_FUSE_DEU_HASH) >> 2) & 0x1)
3148 +/* Fuse for Enabling the ARC4 Submodule (1) */
3149 +#define STATUS_FUSE_DEU_ARC4 (0x1 << 1)
3150 +#define STATUS_FUSE_DEU_ARC4_GET(val) ((((val) & STATUS_FUSE_DEU_ARC4) >> 1) & 0x1)
3151 +/* Fuse for Enabling the DEU Module (0) */
3152 +#define STATUS_FUSE_DEU_DEU (0x1)
3153 +#define STATUS_FUSE_DEU_DEU_GET(val) ((((val) & STATUS_FUSE_DEU_DEU) >> 0) & 0x1)
3154 +
3155 +/*******************************************************************************
3156 + * Fuse for CPU Settings
3157 + ******************************************************************************/
3158 +
3159 +/* Fuse for Enabling CPU5 (5) */
3160 +#define STATUS_FUSE_CPU_CPU5 (0x1 << 5)
3161 +#define STATUS_FUSE_CPU_CPU5_GET(val) ((((val) & STATUS_FUSE_CPU_CPU5) >> 5) & 0x1)
3162 +/* Fuse for Enabling the CPU4 (4) */
3163 +#define STATUS_FUSE_CPU_CPU4 (0x1 << 4)
3164 +#define STATUS_FUSE_CPU_CPU4_GET(val) ((((val) & STATUS_FUSE_CPU_CPU4) >> 4) & 0x1)
3165 +/* Fuse for Enabling the CPU3 (3) */
3166 +#define STATUS_FUSE_CPU_CPU3 (0x1 << 3)
3167 +#define STATUS_FUSE_CPU_CPU3_GET(val) ((((val) & STATUS_FUSE_CPU_CPU3) >> 3) & 0x1)
3168 +/* Fuse for Enabling the CPU2 (2) */
3169 +#define STATUS_FUSE_CPU_CPU2 (0x1 << 2)
3170 +#define STATUS_FUSE_CPU_CPU2_GET(val) ((((val) & STATUS_FUSE_CPU_CPU2) >> 2) & 0x1)
3171 +/* Fuse for Enabling the CPU1 (1) */
3172 +#define STATUS_FUSE_CPU_CPU1 (0x1 << 1)
3173 +#define STATUS_FUSE_CPU_CPU1_GET(val) ((((val) & STATUS_FUSE_CPU_CPU1) >> 1) & 0x1)
3174 +/* Fuse for Enabling the CPU0 (0) */
3175 +#define STATUS_FUSE_CPU_CPU0 (0x1)
3176 +#define STATUS_FUSE_CPU_CPU0_GET(val) ((((val) & STATUS_FUSE_CPU_CPU0) >> 0) & 0x1)
3177 +
3178 +/*******************************************************************************
3179 + * Fuse for PLL Settings
3180 + ******************************************************************************/
3181 +
3182 +/* Fuse for Enabling PLL (7:0) */
3183 +#define STATUS_FUSE_PLL_PLL (0xff)
3184 +#define STATUS_FUSE_PLL_PLL_GET(val) ((((val) & STATUS_FUSE_PLL_PLL) >> 0) & 0xff)
3185 +
3186 +/*******************************************************************************
3187 + * Chip Identification Register
3188 + ******************************************************************************/
3189 +
3190 +/* Chip Version Number (31:28) */
3191 +#define STATUS_CHIPID_VERSION (0xf << 28)
3192 +#define STATUS_CHIPID_VERSION_GET(val) ((((val) & STATUS_CHIPID_VERSION) >> 28) & 0xf)
3193 +/* Part Number (27:12) */
3194 +#define STATUS_CHIPID_PART_NUMBER (0xffff << 12)
3195 +#define STATUS_CHIPID_PART_NUMBER_GET(val) ((((val) & STATUS_CHIPID_PART_NUMBER) >> 12) & 0xffff)
3196 +/* Manufacturer ID (11:1) */
3197 +#define STATUS_CHIPID_MANID (0x7ff << 1)
3198 +#define STATUS_CHIPID_MANID_GET(val) ((((val) & STATUS_CHIPID_MANID) >> 1) & 0x7ff)
3199 +
3200 +/*******************************************************************************
3201 + * Chip Configuration Register
3202 + ******************************************************************************/
3203 +
3204 +/* Number of Analog Channels (8:5) */
3205 +#define STATUS_CONFIG_ANA_CHAN (0xf << 5)
3206 +#define STATUS_CONFIG_ANA_CHAN_GET(val) ((((val) & STATUS_CONFIG_ANA_CHAN) >> 5) & 0xf)
3207 +/* Clock Mode (4) */
3208 +#define STATUS_CONFIG_CLK_MODE (0x1 << 1)
3209 +#define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1)
3210 +/* Subversion Number (3:0) */
3211 +#define STATUS_CONFIG_SUB_VERS (0xF)
3212 +#define STATUS_CONFIG_SUB_VERS_GET(val) ((((val) & STATUS_SUBVER_SUB_VERS) >> 0) & 0xF)
3213 +
3214 +/*******************************************************************************
3215 + * Chip Location Register
3216 + ******************************************************************************/
3217 +
3218 +/* Chip Lot ID (31:16) */
3219 +#define STATUS_CHIP_LOC_CHIP_LOT (0xffff << 16)
3220 +#define STATUS_CHIP_LOC_CHIP_LOT_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_LOT) >> 16) & 0xffff)
3221 +/* Chip X Coordinate (15:8) */