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[lantiq] add linux-v3.7
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.7 / 0117-NET-MIPS-lantiq-adds-xrx200-net.patch
1 From a0a6f7f03c914327064364767b7ba688cdbcf611 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Oct 2012 12:22:23 +0200
4 Subject: [PATCH 117/123] NET: MIPS: lantiq: adds xrx200-net
5
6 ---
7 drivers/net/ethernet/Kconfig | 8 +-
8 drivers/net/ethernet/Makefile | 1 +
9 drivers/net/ethernet/lantiq_pce.h | 163 +++++
10 drivers/net/ethernet/lantiq_xrx200.c | 1191 ++++++++++++++++++++++++++++++++++
11 4 files changed, 1362 insertions(+), 1 deletion(-)
12 create mode 100644 drivers/net/ethernet/lantiq_pce.h
13 create mode 100644 drivers/net/ethernet/lantiq_xrx200.c
14
15 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
16 index e4ff389..35cb7b0 100644
17 --- a/drivers/net/ethernet/Kconfig
18 +++ b/drivers/net/ethernet/Kconfig
19 @@ -83,7 +83,13 @@ config LANTIQ_ETOP
20 tristate "Lantiq SoC ETOP driver"
21 depends on SOC_TYPE_XWAY
22 ---help---
23 - Support for the MII0 inside the Lantiq SoC
24 + Support for the MII0 inside the Lantiq ADSL SoC
25 +
26 +config LANTIQ_XRX200
27 + tristate "Lantiq SoC XRX200 driver"
28 + depends on SOC_TYPE_XWAY
29 + ---help---
30 + Support for the MII0 inside the Lantiq VDSL SoC
31
32 source "drivers/net/ethernet/marvell/Kconfig"
33 source "drivers/net/ethernet/mellanox/Kconfig"
34 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
35 index d447307..4f95100 100644
36 --- a/drivers/net/ethernet/Makefile
37 +++ b/drivers/net/ethernet/Makefile
38 @@ -36,6 +36,7 @@ obj-$(CONFIG_IP1000) += icplus/
39 obj-$(CONFIG_JME) += jme.o
40 obj-$(CONFIG_KORINA) += korina.o
41 obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
42 +obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o
43 obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
44 obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
45 obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
46 diff --git a/drivers/net/ethernet/lantiq_pce.h b/drivers/net/ethernet/lantiq_pce.h
47 new file mode 100644
48 index 0000000..0c38efe
49 --- /dev/null
50 +++ b/drivers/net/ethernet/lantiq_pce.h
51 @@ -0,0 +1,163 @@
52 +/*
53 + * This program is free software; you can redistribute it and/or modify it
54 + * under the terms of the GNU General Public License version 2 as published
55 + * by the Free Software Foundation.
56 + *
57 + * This program is distributed in the hope that it will be useful,
58 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
59 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
60 + * GNU General Public License for more details.
61 + *
62 + * You should have received a copy of the GNU General Public License
63 + * along with this program; if not, write to the Free Software
64 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
65 + *
66 + * Copyright (C) 2010 Lantiq Deutschland GmbH
67 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
68 + *
69 + * PCE microcode extracted from UGW5.2 switch api
70 + */
71 +
72 +/* Switch API Micro Code V0.3 */
73 +enum {
74 + OUT_MAC0 = 0,
75 + OUT_MAC1,
76 + OUT_MAC2,
77 + OUT_MAC3,
78 + OUT_MAC4,
79 + OUT_MAC5,
80 + OUT_ETHTYP,
81 + OUT_VTAG0,
82 + OUT_VTAG1,
83 + OUT_ITAG0,
84 + OUT_ITAG1, /*10 */
85 + OUT_ITAG2,
86 + OUT_ITAG3,
87 + OUT_IP0,
88 + OUT_IP1,
89 + OUT_IP2,
90 + OUT_IP3,
91 + OUT_SIP0,
92 + OUT_SIP1,
93 + OUT_SIP2,
94 + OUT_SIP3, /*20*/
95 + OUT_SIP4,
96 + OUT_SIP5,
97 + OUT_SIP6,
98 + OUT_SIP7,
99 + OUT_DIP0,
100 + OUT_DIP1,
101 + OUT_DIP2,
102 + OUT_DIP3,
103 + OUT_DIP4,
104 + OUT_DIP5, /*30*/
105 + OUT_DIP6,
106 + OUT_DIP7,
107 + OUT_SESID,
108 + OUT_PROT,
109 + OUT_APP0,
110 + OUT_APP1,
111 + OUT_IGMP0,
112 + OUT_IGMP1,
113 + OUT_IPOFF, /*39*/
114 + OUT_NONE = 63
115 +};
116 +
117 +/* parser's microcode length type */
118 +#define INSTR 0
119 +#define IPV6 1
120 +#define LENACCU 2
121 +
122 +/* parser's microcode flag type */
123 +enum {
124 + FLAG_ITAG = 0,
125 + FLAG_VLAN,
126 + FLAG_SNAP,
127 + FLAG_PPPOE,
128 + FLAG_IPV6,
129 + FLAG_IPV6FL,
130 + FLAG_IPV4,
131 + FLAG_IGMP,
132 + FLAG_TU,
133 + FLAG_HOP,
134 + FLAG_NN1, /*10 */
135 + FLAG_NN2,
136 + FLAG_END,
137 + FLAG_NO, /*13*/
138 +};
139 +
140 +/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */
141 +#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \
142 + { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }}
143 +struct pce_microcode {
144 + unsigned short val[4];
145 +/* unsigned short val_2;
146 + unsigned short val_1;
147 + unsigned short val_0;*/
148 +} pce_microcode[] = {
149 + /* value mask ns fields L type flags ipv4_len */
150 + MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
151 + MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
152 + MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
153 + MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
154 + MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
155 + MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
156 + MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
157 + MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
158 + MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0),
159 + MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
160 + MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
161 + MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0),
162 + MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0),
163 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
164 + MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0),
165 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
166 + MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0),
167 + MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0),
168 + MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0),
169 + MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0),
170 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
171 + MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1),
172 + MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0),
173 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
174 + MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0),
175 + MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0),
176 + MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0),
177 + MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
178 + MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
179 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0),
180 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0),
181 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0),
182 + MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
183 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0),
184 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0),
185 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0),
186 + MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0),
187 + MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0),
188 + MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0),
189 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
190 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
191 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
192 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
193 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
194 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
195 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
196 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
197 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
198 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
199 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
200 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
201 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
202 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
203 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
204 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
205 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
206 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
207 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
208 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
209 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
210 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
211 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
212 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
213 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
214 +};
215 diff --git a/drivers/net/ethernet/lantiq_xrx200.c b/drivers/net/ethernet/lantiq_xrx200.c
216 new file mode 100644
217 index 0000000..458bc11
218 --- /dev/null
219 +++ b/drivers/net/ethernet/lantiq_xrx200.c
220 @@ -0,0 +1,1191 @@
221 +/*
222 + * This program is free software; you can redistribute it and/or modify it
223 + * under the terms of the GNU General Public License version 2 as published
224 + * by the Free Software Foundation.
225 + *
226 + * This program is distributed in the hope that it will be useful,
227 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
228 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
229 + * GNU General Public License for more details.
230 + *
231 + * You should have received a copy of the GNU General Public License
232 + * along with this program; if not, write to the Free Software
233 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
234 + *
235 + * Copyright (C) 2010 Lantiq Deutschland
236 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
237 + */
238 +
239 +#include <linux/etherdevice.h>
240 +#include <linux/module.h>
241 +#include <linux/platform_device.h>
242 +#include <linux/interrupt.h>
243 +#include <linux/clk.h>
244 +#include <asm/delay.h>
245 +
246 +#include <linux/of_net.h>
247 +#include <linux/of_mdio.h>
248 +
249 +#include <xway_dma.h>
250 +#include <lantiq_soc.h>
251 +
252 +#include "lantiq_pce.h"
253 +
254 +#define SW_POLLING
255 +#define SW_ROUTING
256 +#define SW_PORTMAP
257 +
258 +#ifdef SW_ROUTING
259 + #ifdef SW_PORTMAP
260 +#define XRX200_MAX_DEV 7
261 + #else
262 +#define XRX200_MAX_DEV 2
263 + #endif
264 +#else
265 +#define XRX200_MAX_DEV 1
266 +#endif
267 +
268 +#define XRX200_MAX_PORT 7
269 +#define XRX200_MAX_DMA 8
270 +
271 +#define XRX200_HEADROOM 4
272 +
273 +#define XRX200_TX_TIMEOUT (10 * HZ)
274 +
275 +/* port type */
276 +#define XRX200_PORT_TYPE_PHY 1
277 +#define XRX200_PORT_TYPE_MAC 2
278 +
279 +/* DMA */
280 +#define XRX200_DMA_CRC_LEN 0x4
281 +#define XRX200_DMA_DATA_LEN 0x600
282 +#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0
283 +#define XRX200_DMA_RX 0
284 +#define XRX200_DMA_TX 1
285 +
286 +/* fetch / store dma */
287 +#define FDMA_PCTRL0 0x2A00
288 +#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18))
289 +#define SDMA_PCTRL0 0x2F00
290 +#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18))
291 +
292 +/* buffer management */
293 +#define BM_PCFG0 0x200
294 +#define BM_PCFGx(x) (BM_PCFG0 + (x * 8))
295 +
296 +/* MDIO */
297 +#define MDIO_GLOB 0x0000
298 +#define MDIO_CTRL 0x0020
299 +#define MDIO_READ 0x0024
300 +#define MDIO_WRITE 0x0028
301 +#define MDIO_PHY0 0x0054
302 +#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned)))
303 +#define MDIO_CLK_CFG0 0x002C
304 +#define MDIO_CLK_CFG1 0x0030
305 +
306 +#define MDIO_GLOB_ENABLE 0x8000
307 +#define MDIO_BUSY BIT(12)
308 +#define MDIO_RD BIT(11)
309 +#define MDIO_WR BIT(10)
310 +#define MDIO_MASK 0x1f
311 +#define MDIO_ADDRSHIFT 5
312 +#define MDIO1_25MHZ 9
313 +
314 +#define MDIO_PHY_LINK_DOWN 0x4000
315 +#define MDIO_PHY_LINK_UP 0x2000
316 +
317 +#define MDIO_PHY_SPEED_M10 0x0000
318 +#define MDIO_PHY_SPEED_M100 0x0800
319 +#define MDIO_PHY_SPEED_G1 0x1000
320 +
321 +#define MDIO_PHY_FDUP_EN 0x0600
322 +#define MDIO_PHY_FDUP_DIS 0x0200
323 +
324 +#define MDIO_PHY_LINK_MASK 0x6000
325 +#define MDIO_PHY_SPEED_MASK 0x1800
326 +#define MDIO_PHY_FDUP_MASK 0x0600
327 +#define MDIO_PHY_ADDR_MASK 0x001f
328 +#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \
329 + MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK
330 +
331 +/* MII */
332 +#define MII_CFG(p) (p * 8)
333 +
334 +#define MII_CFG_EN BIT(14)
335 +
336 +#define MII_CFG_MODE_MIIP 0x0
337 +#define MII_CFG_MODE_MIIM 0x1
338 +#define MII_CFG_MODE_RMIIP 0x2
339 +#define MII_CFG_MODE_RMIIM 0x3
340 +#define MII_CFG_MODE_RGMII 0x4
341 +#define MII_CFG_MODE_MASK 0xf
342 +
343 +#define MII_CFG_RATE_M2P5 0x00
344 +#define MII_CFG_RATE_M25 0x10
345 +#define MII_CFG_RATE_M125 0x20
346 +#define MII_CFG_RATE_M50 0x30
347 +#define MII_CFG_RATE_AUTO 0x40
348 +#define MII_CFG_RATE_MASK 0x70
349 +
350 +/* cpu port mac */
351 +#define PMAC_HD_CTL 0x0000
352 +#define PMAC_RX_IPG 0x0024
353 +#define PMAC_EWAN 0x002c
354 +
355 +#define PMAC_IPG_MASK 0xf
356 +#define PMAC_HD_CTL_AS 0x0008
357 +#define PMAC_HD_CTL_AC 0x0004
358 +#define PMAC_HD_CTL_RXSH 0x0040
359 +#define PMAC_HD_CTL_AST 0x0080
360 +#define PMAC_HD_CTL_RST 0x0100
361 +
362 +/* PCE */
363 +#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4))
364 +#define PCE_TBL_MASK 0x1120
365 +#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4))
366 +#define PCE_TBL_ADDR 0x1138
367 +#define PCE_TBL_CTRL 0x113c
368 +#define PCE_PMAP1 0x114c
369 +#define PCE_PMAP2 0x1150
370 +#define PCE_PMAP3 0x1154
371 +#define PCE_GCTRL_REG(x) (0x1158 + (x * 4))
372 +#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4))
373 +
374 +#define PCE_TBL_BUSY BIT(15)
375 +#define PCE_TBL_CFG_ADDR_MASK 0x1f
376 +#define PCE_TBL_CFG_ADWR 0x20
377 +#define PCE_TBL_CFG_ADWR_MASK 0x60
378 +#define PCE_INGRESS BIT(11)
379 +
380 +/* MAC */
381 +#define MAC_FLEN_REG (0x2314)
382 +#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4))
383 +
384 +/* buffer management */
385 +#define BM_PCFG(p) (0x200 + (p * 8))
386 +
387 +/* special tag in TX path header */
388 +#define SPID_SHIFT 24
389 +#define DPID_SHIFT 16
390 +#define DPID_ENABLE 1
391 +#define SPID_CPU_PORT 2
392 +#define PORT_MAP_SEL BIT(15)
393 +#define PORT_MAP_EN BIT(14)
394 +#define PORT_MAP_SHIFT 1
395 +#define PORT_MAP_MASK 0x3f
396 +
397 +#define SPPID_MASK 0x7
398 +#define SPPID_SHIFT 4
399 +
400 +/* MII regs not yet in linux */
401 +#define MDIO_DEVAD_NONE (-1)
402 +#define ADVERTIZE_MPD (1 << 10)
403 +
404 +struct xrx200_port {
405 + u8 num;
406 + u8 phy_addr;
407 + u16 flags;
408 + phy_interface_t phy_if;
409 +
410 + int link;
411 +
412 + struct phy_device *phydev;
413 + struct device_node *phy_node;
414 +};
415 +
416 +struct xrx200_chan {
417 + int idx;
418 + int refcount;
419 + int tx_free;
420 +
421 + struct net_device dummy_dev;
422 + struct net_device *devs[XRX200_MAX_DEV];
423 +
424 + struct napi_struct napi;
425 + struct ltq_dma_channel dma;
426 + struct sk_buff *skb[LTQ_DESC_NUM];
427 +};
428 +
429 +struct xrx200_hw {
430 + struct clk *clk;
431 + struct mii_bus *mii_bus;
432 +
433 + struct xrx200_chan chan[XRX200_MAX_DMA];
434 +
435 + struct net_device *devs[XRX200_MAX_DEV];
436 + int num_devs;
437 +
438 + int port_map[XRX200_MAX_PORT];
439 + unsigned short wan_map;
440 +
441 + spinlock_t lock;
442 +};
443 +
444 +struct xrx200_priv {
445 + struct net_device_stats stats;
446 + int id;
447 +
448 + struct xrx200_port port[XRX200_MAX_PORT];
449 + int num_port;
450 + int wan;
451 + unsigned short port_map;
452 + const void *mac;
453 +
454 + struct xrx200_hw *hw;
455 +};
456 +
457 +static __iomem void *xrx200_switch_membase;
458 +static __iomem void *xrx200_mii_membase;
459 +static __iomem void *xrx200_mdio_membase;
460 +static __iomem void *xrx200_pmac_membase;
461 +
462 +#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x))
463 +#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y))
464 +#define ltq_switch_w32_mask(x, y, z) \
465 + ltq_w32_mask(x, y, xrx200_switch_membase + (z))
466 +
467 +#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x))
468 +#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y))
469 +#define ltq_mdio_w32_mask(x, y, z) \
470 + ltq_w32_mask(x, y, xrx200_mdio_membase + (z))
471 +
472 +#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x))
473 +#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y))
474 +#define ltq_mii_w32_mask(x, y, z) \
475 + ltq_w32_mask(x, y, xrx200_mii_membase + (z))
476 +
477 +#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x))
478 +#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y))
479 +#define ltq_pmac_w32_mask(x, y, z) \
480 + ltq_w32_mask(x, y, xrx200_pmac_membase + (z))
481 +
482 +static int xrx200_open(struct net_device *dev)
483 +{
484 + struct xrx200_priv *priv = netdev_priv(dev);
485 + unsigned long flags;
486 + int i;
487 +
488 + for (i = 0; i < XRX200_MAX_DMA; i++) {
489 + if (!priv->hw->chan[i].dma.irq)
490 + continue;
491 + spin_lock_irqsave(&priv->hw->lock, flags);
492 + if (!priv->hw->chan[i].refcount) {
493 + napi_enable(&priv->hw->chan[i].napi);
494 + ltq_dma_open(&priv->hw->chan[i].dma);
495 + }
496 + priv->hw->chan[i].refcount++;
497 + spin_unlock_irqrestore(&priv->hw->lock, flags);
498 + }
499 + for (i = 0; i < priv->num_port; i++)
500 + if (priv->port[i].phydev)
501 + phy_start(priv->port[i].phydev);
502 + netif_start_queue(dev);
503 +
504 + return 0;
505 +}
506 +
507 +static int xrx200_close(struct net_device *dev)
508 +{
509 + struct xrx200_priv *priv = netdev_priv(dev);
510 + unsigned long flags;
511 + int i;
512 +
513 + netif_stop_queue(dev);
514 +
515 + for (i = 0; i < priv->num_port; i++)
516 + if (priv->port[i].phydev)
517 + phy_stop(priv->port[i].phydev);
518 +
519 + for (i = 0; i < XRX200_MAX_DMA; i++) {
520 + if (!priv->hw->chan[i].dma.irq)
521 + continue;
522 + spin_lock_irqsave(&priv->hw->lock, flags);
523 + priv->hw->chan[i].refcount--;
524 + if (!priv->hw->chan[i].refcount) {
525 + napi_disable(&priv->hw->chan[i].napi);
526 + ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma);
527 + }
528 + spin_unlock_irqrestore(&priv->hw->lock, flags);
529 + }
530 +
531 + return 0;
532 +}
533 +
534 +static int xrx200_alloc_skb(struct xrx200_chan *ch)
535 +{
536 +#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD)
537 + ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD);
538 + if (!ch->skb[ch->dma.desc])
539 + return -ENOMEM;
540 +
541 + skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD);
542 + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
543 + ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
544 + DMA_FROM_DEVICE);
545 + ch->dma.desc_base[ch->dma.desc].addr =
546 + CPHYSADDR(ch->skb[ch->dma.desc]->data);
547 + ch->dma.desc_base[ch->dma.desc].ctl =
548 + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
549 + XRX200_DMA_DATA_LEN;
550 + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
551 +
552 + return 0;
553 +}
554 +
555 +static void xrx200_hw_receive(struct xrx200_chan *ch, int id)
556 +{
557 + struct net_device *dev = ch->devs[id];
558 + struct xrx200_priv *priv = netdev_priv(dev);
559 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
560 + struct sk_buff *skb = ch->skb[ch->dma.desc];
561 + int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - XRX200_DMA_CRC_LEN;
562 + unsigned long flags;
563 +
564 + spin_lock_irqsave(&priv->hw->lock, flags);
565 + if (xrx200_alloc_skb(ch)) {
566 + netdev_err(dev,
567 + "failed to allocate new rx buffer, stopping DMA\n");
568 + ltq_dma_close(&ch->dma);
569 + }
570 +
571 + ch->dma.desc++;
572 + ch->dma.desc %= LTQ_DESC_NUM;
573 + spin_unlock_irqrestore(&priv->hw->lock, flags);
574 +
575 + skb_put(skb, len);
576 +#ifdef SW_ROUTING
577 + skb_pull(skb, 8);
578 +#endif
579 + skb->dev = dev;
580 + skb->protocol = eth_type_trans(skb, dev);
581 + netif_receive_skb(skb);
582 + priv->stats.rx_packets++;
583 + priv->stats.rx_bytes+=len;
584 +}
585 +
586 +static int xrx200_poll_rx(struct napi_struct *napi, int budget)
587 +{
588 + struct xrx200_chan *ch = container_of(napi,
589 + struct xrx200_chan, napi);
590 + struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
591 + int rx = 0;
592 + int complete = 0;
593 + unsigned long flags;
594 +
595 + while ((rx < budget) && !complete) {
596 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
597 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
598 +#ifdef SW_ROUTING
599 + struct sk_buff *skb = ch->skb[ch->dma.desc];
600 + u32 *special_tag = (u32*)skb->data;
601 + int port = (special_tag[1] >> SPPID_SHIFT) & SPPID_MASK;
602 + xrx200_hw_receive(ch, priv->hw->port_map[port]);
603 +#else
604 + xrx200_hw_receive(ch, 0);
605 +#endif
606 + rx++;
607 + } else {
608 + complete = 1;
609 + }
610 + }
611 + if (complete || !rx) {
612 + napi_complete(&ch->napi);
613 + spin_lock_irqsave(&priv->hw->lock, flags);
614 + ltq_dma_ack_irq(&ch->dma);
615 + spin_unlock_irqrestore(&priv->hw->lock, flags);
616 + }
617 + return rx;
618 +}
619 +
620 +static int xrx200_poll_tx(struct napi_struct *napi, int budget)
621 +{
622 + struct xrx200_chan *ch =
623 + container_of(napi, struct xrx200_chan, napi);
624 + struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
625 + unsigned long flags;
626 + int i;
627 +
628 + spin_lock_irqsave(&priv->hw->lock, flags);
629 + while ((ch->dma.desc_base[ch->tx_free].ctl &
630 + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
631 + dev_kfree_skb_any(ch->skb[ch->tx_free]);
632 + ch->skb[ch->tx_free] = NULL;
633 + memset(&ch->dma.desc_base[ch->tx_free], 0,
634 + sizeof(struct ltq_dma_desc));
635 + ch->tx_free++;
636 + ch->tx_free %= LTQ_DESC_NUM;
637 + }
638 + spin_unlock_irqrestore(&priv->hw->lock, flags);
639 +
640 + for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) {
641 + struct netdev_queue *txq =
642 + netdev_get_tx_queue(ch->devs[i], 0);
643 + if (netif_tx_queue_stopped(txq))
644 + netif_tx_start_queue(txq);
645 + }
646 + napi_complete(&ch->napi);
647 + spin_lock_irqsave(&priv->hw->lock, flags);
648 + ltq_dma_ack_irq(&ch->dma);
649 + spin_unlock_irqrestore(&priv->hw->lock, flags);
650 +
651 + return 1;
652 +}
653 +
654 +static struct net_device_stats *xrx200_get_stats (struct net_device *dev)
655 +{
656 + struct xrx200_priv *priv = netdev_priv(dev);
657 +
658 + return &priv->stats;
659 +}
660 +
661 +static void xrx200_tx_timeout(struct net_device *dev)
662 +{
663 + struct xrx200_priv *priv = netdev_priv(dev);
664 +
665 + printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name);
666 +
667 + priv->stats.tx_errors++;
668 + netif_wake_queue(dev);
669 +}
670 +
671 +static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev)
672 +{
673 + int queue = skb_get_queue_mapping(skb);
674 + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
675 + struct xrx200_priv *priv = netdev_priv(dev);
676 + struct xrx200_chan *ch = &priv->hw->chan[XRX200_DMA_TX];
677 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
678 + unsigned long flags;
679 + u32 byte_offset;
680 + int len;
681 +#ifdef SW_ROUTING
682 + #ifdef SW_PORTMAP
683 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | PORT_MAP_SEL | PORT_MAP_EN | DPID_ENABLE;
684 + #else
685 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE;
686 + #endif
687 +#endif
688 +
689 + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
690 +
691 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
692 + netdev_err(dev, "tx ring full\n");
693 + netif_tx_stop_queue(txq);
694 + return NETDEV_TX_BUSY;
695 + }
696 +#ifdef SW_ROUTING
697 + #ifdef SW_PORTMAP
698 + special_tag |= priv->port_map << PORT_MAP_SHIFT;
699 + #else
700 + if(priv->id)
701 + special_tag |= (1 << DPID_SHIFT);
702 + #endif
703 + if(skb_headroom(skb) < 4) {
704 + struct sk_buff *tmp = skb_realloc_headroom(skb, 4);
705 + dev_kfree_skb_any(skb);
706 + skb = tmp;
707 + }
708 + skb_push(skb, 4);
709 + memcpy(skb->data, &special_tag, sizeof(u32));
710 + len += 4;
711 +#endif
712 +
713 + /* dma needs to start on a 16 byte aligned address */
714 + byte_offset = CPHYSADDR(skb->data) % 16;
715 + ch->skb[ch->dma.desc] = skb;
716 +
717 + dev->trans_start = jiffies;
718 +
719 + spin_lock_irqsave(&priv->hw->lock, flags);
720 + desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
721 + DMA_TO_DEVICE)) - byte_offset;
722 + wmb();
723 + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
724 + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
725 + ch->dma.desc++;
726 + ch->dma.desc %= LTQ_DESC_NUM;
727 + spin_unlock_irqrestore(&priv->hw->lock, flags);
728 +
729 + if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
730 + netif_tx_stop_queue(txq);
731 +
732 + priv->stats.tx_packets++;
733 + priv->stats.tx_bytes+=len;
734 +
735 + return NETDEV_TX_OK;
736 +}
737 +
738 +static irqreturn_t xrx200_dma_irq(int irq, void *priv)
739 +{
740 + struct xrx200_hw *hw = priv;
741 + int ch = irq - XRX200_DMA_IRQ;
742 +
743 + napi_schedule(&hw->chan[ch].napi);
744 +
745 + return IRQ_HANDLED;
746 +}
747 +
748 +static int xrx200_dma_init(struct xrx200_hw *hw)
749 +{
750 + int i, err = 0;
751 +
752 + ltq_dma_init_port(DMA_PORT_ETOP);
753 +
754 + for (i = 0; i < 8 && !err; i++) {
755 + int irq = XRX200_DMA_IRQ + i;
756 + struct xrx200_chan *ch = &hw->chan[i];
757 +
758 + ch->idx = ch->dma.nr = i;
759 +
760 + if (i == XRX200_DMA_TX) {
761 + ltq_dma_alloc_tx(&ch->dma);
762 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw);
763 + } else if (i == XRX200_DMA_RX) {
764 + ltq_dma_alloc_rx(&ch->dma);
765 + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
766 + ch->dma.desc++)
767 + if (xrx200_alloc_skb(ch))
768 + err = -ENOMEM;
769 + ch->dma.desc = 0;
770 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw);
771 + } else
772 + continue;
773 +
774 + if (!err)
775 + ch->dma.irq = irq;
776 + }
777 +
778 + return err;
779 +}
780 +
781 +#ifdef SW_POLLING
782 +static void xrx200_gmac_update(struct xrx200_port *port)
783 +{
784 + u16 phyaddr = port->phydev->addr & MDIO_PHY_ADDR_MASK;
785 + u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK;
786 + u16 miirate = 0;
787 +
788 + switch (port->phydev->speed) {
789 + case SPEED_1000:
790 + phyaddr |= MDIO_PHY_SPEED_G1;
791 + miirate = MII_CFG_RATE_M125;
792 + break;
793 +
794 + case SPEED_100:
795 + phyaddr |= MDIO_PHY_SPEED_M100;
796 + switch (miimode) {
797 + case MII_CFG_MODE_RMIIM:
798 + case MII_CFG_MODE_RMIIP:
799 + miirate = MII_CFG_RATE_M50;
800 + break;
801 + default:
802 + miirate = MII_CFG_RATE_M25;
803 + break;
804 + }
805 + break;
806 +
807 + default:
808 + phyaddr |= MDIO_PHY_SPEED_M10;
809 + miirate = MII_CFG_RATE_M2P5;
810 + break;
811 + }
812 +
813 + if (port->phydev->link)
814 + phyaddr |= MDIO_PHY_LINK_UP;
815 + else
816 + phyaddr |= MDIO_PHY_LINK_DOWN;
817 +
818 + if (port->phydev->duplex == DUPLEX_FULL)
819 + phyaddr |= MDIO_PHY_FDUP_EN;
820 + else
821 + phyaddr |= MDIO_PHY_FDUP_DIS;
822 +
823 + ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num));
824 + ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num));
825 + udelay(1);
826 +}
827 +#else
828 +static void xrx200_gmac_update(struct xrx200_port *port)
829 +{
830 +
831 +}
832 +#endif
833 +
834 +static void xrx200_mdio_link(struct net_device *dev)
835 +{
836 + struct xrx200_priv *priv = netdev_priv(dev);
837 + int i;
838 +
839 + for (i = 0; i < priv->num_port; i++) {
840 + if (!priv->port[i].phydev)
841 + continue;
842 +
843 + if (priv->port[i].link != priv->port[i].phydev->link) {
844 + xrx200_gmac_update(&priv->port[i]);
845 + priv->port[i].link = priv->port[i].phydev->link;
846 + netdev_info(dev, "port %d %s link\n",
847 + priv->port[i].num,
848 + (priv->port[i].link)?("got"):("lost"));
849 + }
850 + }
851 +}
852 +
853 +static inline int xrx200_mdio_poll(struct mii_bus *bus)
854 +{
855 + unsigned cnt = 10000;
856 +
857 + while (likely(cnt--)) {
858 + unsigned ctrl = ltq_mdio_r32(MDIO_CTRL);
859 + if ((ctrl & MDIO_BUSY) == 0)
860 + return 0;
861 + }
862 +
863 + return 1;
864 +}
865 +
866 +static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
867 +{
868 + if (xrx200_mdio_poll(bus))
869 + return 1;
870 +
871 + ltq_mdio_w32(val, MDIO_WRITE);
872 + ltq_mdio_w32(MDIO_BUSY | MDIO_WR |
873 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
874 + (reg & MDIO_MASK),
875 + MDIO_CTRL);
876 +
877 + return 0;
878 +}
879 +
880 +static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg)
881 +{
882 + if (xrx200_mdio_poll(bus))
883 + return -1;
884 +
885 + ltq_mdio_w32(MDIO_BUSY | MDIO_RD |
886 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
887 + (reg & MDIO_MASK),
888 + MDIO_CTRL);
889 +
890 + if (xrx200_mdio_poll(bus))
891 + return -1;
892 +
893 + return ltq_mdio_r32(MDIO_READ);
894 +}
895 +
896 +static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port)
897 +{
898 + struct xrx200_priv *priv = netdev_priv(dev);
899 + struct phy_device *phydev = NULL;
900 + unsigned val;
901 +
902 + phydev = priv->hw->mii_bus->phy_map[port->phy_addr];
903 +
904 + if (!phydev) {
905 + netdev_err(dev, "no PHY found\n");
906 + return -ENODEV;
907 + }
908 +
909 + phydev = phy_connect(dev, dev_name(&phydev->dev), &xrx200_mdio_link,
910 + 0, port->phy_if);
911 +
912 + if (IS_ERR(phydev)) {
913 + netdev_err(dev, "Could not attach to PHY\n");
914 + return PTR_ERR(phydev);
915 + }
916 +
917 + phydev->supported &= (SUPPORTED_10baseT_Half
918 + | SUPPORTED_10baseT_Full
919 + | SUPPORTED_100baseT_Half
920 + | SUPPORTED_100baseT_Full
921 + | SUPPORTED_1000baseT_Half
922 + | SUPPORTED_1000baseT_Full
923 + | SUPPORTED_Autoneg
924 + | SUPPORTED_MII
925 + | SUPPORTED_TP);
926 + phydev->advertising = phydev->supported;
927 + port->phydev = phydev;
928 +
929 + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
930 + dev->name, phydev->drv->name,
931 + dev_name(&phydev->dev), phydev->irq);
932 +
933 +#ifdef SW_POLLING
934 + phy_read_status(phydev);
935 +
936 + val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
937 + val |= ADVERTIZE_MPD;
938 + xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
939 + xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040);
940 +
941 + phy_start_aneg(phydev);
942 +#endif
943 + return 0;
944 +}
945 +
946 +static void xrx200_port_config(struct xrx200_priv *priv,
947 + const struct xrx200_port *port)
948 +{
949 + u16 miimode = 0;
950 +
951 + switch (port->num) {
952 + case 0: /* xMII0 */
953 + case 1: /* xMII1 */
954 + switch (port->phy_if) {
955 + case PHY_INTERFACE_MODE_MII:
956 + if (port->flags & XRX200_PORT_TYPE_PHY)
957 + /* MII MAC mode, connected to external PHY */
958 + miimode = MII_CFG_MODE_MIIM;
959 + else
960 + /* MII PHY mode, connected to external MAC */
961 + miimode = MII_CFG_MODE_MIIP;
962 + break;
963 + case PHY_INTERFACE_MODE_RMII:
964 + if (port->flags & XRX200_PORT_TYPE_PHY)
965 + /* RMII MAC mode, connected to external PHY */
966 + miimode = MII_CFG_MODE_RMIIM;
967 + else
968 + /* RMII PHY mode, connected to external MAC */
969 + miimode = MII_CFG_MODE_RMIIP;
970 + break;
971 + case PHY_INTERFACE_MODE_RGMII:
972 + /* RGMII MAC mode, connected to external PHY */
973 + miimode = MII_CFG_MODE_RGMII;
974 + break;
975 + default:
976 + break;
977 + }
978 + break;
979 + case 2: /* internal GPHY0 */
980 + case 3: /* internal GPHY0 */
981 + case 4: /* internal GPHY1 */
982 + switch (port->phy_if) {
983 + case PHY_INTERFACE_MODE_MII:
984 + case PHY_INTERFACE_MODE_GMII:
985 + /* MII MAC mode, connected to internal GPHY */
986 + miimode = MII_CFG_MODE_MIIM;
987 + break;
988 + default:
989 + break;
990 + }
991 + break;
992 + case 5: /* internal GPHY1 or xMII2 */
993 + switch (port->phy_if) {
994 + case PHY_INTERFACE_MODE_MII:
995 + /* MII MAC mode, connected to internal GPHY */
996 + miimode = MII_CFG_MODE_MIIM;
997 + break;
998 + case PHY_INTERFACE_MODE_RGMII:
999 + /* RGMII MAC mode, connected to external PHY */
1000 + miimode = MII_CFG_MODE_RGMII;
1001 + break;
1002 + default:
1003 + break;
1004 + }
1005 + break;
1006 + default:
1007 + break;
1008 + }
1009 +
1010 + ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN,
1011 + MII_CFG(port->num));
1012 +}
1013 +
1014 +static int xrx200_init(struct net_device *dev)
1015 +{
1016 + struct xrx200_priv *priv = netdev_priv(dev);
1017 + struct sockaddr mac;
1018 + int err, i;
1019 +
1020 +#ifndef SW_POLLING
1021 + unsigned int reg = 0;
1022 +
1023 + /* enable auto polling */
1024 + for (i = 0; i < priv->num_port; i++)
1025 + reg |= BIT(priv->port[i].num);
1026 + ltq_mdio_w32(reg, MDIO_CLK_CFG0);
1027 + ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1);
1028 +#endif
1029 +
1030 + /* setup each port */
1031 + for (i = 0; i < priv->num_port; i++)
1032 + xrx200_port_config(priv, &priv->port[i]);
1033 +
1034 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
1035 + if (!is_valid_ether_addr(mac.sa_data)) {
1036 + pr_warn("net-xrx200: invalid MAC, using random\n");
1037 + eth_random_addr(mac.sa_data);
1038 + dev->addr_assign_type |= NET_ADDR_RANDOM;
1039 + }
1040 +
1041 + err = eth_mac_addr(dev, &mac);
1042 + if (err)
1043 + goto err_netdev;
1044 +
1045 + for (i = 0; i < priv->num_port; i++)
1046 + if (xrx200_mdio_probe(dev, &priv->port[i]))
1047 + pr_warn("xrx200-mdio: probing phy of port %d failed\n",
1048 + priv->port[i].num);
1049 +
1050 + return 0;
1051 +
1052 +err_netdev:
1053 + unregister_netdev(dev);
1054 + free_netdev(dev);
1055 + return err;
1056 +}
1057 +
1058 +static void xrx200_pci_microcode(void)
1059 +{
1060 + int i;
1061 +
1062 + ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK,
1063 + PCE_TBL_CFG_ADWR, PCE_TBL_CTRL);
1064 + ltq_switch_w32(0, PCE_TBL_MASK);
1065 +
1066 + for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) {
1067 + ltq_switch_w32(i, PCE_TBL_ADDR);
1068 + ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0));
1069 + ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1));
1070 + ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2));
1071 + ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3));
1072 +
1073 + // start the table access:
1074 + ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL);
1075 + while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY);
1076 + }
1077 +
1078 + /* tell the switch that the microcode is loaded */
1079 + ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0));
1080 +}
1081 +
1082 +static void xrx200_hw_init(struct xrx200_hw *hw)
1083 +{
1084 + int i;
1085 +
1086 + /* enable clock gate */
1087 + clk_enable(hw->clk);
1088 +
1089 + ltq_switch_w32(1, 0);
1090 + mdelay(100);
1091 + ltq_switch_w32(0, 0);
1092 + /*
1093 + * TODO: we should really disbale all phys/miis here and explicitly
1094 + * enable them in the device secific init function
1095 + */
1096 +
1097 + /* disable port fetch/store dma */
1098 + for (i = 0; i < 7; i++ ) {
1099 + ltq_switch_w32(0, FDMA_PCTRLx(i));
1100 + ltq_switch_w32(0, SDMA_PCTRLx(i));
1101 + }
1102 +
1103 + /* enable Switch */
1104 + ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB);
1105 +
1106 + /* load the pce microcode */
1107 + xrx200_pci_microcode();
1108 +
1109 + /* Default unknown Broadcat/Multicast/Unicast port maps */
1110 + ltq_switch_w32(0x7f, PCE_PMAP1);
1111 + ltq_switch_w32(0x7f, PCE_PMAP2);
1112 + ltq_switch_w32(0x7f, PCE_PMAP3);
1113 +
1114 + /* RMON Counter Enable for all physical ports */
1115 + for (i = 0; i < 7; i++)
1116 + ltq_switch_w32(0x1, BM_PCFG(i));
1117 +
1118 + /* disable auto polling */
1119 + ltq_mdio_w32(0x0, MDIO_CLK_CFG0);
1120 +
1121 + /* enable port statistic counters */
1122 + for (i = 0; i < 7; i++)
1123 + ltq_switch_w32(0x1, BM_PCFGx(i));
1124 +
1125 + /* set IPG to 12 */
1126 + ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG);
1127 +
1128 +#ifdef SW_ROUTING
1129 + /* enable status header, enable CRC */
1130 + ltq_pmac_w32_mask(0,
1131 + PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC,
1132 + PMAC_HD_CTL);
1133 +#else
1134 + /* disable status header, enable CRC */
1135 + ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS,
1136 + PMAC_HD_CTL_AC,
1137 + PMAC_HD_CTL);
1138 +#endif
1139 +
1140 + /* enable port fetch/store dma */
1141 + for (i = 0; i < 7; i++ ) {
1142 + ltq_switch_w32_mask(0, 0x01, FDMA_PCTRLx(i));
1143 + ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i));
1144 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0));
1145 + }
1146 +
1147 + /* enable special tag insertion on cpu port */
1148 + ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6));
1149 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0));
1150 + ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2));
1151 + ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG);
1152 +}
1153 +
1154 +static void xrx200_hw_cleanup(struct xrx200_hw *hw)
1155 +{
1156 + int i;
1157 +
1158 + /* disable the switch */
1159 + ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB);
1160 +
1161 + /* free the channels and IRQs */
1162 + for (i = 0; i < 2; i++) {
1163 + ltq_dma_free(&hw->chan[i].dma);
1164 + if (hw->chan[i].dma.irq)
1165 + free_irq(hw->chan[i].dma.irq, hw);
1166 + }
1167 +
1168 + /* free the allocated RX ring */
1169 + for (i = 0; i < LTQ_DESC_NUM; i++)
1170 + dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]);
1171 +
1172 + /* clear the mdio bus */
1173 + mdiobus_unregister(hw->mii_bus);
1174 + mdiobus_free(hw->mii_bus);
1175 +
1176 + /* release the clock */
1177 + clk_disable(hw->clk);
1178 + clk_put(hw->clk);
1179 +}
1180 +
1181 +static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np)
1182 +{
1183 + hw->mii_bus = mdiobus_alloc();
1184 + if (!hw->mii_bus)
1185 + return -ENOMEM;
1186 +
1187 + hw->mii_bus->read = xrx200_mdio_rd;
1188 + hw->mii_bus->write = xrx200_mdio_wr;
1189 + hw->mii_bus->name = "lantiq,xrx200-mdio";
1190 + snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
1191 +
1192 + if (of_mdiobus_register(hw->mii_bus, np)) {
1193 + mdiobus_free(hw->mii_bus);
1194 + return -ENXIO;
1195 + }
1196 +
1197 + return 0;
1198 +}
1199 +
1200 +static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port)
1201 +{
1202 + const __be32 *addr, *id = of_get_property(port, "reg", NULL);
1203 + struct xrx200_port *p = &priv->port[priv->num_port];
1204 +
1205 + if (!id)
1206 + return;
1207 +
1208 + memset(p, 0, sizeof(struct xrx200_port));
1209 + p->phy_node = of_parse_phandle(port, "phy-handle", 0);
1210 + addr = of_get_property(p->phy_node, "reg", NULL);
1211 + if (!addr)
1212 + return;
1213 +
1214 + p->num = *id;
1215 + p->phy_addr = *addr;
1216 + p->phy_if = of_get_phy_mode(port);
1217 + if (p->phy_addr > 0x10)
1218 + p->flags = XRX200_PORT_TYPE_MAC;
1219 + else
1220 + p->flags = XRX200_PORT_TYPE_PHY;
1221 + priv->num_port++;
1222 +
1223 + /* is this port a wan port ? */
1224 + if (priv->wan)
1225 + priv->hw->wan_map |= BIT(p->num);
1226 +
1227 + priv->port_map |= BIT(p->num);
1228 +
1229 + /* store the port id in the hw struct so we can map ports -> devices */
1230 + priv->hw->port_map[p->num] = priv->hw->num_devs;
1231 +}
1232 +
1233 +static const struct net_device_ops xrx200_netdev_ops = {
1234 + .ndo_init = xrx200_init,
1235 + .ndo_open = xrx200_open,
1236 + .ndo_stop = xrx200_close,
1237 + .ndo_start_xmit = xrx200_start_xmit,
1238 + .ndo_set_mac_address = eth_mac_addr,
1239 + .ndo_validate_addr = eth_validate_addr,
1240 + .ndo_change_mtu = eth_change_mtu,
1241 + .ndo_get_stats = xrx200_get_stats,
1242 + .ndo_tx_timeout = xrx200_tx_timeout,
1243 +};
1244 +
1245 +static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface)
1246 +{
1247 + struct xrx200_priv *priv;
1248 + struct device_node *port;
1249 + const __be32 *wan;
1250 +
1251 + /* alloc the network device */
1252 + hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv));
1253 + if (!hw->devs[hw->num_devs])
1254 + return;
1255 +
1256 + /* setup the network device */
1257 + strcpy(hw->devs[hw->num_devs]->name, "eth%d");
1258 + hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops;
1259 + hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT;
1260 + hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM;
1261 +
1262 + /* setup our private data */
1263 + priv = netdev_priv(hw->devs[hw->num_devs]);
1264 + priv->hw = hw;
1265 + priv->mac = of_get_mac_address(iface);
1266 + priv->id = hw->num_devs;
1267 +
1268 + /* is this the wan interface ? */
1269 + wan = of_get_property(iface, "lantiq,wan", NULL);
1270 + if (wan && (*wan == 1))
1271 + priv->wan = 1;
1272 +
1273 + /* load the ports that are part of the interface */
1274 + for_each_child_of_node(iface, port)
1275 + if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port"))
1276 + xrx200_of_port(priv, port);
1277 +
1278 + /* register the actual device */
1279 + if (!register_netdev(hw->devs[hw->num_devs]))
1280 + hw->num_devs++;
1281 +}
1282 +
1283 +static struct xrx200_hw xrx200_hw;
1284 +
1285 +static int __devinit xrx200_probe(struct platform_device *pdev)
1286 +{
1287 + struct resource *res[4];
1288 + struct device_node *mdio_np, *iface_np;
1289 + int i;
1290 +
1291 + /* load the memory ranges */
1292 + for (i = 0; i < 4; i++) {
1293 + res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
1294 + if (!res[i]) {
1295 + dev_err(&pdev->dev, "failed to get resources\n");
1296 + return -ENOENT;
1297 + }
1298 + }
1299 + xrx200_switch_membase = devm_request_and_ioremap(&pdev->dev, res[0]);
1300 + xrx200_mdio_membase = devm_request_and_ioremap(&pdev->dev, res[1]);
1301 + xrx200_mii_membase = devm_request_and_ioremap(&pdev->dev, res[2]);
1302 + xrx200_pmac_membase = devm_request_and_ioremap(&pdev->dev, res[3]);
1303 + if (!xrx200_switch_membase || !xrx200_mdio_membase ||
1304 + !xrx200_mii_membase || !xrx200_pmac_membase) {
1305 + dev_err(&pdev->dev, "failed to request and remap io ranges \n");
1306 + return -ENOMEM;
1307 + }
1308 +
1309 + /* get the clock */
1310 + xrx200_hw.clk = clk_get(&pdev->dev, NULL);
1311 + if (IS_ERR(xrx200_hw.clk)) {
1312 + dev_err(&pdev->dev, "failed to get clock\n");
1313 + return PTR_ERR(xrx200_hw.clk);
1314 + }
1315 +
1316 + /* bring up the dma engine and IP core */
1317 + spin_lock_init(&xrx200_hw.lock);
1318 + xrx200_dma_init(&xrx200_hw);
1319 + xrx200_hw_init(&xrx200_hw);
1320 +
1321 + /* bring up the mdio bus */
1322 + mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL,
1323 + "lantiq,xrx200-mdio");
1324 + if (mdio_np)
1325 + if (xrx200_of_mdio(&xrx200_hw, mdio_np))
1326 + dev_err(&pdev->dev, "mdio probe failed\n");
1327 +
1328 + /* load the interfaces */
1329 + for_each_child_of_node(pdev->dev.of_node, iface_np)
1330 + if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) {
1331 + if (xrx200_hw.num_devs < XRX200_MAX_DEV)
1332 + xrx200_of_iface(&xrx200_hw, iface_np);
1333 + else
1334 + dev_err(&pdev->dev,
1335 + "only %d interfaces allowed\n",
1336 + XRX200_MAX_DEV);
1337 + }
1338 +
1339 + if (!xrx200_hw.num_devs) {
1340 + xrx200_hw_cleanup(&xrx200_hw);
1341 + dev_err(&pdev->dev, "failed to load interfaces\n");
1342 + return -ENOENT;
1343 + }
1344 +
1345 + /* set wan port mask */
1346 + ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN);
1347 +
1348 + for (i = 0; i < xrx200_hw.num_devs; i++) {
1349 + xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i];
1350 + xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i];
1351 + }
1352 +
1353 + /* setup NAPI */
1354 + init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev);
1355 + init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_TX].dummy_dev);
1356 + netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev,
1357 + &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32);
1358 + netif_napi_add(&xrx200_hw.chan[XRX200_DMA_TX].dummy_dev,
1359 + &xrx200_hw.chan[XRX200_DMA_TX].napi, xrx200_poll_tx, 8);
1360 +
1361 + platform_set_drvdata(pdev, &xrx200_hw);
1362 +
1363 + return 0;
1364 +}
1365 +
1366 +static int __devexit xrx200_remove(struct platform_device *pdev)
1367 +{
1368 + struct net_device *dev = platform_get_drvdata(pdev);
1369 + struct xrx200_priv *priv;
1370 +
1371 + if (!dev)
1372 + return 0;
1373 +
1374 + priv = netdev_priv(dev);
1375 +
1376 + /* free stack related instances */
1377 + netif_stop_queue(dev);
1378 + netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi);
1379 + netif_napi_del(&xrx200_hw.chan[XRX200_DMA_TX].napi);
1380 +
1381 + /* shut down hardware */
1382 + xrx200_hw_cleanup(&xrx200_hw);
1383 +
1384 + /* remove the actual device */
1385 + unregister_netdev(dev);
1386 + free_netdev(dev);
1387 +
1388 + return 0;
1389 +}
1390 +
1391 +static const struct of_device_id xrx200_match[] = {
1392 + { .compatible = "lantiq,xrx200-net" },
1393 + {},
1394 +};
1395 +MODULE_DEVICE_TABLE(of, xrx200_match);
1396 +
1397 +static struct platform_driver xrx200_driver = {
1398 + .probe = xrx200_probe,
1399 + .remove = __devexit_p(xrx200_remove),
1400 + .driver = {
1401 + .name = "lantiq,xrx200-net",
1402 + .of_match_table = xrx200_match,
1403 + .owner = THIS_MODULE,
1404 + },
1405 +};
1406 +
1407 +module_platform_driver(xrx200_driver);
1408 +
1409 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1410 +MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
1411 +MODULE_LICENSE("GPL");
1412 --
1413 1.7.10.4
1414
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