[lantiq] bump to v3.8
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.8 / 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
1 From fbfdf78ba827a8f854ae3ed7b11ea6df4054ffb1 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Oct 2012 12:22:23 +0200
4 Subject: [PATCH 25/40] NET: MIPS: lantiq: adds xrx200-net
5
6 ---
7 drivers/net/ethernet/Kconfig | 8 +-
8 drivers/net/ethernet/Makefile | 1 +
9 drivers/net/ethernet/lantiq_pce.h | 163 +++++
10 drivers/net/ethernet/lantiq_xrx200.c | 1203 ++++++++++++++++++++++++++++++++++
11 4 files changed, 1374 insertions(+), 1 deletion(-)
12 create mode 100644 drivers/net/ethernet/lantiq_pce.h
13 create mode 100644 drivers/net/ethernet/lantiq_xrx200.c
14
15 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
16 index e4ff389..35cb7b0 100644
17 --- a/drivers/net/ethernet/Kconfig
18 +++ b/drivers/net/ethernet/Kconfig
19 @@ -83,7 +83,13 @@ config LANTIQ_ETOP
20 tristate "Lantiq SoC ETOP driver"
21 depends on SOC_TYPE_XWAY
22 ---help---
23 - Support for the MII0 inside the Lantiq SoC
24 + Support for the MII0 inside the Lantiq ADSL SoC
25 +
26 +config LANTIQ_XRX200
27 + tristate "Lantiq SoC XRX200 driver"
28 + depends on SOC_TYPE_XWAY
29 + ---help---
30 + Support for the MII0 inside the Lantiq VDSL SoC
31
32 source "drivers/net/ethernet/marvell/Kconfig"
33 source "drivers/net/ethernet/mellanox/Kconfig"
34 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
35 index d447307..4f95100 100644
36 --- a/drivers/net/ethernet/Makefile
37 +++ b/drivers/net/ethernet/Makefile
38 @@ -36,6 +36,7 @@ obj-$(CONFIG_IP1000) += icplus/
39 obj-$(CONFIG_JME) += jme.o
40 obj-$(CONFIG_KORINA) += korina.o
41 obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
42 +obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o
43 obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
44 obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
45 obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
46 diff --git a/drivers/net/ethernet/lantiq_pce.h b/drivers/net/ethernet/lantiq_pce.h
47 new file mode 100644
48 index 0000000..0c38efe
49 --- /dev/null
50 +++ b/drivers/net/ethernet/lantiq_pce.h
51 @@ -0,0 +1,163 @@
52 +/*
53 + * This program is free software; you can redistribute it and/or modify it
54 + * under the terms of the GNU General Public License version 2 as published
55 + * by the Free Software Foundation.
56 + *
57 + * This program is distributed in the hope that it will be useful,
58 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
59 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
60 + * GNU General Public License for more details.
61 + *
62 + * You should have received a copy of the GNU General Public License
63 + * along with this program; if not, write to the Free Software
64 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
65 + *
66 + * Copyright (C) 2010 Lantiq Deutschland GmbH
67 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
68 + *
69 + * PCE microcode extracted from UGW5.2 switch api
70 + */
71 +
72 +/* Switch API Micro Code V0.3 */
73 +enum {
74 + OUT_MAC0 = 0,
75 + OUT_MAC1,
76 + OUT_MAC2,
77 + OUT_MAC3,
78 + OUT_MAC4,
79 + OUT_MAC5,
80 + OUT_ETHTYP,
81 + OUT_VTAG0,
82 + OUT_VTAG1,
83 + OUT_ITAG0,
84 + OUT_ITAG1, /*10 */
85 + OUT_ITAG2,
86 + OUT_ITAG3,
87 + OUT_IP0,
88 + OUT_IP1,
89 + OUT_IP2,
90 + OUT_IP3,
91 + OUT_SIP0,
92 + OUT_SIP1,
93 + OUT_SIP2,
94 + OUT_SIP3, /*20*/
95 + OUT_SIP4,
96 + OUT_SIP5,
97 + OUT_SIP6,
98 + OUT_SIP7,
99 + OUT_DIP0,
100 + OUT_DIP1,
101 + OUT_DIP2,
102 + OUT_DIP3,
103 + OUT_DIP4,
104 + OUT_DIP5, /*30*/
105 + OUT_DIP6,
106 + OUT_DIP7,
107 + OUT_SESID,
108 + OUT_PROT,
109 + OUT_APP0,
110 + OUT_APP1,
111 + OUT_IGMP0,
112 + OUT_IGMP1,
113 + OUT_IPOFF, /*39*/
114 + OUT_NONE = 63
115 +};
116 +
117 +/* parser's microcode length type */
118 +#define INSTR 0
119 +#define IPV6 1
120 +#define LENACCU 2
121 +
122 +/* parser's microcode flag type */
123 +enum {
124 + FLAG_ITAG = 0,
125 + FLAG_VLAN,
126 + FLAG_SNAP,
127 + FLAG_PPPOE,
128 + FLAG_IPV6,
129 + FLAG_IPV6FL,
130 + FLAG_IPV4,
131 + FLAG_IGMP,
132 + FLAG_TU,
133 + FLAG_HOP,
134 + FLAG_NN1, /*10 */
135 + FLAG_NN2,
136 + FLAG_END,
137 + FLAG_NO, /*13*/
138 +};
139 +
140 +/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */
141 +#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \
142 + { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }}
143 +struct pce_microcode {
144 + unsigned short val[4];
145 +/* unsigned short val_2;
146 + unsigned short val_1;
147 + unsigned short val_0;*/
148 +} pce_microcode[] = {
149 + /* value mask ns fields L type flags ipv4_len */
150 + MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
151 + MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
152 + MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
153 + MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
154 + MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
155 + MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
156 + MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
157 + MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
158 + MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0),
159 + MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
160 + MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
161 + MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0),
162 + MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0),
163 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
164 + MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0),
165 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
166 + MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0),
167 + MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0),
168 + MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0),
169 + MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0),
170 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
171 + MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1),
172 + MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0),
173 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
174 + MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0),
175 + MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0),
176 + MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0),
177 + MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
178 + MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
179 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0),
180 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0),
181 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0),
182 + MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
183 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0),
184 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0),
185 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0),
186 + MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0),
187 + MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0),
188 + MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0),
189 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
190 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
191 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
192 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
193 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
194 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
195 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
196 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
197 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
198 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
199 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
200 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
201 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
202 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
203 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
204 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
205 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
206 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
207 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
208 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
209 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
210 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
211 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
212 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
213 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
214 +};
215 diff --git a/drivers/net/ethernet/lantiq_xrx200.c b/drivers/net/ethernet/lantiq_xrx200.c
216 new file mode 100644
217 index 0000000..f815165
218 --- /dev/null
219 +++ b/drivers/net/ethernet/lantiq_xrx200.c
220 @@ -0,0 +1,1203 @@
221 +/*
222 + * This program is free software; you can redistribute it and/or modify it
223 + * under the terms of the GNU General Public License version 2 as published
224 + * by the Free Software Foundation.
225 + *
226 + * This program is distributed in the hope that it will be useful,
227 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
228 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
229 + * GNU General Public License for more details.
230 + *
231 + * You should have received a copy of the GNU General Public License
232 + * along with this program; if not, write to the Free Software
233 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
234 + *
235 + * Copyright (C) 2010 Lantiq Deutschland
236 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
237 + */
238 +
239 +#include <linux/etherdevice.h>
240 +#include <linux/module.h>
241 +#include <linux/platform_device.h>
242 +#include <linux/interrupt.h>
243 +#include <linux/clk.h>
244 +#include <asm/delay.h>
245 +
246 +#include <linux/of_net.h>
247 +#include <linux/of_mdio.h>
248 +#include <linux/of_gpio.h>
249 +
250 +#include <xway_dma.h>
251 +#include <lantiq_soc.h>
252 +
253 +#include "lantiq_pce.h"
254 +
255 +#define SW_POLLING
256 +#define SW_ROUTING
257 +#define SW_PORTMAP
258 +
259 +#ifdef SW_ROUTING
260 + #ifdef SW_PORTMAP
261 +#define XRX200_MAX_DEV 7
262 + #else
263 +#define XRX200_MAX_DEV 2
264 + #endif
265 +#else
266 +#define XRX200_MAX_DEV 1
267 +#endif
268 +
269 +#define XRX200_MAX_PORT 7
270 +#define XRX200_MAX_DMA 8
271 +
272 +#define XRX200_HEADROOM 4
273 +
274 +#define XRX200_TX_TIMEOUT (10 * HZ)
275 +
276 +/* port type */
277 +#define XRX200_PORT_TYPE_PHY 1
278 +#define XRX200_PORT_TYPE_MAC 2
279 +
280 +/* DMA */
281 +#define XRX200_DMA_CRC_LEN 0x4
282 +#define XRX200_DMA_DATA_LEN 0x600
283 +#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0
284 +#define XRX200_DMA_RX 0
285 +#define XRX200_DMA_TX 1
286 +
287 +/* fetch / store dma */
288 +#define FDMA_PCTRL0 0x2A00
289 +#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18))
290 +#define SDMA_PCTRL0 0x2F00
291 +#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18))
292 +
293 +/* buffer management */
294 +#define BM_PCFG0 0x200
295 +#define BM_PCFGx(x) (BM_PCFG0 + (x * 8))
296 +
297 +/* MDIO */
298 +#define MDIO_GLOB 0x0000
299 +#define MDIO_CTRL 0x0020
300 +#define MDIO_READ 0x0024
301 +#define MDIO_WRITE 0x0028
302 +#define MDIO_PHY0 0x0054
303 +#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned)))
304 +#define MDIO_CLK_CFG0 0x002C
305 +#define MDIO_CLK_CFG1 0x0030
306 +
307 +#define MDIO_GLOB_ENABLE 0x8000
308 +#define MDIO_BUSY BIT(12)
309 +#define MDIO_RD BIT(11)
310 +#define MDIO_WR BIT(10)
311 +#define MDIO_MASK 0x1f
312 +#define MDIO_ADDRSHIFT 5
313 +#define MDIO1_25MHZ 9
314 +
315 +#define MDIO_PHY_LINK_DOWN 0x4000
316 +#define MDIO_PHY_LINK_UP 0x2000
317 +
318 +#define MDIO_PHY_SPEED_M10 0x0000
319 +#define MDIO_PHY_SPEED_M100 0x0800
320 +#define MDIO_PHY_SPEED_G1 0x1000
321 +
322 +#define MDIO_PHY_FDUP_EN 0x0600
323 +#define MDIO_PHY_FDUP_DIS 0x0200
324 +
325 +#define MDIO_PHY_LINK_MASK 0x6000
326 +#define MDIO_PHY_SPEED_MASK 0x1800
327 +#define MDIO_PHY_FDUP_MASK 0x0600
328 +#define MDIO_PHY_ADDR_MASK 0x001f
329 +#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \
330 + MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK
331 +
332 +/* MII */
333 +#define MII_CFG(p) (p * 8)
334 +
335 +#define MII_CFG_EN BIT(14)
336 +
337 +#define MII_CFG_MODE_MIIP 0x0
338 +#define MII_CFG_MODE_MIIM 0x1
339 +#define MII_CFG_MODE_RMIIP 0x2
340 +#define MII_CFG_MODE_RMIIM 0x3
341 +#define MII_CFG_MODE_RGMII 0x4
342 +#define MII_CFG_MODE_MASK 0xf
343 +
344 +#define MII_CFG_RATE_M2P5 0x00
345 +#define MII_CFG_RATE_M25 0x10
346 +#define MII_CFG_RATE_M125 0x20
347 +#define MII_CFG_RATE_M50 0x30
348 +#define MII_CFG_RATE_AUTO 0x40
349 +#define MII_CFG_RATE_MASK 0x70
350 +
351 +/* cpu port mac */
352 +#define PMAC_HD_CTL 0x0000
353 +#define PMAC_RX_IPG 0x0024
354 +#define PMAC_EWAN 0x002c
355 +
356 +#define PMAC_IPG_MASK 0xf
357 +#define PMAC_HD_CTL_AS 0x0008
358 +#define PMAC_HD_CTL_AC 0x0004
359 +#define PMAC_HD_CTL_RXSH 0x0040
360 +#define PMAC_HD_CTL_AST 0x0080
361 +#define PMAC_HD_CTL_RST 0x0100
362 +
363 +/* PCE */
364 +#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4))
365 +#define PCE_TBL_MASK 0x1120
366 +#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4))
367 +#define PCE_TBL_ADDR 0x1138
368 +#define PCE_TBL_CTRL 0x113c
369 +#define PCE_PMAP1 0x114c
370 +#define PCE_PMAP2 0x1150
371 +#define PCE_PMAP3 0x1154
372 +#define PCE_GCTRL_REG(x) (0x1158 + (x * 4))
373 +#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4))
374 +
375 +#define PCE_TBL_BUSY BIT(15)
376 +#define PCE_TBL_CFG_ADDR_MASK 0x1f
377 +#define PCE_TBL_CFG_ADWR 0x20
378 +#define PCE_TBL_CFG_ADWR_MASK 0x60
379 +#define PCE_INGRESS BIT(11)
380 +
381 +/* MAC */
382 +#define MAC_FLEN_REG (0x2314)
383 +#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4))
384 +
385 +/* buffer management */
386 +#define BM_PCFG(p) (0x200 + (p * 8))
387 +
388 +/* special tag in TX path header */
389 +#define SPID_SHIFT 24
390 +#define DPID_SHIFT 16
391 +#define DPID_ENABLE 1
392 +#define SPID_CPU_PORT 2
393 +#define PORT_MAP_SEL BIT(15)
394 +#define PORT_MAP_EN BIT(14)
395 +#define PORT_MAP_SHIFT 1
396 +#define PORT_MAP_MASK 0x3f
397 +
398 +#define SPPID_MASK 0x7
399 +#define SPPID_SHIFT 4
400 +
401 +/* MII regs not yet in linux */
402 +#define MDIO_DEVAD_NONE (-1)
403 +#define ADVERTIZE_MPD (1 << 10)
404 +
405 +struct xrx200_port {
406 + u8 num;
407 + u8 phy_addr;
408 + u16 flags;
409 + phy_interface_t phy_if;
410 +
411 + int link;
412 + int gpio;
413 + enum of_gpio_flags gpio_flags;
414 +
415 + struct phy_device *phydev;
416 + struct device_node *phy_node;
417 +};
418 +
419 +struct xrx200_chan {
420 + int idx;
421 + int refcount;
422 + int tx_free;
423 +
424 + struct net_device dummy_dev;
425 + struct net_device *devs[XRX200_MAX_DEV];
426 +
427 + struct napi_struct napi;
428 + struct ltq_dma_channel dma;
429 + struct sk_buff *skb[LTQ_DESC_NUM];
430 +};
431 +
432 +struct xrx200_hw {
433 + struct clk *clk;
434 + struct mii_bus *mii_bus;
435 +
436 + struct xrx200_chan chan[XRX200_MAX_DMA];
437 +
438 + struct net_device *devs[XRX200_MAX_DEV];
439 + int num_devs;
440 +
441 + int port_map[XRX200_MAX_PORT];
442 + unsigned short wan_map;
443 +
444 + spinlock_t lock;
445 +};
446 +
447 +struct xrx200_priv {
448 + struct net_device_stats stats;
449 + int id;
450 +
451 + struct xrx200_port port[XRX200_MAX_PORT];
452 + int num_port;
453 + int wan;
454 + unsigned short port_map;
455 + const void *mac;
456 +
457 + struct xrx200_hw *hw;
458 +};
459 +
460 +static __iomem void *xrx200_switch_membase;
461 +static __iomem void *xrx200_mii_membase;
462 +static __iomem void *xrx200_mdio_membase;
463 +static __iomem void *xrx200_pmac_membase;
464 +
465 +#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x))
466 +#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y))
467 +#define ltq_switch_w32_mask(x, y, z) \
468 + ltq_w32_mask(x, y, xrx200_switch_membase + (z))
469 +
470 +#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x))
471 +#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y))
472 +#define ltq_mdio_w32_mask(x, y, z) \
473 + ltq_w32_mask(x, y, xrx200_mdio_membase + (z))
474 +
475 +#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x))
476 +#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y))
477 +#define ltq_mii_w32_mask(x, y, z) \
478 + ltq_w32_mask(x, y, xrx200_mii_membase + (z))
479 +
480 +#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x))
481 +#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y))
482 +#define ltq_pmac_w32_mask(x, y, z) \
483 + ltq_w32_mask(x, y, xrx200_pmac_membase + (z))
484 +
485 +static int xrx200_open(struct net_device *dev)
486 +{
487 + struct xrx200_priv *priv = netdev_priv(dev);
488 + unsigned long flags;
489 + int i;
490 +
491 + for (i = 0; i < XRX200_MAX_DMA; i++) {
492 + if (!priv->hw->chan[i].dma.irq)
493 + continue;
494 + spin_lock_irqsave(&priv->hw->lock, flags);
495 + if (!priv->hw->chan[i].refcount) {
496 + napi_enable(&priv->hw->chan[i].napi);
497 + ltq_dma_open(&priv->hw->chan[i].dma);
498 + }
499 + priv->hw->chan[i].refcount++;
500 + spin_unlock_irqrestore(&priv->hw->lock, flags);
501 + }
502 + for (i = 0; i < priv->num_port; i++)
503 + if (priv->port[i].phydev)
504 + phy_start(priv->port[i].phydev);
505 + netif_start_queue(dev);
506 +
507 + return 0;
508 +}
509 +
510 +static int xrx200_close(struct net_device *dev)
511 +{
512 + struct xrx200_priv *priv = netdev_priv(dev);
513 + unsigned long flags;
514 + int i;
515 +
516 + netif_stop_queue(dev);
517 +
518 + for (i = 0; i < priv->num_port; i++)
519 + if (priv->port[i].phydev)
520 + phy_stop(priv->port[i].phydev);
521 +
522 + for (i = 0; i < XRX200_MAX_DMA; i++) {
523 + if (!priv->hw->chan[i].dma.irq)
524 + continue;
525 + spin_lock_irqsave(&priv->hw->lock, flags);
526 + priv->hw->chan[i].refcount--;
527 + if (!priv->hw->chan[i].refcount) {
528 + napi_disable(&priv->hw->chan[i].napi);
529 + ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma);
530 + }
531 + spin_unlock_irqrestore(&priv->hw->lock, flags);
532 + }
533 +
534 + return 0;
535 +}
536 +
537 +static int xrx200_alloc_skb(struct xrx200_chan *ch)
538 +{
539 +#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD)
540 + ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD);
541 + if (!ch->skb[ch->dma.desc])
542 + return -ENOMEM;
543 +
544 + skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD);
545 + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
546 + ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
547 + DMA_FROM_DEVICE);
548 + ch->dma.desc_base[ch->dma.desc].addr =
549 + CPHYSADDR(ch->skb[ch->dma.desc]->data);
550 + ch->dma.desc_base[ch->dma.desc].ctl =
551 + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
552 + XRX200_DMA_DATA_LEN;
553 + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
554 +
555 + return 0;
556 +}
557 +
558 +static void xrx200_hw_receive(struct xrx200_chan *ch, int id)
559 +{
560 + struct net_device *dev = ch->devs[id];
561 + struct xrx200_priv *priv = netdev_priv(dev);
562 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
563 + struct sk_buff *skb = ch->skb[ch->dma.desc];
564 + int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - XRX200_DMA_CRC_LEN;
565 + unsigned long flags;
566 +
567 + spin_lock_irqsave(&priv->hw->lock, flags);
568 + if (xrx200_alloc_skb(ch)) {
569 + netdev_err(dev,
570 + "failed to allocate new rx buffer, stopping DMA\n");
571 + ltq_dma_close(&ch->dma);
572 + }
573 +
574 + ch->dma.desc++;
575 + ch->dma.desc %= LTQ_DESC_NUM;
576 + spin_unlock_irqrestore(&priv->hw->lock, flags);
577 +
578 + skb_put(skb, len);
579 +#ifdef SW_ROUTING
580 + skb_pull(skb, 8);
581 +#endif
582 + skb->dev = dev;
583 + skb->protocol = eth_type_trans(skb, dev);
584 + netif_receive_skb(skb);
585 + priv->stats.rx_packets++;
586 + priv->stats.rx_bytes+=len;
587 +}
588 +
589 +static int xrx200_poll_rx(struct napi_struct *napi, int budget)
590 +{
591 + struct xrx200_chan *ch = container_of(napi,
592 + struct xrx200_chan, napi);
593 + struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
594 + int rx = 0;
595 + int complete = 0;
596 + unsigned long flags;
597 +
598 + while ((rx < budget) && !complete) {
599 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
600 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
601 +#ifdef SW_ROUTING
602 + struct sk_buff *skb = ch->skb[ch->dma.desc];
603 + u32 *special_tag = (u32*)skb->data;
604 + int port = (special_tag[1] >> SPPID_SHIFT) & SPPID_MASK;
605 + xrx200_hw_receive(ch, priv->hw->port_map[port]);
606 +#else
607 + xrx200_hw_receive(ch, 0);
608 +#endif
609 + rx++;
610 + } else {
611 + complete = 1;
612 + }
613 + }
614 + if (complete || !rx) {
615 + napi_complete(&ch->napi);
616 + spin_lock_irqsave(&priv->hw->lock, flags);
617 + ltq_dma_ack_irq(&ch->dma);
618 + spin_unlock_irqrestore(&priv->hw->lock, flags);
619 + }
620 + return rx;
621 +}
622 +
623 +static int xrx200_poll_tx(struct napi_struct *napi, int budget)
624 +{
625 + struct xrx200_chan *ch =
626 + container_of(napi, struct xrx200_chan, napi);
627 + struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
628 + unsigned long flags;
629 + int i;
630 +
631 + spin_lock_irqsave(&priv->hw->lock, flags);
632 + while ((ch->dma.desc_base[ch->tx_free].ctl &
633 + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
634 + dev_kfree_skb_any(ch->skb[ch->tx_free]);
635 + ch->skb[ch->tx_free] = NULL;
636 + memset(&ch->dma.desc_base[ch->tx_free], 0,
637 + sizeof(struct ltq_dma_desc));
638 + ch->tx_free++;
639 + ch->tx_free %= LTQ_DESC_NUM;
640 + }
641 + spin_unlock_irqrestore(&priv->hw->lock, flags);
642 +
643 + for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) {
644 + struct netdev_queue *txq =
645 + netdev_get_tx_queue(ch->devs[i], 0);
646 + if (netif_tx_queue_stopped(txq))
647 + netif_tx_start_queue(txq);
648 + }
649 + napi_complete(&ch->napi);
650 + spin_lock_irqsave(&priv->hw->lock, flags);
651 + ltq_dma_ack_irq(&ch->dma);
652 + spin_unlock_irqrestore(&priv->hw->lock, flags);
653 +
654 + return 1;
655 +}
656 +
657 +static struct net_device_stats *xrx200_get_stats (struct net_device *dev)
658 +{
659 + struct xrx200_priv *priv = netdev_priv(dev);
660 +
661 + return &priv->stats;
662 +}
663 +
664 +static void xrx200_tx_timeout(struct net_device *dev)
665 +{
666 + struct xrx200_priv *priv = netdev_priv(dev);
667 +
668 + printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name);
669 +
670 + priv->stats.tx_errors++;
671 + netif_wake_queue(dev);
672 +}
673 +
674 +static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev)
675 +{
676 + int queue = skb_get_queue_mapping(skb);
677 + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
678 + struct xrx200_priv *priv = netdev_priv(dev);
679 + struct xrx200_chan *ch = &priv->hw->chan[XRX200_DMA_TX];
680 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
681 + unsigned long flags;
682 + u32 byte_offset;
683 + int len;
684 +#ifdef SW_ROUTING
685 + #ifdef SW_PORTMAP
686 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | PORT_MAP_SEL | PORT_MAP_EN | DPID_ENABLE;
687 + #else
688 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE;
689 + #endif
690 +#endif
691 +
692 + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
693 +
694 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
695 + netdev_err(dev, "tx ring full\n");
696 + netif_tx_stop_queue(txq);
697 + return NETDEV_TX_BUSY;
698 + }
699 +#ifdef SW_ROUTING
700 + #ifdef SW_PORTMAP
701 + special_tag |= priv->port_map << PORT_MAP_SHIFT;
702 + #else
703 + if(priv->id)
704 + special_tag |= (1 << DPID_SHIFT);
705 + #endif
706 + if(skb_headroom(skb) < 4) {
707 + struct sk_buff *tmp = skb_realloc_headroom(skb, 4);
708 + dev_kfree_skb_any(skb);
709 + skb = tmp;
710 + }
711 + skb_push(skb, 4);
712 + memcpy(skb->data, &special_tag, sizeof(u32));
713 + len += 4;
714 +#endif
715 +
716 + /* dma needs to start on a 16 byte aligned address */
717 + byte_offset = CPHYSADDR(skb->data) % 16;
718 + ch->skb[ch->dma.desc] = skb;
719 +
720 + dev->trans_start = jiffies;
721 +
722 + spin_lock_irqsave(&priv->hw->lock, flags);
723 + desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
724 + DMA_TO_DEVICE)) - byte_offset;
725 + wmb();
726 + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
727 + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
728 + ch->dma.desc++;
729 + ch->dma.desc %= LTQ_DESC_NUM;
730 + spin_unlock_irqrestore(&priv->hw->lock, flags);
731 +
732 + if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
733 + netif_tx_stop_queue(txq);
734 +
735 + priv->stats.tx_packets++;
736 + priv->stats.tx_bytes+=len;
737 +
738 + return NETDEV_TX_OK;
739 +}
740 +
741 +static irqreturn_t xrx200_dma_irq(int irq, void *priv)
742 +{
743 + struct xrx200_hw *hw = priv;
744 + int ch = irq - XRX200_DMA_IRQ;
745 +
746 + napi_schedule(&hw->chan[ch].napi);
747 +
748 + return IRQ_HANDLED;
749 +}
750 +
751 +static int xrx200_dma_init(struct xrx200_hw *hw)
752 +{
753 + int i, err = 0;
754 +
755 + ltq_dma_init_port(DMA_PORT_ETOP);
756 +
757 + for (i = 0; i < 8 && !err; i++) {
758 + int irq = XRX200_DMA_IRQ + i;
759 + struct xrx200_chan *ch = &hw->chan[i];
760 +
761 + ch->idx = ch->dma.nr = i;
762 +
763 + if (i == XRX200_DMA_TX) {
764 + ltq_dma_alloc_tx(&ch->dma);
765 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw);
766 + } else if (i == XRX200_DMA_RX) {
767 + ltq_dma_alloc_rx(&ch->dma);
768 + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
769 + ch->dma.desc++)
770 + if (xrx200_alloc_skb(ch))
771 + err = -ENOMEM;
772 + ch->dma.desc = 0;
773 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw);
774 + } else
775 + continue;
776 +
777 + if (!err)
778 + ch->dma.irq = irq;
779 + }
780 +
781 + return err;
782 +}
783 +
784 +#ifdef SW_POLLING
785 +static void xrx200_gmac_update(struct xrx200_port *port)
786 +{
787 + u16 phyaddr = port->phydev->addr & MDIO_PHY_ADDR_MASK;
788 + u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK;
789 + u16 miirate = 0;
790 +
791 + switch (port->phydev->speed) {
792 + case SPEED_1000:
793 + phyaddr |= MDIO_PHY_SPEED_G1;
794 + miirate = MII_CFG_RATE_M125;
795 + break;
796 +
797 + case SPEED_100:
798 + phyaddr |= MDIO_PHY_SPEED_M100;
799 + switch (miimode) {
800 + case MII_CFG_MODE_RMIIM:
801 + case MII_CFG_MODE_RMIIP:
802 + miirate = MII_CFG_RATE_M50;
803 + break;
804 + default:
805 + miirate = MII_CFG_RATE_M25;
806 + break;
807 + }
808 + break;
809 +
810 + default:
811 + phyaddr |= MDIO_PHY_SPEED_M10;
812 + miirate = MII_CFG_RATE_M2P5;
813 + break;
814 + }
815 +
816 + if (port->phydev->link)
817 + phyaddr |= MDIO_PHY_LINK_UP;
818 + else
819 + phyaddr |= MDIO_PHY_LINK_DOWN;
820 +
821 + if (port->phydev->duplex == DUPLEX_FULL)
822 + phyaddr |= MDIO_PHY_FDUP_EN;
823 + else
824 + phyaddr |= MDIO_PHY_FDUP_DIS;
825 +
826 + ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num));
827 + ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num));
828 + udelay(1);
829 +}
830 +#else
831 +static void xrx200_gmac_update(struct xrx200_port *port)
832 +{
833 +
834 +}
835 +#endif
836 +
837 +static void xrx200_mdio_link(struct net_device *dev)
838 +{
839 + struct xrx200_priv *priv = netdev_priv(dev);
840 + int i;
841 +
842 + for (i = 0; i < priv->num_port; i++) {
843 + if (!priv->port[i].phydev)
844 + continue;
845 +
846 + if (priv->port[i].link != priv->port[i].phydev->link) {
847 + xrx200_gmac_update(&priv->port[i]);
848 + priv->port[i].link = priv->port[i].phydev->link;
849 + netdev_info(dev, "port %d %s link\n",
850 + priv->port[i].num,
851 + (priv->port[i].link)?("got"):("lost"));
852 + }
853 + }
854 +}
855 +
856 +static inline int xrx200_mdio_poll(struct mii_bus *bus)
857 +{
858 + unsigned cnt = 10000;
859 +
860 + while (likely(cnt--)) {
861 + unsigned ctrl = ltq_mdio_r32(MDIO_CTRL);
862 + if ((ctrl & MDIO_BUSY) == 0)
863 + return 0;
864 + }
865 +
866 + return 1;
867 +}
868 +
869 +static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
870 +{
871 + if (xrx200_mdio_poll(bus))
872 + return 1;
873 +
874 + ltq_mdio_w32(val, MDIO_WRITE);
875 + ltq_mdio_w32(MDIO_BUSY | MDIO_WR |
876 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
877 + (reg & MDIO_MASK),
878 + MDIO_CTRL);
879 +
880 + return 0;
881 +}
882 +
883 +static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg)
884 +{
885 + if (xrx200_mdio_poll(bus))
886 + return -1;
887 +
888 + ltq_mdio_w32(MDIO_BUSY | MDIO_RD |
889 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
890 + (reg & MDIO_MASK),
891 + MDIO_CTRL);
892 +
893 + if (xrx200_mdio_poll(bus))
894 + return -1;
895 +
896 + return ltq_mdio_r32(MDIO_READ);
897 +}
898 +
899 +static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port)
900 +{
901 + struct xrx200_priv *priv = netdev_priv(dev);
902 + struct phy_device *phydev = NULL;
903 + unsigned val;
904 +
905 + phydev = priv->hw->mii_bus->phy_map[port->phy_addr];
906 +
907 + if (!phydev) {
908 + netdev_err(dev, "no PHY found\n");
909 + return -ENODEV;
910 + }
911 +
912 + phydev = phy_connect(dev, dev_name(&phydev->dev), &xrx200_mdio_link,
913 + 0, port->phy_if);
914 +
915 + if (IS_ERR(phydev)) {
916 + netdev_err(dev, "Could not attach to PHY\n");
917 + return PTR_ERR(phydev);
918 + }
919 +
920 + phydev->supported &= (SUPPORTED_10baseT_Half
921 + | SUPPORTED_10baseT_Full
922 + | SUPPORTED_100baseT_Half
923 + | SUPPORTED_100baseT_Full
924 + | SUPPORTED_1000baseT_Half
925 + | SUPPORTED_1000baseT_Full
926 + | SUPPORTED_Autoneg
927 + | SUPPORTED_MII
928 + | SUPPORTED_TP);
929 + phydev->advertising = phydev->supported;
930 + port->phydev = phydev;
931 +
932 + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
933 + dev->name, phydev->drv->name,
934 + dev_name(&phydev->dev), phydev->irq);
935 +
936 +#ifdef SW_POLLING
937 + phy_read_status(phydev);
938 +
939 + val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
940 + val |= ADVERTIZE_MPD;
941 + xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
942 + xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040);
943 +
944 + phy_start_aneg(phydev);
945 +#endif
946 + return 0;
947 +}
948 +
949 +static void xrx200_port_config(struct xrx200_priv *priv,
950 + const struct xrx200_port *port)
951 +{
952 + u16 miimode = 0;
953 +
954 + switch (port->num) {
955 + case 0: /* xMII0 */
956 + case 1: /* xMII1 */
957 + switch (port->phy_if) {
958 + case PHY_INTERFACE_MODE_MII:
959 + if (port->flags & XRX200_PORT_TYPE_PHY)
960 + /* MII MAC mode, connected to external PHY */
961 + miimode = MII_CFG_MODE_MIIM;
962 + else
963 + /* MII PHY mode, connected to external MAC */
964 + miimode = MII_CFG_MODE_MIIP;
965 + break;
966 + case PHY_INTERFACE_MODE_RMII:
967 + if (port->flags & XRX200_PORT_TYPE_PHY)
968 + /* RMII MAC mode, connected to external PHY */
969 + miimode = MII_CFG_MODE_RMIIM;
970 + else
971 + /* RMII PHY mode, connected to external MAC */
972 + miimode = MII_CFG_MODE_RMIIP;
973 + break;
974 + case PHY_INTERFACE_MODE_RGMII:
975 + /* RGMII MAC mode, connected to external PHY */
976 + miimode = MII_CFG_MODE_RGMII;
977 + break;
978 + default:
979 + break;
980 + }
981 + break;
982 + case 2: /* internal GPHY0 */
983 + case 3: /* internal GPHY0 */
984 + case 4: /* internal GPHY1 */
985 + switch (port->phy_if) {
986 + case PHY_INTERFACE_MODE_MII:
987 + case PHY_INTERFACE_MODE_GMII:
988 + /* MII MAC mode, connected to internal GPHY */
989 + miimode = MII_CFG_MODE_MIIM;
990 + break;
991 + default:
992 + break;
993 + }
994 + break;
995 + case 5: /* internal GPHY1 or xMII2 */
996 + switch (port->phy_if) {
997 + case PHY_INTERFACE_MODE_MII:
998 + /* MII MAC mode, connected to internal GPHY */
999 + miimode = MII_CFG_MODE_MIIM;
1000 + break;
1001 + case PHY_INTERFACE_MODE_RGMII:
1002 + /* RGMII MAC mode, connected to external PHY */
1003 + miimode = MII_CFG_MODE_RGMII;
1004 + break;
1005 + default:
1006 + break;
1007 + }
1008 + break;
1009 + default:
1010 + break;
1011 + }
1012 +
1013 + ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN,
1014 + MII_CFG(port->num));
1015 +}
1016 +
1017 +static int xrx200_init(struct net_device *dev)
1018 +{
1019 + struct xrx200_priv *priv = netdev_priv(dev);
1020 + struct sockaddr mac;
1021 + int err, i;
1022 +
1023 +#ifndef SW_POLLING
1024 + unsigned int reg = 0;
1025 +
1026 + /* enable auto polling */
1027 + for (i = 0; i < priv->num_port; i++)
1028 + reg |= BIT(priv->port[i].num);
1029 + ltq_mdio_w32(reg, MDIO_CLK_CFG0);
1030 + ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1);
1031 +#endif
1032 +
1033 + /* setup each port */
1034 + for (i = 0; i < priv->num_port; i++)
1035 + xrx200_port_config(priv, &priv->port[i]);
1036 +
1037 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
1038 + if (!is_valid_ether_addr(mac.sa_data)) {
1039 + pr_warn("net-xrx200: invalid MAC, using random\n");
1040 + eth_random_addr(mac.sa_data);
1041 + dev->addr_assign_type |= NET_ADDR_RANDOM;
1042 + }
1043 +
1044 + err = eth_mac_addr(dev, &mac);
1045 + if (err)
1046 + goto err_netdev;
1047 +
1048 + for (i = 0; i < priv->num_port; i++)
1049 + if (xrx200_mdio_probe(dev, &priv->port[i]))
1050 + pr_warn("xrx200-mdio: probing phy of port %d failed\n",
1051 + priv->port[i].num);
1052 +
1053 + return 0;
1054 +
1055 +err_netdev:
1056 + unregister_netdev(dev);
1057 + free_netdev(dev);
1058 + return err;
1059 +}
1060 +
1061 +static void xrx200_pci_microcode(void)
1062 +{
1063 + int i;
1064 +
1065 + ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK,
1066 + PCE_TBL_CFG_ADWR, PCE_TBL_CTRL);
1067 + ltq_switch_w32(0, PCE_TBL_MASK);
1068 +
1069 + for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) {
1070 + ltq_switch_w32(i, PCE_TBL_ADDR);
1071 + ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0));
1072 + ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1));
1073 + ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2));
1074 + ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3));
1075 +
1076 + // start the table access:
1077 + ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL);
1078 + while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY);
1079 + }
1080 +
1081 + /* tell the switch that the microcode is loaded */
1082 + ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0));
1083 +}
1084 +
1085 +static void xrx200_hw_init(struct xrx200_hw *hw)
1086 +{
1087 + int i;
1088 +
1089 + /* enable clock gate */
1090 + clk_enable(hw->clk);
1091 +
1092 + ltq_switch_w32(1, 0);
1093 + mdelay(100);
1094 + ltq_switch_w32(0, 0);
1095 + /*
1096 + * TODO: we should really disbale all phys/miis here and explicitly
1097 + * enable them in the device secific init function
1098 + */
1099 +
1100 + /* disable port fetch/store dma */
1101 + for (i = 0; i < 7; i++ ) {
1102 + ltq_switch_w32(0, FDMA_PCTRLx(i));
1103 + ltq_switch_w32(0, SDMA_PCTRLx(i));
1104 + }
1105 +
1106 + /* enable Switch */
1107 + ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB);
1108 +
1109 + /* load the pce microcode */
1110 + xrx200_pci_microcode();
1111 +
1112 + /* Default unknown Broadcat/Multicast/Unicast port maps */
1113 + ltq_switch_w32(0x7f, PCE_PMAP1);
1114 + ltq_switch_w32(0x7f, PCE_PMAP2);
1115 + ltq_switch_w32(0x7f, PCE_PMAP3);
1116 +
1117 + /* RMON Counter Enable for all physical ports */
1118 + for (i = 0; i < 7; i++)
1119 + ltq_switch_w32(0x1, BM_PCFG(i));
1120 +
1121 + /* disable auto polling */
1122 + ltq_mdio_w32(0x0, MDIO_CLK_CFG0);
1123 +
1124 + /* enable port statistic counters */
1125 + for (i = 0; i < 7; i++)
1126 + ltq_switch_w32(0x1, BM_PCFGx(i));
1127 +
1128 + /* set IPG to 12 */
1129 + ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG);
1130 +
1131 +#ifdef SW_ROUTING
1132 + /* enable status header, enable CRC */
1133 + ltq_pmac_w32_mask(0,
1134 + PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC,
1135 + PMAC_HD_CTL);
1136 +#else
1137 + /* disable status header, enable CRC */
1138 + ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS,
1139 + PMAC_HD_CTL_AC,
1140 + PMAC_HD_CTL);
1141 +#endif
1142 +
1143 + /* enable port fetch/store dma */
1144 + for (i = 0; i < 7; i++ ) {
1145 + ltq_switch_w32_mask(0, 0x01, FDMA_PCTRLx(i));
1146 + ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i));
1147 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0));
1148 + }
1149 +
1150 + /* enable special tag insertion on cpu port */
1151 + ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6));
1152 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0));
1153 + ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2));
1154 + ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG);
1155 +}
1156 +
1157 +static void xrx200_hw_cleanup(struct xrx200_hw *hw)
1158 +{
1159 + int i;
1160 +
1161 + /* disable the switch */
1162 + ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB);
1163 +
1164 + /* free the channels and IRQs */
1165 + for (i = 0; i < 2; i++) {
1166 + ltq_dma_free(&hw->chan[i].dma);
1167 + if (hw->chan[i].dma.irq)
1168 + free_irq(hw->chan[i].dma.irq, hw);
1169 + }
1170 +
1171 + /* free the allocated RX ring */
1172 + for (i = 0; i < LTQ_DESC_NUM; i++)
1173 + dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]);
1174 +
1175 + /* clear the mdio bus */
1176 + mdiobus_unregister(hw->mii_bus);
1177 + mdiobus_free(hw->mii_bus);
1178 +
1179 + /* release the clock */
1180 + clk_disable(hw->clk);
1181 + clk_put(hw->clk);
1182 +}
1183 +
1184 +static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np)
1185 +{
1186 + int i;
1187 + hw->mii_bus = mdiobus_alloc();
1188 + if (!hw->mii_bus)
1189 + return -ENOMEM;
1190 +
1191 + hw->mii_bus->read = xrx200_mdio_rd;
1192 + hw->mii_bus->write = xrx200_mdio_wr;
1193 + hw->mii_bus->name = "lantiq,xrx200-mdio";
1194 + snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
1195 +
1196 + if (of_mdiobus_register(hw->mii_bus, np)) {
1197 + mdiobus_free(hw->mii_bus);
1198 + return -ENXIO;
1199 + }
1200 +
1201 + return 0;
1202 +}
1203 +
1204 +static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port)
1205 +{
1206 + const __be32 *addr, *id = of_get_property(port, "reg", NULL);
1207 + struct xrx200_port *p = &priv->port[priv->num_port];
1208 +
1209 + if (!id)
1210 + return;
1211 +
1212 + memset(p, 0, sizeof(struct xrx200_port));
1213 + p->phy_node = of_parse_phandle(port, "phy-handle", 0);
1214 + addr = of_get_property(p->phy_node, "reg", NULL);
1215 + if (!addr)
1216 + return;
1217 +
1218 + p->num = *id;
1219 + p->phy_addr = *addr;
1220 + p->phy_if = of_get_phy_mode(port);
1221 + if (p->phy_addr > 0x10)
1222 + p->flags = XRX200_PORT_TYPE_MAC;
1223 + else
1224 + p->flags = XRX200_PORT_TYPE_PHY;
1225 + priv->num_port++;
1226 +
1227 + p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags);
1228 + if (gpio_is_valid(p->gpio))
1229 + if (!gpio_request(p->gpio, "phy-reset")) {
1230 + gpio_direction_output(p->gpio,
1231 + (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0));
1232 + udelay(100);
1233 + gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
1234 + }
1235 + /* is this port a wan port ? */
1236 + if (priv->wan)
1237 + priv->hw->wan_map |= BIT(p->num);
1238 +
1239 + priv->port_map |= BIT(p->num);
1240 +
1241 + /* store the port id in the hw struct so we can map ports -> devices */
1242 + priv->hw->port_map[p->num] = priv->hw->num_devs;
1243 +}
1244 +
1245 +static const struct net_device_ops xrx200_netdev_ops = {
1246 + .ndo_init = xrx200_init,
1247 + .ndo_open = xrx200_open,
1248 + .ndo_stop = xrx200_close,
1249 + .ndo_start_xmit = xrx200_start_xmit,
1250 + .ndo_set_mac_address = eth_mac_addr,
1251 + .ndo_validate_addr = eth_validate_addr,
1252 + .ndo_change_mtu = eth_change_mtu,
1253 + .ndo_get_stats = xrx200_get_stats,
1254 + .ndo_tx_timeout = xrx200_tx_timeout,
1255 +};
1256 +
1257 +static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface)
1258 +{
1259 + struct xrx200_priv *priv;
1260 + struct device_node *port;
1261 + const __be32 *wan;
1262 +
1263 + /* alloc the network device */
1264 + hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv));
1265 + if (!hw->devs[hw->num_devs])
1266 + return;
1267 +
1268 + /* setup the network device */
1269 + strcpy(hw->devs[hw->num_devs]->name, "eth%d");
1270 + hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops;
1271 + hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT;
1272 + hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM;
1273 +
1274 + /* setup our private data */
1275 + priv = netdev_priv(hw->devs[hw->num_devs]);
1276 + priv->hw = hw;
1277 + priv->mac = of_get_mac_address(iface);
1278 + priv->id = hw->num_devs;
1279 +
1280 + /* is this the wan interface ? */
1281 + wan = of_get_property(iface, "lantiq,wan", NULL);
1282 + if (wan && (*wan == 1))
1283 + priv->wan = 1;
1284 +
1285 + /* load the ports that are part of the interface */
1286 + for_each_child_of_node(iface, port)
1287 + if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port"))
1288 + xrx200_of_port(priv, port);
1289 +
1290 + /* register the actual device */
1291 + if (!register_netdev(hw->devs[hw->num_devs]))
1292 + hw->num_devs++;
1293 +}
1294 +
1295 +static struct xrx200_hw xrx200_hw;
1296 +
1297 +static int xrx200_probe(struct platform_device *pdev)
1298 +{
1299 + struct resource *res[4];
1300 + struct device_node *mdio_np, *iface_np;
1301 + int i;
1302 +
1303 + /* load the memory ranges */
1304 + for (i = 0; i < 4; i++) {
1305 + res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
1306 + if (!res[i]) {
1307 + dev_err(&pdev->dev, "failed to get resources\n");
1308 + return -ENOENT;
1309 + }
1310 + }
1311 + xrx200_switch_membase = devm_request_and_ioremap(&pdev->dev, res[0]);
1312 + xrx200_mdio_membase = devm_request_and_ioremap(&pdev->dev, res[1]);
1313 + xrx200_mii_membase = devm_request_and_ioremap(&pdev->dev, res[2]);
1314 + xrx200_pmac_membase = devm_request_and_ioremap(&pdev->dev, res[3]);
1315 + if (!xrx200_switch_membase || !xrx200_mdio_membase ||
1316 + !xrx200_mii_membase || !xrx200_pmac_membase) {
1317 + dev_err(&pdev->dev, "failed to request and remap io ranges \n");
1318 + return -ENOMEM;
1319 + }
1320 +
1321 + /* get the clock */
1322 + xrx200_hw.clk = clk_get(&pdev->dev, NULL);
1323 + if (IS_ERR(xrx200_hw.clk)) {
1324 + dev_err(&pdev->dev, "failed to get clock\n");
1325 + return PTR_ERR(xrx200_hw.clk);
1326 + }
1327 +
1328 + /* bring up the dma engine and IP core */
1329 + spin_lock_init(&xrx200_hw.lock);
1330 + xrx200_dma_init(&xrx200_hw);
1331 + xrx200_hw_init(&xrx200_hw);
1332 +
1333 + /* bring up the mdio bus */
1334 + mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL,
1335 + "lantiq,xrx200-mdio");
1336 + if (mdio_np)
1337 + if (xrx200_of_mdio(&xrx200_hw, mdio_np))
1338 + dev_err(&pdev->dev, "mdio probe failed\n");
1339 +
1340 + /* load the interfaces */
1341 + for_each_child_of_node(pdev->dev.of_node, iface_np)
1342 + if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) {
1343 + if (xrx200_hw.num_devs < XRX200_MAX_DEV)
1344 + xrx200_of_iface(&xrx200_hw, iface_np);
1345 + else
1346 + dev_err(&pdev->dev,
1347 + "only %d interfaces allowed\n",
1348 + XRX200_MAX_DEV);
1349 + }
1350 +
1351 + if (!xrx200_hw.num_devs) {
1352 + xrx200_hw_cleanup(&xrx200_hw);
1353 + dev_err(&pdev->dev, "failed to load interfaces\n");
1354 + return -ENOENT;
1355 + }
1356 +
1357 + /* set wan port mask */
1358 + ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN);
1359 +
1360 + for (i = 0; i < xrx200_hw.num_devs; i++) {
1361 + xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i];
1362 + xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i];
1363 + }
1364 +
1365 + /* setup NAPI */
1366 + init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev);
1367 + init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_TX].dummy_dev);
1368 + netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev,
1369 + &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32);
1370 + netif_napi_add(&xrx200_hw.chan[XRX200_DMA_TX].dummy_dev,
1371 + &xrx200_hw.chan[XRX200_DMA_TX].napi, xrx200_poll_tx, 8);
1372 +
1373 + platform_set_drvdata(pdev, &xrx200_hw);
1374 +
1375 + return 0;
1376 +}
1377 +
1378 +static int xrx200_remove(struct platform_device *pdev)
1379 +{
1380 + struct net_device *dev = platform_get_drvdata(pdev);
1381 + struct xrx200_priv *priv;
1382 +
1383 + if (!dev)
1384 + return 0;
1385 +
1386 + priv = netdev_priv(dev);
1387 +
1388 + /* free stack related instances */
1389 + netif_stop_queue(dev);
1390 + netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi);
1391 + netif_napi_del(&xrx200_hw.chan[XRX200_DMA_TX].napi);
1392 +
1393 + /* shut down hardware */
1394 + xrx200_hw_cleanup(&xrx200_hw);
1395 +
1396 + /* remove the actual device */
1397 + unregister_netdev(dev);
1398 + free_netdev(dev);
1399 +
1400 + return 0;
1401 +}
1402 +
1403 +static const struct of_device_id xrx200_match[] = {
1404 + { .compatible = "lantiq,xrx200-net" },
1405 + {},
1406 +};
1407 +MODULE_DEVICE_TABLE(of, xrx200_match);
1408 +
1409 +static struct platform_driver xrx200_driver = {
1410 + .probe = xrx200_probe,
1411 + .remove = xrx200_remove,
1412 + .driver = {
1413 + .name = "lantiq,xrx200-net",
1414 + .of_match_table = xrx200_match,
1415 + .owner = THIS_MODULE,
1416 + },
1417 +};
1418 +
1419 +module_platform_driver(xrx200_driver);
1420 +
1421 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1422 +MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
1423 +MODULE_LICENSE("GPL");
1424 --
1425 1.7.10.4
1426