[lantiq] bump to v3.8
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.8 / 0040-owrt-lantiq-add-atm-hack.patch
1 From ae15f50544e6012c998ef59f6c12e334da3c9bff Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 3 Aug 2012 10:27:25 +0200
4 Subject: [PATCH 40/40] owrt: lantiq: add atm hack
5
6 ---
7 arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++
8 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++
9 arch/mips/lantiq/irq.c | 2 +
10 arch/mips/mm/cache.c | 2 +
11 include/uapi/linux/atm.h | 6 +
12 net/atm/common.c | 6 +
13 net/atm/proc.c | 2 +-
14 7 files changed, 416 insertions(+), 1 deletion(-)
15 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
16 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
17
18 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_atm.h b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
19 new file mode 100644
20 index 0000000..bf045a9
21 --- /dev/null
22 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
23 @@ -0,0 +1,196 @@
24 +/******************************************************************************
25 +**
26 +** FILE NAME : ifx_atm.h
27 +** PROJECT : UEIP
28 +** MODULES : ATM
29 +**
30 +** DATE : 17 Jun 2009
31 +** AUTHOR : Xu Liang
32 +** DESCRIPTION : Global ATM driver header file
33 +** COPYRIGHT : Copyright (c) 2006
34 +** Infineon Technologies AG
35 +** Am Campeon 1-12, 85579 Neubiberg, Germany
36 +**
37 +** This program is free software; you can redistribute it and/or modify
38 +** it under the terms of the GNU General Public License as published by
39 +** the Free Software Foundation; either version 2 of the License, or
40 +** (at your option) any later version.
41 +**
42 +** HISTORY
43 +** $Date $Author $Comment
44 +** 07 JUL 2009 Xu Liang Init Version
45 +*******************************************************************************/
46 +
47 +#ifndef IFX_ATM_H
48 +#define IFX_ATM_H
49 +
50 +
51 +
52 +/*!
53 + \defgroup IFX_ATM UEIP Project - ATM driver module
54 + \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
55 + */
56 +
57 +/*!
58 + \defgroup IFX_ATM_IOCTL IOCTL Commands
59 + \ingroup IFX_ATM
60 + \brief IOCTL Commands used by user application.
61 + */
62 +
63 +/*!
64 + \defgroup IFX_ATM_STRUCT Structures
65 + \ingroup IFX_ATM
66 + \brief Structures used by user application.
67 + */
68 +
69 +/*!
70 + \file ifx_atm.h
71 + \ingroup IFX_ATM
72 + \brief ATM driver header file
73 + */
74 +
75 +
76 +
77 +/*
78 + * ####################################
79 + * Definition
80 + * ####################################
81 + */
82 +
83 +/*!
84 + \addtogroup IFX_ATM_STRUCT
85 + */
86 +/*@{*/
87 +
88 +/*
89 + * ATM MIB
90 + */
91 +
92 +/*!
93 + \struct atm_cell_ifEntry_t
94 + \brief Structure used for Cell Level MIB Counters.
95 +
96 + User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
97 + */
98 +typedef struct {
99 + __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
100 + __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
101 + __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
102 + __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
103 + __u32 ifInErrors; /*!< counter of error ingress cells */
104 + __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
105 + __u32 ifOutErrors; /*!< counter of error egress cells */
106 +} atm_cell_ifEntry_t;
107 +
108 +/*!
109 + \struct atm_aal5_ifEntry_t
110 + \brief Structure used for AAL5 Frame Level MIB Counters.
111 +
112 + User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
113 + */
114 +typedef struct {
115 + __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
116 + __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
117 + __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
118 + __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
119 + __u32 ifInUcastPkts; /*!< counter of ingress packets */
120 + __u32 ifOutUcastPkts; /*!< counter of egress packets */
121 + __u32 ifInErrors; /*!< counter of error ingress packets */
122 + __u32 ifInDiscards; /*!< counter of dropped ingress packets */
123 + __u32 ifOutErros; /*!< counter of error egress packets */
124 + __u32 ifOutDiscards; /*!< counter of dropped egress packets */
125 +} atm_aal5_ifEntry_t;
126 +
127 +/*!
128 + \struct atm_aal5_vcc_t
129 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
130 +
131 + This structure is a part of structure "atm_aal5_vcc_x_t".
132 + */
133 +typedef struct {
134 + __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
135 + __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
136 + __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
137 +} atm_aal5_vcc_t;
138 +
139 +/*!
140 + \struct atm_aal5_vcc_x_t
141 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
142 +
143 + User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
144 + */
145 +typedef struct {
146 + int vpi; /*!< VPI of the VCC to get MIB counters */
147 + int vci; /*!< VCI of the VCC to get MIB counters */
148 + atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
149 +} atm_aal5_vcc_x_t;
150 +
151 +/*@}*/
152 +
153 +
154 +
155 +/*
156 + * ####################################
157 + * IOCTL
158 + * ####################################
159 + */
160 +
161 +/*!
162 + \addtogroup IFX_ATM_IOCTL
163 + */
164 +/*@{*/
165 +
166 +/*
167 + * ioctl Command
168 + */
169 +/*!
170 + \brief ATM IOCTL Magic Number
171 + */
172 +#define PPE_ATM_IOC_MAGIC 'o'
173 +/*!
174 + \brief ATM IOCTL Command - Get Cell Level MIB Counters
175 +
176 + This command is obsolete. User can get cell level MIB from DSL API.
177 + This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
178 + */
179 +#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
180 +/*!
181 + \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
182 +
183 + Get AAL5 packet counters.
184 + This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
185 + */
186 +#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
187 +/*!
188 + \brief ATM IOCTL Command - Get Per PVC MIB Counters
189 +
190 + Get AAL5 packet counters for each PVC.
191 + This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
192 + */
193 +#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
194 +/*!
195 + \brief Total Number of ATM IOCTL Commands
196 + */
197 +#define PPE_ATM_IOC_MAXNR 3
198 +
199 +/*@}*/
200 +
201 +
202 +
203 +/*
204 + * ####################################
205 + * API
206 + * ####################################
207 + */
208 +
209 +#ifdef __KERNEL__
210 +struct port_cell_info {
211 + unsigned int port_num;
212 + unsigned int tx_link_rate[2];
213 +};
214 +#endif
215 +
216 +
217 +
218 +#endif // IFX_ATM_H
219 +
220 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
221 new file mode 100644
222 index 0000000..698e5c3
223 --- /dev/null
224 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
225 @@ -0,0 +1,203 @@
226 +/******************************************************************************
227 +**
228 +** FILE NAME : ifx_ptm.h
229 +** PROJECT : UEIP
230 +** MODULES : PTM
231 +**
232 +** DATE : 17 Jun 2009
233 +** AUTHOR : Xu Liang
234 +** DESCRIPTION : Global PTM driver header file
235 +** COPYRIGHT : Copyright (c) 2006
236 +** Infineon Technologies AG
237 +** Am Campeon 1-12, 85579 Neubiberg, Germany
238 +**
239 +** This program is free software; you can redistribute it and/or modify
240 +** it under the terms of the GNU General Public License as published by
241 +** the Free Software Foundation; either version 2 of the License, or
242 +** (at your option) any later version.
243 +**
244 +** HISTORY
245 +** $Date $Author $Comment
246 +** 07 JUL 2009 Xu Liang Init Version
247 +*******************************************************************************/
248 +
249 +#ifndef IFX_PTM_H
250 +#define IFX_PTM_H
251 +
252 +
253 +
254 +/*!
255 + \defgroup IFX_PTM UEIP Project - PTM driver module
256 + \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
257 + */
258 +
259 +/*!
260 + \defgroup IFX_PTM_IOCTL IOCTL Commands
261 + \ingroup IFX_PTM
262 + \brief IOCTL Commands used by user application.
263 + */
264 +
265 +/*!
266 + \defgroup IFX_PTM_STRUCT Structures
267 + \ingroup IFX_PTM
268 + \brief Structures used by user application.
269 + */
270 +
271 +/*!
272 + \file ifx_ptm.h
273 + \ingroup IFX_PTM
274 + \brief PTM driver header file
275 + */
276 +
277 +
278 +
279 +/*
280 + * ####################################
281 + * Definition
282 + * ####################################
283 + */
284 +
285 +
286 +
287 +/*
288 + * ####################################
289 + * IOCTL
290 + * ####################################
291 + */
292 +
293 +/*!
294 + \addtogroup IFX_PTM_IOCTL
295 + */
296 +/*@{*/
297 +
298 +/*
299 + * ioctl Command
300 + */
301 +/*!
302 + \brief PTM IOCTL Command - Get codeword MIB counters.
303 +
304 + This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
305 + */
306 +#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
307 +/*!
308 + \brief PTM IOCTL Command - Get packet MIB counters.
309 +
310 + This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
311 + */
312 +#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
313 +/*!
314 + \brief PTM IOCTL Command - Get firmware configuration (CRC).
315 +
316 + This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
317 + */
318 +#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
319 +/*!
320 + \brief PTM IOCTL Command - Set firmware configuration (CRC).
321 +
322 + This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
323 + */
324 +#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
325 +/*!
326 + \brief PTM IOCTL Command - Program priority value to TX queue mapping.
327 +
328 + This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
329 + */
330 +#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
331 +
332 +/*@}*/
333 +
334 +
335 +/*!
336 + \addtogroup IFX_PTM_STRUCT
337 + */
338 +/*@{*/
339 +
340 +/*
341 + * ioctl Data Type
342 + */
343 +
344 +/*!
345 + \typedef PTM_CW_IF_ENTRY_T
346 + \brief Wrapping of structure "ptm_cw_ifEntry_t".
347 + */
348 +/*!
349 + \struct ptm_cw_ifEntry_t
350 + \brief Structure used for CodeWord level MIB counters.
351 + */
352 +typedef struct ptm_cw_ifEntry_t {
353 + uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
354 + uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
355 + uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
356 + uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
357 + uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
358 +} PTM_CW_IF_ENTRY_T;
359 +
360 +/*!
361 + \typedef PTM_FRAME_MIB_T
362 + \brief Wrapping of structure "ptm_frame_mib_t".
363 + */
364 +/*!
365 + \struct ptm_frame_mib_t
366 + \brief Structure used for packet level MIB counters.
367 + */
368 +typedef struct ptm_frame_mib_t {
369 + uint32_t RxCorrect; /*!< output, number of ingress packet */
370 + uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
371 + uint32_t RxDropped; /*!< output, number of dropped ingress packet */
372 + uint32_t TxSend; /*!< output, number of egress packet */
373 +} PTM_FRAME_MIB_T;
374 +
375 +/*!
376 + \typedef IFX_PTM_CFG_T
377 + \brief Wrapping of structure "ptm_cfg_t".
378 + */
379 +/*!
380 + \struct ptm_cfg_t
381 + \brief Structure used for ETH/TC CRC configuration.
382 + */
383 +typedef struct ptm_cfg_t {
384 + uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
385 + uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
386 + uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
387 + uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
388 + uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
389 + uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
390 + uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
391 +} IFX_PTM_CFG_T;
392 +
393 +/*!
394 + \typedef IFX_PTM_PRIO_Q_MAP_T
395 + \brief Wrapping of structure "ppe_prio_q_map".
396 + */
397 +/*!
398 + \struct ppe_prio_q_map
399 + \brief Structure used for Priority Value to TX Queue mapping.
400 + */
401 +typedef struct ppe_prio_q_map {
402 + int pkt_prio;
403 + int qid;
404 + int vpi; // ignored in eth interface
405 + int vci; // ignored in eth interface
406 +} IFX_PTM_PRIO_Q_MAP_T;
407 +
408 +/*@}*/
409 +
410 +
411 +
412 +/*
413 + * ####################################
414 + * API
415 + * ####################################
416 + */
417 +
418 +#ifdef __KERNEL__
419 +struct port_cell_info {
420 + unsigned int port_num;
421 + unsigned int tx_link_rate[2];
422 +};
423 +#endif
424 +
425 +
426 +
427 +#endif // IFX_PTM_H
428 +
429 diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
430 index 5119487..6d2c486 100644
431 --- a/arch/mips/lantiq/irq.c
432 +++ b/arch/mips/lantiq/irq.c
433 @@ -14,6 +14,7 @@
434 #include <linux/of_platform.h>
435 #include <linux/of_address.h>
436 #include <linux/of_irq.h>
437 +#include <linux/module.h>
438
439 #include <asm/bootinfo.h>
440 #include <asm/irq_cpu.h>
441 @@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_data *d)
442 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
443 ltq_icu_w32(im, BIT(offset), isr);
444 }
445 +EXPORT_SYMBOL(ltq_mask_and_ack_irq);
446
447 static void ltq_ack_irq(struct irq_data *d)
448 {
449 diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
450 index 07cec44..a3e3872 100644
451 --- a/arch/mips/mm/cache.c
452 +++ b/arch/mips/mm/cache.c
453 @@ -57,6 +57,8 @@ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
454 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
455
456 EXPORT_SYMBOL(_dma_cache_wback_inv);
457 +EXPORT_SYMBOL(_dma_cache_wback);
458 +EXPORT_SYMBOL(_dma_cache_inv);
459
460 #endif /* CONFIG_DMA_NONCOHERENT */
461
462 diff --git a/include/uapi/linux/atm.h b/include/uapi/linux/atm.h
463 index 88399db..78c8bbc 100644
464 --- a/include/uapi/linux/atm.h
465 +++ b/include/uapi/linux/atm.h
466 @@ -130,8 +130,14 @@
467 #define ATM_ABR 4
468 #define ATM_ANYCLASS 5 /* compatible with everything */
469
470 +#define ATM_VBR_NRT ATM_VBR
471 +#define ATM_VBR_RT 6
472 +#define ATM_UBR_PLUS 7
473 +#define ATM_GFR 8
474 +
475 #define ATM_MAX_PCR -1 /* maximum available PCR */
476
477 +
478 struct atm_trafprm {
479 unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
480 int max_pcr; /* maximum PCR in cells per second */
481 diff --git a/net/atm/common.c b/net/atm/common.c
482 index 806fc0a..82bc78e 100644
483 --- a/net/atm/common.c
484 +++ b/net/atm/common.c
485 @@ -62,11 +62,17 @@ static void vcc_remove_socket(struct sock *sk)
486 write_unlock_irq(&vcc_sklist_lock);
487 }
488
489 +struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
490 +EXPORT_SYMBOL(ifx_atm_alloc_tx);
491 +
492 static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
493 {
494 struct sk_buff *skb;
495 struct sock *sk = sk_atm(vcc);
496
497 + if (ifx_atm_alloc_tx != NULL)
498 + return ifx_atm_alloc_tx(vcc, size);
499 +
500 if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
501 pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
502 sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
503 diff --git a/net/atm/proc.c b/net/atm/proc.c
504 index 0d020de..9fdb539 100644
505 --- a/net/atm/proc.c
506 +++ b/net/atm/proc.c
507 @@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
508 static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
509 {
510 static const char *const class_name[] = {
511 - "off", "UBR", "CBR", "VBR", "ABR"};
512 + "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
513 static const char *const aal_name[] = {
514 "---", "1", "2", "3/4", /* 0- 3 */
515 "???", "5", "???", "???", /* 4- 7 */
516 --
517 1.7.10.4
518