target/linux/lantiq/patches-3.9/0004-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch

   1 From 6a68cfb053a7c95ff36c7c2ce2a092aa98620422 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 20 May 2012 00:42:39 +0200
   4 Subject: [PATCH 04/22] I2C: MIPS: lantiq: add FALC-ON i2c bus master
   5
   6 This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs.
   7
   8 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  drivers/i2c/busses/Kconfig      |   10 +
  12  drivers/i2c/busses/Makefile     |    1 +
  13  drivers/i2c/busses/i2c-lantiq.c |  747 +++++++++++++++++++++++++++++++++++++++
  14  drivers/i2c/busses/i2c-lantiq.h |  234 ++++++++++++
  15  4 files changed, 992 insertions(+)
  16  create mode 100644 drivers/i2c/busses/i2c-lantiq.c
  17  create mode 100644 drivers/i2c/busses/i2c-lantiq.h
  18
  19 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
  20 index adfee98..83d3147 100644
  21 --- a/drivers/i2c/busses/Kconfig
  22 +++ b/drivers/i2c/busses/Kconfig
  23 @@ -494,6 +494,16 @@ config I2C_IOP3XX
  24           This driver can also be built as a module.  If so, the module
  25           will be called i2c-iop3xx.
  26
  27 +config I2C_LANTIQ
  28 +       tristate "Lantiq I2C interface"
  29 +       depends on LANTIQ && SOC_FALCON
  30 +       help
  31 +         If you say yes to this option, support will be included for the
  32 +         Lantiq I2C core.
  33 +
  34 +         This driver can also be built as a module. If so, the module
  35 +         will be called i2c-lantiq.
  36 +
  37  config I2C_MPC
  38         tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
  39         depends on PPC
  40 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
  41 index 8f4fc23..3273061 100644
  42 --- a/drivers/i2c/busses/Makefile
  43 +++ b/drivers/i2c/busses/Makefile
  44 @@ -48,6 +48,7 @@ obj-$(CONFIG_I2C_IBM_IIC)     += i2c-ibm_iic.o
  45  obj-$(CONFIG_I2C_IMX)          += i2c-imx.o
  46  obj-$(CONFIG_I2C_INTEL_MID)    += i2c-intel-mid.o
  47  obj-$(CONFIG_I2C_IOP3XX)       += i2c-iop3xx.o
  48 +obj-$(CONFIG_I2C_LANTIQ)       += i2c-lantiq.o
  49  obj-$(CONFIG_I2C_MPC)          += i2c-mpc.o
  50  obj-$(CONFIG_I2C_MV64XXX)      += i2c-mv64xxx.o
  51  obj-$(CONFIG_I2C_MXS)          += i2c-mxs.o
  52 diff --git a/drivers/i2c/busses/i2c-lantiq.c b/drivers/i2c/busses/i2c-lantiq.c
  53 new file mode 100644
  54 index 0000000..9a5f58b
  55 --- /dev/null
  56 +++ b/drivers/i2c/busses/i2c-lantiq.c
  57 @@ -0,0 +1,747 @@
  58 +
  59 +/*
  60 + * Lantiq I2C bus adapter
  61 + *
  62 + * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33
  63 + *
  64 + * This program is free software; you can redistribute it and/or modify
  65 + * it under the terms of the GNU General Public License as published by
  66 + * the Free Software Foundation; either version 2 of the License, or
  67 + * (at your option) any later version.
  68 + *
  69 + * This program is distributed in the hope that it will be useful,
  70 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  71 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  72 + * GNU General Public License for more details.
  73 + *
  74 + * You should have received a copy of the GNU General Public License
  75 + * along with this program; if not, write to the Free Software
  76 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  77 + *
  78 + * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
  79 + */
  80 +
  81 +#include <linux/kernel.h>
  82 +#include <linux/module.h>
  83 +#include <linux/delay.h>
  84 +#include <linux/slab.h> /* for kzalloc, kfree */
  85 +#include <linux/i2c.h>
  86 +#include <linux/errno.h>
  87 +#include <linux/completion.h>
  88 +#include <linux/interrupt.h>
  89 +#include <linux/platform_device.h>
  90 +#include <linux/io.h>
  91 +#include <linux/of_irq.h>
  92 +#include <linux/of_i2c.h>
  93 +
  94 +#include <lantiq_soc.h>
  95 +#include "i2c-lantiq.h"
  96 +
  97 +/*
  98 + * CURRENT ISSUES:
  99 + * - no high speed support
 100 + * - ten bit mode is not tested (no slave devices)
 101 + */
 102 +
 103 +/* access macros */
 104 +#define i2c_r32(reg)   \
 105 +       __raw_readl(&(priv->membase)->reg)
 106 +#define i2c_w32(val, reg)      \
 107 +       __raw_writel(val, &(priv->membase)->reg)
 108 +#define i2c_w32_mask(clear, set, reg)  \
 109 +       i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg)
 110 +
 111 +#define DRV_NAME "i2c-lantiq"
 112 +#define DRV_VERSION "1.00"
 113 +
 114 +#define LTQ_I2C_BUSY_TIMEOUT           20 /* ms */
 115 +
 116 +#ifdef DEBUG
 117 +#define LTQ_I2C_XFER_TIMEOUT           (25*HZ)
 118 +#else
 119 +#define LTQ_I2C_XFER_TIMEOUT           HZ
 120 +#endif
 121 +
 122 +#define LTQ_I2C_IMSC_DEFAULT_MASK      (I2C_IMSC_I2C_P_INT_EN | \
 123 +                                        I2C_IMSC_I2C_ERR_INT_EN)
 124 +
 125 +#define LTQ_I2C_ARB_LOST               (1 << 0)
 126 +#define LTQ_I2C_NACK                   (1 << 1)
 127 +#define LTQ_I2C_RX_UFL                 (1 << 2)
 128 +#define LTQ_I2C_RX_OFL                 (1 << 3)
 129 +#define LTQ_I2C_TX_UFL                 (1 << 4)
 130 +#define LTQ_I2C_TX_OFL                 (1 << 5)
 131 +
 132 +struct ltq_i2c {
 133 +       struct mutex mutex;
 134 +
 135 +
 136 +       /* active clock settings */
 137 +       unsigned int input_clock;       /* clock input for i2c hardware block */
 138 +       unsigned int i2c_clock;         /* approximated bus clock in kHz */
 139 +
 140 +       struct clk *clk_gate;
 141 +       struct clk *clk_input;
 142 +
 143 +
 144 +       /* resources (memory and interrupts) */
 145 +       int irq_lb;                             /* last burst irq */
 146 +
 147 +       struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */
 148 +
 149 +       struct i2c_adapter adap;
 150 +       struct device *dev;
 151 +
 152 +       struct completion cmd_complete;
 153 +
 154 +
 155 +       /* message transfer data */
 156 +       struct i2c_msg *current_msg;    /* current message */
 157 +       int msgs_num;           /* number of messages to handle */
 158 +       u8 *msg_buf;            /* current buffer */
 159 +       u32 msg_buf_len;        /* remaining length of current buffer */
 160 +       int msg_err;            /* error status of the current transfer */
 161 +
 162 +
 163 +       /* master status codes */
 164 +       enum {
 165 +               STATUS_IDLE,
 166 +               STATUS_ADDR,    /* address phase */
 167 +               STATUS_WRITE,
 168 +               STATUS_READ,
 169 +               STATUS_READ_END,
 170 +               STATUS_STOP
 171 +       } status;
 172 +};
 173 +
 174 +static irqreturn_t ltq_i2c_isr(int irq, void *dev_id);
 175 +
 176 +static inline void enable_burst_irq(struct ltq_i2c *priv)
 177 +{
 178 +       i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
 179 +}
 180 +static inline void disable_burst_irq(struct ltq_i2c *priv)
 181 +{
 182 +       i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
 183 +}
 184 +
 185 +static void prepare_msg_send_addr(struct ltq_i2c *priv)
 186 +{
 187 +       struct i2c_msg *msg = priv->current_msg;
 188 +       int rd = !!(msg->flags & I2C_M_RD);     /* extends to 0 or 1 */
 189 +       u16 addr = msg->addr;
 190 +
 191 +       /* new i2c_msg */
 192 +       priv->msg_buf = msg->buf;
 193 +       priv->msg_buf_len = msg->len;
 194 +       if (rd)
 195 +               priv->status = STATUS_READ;
 196 +       else
 197 +               priv->status = STATUS_WRITE;
 198 +
 199 +       /* send slave address */
 200 +       if (msg->flags & I2C_M_TEN) {
 201 +               i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);
 202 +               i2c_w32(addr & 0xff, txd);
 203 +       } else {
 204 +               i2c_w32((addr & 0x7f) << 1 | rd, txd);
 205 +       }
 206 +}
 207 +
 208 +static void ltq_i2c_set_tx_len(struct ltq_i2c *priv)
 209 +{
 210 +       struct i2c_msg *msg = priv->current_msg;
 211 +       int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
 212 +
 213 +       pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T');
 214 +
 215 +       priv->status = STATUS_ADDR;
 216 +
 217 +       if (!(msg->flags & I2C_M_RD))
 218 +               len += msg->len;
 219 +       else
 220 +               /* set maximum received packet size (before rx int!) */
 221 +               i2c_w32(msg->len, mrps_ctrl);
 222 +       i2c_w32(len, tps_ctrl);
 223 +       enable_burst_irq(priv);
 224 +}
 225 +
 226 +static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap)
 227 +{
 228 +       struct ltq_i2c *priv = i2c_get_adapdata(adap);
 229 +       unsigned int input_clock = clk_get_rate(priv->clk_input);
 230 +       u32 dec, inc = 1;
 231 +
 232 +       /* clock changed? */
 233 +       if (priv->input_clock == input_clock)
 234 +               return 0;
 235 +
 236 +       /*
 237 +        * this formula is only an approximation, found by the recommended
 238 +        * values in the "I2C Architecture Specification 1.7.1"
 239 +        */
 240 +       dec = input_clock / (priv->i2c_clock * 2);
 241 +       if (dec <= 6)
 242 +               return -ENXIO;
 243 +
 244 +       i2c_w32(0, fdiv_high_cfg);
 245 +       i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) |
 246 +               (dec << I2C_FDIV_CFG_DEC_OFFSET),
 247 +               fdiv_cfg);
 248 +
 249 +       dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n",
 250 +               input_clock, priv->i2c_clock, dec);
 251 +
 252 +       priv->input_clock = input_clock;
 253 +       return 0;
 254 +}
 255 +
 256 +static int ltq_i2c_hw_init(struct i2c_adapter *adap)
 257 +{
 258 +       int ret = 0;
 259 +       struct ltq_i2c *priv = i2c_get_adapdata(adap);
 260 +
 261 +       /* disable bus */
 262 +       i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 263 +
 264 +#ifndef DEBUG
 265 +       /* set normal operation clock divider */
 266 +       i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
 267 +#else
 268 +       /* for debugging a higher divider value! */
 269 +       i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);
 270 +#endif
 271 +
 272 +       /* setup clock */
 273 +       ret = ltq_i2c_hw_set_clock(adap);
 274 +       if (ret != 0) {
 275 +               dev_warn(priv->dev, "invalid clock settings\n");
 276 +               return ret;
 277 +       }
 278 +
 279 +       /* configure fifo */
 280 +       i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */
 281 +               I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */
 282 +               I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */
 283 +               I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */
 284 +               I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */
 285 +               I2C_FIFO_CFG_RXBS_RXBS0,  /* rx fifo burst size is 1 word */
 286 +               fifo_cfg);
 287 +
 288 +       /* configure address */
 289 +       i2c_w32(I2C_ADDR_CFG_SOPE_EN |  /* generate stop when no more data in
 290 +                                          the fifo */
 291 +               I2C_ADDR_CFG_SONA_EN |  /* generate stop when NA received */
 292 +               I2C_ADDR_CFG_MnS_EN |   /* we are master device */
 293 +               0,                      /* our slave address (not used!) */
 294 +               addr_cfg);
 295 +
 296 +       /* enable bus */
 297 +       i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
 298 +
 299 +       return 0;
 300 +}
 301 +
 302 +static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv)
 303 +{
 304 +       unsigned long timeout;
 305 +
 306 +       timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT);
 307 +
 308 +       do {
 309 +               u32 stat = i2c_r32(bus_stat);
 310 +
 311 +               if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE)
 312 +                       return 0;
 313 +
 314 +               cond_resched();
 315 +       } while (!time_after_eq(jiffies, timeout));
 316 +
 317 +       dev_err(priv->dev, "timeout waiting for bus ready\n");
 318 +       return -ETIMEDOUT;
 319 +}
 320 +
 321 +static void ltq_i2c_tx(struct ltq_i2c *priv, int last)
 322 +{
 323 +       if (priv->msg_buf_len && priv->msg_buf) {
 324 +               i2c_w32(*priv->msg_buf, txd);
 325 +
 326 +               if (--priv->msg_buf_len)
 327 +                       priv->msg_buf++;
 328 +               else
 329 +                       priv->msg_buf = NULL;
 330 +       } else {
 331 +               last = 1;
 332 +       }
 333 +
 334 +       if (last)
 335 +               disable_burst_irq(priv);
 336 +}
 337 +
 338 +static void ltq_i2c_rx(struct ltq_i2c *priv, int last)
 339 +{
 340 +       u32 fifo_stat, timeout;
 341 +       if (priv->msg_buf_len && priv->msg_buf) {
 342 +               timeout = 5000000;
 343 +               do {
 344 +                       fifo_stat = i2c_r32(ffs_stat);
 345 +               } while (!fifo_stat && --timeout);
 346 +               if (!timeout) {
 347 +                       last = 1;
 348 +                       pr_debug("\nrx timeout\n");
 349 +                       goto err;
 350 +               }
 351 +               while (fifo_stat) {
 352 +                       *priv->msg_buf = i2c_r32(rxd);
 353 +                       if (--priv->msg_buf_len) {
 354 +                               priv->msg_buf++;
 355 +                       } else {
 356 +                               priv->msg_buf = NULL;
 357 +                               last = 1;
 358 +                               break;
 359 +                       }
 360 +                       /*
 361 +                        * do not read more than burst size, otherwise no "last
 362 +                        * burst" is generated and the transaction is blocked!
 363 +                        */
 364 +                       fifo_stat = 0;
 365 +               }
 366 +       } else {
 367 +               last = 1;
 368 +       }
 369 +err:
 370 +       if (last) {
 371 +               disable_burst_irq(priv);
 372 +
 373 +               if (priv->status == STATUS_READ_END) {
 374 +                       /*
 375 +                        * do the STATUS_STOP and complete() here, as sometimes
 376 +                        * the tx_end is already seen before this is finished
 377 +                        */
 378 +                       priv->status = STATUS_STOP;
 379 +                       complete(&priv->cmd_complete);
 380 +               } else {
 381 +                       i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
 382 +                       priv->status = STATUS_READ_END;
 383 +               }
 384 +       }
 385 +}
 386 +
 387 +static void ltq_i2c_xfer_init(struct ltq_i2c *priv)
 388 +{
 389 +       /* enable interrupts */
 390 +       i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc);
 391 +
 392 +       /* trigger transfer of first msg */
 393 +       ltq_i2c_set_tx_len(priv);
 394 +}
 395 +
 396 +static void dump_msgs(struct i2c_msg msgs[], int num, int rx)
 397 +{
 398 +#if defined(DEBUG)
 399 +       int i, j;
 400 +       pr_debug("Messages %d %s\n", num, rx ? "out" : "in");
 401 +       for (i = 0; i < num; i++) {
 402 +               pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i,
 403 +                       (msgs[i].flags & I2C_M_RD) ? 'R' : 'T',
 404 +                       msgs[i].len, msgs[i].addr);
 405 +               if (!(msgs[i].flags & I2C_M_RD) || rx) {
 406 +                       for (j = 0; j < msgs[i].len; j++)
 407 +                               pr_debug("%02X ", msgs[i].buf[j]);
 408 +               }
 409 +               pr_debug("\n");
 410 +       }
 411 +#endif
 412 +}
 413 +
 414 +static void ltq_i2c_release_bus(struct ltq_i2c *priv)
 415 +{
 416 +       if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)
 417 +               i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
 418 +}
 419 +
 420 +static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 421 +                          int num)
 422 +{
 423 +       struct ltq_i2c *priv = i2c_get_adapdata(adap);
 424 +       int ret;
 425 +
 426 +       dev_dbg(priv->dev, "xfer %u messages\n", num);
 427 +       dump_msgs(msgs, num, 0);
 428 +
 429 +       mutex_lock(&priv->mutex);
 430 +
 431 +       INIT_COMPLETION(priv->cmd_complete);
 432 +       priv->current_msg = msgs;
 433 +       priv->msgs_num = num;
 434 +       priv->msg_err = 0;
 435 +       priv->status = STATUS_IDLE;
 436 +
 437 +       /* wait for the bus to become ready */
 438 +       ret = ltq_i2c_wait_bus_not_busy(priv);
 439 +       if (ret)
 440 +               goto done;
 441 +
 442 +       while (priv->msgs_num) {
 443 +               /* start the transfers */
 444 +               ltq_i2c_xfer_init(priv);
 445 +
 446 +               /* wait for transfers to complete */
 447 +               ret = wait_for_completion_interruptible_timeout(
 448 +                       &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT);
 449 +               if (ret == 0) {
 450 +                       dev_err(priv->dev, "controller timed out\n");
 451 +                       ltq_i2c_hw_init(adap);
 452 +                       ret = -ETIMEDOUT;
 453 +                       goto done;
 454 +               } else if (ret < 0)
 455 +                       goto done;
 456 +
 457 +               if (priv->msg_err) {
 458 +                       if (priv->msg_err & LTQ_I2C_NACK)
 459 +                               ret = -ENXIO;
 460 +                       else
 461 +                               ret = -EREMOTEIO;
 462 +                       goto done;
 463 +               }
 464 +               if (--priv->msgs_num)
 465 +                       priv->current_msg++;
 466 +       }
 467 +       /* no error? */
 468 +       ret = num;
 469 +
 470 +done:
 471 +       ltq_i2c_release_bus(priv);
 472 +
 473 +       mutex_unlock(&priv->mutex);
 474 +
 475 +       if (ret >= 0)
 476 +               dump_msgs(msgs, num, 1);
 477 +
 478 +       pr_debug("XFER ret %d\n", ret);
 479 +       return ret;
 480 +}
 481 +
 482 +static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id)
 483 +{
 484 +       struct ltq_i2c *priv = dev_id;
 485 +       struct i2c_msg *msg = priv->current_msg;
 486 +       int last = (irq == priv->irq_lb);
 487 +
 488 +       if (last)
 489 +               pr_debug("LB ");
 490 +       else
 491 +               pr_debug("B ");
 492 +
 493 +       if (msg->flags & I2C_M_RD) {
 494 +               switch (priv->status) {
 495 +               case STATUS_ADDR:
 496 +                       pr_debug("X");
 497 +                       prepare_msg_send_addr(priv);
 498 +                       disable_burst_irq(priv);
 499 +                       break;
 500 +               case STATUS_READ:
 501 +               case STATUS_READ_END:
 502 +                       pr_debug("R");
 503 +                       ltq_i2c_rx(priv, last);
 504 +                       break;
 505 +               default:
 506 +                       disable_burst_irq(priv);
 507 +                       pr_warn("Status R %d\n", priv->status);
 508 +                       break;
 509 +               }
 510 +       } else {
 511 +               switch (priv->status) {
 512 +               case STATUS_ADDR:
 513 +                       pr_debug("x");
 514 +                       prepare_msg_send_addr(priv);
 515 +                       break;
 516 +               case STATUS_WRITE:
 517 +                       pr_debug("w");
 518 +                       ltq_i2c_tx(priv, last);
 519 +                       break;
 520 +               default:
 521 +                       disable_burst_irq(priv);
 522 +                       pr_warn("Status W %d\n", priv->status);
 523 +                       break;
 524 +               }
 525 +       }
 526 +
 527 +       i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);
 528 +       return IRQ_HANDLED;
 529 +}
 530 +
 531 +static void ltq_i2c_isr_prot(struct ltq_i2c *priv)
 532 +{
 533 +       u32 i_pro = i2c_r32(p_irqss);
 534 +
 535 +       pr_debug("i2c-p");
 536 +
 537 +       /* not acknowledge */
 538 +       if (i_pro & I2C_P_IRQSS_NACK) {
 539 +               priv->msg_err |= LTQ_I2C_NACK;
 540 +               pr_debug(" nack");
 541 +       }
 542 +
 543 +       /* arbitration lost */
 544 +       if (i_pro & I2C_P_IRQSS_AL) {
 545 +               priv->msg_err |= LTQ_I2C_ARB_LOST;
 546 +               pr_debug(" arb-lost");
 547 +       }
 548 +       /* tx -> rx switch */
 549 +       if (i_pro & I2C_P_IRQSS_RX)
 550 +               pr_debug(" rx");
 551 +
 552 +       /* tx end */
 553 +       if (i_pro & I2C_P_IRQSS_TX_END)
 554 +               pr_debug(" txend");
 555 +       pr_debug("\n");
 556 +
 557 +       if (!priv->msg_err) {
 558 +               /* tx -> rx switch */
 559 +               if (i_pro & I2C_P_IRQSS_RX) {
 560 +                       priv->status = STATUS_READ;
 561 +                       enable_burst_irq(priv);
 562 +               }
 563 +               if (i_pro & I2C_P_IRQSS_TX_END) {
 564 +                       if (priv->status == STATUS_READ)
 565 +                               priv->status = STATUS_READ_END;
 566 +                       else {
 567 +                               disable_burst_irq(priv);
 568 +                               priv->status = STATUS_STOP;
 569 +                       }
 570 +               }
 571 +       }
 572 +
 573 +       i2c_w32(i_pro, p_irqsc);
 574 +}
 575 +
 576 +static irqreturn_t ltq_i2c_isr(int irq, void *dev_id)
 577 +{
 578 +       u32 i_raw, i_err = 0;
 579 +       struct ltq_i2c *priv = dev_id;
 580 +
 581 +       i_raw = i2c_r32(mis);
 582 +       pr_debug("i_raw 0x%08X\n", i_raw);
 583 +
 584 +       /* error interrupt */
 585 +       if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
 586 +               i_err = i2c_r32(err_irqss);
 587 +               pr_debug("i_err 0x%08X bus_stat 0x%04X\n",
 588 +                       i_err, i2c_r32(bus_stat));
 589 +
 590 +               /* tx fifo overflow (8) */
 591 +               if (i_err & I2C_ERR_IRQSS_TXF_OFL)
 592 +                       priv->msg_err |= LTQ_I2C_TX_OFL;
 593 +
 594 +               /* tx fifo underflow (4) */
 595 +               if (i_err & I2C_ERR_IRQSS_TXF_UFL)
 596 +                       priv->msg_err |= LTQ_I2C_TX_UFL;
 597 +
 598 +               /* rx fifo overflow (2) */
 599 +               if (i_err & I2C_ERR_IRQSS_RXF_OFL)
 600 +                       priv->msg_err |= LTQ_I2C_RX_OFL;
 601 +
 602 +               /* rx fifo underflow (1) */
 603 +               if (i_err & I2C_ERR_IRQSS_RXF_UFL)
 604 +                       priv->msg_err |= LTQ_I2C_RX_UFL;
 605 +
 606 +               i2c_w32(i_err, err_irqsc);
 607 +       }
 608 +
 609 +       /* protocol interrupt */
 610 +       if (i_raw & I2C_RIS_I2C_P_INT_INTOCC)
 611 +               ltq_i2c_isr_prot(priv);
 612 +
 613 +       if ((priv->msg_err) || (priv->status == STATUS_STOP))
 614 +               complete(&priv->cmd_complete);
 615 +
 616 +       return IRQ_HANDLED;
 617 +}
 618 +
 619 +static u32 ltq_i2c_functionality(struct i2c_adapter *adap)
 620 +{
 621 +       return  I2C_FUNC_I2C |
 622 +               I2C_FUNC_10BIT_ADDR |
 623 +               I2C_FUNC_SMBUS_EMUL;
 624 +}
 625 +
 626 +static struct i2c_algorithm ltq_i2c_algorithm = {
 627 +       .master_xfer    = ltq_i2c_xfer,
 628 +       .functionality  = ltq_i2c_functionality,
 629 +};
 630 +
 631 +static int __devinit ltq_i2c_probe(struct platform_device *pdev)
 632 +{
 633 +       struct device_node *node = pdev->dev.of_node;
 634 +       struct ltq_i2c *priv;
 635 +       struct i2c_adapter *adap;
 636 +       struct resource *mmres, irqres[4];
 637 +       int ret = 0;
 638 +
 639 +       dev_dbg(&pdev->dev, "probing\n");
 640 +
 641 +       mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 642 +       ret = of_irq_to_resource_table(node, irqres, 4);
 643 +       if (!mmres || (ret != 4)) {
 644 +               dev_err(&pdev->dev, "no resources\n");
 645 +               return -ENODEV;
 646 +       }
 647 +
 648 +       /* allocate private data */
 649 +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 650 +       if (!priv) {
 651 +               dev_err(&pdev->dev, "can't allocate private data\n");
 652 +               return -ENOMEM;
 653 +       }
 654 +
 655 +       adap = &priv->adap;
 656 +       i2c_set_adapdata(adap, priv);
 657 +       adap->owner = THIS_MODULE;
 658 +       adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 659 +       strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
 660 +       adap->algo = &ltq_i2c_algorithm;
 661 +
 662 +       if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) {
 663 +               dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n");
 664 +               priv->i2c_clock = 100000;
 665 +       }
 666 +
 667 +       init_completion(&priv->cmd_complete);
 668 +       mutex_init(&priv->mutex);
 669 +
 670 +       priv->membase = devm_request_and_ioremap(&pdev->dev, mmres);
 671 +       if (priv->membase == NULL)
 672 +               return -ENOMEM;
 673 +
 674 +       priv->dev = &pdev->dev;
 675 +       priv->irq_lb = irqres[0].start;
 676 +
 677 +       ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst,
 678 +               IRQF_DISABLED, "i2c lb", priv);
 679 +       if (ret) {
 680 +               dev_err(&pdev->dev, "can't get last burst IRQ %d\n",
 681 +                       irqres[0].start);
 682 +               return -ENODEV;
 683 +       }
 684 +
 685 +       ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst,
 686 +               IRQF_DISABLED, "i2c b", priv);
 687 +       if (ret) {
 688 +               dev_err(&pdev->dev, "can't get burst IRQ %d\n",
 689 +                       irqres[1].start);
 690 +               return -ENODEV;
 691 +       }
 692 +
 693 +       ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr,
 694 +               IRQF_DISABLED, "i2c err", priv);
 695 +       if (ret) {
 696 +               dev_err(&pdev->dev, "can't get error IRQ %d\n",
 697 +                       irqres[2].start);
 698 +               return -ENODEV;
 699 +       }
 700 +
 701 +       ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr,
 702 +               IRQF_DISABLED, "i2c p", priv);
 703 +       if (ret) {
 704 +               dev_err(&pdev->dev, "can't get protocol IRQ %d\n",
 705 +                       irqres[3].start);
 706 +               return -ENODEV;
 707 +       }
 708 +
 709 +       dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
 710 +       dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start,
 711 +               irqres[1].start, irqres[2].start, irqres[3].start);
 712 +
 713 +       priv->clk_gate = devm_clk_get(&pdev->dev, NULL);
 714 +       if (IS_ERR(priv->clk_gate)) {
 715 +               dev_err(&pdev->dev, "failed to get i2c clk\n");
 716 +               return -ENOENT;
 717 +       }
 718 +
 719 +       /* this is a static clock, which has no refcounting */
 720 +       priv->clk_input = clk_get_fpi();
 721 +       if (IS_ERR(priv->clk_input)) {
 722 +               dev_err(&pdev->dev, "failed to get fpi clk\n");
 723 +               return -ENOENT;
 724 +       }
 725 +
 726 +       clk_activate(priv->clk_gate);
 727 +
 728 +       /* add our adapter to the i2c stack */
 729 +       ret = i2c_add_numbered_adapter(adap);
 730 +       if (ret) {
 731 +               dev_err(&pdev->dev, "can't register I2C adapter\n");
 732 +               goto out;
 733 +       }
 734 +
 735 +       platform_set_drvdata(pdev, priv);
 736 +       i2c_set_adapdata(adap, priv);
 737 +
 738 +       /* print module version information */
 739 +       dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
 740 +               (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
 741 +               (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
 742 +
 743 +       /* initialize HW */
 744 +       ret = ltq_i2c_hw_init(adap);
 745 +       if (ret) {
 746 +               dev_err(&pdev->dev, "can't configure adapter\n");
 747 +               i2c_del_adapter(adap);
 748 +               platform_set_drvdata(pdev, NULL);
 749 +       } else {
 750 +               dev_info(&pdev->dev, "version %s\n", DRV_VERSION);
 751 +       }
 752 +
 753 +       of_i2c_register_devices(adap);
 754 +
 755 +out:
 756 +       /* if init failed, we need to deactivate the clock gate */
 757 +       if (ret)
 758 +               clk_deactivate(priv->clk_gate);
 759 +
 760 +       return ret;
 761 +}
 762 +
 763 +static int __devexit ltq_i2c_remove(struct platform_device *pdev)
 764 +{
 765 +       struct ltq_i2c *priv = platform_get_drvdata(pdev);
 766 +
 767 +       /* disable bus */
 768 +       i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 769 +
 770 +       /* power down the core */
 771 +       clk_deactivate(priv->clk_gate);
 772 +
 773 +       /* remove driver */
 774 +       i2c_del_adapter(&priv->adap);
 775 +       kfree(priv);
 776 +
 777 +       dev_dbg(&pdev->dev, "removed\n");
 778 +       platform_set_drvdata(pdev, NULL);
 779 +
 780 +       return 0;
 781 +}
 782 +static const struct of_device_id ltq_i2c_match[] = {
 783 +       { .compatible = "lantiq,lantiq-i2c" },
 784 +       {},
 785 +};
 786 +MODULE_DEVICE_TABLE(of, ltq_i2c_match);
 787 +
 788 +static struct platform_driver ltq_i2c_driver = {
 789 +       .probe  = ltq_i2c_probe,
 790 +       .remove = __devexit_p(ltq_i2c_remove),
 791 +       .driver = {
 792 +               .name   = DRV_NAME,
 793 +               .owner  = THIS_MODULE,
 794 +               .of_match_table = ltq_i2c_match,
 795 +       },
 796 +};
 797 +
 798 +module_platform_driver(ltq_i2c_driver);
 799 +
 800 +MODULE_DESCRIPTION("Lantiq I2C bus adapter");
 801 +MODULE_AUTHOR("Thomas Langer <thomas.langer@lantiq.com>");
 802 +MODULE_ALIAS("platform:" DRV_NAME);
 803 +MODULE_LICENSE("GPL");
 804 +MODULE_VERSION(DRV_VERSION);
 805 diff --git a/drivers/i2c/busses/i2c-lantiq.h b/drivers/i2c/busses/i2c-lantiq.h
 806 new file mode 100644
 807 index 0000000..7a86b89
 808 --- /dev/null
 809 +++ b/drivers/i2c/busses/i2c-lantiq.h
 810 @@ -0,0 +1,234 @@
 811 +#ifndef I2C_LANTIQ_H
 812 +#define I2C_LANTIQ_H
 813 +
 814 +/* I2C register structure */
 815 +struct lantiq_reg_i2c {
 816 +       /* I2C Kernel Clock Control Register */
 817 +       unsigned int clc; /* 0x00000000 */
 818 +       /* Reserved */
 819 +       unsigned int res_0; /* 0x00000004 */
 820 +       /* I2C Identification Register */
 821 +       unsigned int id; /* 0x00000008 */
 822 +       /* Reserved */
 823 +       unsigned int res_1; /* 0x0000000C */
 824 +       /*
 825 +        * I2C RUN Control Register
 826 +        * This register enables and disables the I2C peripheral. Before
 827 +        * enabling, the I2C has to be configured properly. After enabling
 828 +        * no configuration is possible
 829 +        */
 830 +       unsigned int run_ctrl; /* 0x00000010 */
 831 +       /*
 832 +        * I2C End Data Control Register
 833 +        * This register is used to either turn around the data transmission
 834 +        * direction or to address another slave without sending a stop
 835 +        * condition. Also the software can stop the slave-transmitter by
 836 +        * sending a not-accolade when working as master-receiver or even
 837 +        * stop data transmission immediately when operating as
 838 +        * master-transmitter. The writing to the bits of this control
 839 +        * register is only effective when in MASTER RECEIVES BYTES, MASTER
 840 +        * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state
 841 +        */
 842 +       unsigned int endd_ctrl; /* 0x00000014 */
 843 +       /*
 844 +        * I2C Fractional Divider Configuration Register
 845 +        * These register is used to program the fractional divider of the I2C
 846 +        * bus. Before the peripheral is switched on by setting the RUN-bit the
 847 +        * two (fixed) values for the two operating frequencies are programmed
 848 +        * into these (configuration) registers. The Register FDIV_HIGH_CFG has
 849 +        * the same layout as I2C_FDIV_CFG.
 850 +        */
 851 +       unsigned int fdiv_cfg; /* 0x00000018 */
 852 +       /*
 853 +        * I2C Fractional Divider (highspeed mode) Configuration Register
 854 +        * These register is used to program the fractional divider of the I2C
 855 +        * bus. Before the peripheral is switched on by setting the RUN-bit the
 856 +        * two (fixed) values for the two operating frequencies are programmed
 857 +        * into these (configuration) registers. The Register FDIV_CFG has the
 858 +        * same layout as I2C_FDIV_CFG.
 859 +        */
 860 +       unsigned int fdiv_high_cfg; /* 0x0000001C */
 861 +       /* I2C Address Configuration Register */
 862 +       unsigned int addr_cfg; /* 0x00000020 */
 863 +       /* I2C Bus Status Register
 864 +        * This register gives a status information of the I2C. This additional
 865 +        * information can be used by the software to start proper actions.
 866 +        */
 867 +       unsigned int bus_stat; /* 0x00000024 */
 868 +       /* I2C FIFO Configuration Register */
 869 +       unsigned int fifo_cfg; /* 0x00000028 */
 870 +       /* I2C Maximum Received Packet Size Register */
 871 +       unsigned int mrps_ctrl; /* 0x0000002C */
 872 +       /* I2C Received Packet Size Status Register */
 873 +       unsigned int rps_stat; /* 0x00000030 */
 874 +       /* I2C Transmit Packet Size Register */
 875 +       unsigned int tps_ctrl; /* 0x00000034 */
 876 +       /* I2C Filled FIFO Stages Status Register */
 877 +       unsigned int ffs_stat; /* 0x00000038 */
 878 +       /* Reserved */
 879 +       unsigned int res_2; /* 0x0000003C */
 880 +       /* I2C Timing Configuration Register */
 881 +       unsigned int tim_cfg; /* 0x00000040 */
 882 +       /* Reserved */
 883 +       unsigned int res_3[7]; /* 0x00000044 */
 884 +       /* I2C Error Interrupt Request Source Mask Register */
 885 +       unsigned int err_irqsm; /* 0x00000060 */
 886 +       /* I2C Error Interrupt Request Source Status Register */
 887 +       unsigned int err_irqss; /* 0x00000064 */
 888 +       /* I2C Error Interrupt Request Source Clear Register */
 889 +       unsigned int err_irqsc; /* 0x00000068 */
 890 +       /* Reserved */
 891 +       unsigned int res_4; /* 0x0000006C */
 892 +       /* I2C Protocol Interrupt Request Source Mask Register */
 893 +       unsigned int p_irqsm; /* 0x00000070 */
 894 +       /* I2C Protocol Interrupt Request Source Status Register */
 895 +       unsigned int p_irqss; /* 0x00000074 */
 896 +       /* I2C Protocol Interrupt Request Source Clear Register */
 897 +       unsigned int p_irqsc; /* 0x00000078 */
 898 +       /* Reserved */
 899 +       unsigned int res_5; /* 0x0000007C */
 900 +       /* I2C Raw Interrupt Status Register */
 901 +       unsigned int ris; /* 0x00000080 */
 902 +       /* I2C Interrupt Mask Control Register */
 903 +       unsigned int imsc; /* 0x00000084 */
 904 +       /* I2C Masked Interrupt Status Register */
 905 +       unsigned int mis; /* 0x00000088 */
 906 +       /* I2C Interrupt Clear Register */
 907 +       unsigned int icr; /* 0x0000008C */
 908 +       /* I2C Interrupt Set Register */
 909 +       unsigned int isr; /* 0x00000090 */
 910 +       /* I2C DMA Enable Register */
 911 +       unsigned int dmae; /* 0x00000094 */
 912 +       /* Reserved */
 913 +       unsigned int res_6[8154]; /* 0x00000098 */
 914 +       /* I2C Transmit Data Register */
 915 +       unsigned int txd; /* 0x00008000 */
 916 +       /* Reserved */
 917 +       unsigned int res_7[4095]; /* 0x00008004 */
 918 +       /* I2C Receive Data Register */
 919 +       unsigned int rxd; /* 0x0000C000 */
 920 +       /* Reserved */
 921 +       unsigned int res_8[4095]; /* 0x0000C004 */
 922 +};
 923 +
 924 +/*
 925 + * Clock Divider for Normal Run Mode
 926 + * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long
 927 + * as the new divider value RMC is not valid, the register returns 0x0000 00xx
 928 + * on reading.
 929 + */
 930 +#define I2C_CLC_RMC_MASK 0x0000FF00
 931 +/* field offset */
 932 +#define I2C_CLC_RMC_OFFSET 8
 933 +
 934 +/* Fields of "I2C Identification Register" */
 935 +/* Module ID */
 936 +#define I2C_ID_ID_MASK 0x0000FF00
 937 +/* field offset */
 938 +#define I2C_ID_ID_OFFSET 8
 939 +/* Revision */
 940 +#define I2C_ID_REV_MASK 0x000000FF
 941 +/* field offset */
 942 +#define I2C_ID_REV_OFFSET 0
 943 +
 944 +/* Fields of "I2C Interrupt Mask Control Register" */
 945 +/* Enable */
 946 +#define I2C_IMSC_BREQ_INT_EN 0x00000008
 947 +/* Enable */
 948 +#define I2C_IMSC_LBREQ_INT_EN 0x00000004
 949 +
 950 +/* Fields of "I2C Fractional Divider Configuration Register" */
 951 +/* field offset */
 952 +#define I2C_FDIV_CFG_INC_OFFSET 16
 953 +
 954 +/* Fields of "I2C Interrupt Mask Control Register" */
 955 +/* Enable */
 956 +#define I2C_IMSC_I2C_P_INT_EN 0x00000020
 957 +/* Enable */
 958 +#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
 959 +
 960 +/* Fields of "I2C Error Interrupt Request Source Status Register" */
 961 +/* TXF_OFL */
 962 +#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
 963 +/* TXF_UFL */
 964 +#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
 965 +/* RXF_OFL */
 966 +#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
 967 +/* RXF_UFL */
 968 +#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
 969 +
 970 +/* Fields of "I2C Raw Interrupt Status Register" */
 971 +/* Read: Interrupt occurred. */
 972 +#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
 973 +/* Read: Interrupt occurred. */
 974 +#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
 975 +
 976 +/* Fields of "I2C FIFO Configuration Register" */
 977 +/* TX FIFO Flow Control */
 978 +#define I2C_FIFO_CFG_TXFC 0x00020000
 979 +/* RX FIFO Flow Control */
 980 +#define I2C_FIFO_CFG_RXFC 0x00010000
 981 +/* Word aligned (character alignment of four characters) */
 982 +#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
 983 +/* Word aligned (character alignment of four characters) */
 984 +#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
 985 +/* 1 word */
 986 +#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
 987 +
 988 +/* Fields of "I2C FIFO Configuration Register" */
 989 +/* 1 word */
 990 +#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
 991 +/* Stop on Packet End Enable */
 992 +#define I2C_ADDR_CFG_SOPE_EN 0x00200000
 993 +/* Stop on Not Acknowledge Enable */
 994 +#define I2C_ADDR_CFG_SONA_EN 0x00100000
 995 +/* Enable */
 996 +#define I2C_ADDR_CFG_MnS_EN 0x00080000
 997 +
 998 +/* Fields of "I2C Interrupt Clear Register" */
 999 +/* Clear */
1000 +#define I2C_ICR_BREQ_INT_CLR 0x00000008
1001 +/* Clear */
1002 +#define I2C_ICR_LBREQ_INT_CLR 0x00000004
1003 +
1004 +/* Fields of "I2C Fractional Divider Configuration Register" */
1005 +/* field offset */
1006 +#define I2C_FDIV_CFG_DEC_OFFSET 0
1007 +
1008 +/* Fields of "I2C Bus Status Register" */
1009 +/* Bus Status */
1010 +#define I2C_BUS_STAT_BS_MASK 0x00000003
1011 +/* Read from I2C Bus. */
1012 +#define I2C_BUS_STAT_RNW_READ 0x00000004
1013 +/* I2C Bus is free. */
1014 +#define I2C_BUS_STAT_BS_FREE 0x00000000
1015 +/*
1016 + * The device is working as master and has claimed the control on the
1017 + * I2C-bus (busy master).
1018 + */
1019 +#define I2C_BUS_STAT_BS_BM 0x00000002
1020 +
1021 +/* Fields of "I2C RUN Control Register" */
1022 +/* Enable */
1023 +#define I2C_RUN_CTRL_RUN_EN 0x00000001
1024 +
1025 +/* Fields of "I2C End Data Control Register" */
1026 +/*
1027 + * Set End of Transmission
1028 + * Note:Do not write '1' to this bit when bus is free. This will cause an
1029 + * abort after the first byte when a new transfer is started.
1030 + */
1031 +#define I2C_ENDD_CTRL_SETEND 0x00000002
1032 +
1033 +/* Fields of "I2C Protocol Interrupt Request Source Status Register" */
1034 +/* NACK */
1035 +#define I2C_P_IRQSS_NACK 0x00000010
1036 +/* AL */
1037 +#define I2C_P_IRQSS_AL 0x00000008
1038 +/* RX */
1039 +#define I2C_P_IRQSS_RX 0x00000040
1040 +/* TX_END */
1041 +#define I2C_P_IRQSS_TX_END 0x00000020
1042 +
1043 +
1044 +#endif /* I2C_LANTIQ_H */
1045 --
1046 1.7.10.4
1047