kernel: update 3.9 to 3.9.11
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.9 / 0010-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch
1 From fd69e82feee0966fd61374ea76d6ff36ce42e51c Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 29 Jun 2013 19:42:16 +0200
4 Subject: [PATCH 10/22] NET: MIPS: lantiq: update etop driver for devicetree
5
6 ---
7 drivers/net/ethernet/lantiq_etop.c | 500 +++++++++++++++++++++++++-----------
8 1 file changed, 354 insertions(+), 146 deletions(-)
9
10 --- a/drivers/net/ethernet/lantiq_etop.c
11 +++ b/drivers/net/ethernet/lantiq_etop.c
12 @@ -12,7 +12,7 @@
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
17 + * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
18 */
19
20 #include <linux/kernel.h>
21 @@ -36,6 +36,10 @@
22 #include <linux/io.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/module.h>
25 +#include <linux/clk.h>
26 +#include <linux/of_net.h>
27 +#include <linux/of_irq.h>
28 +#include <linux/of_platform.h>
29
30 #include <asm/checksum.h>
31
32 @@ -71,25 +75,61 @@
33 #define ETOP_MII_REVERSE 0xe
34 #define ETOP_PLEN_UNDER 0x40
35 #define ETOP_CGEN 0x800
36 +#define ETOP_CFG_MII0 0x01
37
38 -/* use 2 static channels for TX/RX */
39 -#define LTQ_ETOP_TX_CHANNEL 1
40 -#define LTQ_ETOP_RX_CHANNEL 6
41 -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
42 -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
43 +#define LTQ_GBIT_MDIO_CTL 0xCC
44 +#define LTQ_GBIT_MDIO_DATA 0xd0
45 +#define LTQ_GBIT_GCTL0 0x68
46 +#define LTQ_GBIT_PMAC_HD_CTL 0x8c
47 +#define LTQ_GBIT_P0_CTL 0x4
48 +#define LTQ_GBIT_PMAC_RX_IPG 0xa8
49 +#define LTQ_GBIT_RGMII_CTL 0x78
50 +
51 +#define PMAC_HD_CTL_AS (1 << 19)
52 +#define PMAC_HD_CTL_RXSH (1 << 22)
53 +
54 +/* Switch Enable (0=disable, 1=enable) */
55 +#define GCTL0_SE 0x80000000
56 +/* Disable MDIO auto polling (0=disable, 1=enable) */
57 +#define PX_CTL_DMDIO 0x00400000
58 +
59 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
60 +#define MDC_CLOCK_MASK 0xff000000
61 +#define MDC_CLOCK_OFFSET 24
62 +
63 +/* register information for the gbit's MDIO bus */
64 +#define MDIO_XR9_REQUEST 0x00008000
65 +#define MDIO_XR9_READ 0x00000800
66 +#define MDIO_XR9_WRITE 0x00000400
67 +#define MDIO_XR9_REG_MASK 0x1f
68 +#define MDIO_XR9_ADDR_MASK 0x1f
69 +#define MDIO_XR9_RD_MASK 0xffff
70 +#define MDIO_XR9_REG_OFFSET 0
71 +#define MDIO_XR9_ADDR_OFFSET 5
72 +#define MDIO_XR9_WR_OFFSET 16
73
74 +#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
75 + (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
76 +
77 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
78 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
79 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
80 #define ltq_etop_w32_mask(x, y, z) \
81 ltq_w32_mask(x, y, ltq_etop_membase + (z))
82
83 -#define DRV_VERSION "1.0"
84 +#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
85 +#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
86 +#define ltq_gbit_w32_mask(x, y, z) \
87 + ltq_w32_mask(x, y, ltq_gbit_membase + (z))
88 +
89 +#define DRV_VERSION "1.2"
90
91 static void __iomem *ltq_etop_membase;
92 +static void __iomem *ltq_gbit_membase;
93
94 struct ltq_etop_chan {
95 - int idx;
96 int tx_free;
97 + int irq;
98 struct net_device *netdev;
99 struct napi_struct napi;
100 struct ltq_dma_channel dma;
101 @@ -99,22 +139,35 @@ struct ltq_etop_chan {
102 struct ltq_etop_priv {
103 struct net_device *netdev;
104 struct platform_device *pdev;
105 - struct ltq_eth_data *pldata;
106 struct resource *res;
107
108 struct mii_bus *mii_bus;
109 struct phy_device *phydev;
110
111 - struct ltq_etop_chan ch[MAX_DMA_CHAN];
112 - int tx_free[MAX_DMA_CHAN >> 1];
113 + struct ltq_etop_chan txch;
114 + struct ltq_etop_chan rxch;
115 +
116 + int tx_irq;
117 + int rx_irq;
118 +
119 + const void *mac;
120 + int mii_mode;
121
122 spinlock_t lock;
123 +
124 + struct clk *clk_ppe;
125 + struct clk *clk_switch;
126 + struct clk *clk_ephy;
127 + struct clk *clk_ephycgu;
128 };
129
130 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
131 + int phy_reg, u16 phy_data);
132 +
133 static int
134 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
135 {
136 - ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
137 + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
138 if (!ch->skb[ch->dma.desc])
139 return -ENOMEM;
140 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
141 @@ -149,8 +202,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
142 spin_unlock_irqrestore(&priv->lock, flags);
143
144 skb_put(skb, len);
145 + skb->dev = ch->netdev;
146 skb->protocol = eth_type_trans(skb, ch->netdev);
147 netif_receive_skb(skb);
148 + ch->netdev->stats.rx_packets++;
149 + ch->netdev->stats.rx_bytes += len;
150 }
151
152 static int
153 @@ -158,8 +214,10 @@ ltq_etop_poll_rx(struct napi_struct *nap
154 {
155 struct ltq_etop_chan *ch = container_of(napi,
156 struct ltq_etop_chan, napi);
157 + struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
158 int rx = 0;
159 int complete = 0;
160 + unsigned long flags;
161
162 while ((rx < budget) && !complete) {
163 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
164 @@ -173,7 +231,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
165 }
166 if (complete || !rx) {
167 napi_complete(&ch->napi);
168 + spin_lock_irqsave(&priv->lock, flags);
169 ltq_dma_ack_irq(&ch->dma);
170 + spin_unlock_irqrestore(&priv->lock, flags);
171 }
172 return rx;
173 }
174 @@ -185,12 +245,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
175 container_of(napi, struct ltq_etop_chan, napi);
176 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
177 struct netdev_queue *txq =
178 - netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
179 + netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
180 unsigned long flags;
181
182 spin_lock_irqsave(&priv->lock, flags);
183 while ((ch->dma.desc_base[ch->tx_free].ctl &
184 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
185 + ch->netdev->stats.tx_packets++;
186 + ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
187 dev_kfree_skb_any(ch->skb[ch->tx_free]);
188 ch->skb[ch->tx_free] = NULL;
189 memset(&ch->dma.desc_base[ch->tx_free], 0,
190 @@ -203,7 +265,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
191 if (netif_tx_queue_stopped(txq))
192 netif_tx_start_queue(txq);
193 napi_complete(&ch->napi);
194 + spin_lock_irqsave(&priv->lock, flags);
195 ltq_dma_ack_irq(&ch->dma);
196 + spin_unlock_irqrestore(&priv->lock, flags);
197 return 1;
198 }
199
200 @@ -211,9 +275,10 @@ static irqreturn_t
201 ltq_etop_dma_irq(int irq, void *_priv)
202 {
203 struct ltq_etop_priv *priv = _priv;
204 - int ch = irq - LTQ_DMA_CH0_INT;
205 -
206 - napi_schedule(&priv->ch[ch].napi);
207 + if (irq == priv->txch.dma.irq)
208 + napi_schedule(&priv->txch.napi);
209 + else
210 + napi_schedule(&priv->rxch.napi);
211 return IRQ_HANDLED;
212 }
213
214 @@ -225,7 +290,7 @@ ltq_etop_free_channel(struct net_device
215 ltq_dma_free(&ch->dma);
216 if (ch->dma.irq)
217 free_irq(ch->dma.irq, priv);
218 - if (IS_RX(ch->idx)) {
219 + if (ch == &priv->txch) {
220 int desc;
221 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
222 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
223 @@ -236,23 +301,62 @@ static void
224 ltq_etop_hw_exit(struct net_device *dev)
225 {
226 struct ltq_etop_priv *priv = netdev_priv(dev);
227 - int i;
228
229 - ltq_pmu_disable(PMU_PPE);
230 - for (i = 0; i < MAX_DMA_CHAN; i++)
231 - if (IS_TX(i) || IS_RX(i))
232 - ltq_etop_free_channel(dev, &priv->ch[i]);
233 + clk_disable(priv->clk_ppe);
234 +
235 + if (of_machine_is_compatible("lantiq,ar9"))
236 + clk_disable(priv->clk_switch);
237 +
238 + if (of_machine_is_compatible("lantiq,ase")) {
239 + clk_disable(priv->clk_ephy);
240 + clk_disable(priv->clk_ephycgu);
241 + }
242 +
243 + ltq_etop_free_channel(dev, &priv->txch);
244 + ltq_etop_free_channel(dev, &priv->rxch);
245 +}
246 +
247 +static void
248 +ltq_etop_gbit_init(struct net_device *dev)
249 +{
250 + struct ltq_etop_priv *priv = netdev_priv(dev);
251 +
252 + clk_enable(priv->clk_switch);
253 +
254 + /* enable gbit port0 on the SoC */
255 + ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
256 +
257 + ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
258 + /* disable MDIO auto polling mode */
259 + ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
260 + /* set 1522 packet size */
261 + ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
262 + /* disable pmac & dmac headers */
263 + ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
264 + LTQ_GBIT_PMAC_HD_CTL);
265 + /* Due to traffic halt when burst length 8,
266 + replace default IPG value with 0x3B */
267 + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
268 + /* set mdc clock to 2.5 MHz */
269 + ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
270 + LTQ_GBIT_RGMII_CTL);
271 }
272
273 static int
274 ltq_etop_hw_init(struct net_device *dev)
275 {
276 struct ltq_etop_priv *priv = netdev_priv(dev);
277 - int i;
278 + int mii_mode = priv->mii_mode;
279
280 - ltq_pmu_enable(PMU_PPE);
281 + clk_enable(priv->clk_ppe);
282
283 - switch (priv->pldata->mii_mode) {
284 + if (of_machine_is_compatible("lantiq,ar9")) {
285 + ltq_etop_gbit_init(dev);
286 + /* force the etops link to the gbit to MII */
287 + mii_mode = PHY_INTERFACE_MODE_MII;
288 + }
289 +
290 + switch (mii_mode) {
291 case PHY_INTERFACE_MODE_RMII:
292 ltq_etop_w32_mask(ETOP_MII_MASK,
293 ETOP_MII_REVERSE, LTQ_ETOP_CFG);
294 @@ -264,39 +368,68 @@ ltq_etop_hw_init(struct net_device *dev)
295 break;
296
297 default:
298 + if (of_machine_is_compatible("lantiq,ase")) {
299 + clk_enable(priv->clk_ephy);
300 + /* disable external MII */
301 + ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
302 + /* enable clock for internal PHY */
303 + clk_enable(priv->clk_ephycgu);
304 + /* we need to write this magic to the internal phy to
305 + make it work */
306 + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
307 + pr_info("Selected EPHY mode\n");
308 + break;
309 + }
310 netdev_err(dev, "unknown mii mode %d\n",
311 - priv->pldata->mii_mode);
312 + mii_mode);
313 return -ENOTSUPP;
314 }
315
316 /* enable crc generation */
317 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
318
319 + return 0;
320 +}
321 +
322 +static int
323 +ltq_etop_dma_init(struct net_device *dev)
324 +{
325 + struct ltq_etop_priv *priv = netdev_priv(dev);
326 + int tx = priv->tx_irq - LTQ_DMA_ETOP;
327 + int rx = priv->rx_irq - LTQ_DMA_ETOP;
328 + int err;
329 +
330 ltq_dma_init_port(DMA_PORT_ETOP);
331
332 - for (i = 0; i < MAX_DMA_CHAN; i++) {
333 - int irq = LTQ_DMA_CH0_INT + i;
334 - struct ltq_etop_chan *ch = &priv->ch[i];
335 -
336 - ch->idx = ch->dma.nr = i;
337 -
338 - if (IS_TX(i)) {
339 - ltq_dma_alloc_tx(&ch->dma);
340 - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
341 - "etop_tx", priv);
342 - } else if (IS_RX(i)) {
343 - ltq_dma_alloc_rx(&ch->dma);
344 - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
345 - ch->dma.desc++)
346 - if (ltq_etop_alloc_skb(ch))
347 - return -ENOMEM;
348 - ch->dma.desc = 0;
349 - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
350 - "etop_rx", priv);
351 + priv->txch.dma.nr = tx;
352 + ltq_dma_alloc_tx(&priv->txch.dma);
353 + err = request_irq(priv->tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
354 + "eth_tx", priv);
355 + if (err) {
356 + netdev_err(dev, "failed to allocate tx irq\n");
357 + goto err_out;
358 + }
359 + priv->txch.dma.irq = priv->tx_irq;
360 +
361 + priv->rxch.dma.nr = rx;
362 + ltq_dma_alloc_rx(&priv->rxch.dma);
363 + for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
364 + priv->rxch.dma.desc++) {
365 + if (ltq_etop_alloc_skb(&priv->rxch)) {
366 + netdev_err(dev, "failed to allocate skbs\n");
367 + err = -ENOMEM;
368 + goto err_out;
369 }
370 - ch->dma.irq = irq;
371 }
372 - return 0;
373 + priv->rxch.dma.desc = 0;
374 + err = request_irq(priv->rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
375 + "eth_rx", priv);
376 + if (err)
377 + netdev_err(dev, "failed to allocate rx irq\n");
378 + else
379 + priv->rxch.dma.irq = priv->rx_irq;
380 +err_out:
381 + return err;
382 }
383
384 static void
385 @@ -312,7 +445,10 @@ ltq_etop_get_settings(struct net_device
386 {
387 struct ltq_etop_priv *priv = netdev_priv(dev);
388
389 - return phy_ethtool_gset(priv->phydev, cmd);
390 + if (priv->phydev)
391 + return phy_ethtool_gset(priv->phydev, cmd);
392 + else
393 + return 0;
394 }
395
396 static int
397 @@ -320,7 +456,10 @@ ltq_etop_set_settings(struct net_device
398 {
399 struct ltq_etop_priv *priv = netdev_priv(dev);
400
401 - return phy_ethtool_sset(priv->phydev, cmd);
402 + if (priv->phydev)
403 + return phy_ethtool_sset(priv->phydev, cmd);
404 + else
405 + return 0;
406 }
407
408 static int
409 @@ -328,7 +467,10 @@ ltq_etop_nway_reset(struct net_device *d
410 {
411 struct ltq_etop_priv *priv = netdev_priv(dev);
412
413 - return phy_start_aneg(priv->phydev);
414 + if (priv->phydev)
415 + return phy_start_aneg(priv->phydev);
416 + else
417 + return 0;
418 }
419
420 static const struct ethtool_ops ltq_etop_ethtool_ops = {
421 @@ -339,6 +481,39 @@ static const struct ethtool_ops ltq_etop
422 };
423
424 static int
425 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
426 + int phy_reg, u16 phy_data)
427 +{
428 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
429 + (phy_data << MDIO_XR9_WR_OFFSET) |
430 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
431 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
432 +
433 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
434 + ;
435 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
436 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
437 + ;
438 + return 0;
439 +}
440 +
441 +static int
442 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
443 +{
444 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
445 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
446 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
447 +
448 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
449 + ;
450 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
451 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
452 + ;
453 + val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
454 + return val;
455 +}
456 +
457 +static int
458 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
459 {
460 u32 val = MDIO_REQUEST |
461 @@ -379,14 +554,18 @@ ltq_etop_mdio_probe(struct net_device *d
462 {
463 struct ltq_etop_priv *priv = netdev_priv(dev);
464 struct phy_device *phydev = NULL;
465 - int phy_addr;
466 + u32 phy_supported = (SUPPORTED_10baseT_Half
467 + | SUPPORTED_10baseT_Full
468 + | SUPPORTED_100baseT_Half
469 + | SUPPORTED_100baseT_Full
470 + | SUPPORTED_Autoneg
471 + | SUPPORTED_MII
472 + | SUPPORTED_TP);
473
474 - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
475 - if (priv->mii_bus->phy_map[phy_addr]) {
476 - phydev = priv->mii_bus->phy_map[phy_addr];
477 - break;
478 - }
479 - }
480 + if (of_machine_is_compatible("lantiq,ase"))
481 + phydev = priv->mii_bus->phy_map[8];
482 + else
483 + phydev = priv->mii_bus->phy_map[0];
484
485 if (!phydev) {
486 netdev_err(dev, "no PHY found\n");
487 @@ -394,21 +573,18 @@ ltq_etop_mdio_probe(struct net_device *d
488 }
489
490 phydev = phy_connect(dev, dev_name(&phydev->dev),
491 - &ltq_etop_mdio_link, priv->pldata->mii_mode);
492 + &ltq_etop_mdio_link, priv->mii_mode);
493
494 if (IS_ERR(phydev)) {
495 netdev_err(dev, "Could not attach to PHY\n");
496 return PTR_ERR(phydev);
497 }
498
499 - phydev->supported &= (SUPPORTED_10baseT_Half
500 - | SUPPORTED_10baseT_Full
501 - | SUPPORTED_100baseT_Half
502 - | SUPPORTED_100baseT_Full
503 - | SUPPORTED_Autoneg
504 - | SUPPORTED_MII
505 - | SUPPORTED_TP);
506 + if (of_machine_is_compatible("lantiq,ar9"))
507 + phy_supported |= SUPPORTED_1000baseT_Half
508 + | SUPPORTED_1000baseT_Full;
509
510 + phydev->supported &= phy_supported;
511 phydev->advertising = phydev->supported;
512 priv->phydev = phydev;
513 pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
514 @@ -433,8 +609,13 @@ ltq_etop_mdio_init(struct net_device *de
515 }
516
517 priv->mii_bus->priv = dev;
518 - priv->mii_bus->read = ltq_etop_mdio_rd;
519 - priv->mii_bus->write = ltq_etop_mdio_wr;
520 + if (of_machine_is_compatible("lantiq,ar9")) {
521 + priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
522 + priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
523 + } else {
524 + priv->mii_bus->read = ltq_etop_mdio_rd;
525 + priv->mii_bus->write = ltq_etop_mdio_wr;
526 + }
527 priv->mii_bus->name = "ltq_mii";
528 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
529 priv->pdev->name, priv->pdev->id);
530 @@ -483,17 +664,19 @@ static int
531 ltq_etop_open(struct net_device *dev)
532 {
533 struct ltq_etop_priv *priv = netdev_priv(dev);
534 - int i;
535 + unsigned long flags;
536
537 - for (i = 0; i < MAX_DMA_CHAN; i++) {
538 - struct ltq_etop_chan *ch = &priv->ch[i];
539 + napi_enable(&priv->txch.napi);
540 + napi_enable(&priv->rxch.napi);
541 +
542 + spin_lock_irqsave(&priv->lock, flags);
543 + ltq_dma_open(&priv->txch.dma);
544 + ltq_dma_open(&priv->rxch.dma);
545 + spin_unlock_irqrestore(&priv->lock, flags);
546 +
547 + if (priv->phydev)
548 + phy_start(priv->phydev);
549
550 - if (!IS_TX(i) && (!IS_RX(i)))
551 - continue;
552 - ltq_dma_open(&ch->dma);
553 - napi_enable(&ch->napi);
554 - }
555 - phy_start(priv->phydev);
556 netif_tx_start_all_queues(dev);
557 return 0;
558 }
559 @@ -502,18 +685,19 @@ static int
560 ltq_etop_stop(struct net_device *dev)
561 {
562 struct ltq_etop_priv *priv = netdev_priv(dev);
563 - int i;
564 + unsigned long flags;
565
566 netif_tx_stop_all_queues(dev);
567 - phy_stop(priv->phydev);
568 - for (i = 0; i < MAX_DMA_CHAN; i++) {
569 - struct ltq_etop_chan *ch = &priv->ch[i];
570 -
571 - if (!IS_RX(i) && !IS_TX(i))
572 - continue;
573 - napi_disable(&ch->napi);
574 - ltq_dma_close(&ch->dma);
575 - }
576 + if (priv->phydev)
577 + phy_stop(priv->phydev);
578 + napi_disable(&priv->txch.napi);
579 + napi_disable(&priv->rxch.napi);
580 +
581 + spin_lock_irqsave(&priv->lock, flags);
582 + ltq_dma_close(&priv->txch.dma);
583 + ltq_dma_close(&priv->rxch.dma);
584 + spin_unlock_irqrestore(&priv->lock, flags);
585 +
586 return 0;
587 }
588
589 @@ -523,16 +707,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
590 int queue = skb_get_queue_mapping(skb);
591 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
592 struct ltq_etop_priv *priv = netdev_priv(dev);
593 - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
594 - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
595 - int len;
596 + struct ltq_dma_desc *desc =
597 + &priv->txch.dma.desc_base[priv->txch.dma.desc];
598 unsigned long flags;
599 u32 byte_offset;
600 + int len;
601
602 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
603
604 - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
605 - dev_kfree_skb_any(skb);
606 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
607 + priv->txch.skb[priv->txch.dma.desc]) {
608 netdev_err(dev, "tx ring full\n");
609 netif_tx_stop_queue(txq);
610 return NETDEV_TX_BUSY;
611 @@ -540,7 +724,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
612
613 /* dma needs to start on a 16 byte aligned address */
614 byte_offset = CPHYSADDR(skb->data) % 16;
615 - ch->skb[ch->dma.desc] = skb;
616 + priv->txch.skb[priv->txch.dma.desc] = skb;
617
618 dev->trans_start = jiffies;
619
620 @@ -550,11 +734,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
621 wmb();
622 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
623 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
624 - ch->dma.desc++;
625 - ch->dma.desc %= LTQ_DESC_NUM;
626 + priv->txch.dma.desc++;
627 + priv->txch.dma.desc %= LTQ_DESC_NUM;
628 spin_unlock_irqrestore(&priv->lock, flags);
629
630 - if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
631 + if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
632 netif_tx_stop_queue(txq);
633
634 return NETDEV_TX_OK;
635 @@ -633,34 +817,33 @@ ltq_etop_init(struct net_device *dev)
636 struct ltq_etop_priv *priv = netdev_priv(dev);
637 struct sockaddr mac;
638 int err;
639 - bool random_mac = false;
640
641 ether_setup(dev);
642 dev->watchdog_timeo = 10 * HZ;
643 err = ltq_etop_hw_init(dev);
644 if (err)
645 goto err_hw;
646 + err = ltq_etop_dma_init(dev);
647 + if (err)
648 + goto err_hw;
649 +
650 ltq_etop_change_mtu(dev, 1500);
651
652 - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
653 + if (priv->mac)
654 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
655 if (!is_valid_ether_addr(mac.sa_data)) {
656 pr_warn("etop: invalid MAC, using random\n");
657 - eth_random_addr(mac.sa_data);
658 - random_mac = true;
659 + random_ether_addr(mac.sa_data);
660 }
661
662 err = ltq_etop_set_mac_address(dev, &mac);
663 if (err)
664 goto err_netdev;
665 -
666 - /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
667 - if (random_mac)
668 - dev->addr_assign_type = NET_ADDR_RANDOM;
669 -
670 ltq_etop_set_multicast_list(dev);
671 - err = ltq_etop_mdio_init(dev);
672 - if (err)
673 - goto err_netdev;
674 + if (!ltq_etop_mdio_init(dev))
675 + dev->ethtool_ops = &ltq_etop_ethtool_ops;
676 + else
677 + pr_warn("etop: mdio probe failed\n");;
678 return 0;
679
680 err_netdev:
681 @@ -680,6 +863,9 @@ ltq_etop_tx_timeout(struct net_device *d
682 err = ltq_etop_hw_init(dev);
683 if (err)
684 goto err_hw;
685 + err = ltq_etop_dma_init(dev);
686 + if (err)
687 + goto err_hw;
688 dev->trans_start = jiffies;
689 netif_wake_queue(dev);
690 return;
691 @@ -703,14 +889,18 @@ static const struct net_device_ops ltq_e
692 .ndo_tx_timeout = ltq_etop_tx_timeout,
693 };
694
695 -static int __init
696 -ltq_etop_probe(struct platform_device *pdev)
697 +static int ltq_etop_probe(struct platform_device *pdev)
698 {
699 struct net_device *dev;
700 struct ltq_etop_priv *priv;
701 - struct resource *res;
702 + struct resource *res, *gbit_res, irqres[2];
703 int err;
704 - int i;
705 +
706 + err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
707 + if (err != 2) {
708 + dev_err(&pdev->dev, "failed to get etop irqs\n");
709 + return -EINVAL;
710 + }
711
712 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
713 if (!res) {
714 @@ -736,30 +926,60 @@ ltq_etop_probe(struct platform_device *p
715 goto err_out;
716 }
717
718 - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
719 - if (!dev) {
720 - err = -ENOMEM;
721 - goto err_out;
722 + if (of_machine_is_compatible("lantiq,ar9")) {
723 + gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
724 + if (!gbit_res) {
725 + dev_err(&pdev->dev, "failed to get gbit resource\n");
726 + err = -ENOENT;
727 + goto err_out;
728 + }
729 + ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
730 + gbit_res->start, resource_size(gbit_res));
731 + if (!ltq_gbit_membase) {
732 + dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
733 + pdev->id);
734 + err = -ENOMEM;
735 + goto err_out;
736 + }
737 }
738 +
739 + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
740 strcpy(dev->name, "eth%d");
741 dev->netdev_ops = &ltq_eth_netdev_ops;
742 - dev->ethtool_ops = &ltq_etop_ethtool_ops;
743 priv = netdev_priv(dev);
744 priv->res = res;
745 priv->pdev = pdev;
746 - priv->pldata = dev_get_platdata(&pdev->dev);
747 priv->netdev = dev;
748 + priv->tx_irq = irqres[0].start;
749 + priv->rx_irq = irqres[1].start;
750 + priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
751 + priv->mac = ltq_get_eth_mac();
752 + if (!priv->mac)
753 + priv->mac = of_get_mac_address(pdev->dev.of_node);
754 +
755 + priv->clk_ppe = clk_get(&pdev->dev, NULL);
756 + if (IS_ERR(priv->clk_ppe))
757 + return PTR_ERR(priv->clk_ppe);
758 + if (of_machine_is_compatible("lantiq,ar9")) {
759 + priv->clk_switch = clk_get(&pdev->dev, "switch");
760 + if (IS_ERR(priv->clk_switch))
761 + return PTR_ERR(priv->clk_switch);
762 + }
763 + if (of_machine_is_compatible("lantiq,ase")) {
764 + priv->clk_ephy = clk_get(&pdev->dev, "ephy");
765 + if (IS_ERR(priv->clk_ephy))
766 + return PTR_ERR(priv->clk_ephy);
767 + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
768 + if (IS_ERR(priv->clk_ephycgu))
769 + return PTR_ERR(priv->clk_ephycgu);
770 + }
771 +
772 spin_lock_init(&priv->lock);
773
774 - for (i = 0; i < MAX_DMA_CHAN; i++) {
775 - if (IS_TX(i))
776 - netif_napi_add(dev, &priv->ch[i].napi,
777 - ltq_etop_poll_tx, 8);
778 - else if (IS_RX(i))
779 - netif_napi_add(dev, &priv->ch[i].napi,
780 - ltq_etop_poll_rx, 32);
781 - priv->ch[i].netdev = dev;
782 - }
783 + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
784 + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
785 + priv->txch.netdev = dev;
786 + priv->rxch.netdev = dev;
787
788 err = register_netdev(dev);
789 if (err)
790 @@ -788,32 +1008,23 @@ ltq_etop_remove(struct platform_device *
791 return 0;
792 }
793
794 +static const struct of_device_id ltq_etop_match[] = {
795 + { .compatible = "lantiq,etop-xway" },
796 + {},
797 +};
798 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
799 +
800 static struct platform_driver ltq_mii_driver = {
801 + .probe = ltq_etop_probe,
802 .remove = ltq_etop_remove,
803 .driver = {
804 .name = "ltq_etop",
805 .owner = THIS_MODULE,
806 + .of_match_table = ltq_etop_match,
807 },
808 };
809
810 -int __init
811 -init_ltq_etop(void)
812 -{
813 - int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
814 -
815 - if (ret)
816 - pr_err("ltq_etop: Error registering platform driver!");
817 - return ret;
818 -}
819 -
820 -static void __exit
821 -exit_ltq_etop(void)
822 -{
823 - platform_driver_unregister(&ltq_mii_driver);
824 -}
825 -
826 -module_init(init_ltq_etop);
827 -module_exit(exit_ltq_etop);
828 +module_platform_driver(ltq_mii_driver);
829
830 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
831 MODULE_DESCRIPTION("Lantiq SoC ETOP");