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[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches / 0018-MIPS-lantiq-adds-dwc_otg.patch
1 From ffd7924fcc69ff146d62f131d72ef18575bf0227 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 30 Sep 2011 14:37:36 +0200
4 Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
5
6 ---
7 drivers/usb/Kconfig | 2 +
8 drivers/usb/Makefile | 2 +
9 drivers/usb/core/hub.c | 4 +-
10 drivers/usb/dwc_otg/Kconfig | 37 +
11 drivers/usb/dwc_otg/Makefile | 39 +
12 drivers/usb/dwc_otg/dwc_otg_attr.c | 802 ++++++++
13 drivers/usb/dwc_otg/dwc_otg_attr.h | 67 +
14 drivers/usb/dwc_otg/dwc_otg_cil.c | 3025 +++++++++++++++++++++++++++++++
15 drivers/usb/dwc_otg/dwc_otg_cil.h | 911 ++++++++++
16 drivers/usb/dwc_otg/dwc_otg_cil_ifx.h | 58 +
17 drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 708 ++++++++
18 drivers/usb/dwc_otg/dwc_otg_driver.c | 1274 +++++++++++++
19 drivers/usb/dwc_otg/dwc_otg_driver.h | 84 +
20 drivers/usb/dwc_otg/dwc_otg_hcd.c | 2870 +++++++++++++++++++++++++++++
21 drivers/usb/dwc_otg/dwc_otg_hcd.h | 676 +++++++
22 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1841 +++++++++++++++++++
23 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 794 ++++++++
24 drivers/usb/dwc_otg/dwc_otg_ifx.c | 100 +
25 drivers/usb/dwc_otg/dwc_otg_ifx.h | 85 +
26 drivers/usb/dwc_otg/dwc_otg_plat.h | 269 +++
27 drivers/usb/dwc_otg/dwc_otg_regs.h | 1797 ++++++++++++++++++
28 21 files changed, 15443 insertions(+), 2 deletions(-)
29 create mode 100644 drivers/usb/dwc_otg/Kconfig
30 create mode 100644 drivers/usb/dwc_otg/Makefile
31 create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.c
32 create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.h
33 create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c
34 create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h
35 create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_ifx.h
36 create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c
37 create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.c
38 create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h
39 create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c
40 create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h
41 create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
42 create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
43 create mode 100644 drivers/usb/dwc_otg/dwc_otg_ifx.c
44 create mode 100644 drivers/usb/dwc_otg/dwc_otg_ifx.h
45 create mode 100644 drivers/usb/dwc_otg/dwc_otg_plat.h
46 create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h
47
48 --- a/drivers/usb/Kconfig
49 +++ b/drivers/usb/Kconfig
50 @@ -116,6 +116,8 @@ source "drivers/usb/wusbcore/Kconfig"
51
52 source "drivers/usb/host/Kconfig"
53
54 +source "drivers/usb/dwc_otg/Kconfig"
55 +
56 source "drivers/usb/musb/Kconfig"
57
58 source "drivers/usb/renesas_usbhs/Kconfig"
59 --- a/drivers/usb/Makefile
60 +++ b/drivers/usb/Makefile
61 @@ -28,6 +28,8 @@ obj-$(CONFIG_USB_C67X00_HCD) += c67x00/
62
63 obj-$(CONFIG_USB_WUSB) += wusbcore/
64
65 +obj-$(CONFIG_DWC_OTG) += dwc_otg/
66 +
67 obj-$(CONFIG_USB_ACM) += class/
68 obj-$(CONFIG_USB_PRINTER) += class/
69 obj-$(CONFIG_USB_WDM) += class/
70 --- a/drivers/usb/core/hub.c
71 +++ b/drivers/usb/core/hub.c
72 @@ -2885,11 +2885,11 @@ hub_port_init (struct usb_hub *hub, stru
73 udev->ttport = hdev->ttport;
74 } else if (udev->speed != USB_SPEED_HIGH
75 && hdev->speed == USB_SPEED_HIGH) {
76 - if (!hub->tt.hub) {
77 +/* if (!hub->tt.hub) {
78 dev_err(&udev->dev, "parent hub has no TT\n");
79 retval = -EINVAL;
80 goto fail;
81 - }
82 + }*/
83 udev->tt = &hub->tt;
84 udev->ttport = port1;
85 }
86 --- /dev/null
87 +++ b/drivers/usb/dwc_otg/Kconfig
88 @@ -0,0 +1,37 @@
89 +config DWC_OTG
90 + tristate "Synopsis DWC_OTG support"
91 + depends on USB
92 + help
93 + This driver supports Synopsis DWC_OTG IP core
94 + embebbed on many SOCs (ralink, infineon, etc)
95 +
96 +choice
97 + prompt "USB Operation Mode"
98 + depends on DWC_OTG
99 + default DWC_OTG_HOST_ONLY
100 +
101 +config DWC_OTG_HOST_ONLY
102 + bool "HOST ONLY MODE"
103 + depends on DWC_OTG
104 +
105 +#config DWC_OTG_DEVICE_ONLY
106 +# bool "DEVICE ONLY MODE"
107 +# depends on DWC_OTG
108 +endchoice
109 +
110 +choice
111 + prompt "Platform"
112 + depends on DWC_OTG
113 + default DWC_OTG_LANTIQ
114 +
115 +config DWC_OTG_LANTIQ
116 + bool "Lantiq"
117 + depends on LANTIQ
118 + help
119 + Danube USB Host Controller
120 + platform support
121 +endchoice
122 +
123 +config DWC_OTG_DEBUG
124 + bool "Enable debug mode"
125 + depends on DWC_OTG
126 --- /dev/null
127 +++ b/drivers/usb/dwc_otg/Makefile
128 @@ -0,0 +1,39 @@
129 +#
130 +# Makefile for DWC_otg Highspeed USB controller driver
131 +#
132 +
133 +ifeq ($(CONFIG_DWC_OTG_DEBUG),y)
134 +EXTRA_CFLAGS += -DDEBUG
135 +endif
136 +
137 +# Use one of the following flags to compile the software in host-only or
138 +# device-only mode based on the configuration selected by the user
139 +ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y)
140 + EXTRA_CFLAGS += -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY
141 + EXTRA_CFLAGS += -DDWC_OTG_EN_ISOC -DDWC_EN_ISOC
142 +else ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y)
143 + EXTRA_CFLAGS += -DDWC_OTG_DEVICE_ONLY
144 +else
145 + EXTRA_CFLAGS += -DDWC_OTG_MODE
146 +endif
147 +
148 +# EXTRA_CFLAGS += -DDWC_HS_ELECT_TST
149 +# EXTRA_CFLAGS += -DDWC_OTG_EXT_CHG_PUMP
150 +
151 +ifeq ($(CONFIG_DWC_OTG_LANTIQ),y)
152 + EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY -D__KERNEL__
153 +endif
154 +ifeq ($(CONFIG_DWC_OTG_LANTIQ),m)
155 + EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_HOST_ONLY -DMODULE -D__KERNEL__ -DDEBUG
156 +endif
157 +
158 +obj-$(CONFIG_DWC_OTG) := dwc_otg.o
159 +dwc_otg-objs := dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
160 +#dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
161 +dwc_otg-objs += dwc_otg_attr.o
162 +dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
163 +dwc_otg-objs += dwc_otg_ifx.o
164 +dwc_otg-objs += dwc_otg_driver.o
165 +
166 +#obj-$(CONFIG_DWC_OTG_IFX) := dwc_otg_ifx.o
167 +#dwc_otg_ifx-objs := dwc_otg_ifx.o
168 --- /dev/null
169 +++ b/drivers/usb/dwc_otg/dwc_otg_attr.c
170 @@ -0,0 +1,802 @@
171 +/* ==========================================================================
172 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.c $
173 + * $Revision: 1.1.1.1 $
174 + * $Date: 2009-04-17 06:15:34 $
175 + * $Change: 537387 $
176 + *
177 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
178 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
179 + * otherwise expressly agreed to in writing between Synopsys and you.
180 + *
181 + * The Software IS NOT an item of Licensed Software or Licensed Product under
182 + * any End User Software License Agreement or Agreement for Licensed Product
183 + * with Synopsys or any supplement thereto. You are permitted to use and
184 + * redistribute this Software in source and binary forms, with or without
185 + * modification, provided that redistributions of source code must retain this
186 + * notice. You may not view, use, disclose, copy or distribute this file or
187 + * any information contained herein except pursuant to this license grant from
188 + * Synopsys. If you do not agree with this notice, including the disclaimer
189 + * below, then you are not authorized to use the Software.
190 + *
191 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
192 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
193 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
194 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
195 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
196 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
197 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
198 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
199 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
200 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
201 + * DAMAGE.
202 + * ========================================================================== */
203 +
204 +/** @file
205 + *
206 + * The diagnostic interface will provide access to the controller for
207 + * bringing up the hardware and testing. The Linux driver attributes
208 + * feature will be used to provide the Linux Diagnostic
209 + * Interface. These attributes are accessed through sysfs.
210 + */
211 +
212 +/** @page "Linux Module Attributes"
213 + *
214 + * The Linux module attributes feature is used to provide the Linux
215 + * Diagnostic Interface. These attributes are accessed through sysfs.
216 + * The diagnostic interface will provide access to the controller for
217 + * bringing up the hardware and testing.
218 +
219 +
220 + The following table shows the attributes.
221 + <table>
222 + <tr>
223 + <td><b> Name</b></td>
224 + <td><b> Description</b></td>
225 + <td><b> Access</b></td>
226 + </tr>
227 +
228 + <tr>
229 + <td> mode </td>
230 + <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
231 + <td> Read</td>
232 + </tr>
233 +
234 + <tr>
235 + <td> hnpcapable </td>
236 + <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
237 + Read returns the current value.</td>
238 + <td> Read/Write</td>
239 + </tr>
240 +
241 + <tr>
242 + <td> srpcapable </td>
243 + <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
244 + Read returns the current value.</td>
245 + <td> Read/Write</td>
246 + </tr>
247 +
248 + <tr>
249 + <td> hnp </td>
250 + <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
251 + <td> Read/Write</td>
252 + </tr>
253 +
254 + <tr>
255 + <td> srp </td>
256 + <td> Initiates the Session Request Protocol. Read returns the status.</td>
257 + <td> Read/Write</td>
258 + </tr>
259 +
260 + <tr>
261 + <td> buspower </td>
262 + <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
263 + <td> Read/Write</td>
264 + </tr>
265 +
266 + <tr>
267 + <td> bussuspend </td>
268 + <td> Suspends the USB bus.</td>
269 + <td> Read/Write</td>
270 + </tr>
271 +
272 + <tr>
273 + <td> busconnected </td>
274 + <td> Gets the connection status of the bus</td>
275 + <td> Read</td>
276 + </tr>
277 +
278 + <tr>
279 + <td> gotgctl </td>
280 + <td> Gets or sets the Core Control Status Register.</td>
281 + <td> Read/Write</td>
282 + </tr>
283 +
284 + <tr>
285 + <td> gusbcfg </td>
286 + <td> Gets or sets the Core USB Configuration Register</td>
287 + <td> Read/Write</td>
288 + </tr>
289 +
290 + <tr>
291 + <td> grxfsiz </td>
292 + <td> Gets or sets the Receive FIFO Size Register</td>
293 + <td> Read/Write</td>
294 + </tr>
295 +
296 + <tr>
297 + <td> gnptxfsiz </td>
298 + <td> Gets or sets the non-periodic Transmit Size Register</td>
299 + <td> Read/Write</td>
300 + </tr>
301 +
302 + <tr>
303 + <td> gpvndctl </td>
304 + <td> Gets or sets the PHY Vendor Control Register</td>
305 + <td> Read/Write</td>
306 + </tr>
307 +
308 + <tr>
309 + <td> ggpio </td>
310 + <td> Gets the value in the lower 16-bits of the General Purpose IO Register
311 + or sets the upper 16 bits.</td>
312 + <td> Read/Write</td>
313 + </tr>
314 +
315 + <tr>
316 + <td> guid </td>
317 + <td> Gets or sets the value of the User ID Register</td>
318 + <td> Read/Write</td>
319 + </tr>
320 +
321 + <tr>
322 + <td> gsnpsid </td>
323 + <td> Gets the value of the Synopsys ID Regester</td>
324 + <td> Read</td>
325 + </tr>
326 +
327 + <tr>
328 + <td> devspeed </td>
329 + <td> Gets or sets the device speed setting in the DCFG register</td>
330 + <td> Read/Write</td>
331 + </tr>
332 +
333 + <tr>
334 + <td> enumspeed </td>
335 + <td> Gets the device enumeration Speed.</td>
336 + <td> Read</td>
337 + </tr>
338 +
339 + <tr>
340 + <td> hptxfsiz </td>
341 + <td> Gets the value of the Host Periodic Transmit FIFO</td>
342 + <td> Read</td>
343 + </tr>
344 +
345 + <tr>
346 + <td> hprt0 </td>
347 + <td> Gets or sets the value in the Host Port Control and Status Register</td>
348 + <td> Read/Write</td>
349 + </tr>
350 +
351 + <tr>
352 + <td> regoffset </td>
353 + <td> Sets the register offset for the next Register Access</td>
354 + <td> Read/Write</td>
355 + </tr>
356 +
357 + <tr>
358 + <td> regvalue </td>
359 + <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
360 + <td> Read/Write</td>
361 + </tr>
362 +
363 + <tr>
364 + <td> remote_wakeup </td>
365 + <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
366 + wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
367 + Wakeup signalling bit in the Device Control Register is set for 1
368 + milli-second.</td>
369 + <td> Read/Write</td>
370 + </tr>
371 +
372 + <tr>
373 + <td> regdump </td>
374 + <td> Dumps the contents of core registers.</td>
375 + <td> Read</td>
376 + </tr>
377 +
378 + <tr>
379 + <td> hcddump </td>
380 + <td> Dumps the current HCD state.</td>
381 + <td> Read</td>
382 + </tr>
383 +
384 + <tr>
385 + <td> hcd_frrem </td>
386 + <td> Shows the average value of the Frame Remaining
387 + field in the Host Frame Number/Frame Remaining register when an SOF interrupt
388 + occurs. This can be used to determine the average interrupt latency. Also
389 + shows the average Frame Remaining value for start_transfer and the "a" and
390 + "b" sample points. The "a" and "b" sample points may be used during debugging
391 + bto determine how long it takes to execute a section of the HCD code.</td>
392 + <td> Read</td>
393 + </tr>
394 +
395 + <tr>
396 + <td> rd_reg_test </td>
397 + <td> Displays the time required to read the GNPTXFSIZ register many times
398 + (the output shows the number of times the register is read).
399 + <td> Read</td>
400 + </tr>
401 +
402 + <tr>
403 + <td> wr_reg_test </td>
404 + <td> Displays the time required to write the GNPTXFSIZ register many times
405 + (the output shows the number of times the register is written).
406 + <td> Read</td>
407 + </tr>
408 +
409 + </table>
410 +
411 + Example usage:
412 + To get the current mode:
413 + cat /sys/devices/lm0/mode
414 +
415 + To power down the USB:
416 + echo 0 > /sys/devices/lm0/buspower
417 + */
418 +#include <linux/kernel.h>
419 +#include <linux/module.h>
420 +#include <linux/moduleparam.h>
421 +#include <linux/init.h>
422 +#include <linux/device.h>
423 +#include <linux/errno.h>
424 +#include <linux/types.h>
425 +#include <linux/stat.h> /* permission constants */
426 +
427 +#include <asm/io.h>
428 +
429 +#include "dwc_otg_plat.h"
430 +#include "dwc_otg_attr.h"
431 +#include "dwc_otg_driver.h"
432 +// #include "dwc_otg_pcd.h"
433 +#include "dwc_otg_hcd.h"
434 +
435 +// 20070316, winder added.
436 +#ifndef SZ_256K
437 +#define SZ_256K 0x00040000
438 +#endif
439 +
440 +/*
441 + * MACROs for defining sysfs attribute
442 + */
443 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
444 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
445 +{ \
446 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
447 + uint32_t val; \
448 + val = dwc_read_reg32 (_addr_); \
449 + val = (val & (_mask_)) >> _shift_; \
450 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
451 +}
452 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
453 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \
454 +{ \
455 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
456 + uint32_t set = simple_strtoul(buf, NULL, 16); \
457 + uint32_t clear = set; \
458 + clear = ((~clear) << _shift_) & _mask_; \
459 + set = (set << _shift_) & _mask_; \
460 + dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
461 + dwc_modify_reg32(_addr_, clear, set); \
462 + return count; \
463 +}
464 +
465 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
466 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
467 +DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
468 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
469 +
470 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
471 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
472 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
473 +
474 +/*
475 + * MACROs for defining sysfs attribute for 32-bit registers
476 + */
477 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
478 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
479 +{ \
480 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
481 + uint32_t val; \
482 + val = dwc_read_reg32 (_addr_); \
483 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
484 +}
485 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
486 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \
487 +{ \
488 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
489 + uint32_t val = simple_strtoul(buf, NULL, 16); \
490 + dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
491 + dwc_write_reg32(_addr_, val); \
492 + return count; \
493 +}
494 +
495 +#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
496 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
497 +DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
498 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
499 +
500 +#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
501 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
502 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
503 +
504 +
505 +/** @name Functions for Show/Store of Attributes */
506 +/**@{*/
507 +
508 +/**
509 + * Show the register offset of the Register Access.
510 + */
511 +static ssize_t regoffset_show( struct device *_dev, struct device_attribute *attr, char *buf)
512 +{
513 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
514 + return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
515 +}
516 +
517 +/**
518 + * Set the register offset for the next Register Access Read/Write
519 + */
520 +static ssize_t regoffset_store( struct device *_dev, struct device_attribute *attr, const char *buf,
521 + size_t count )
522 +{
523 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
524 + uint32_t offset = simple_strtoul(buf, NULL, 16);
525 + //dev_dbg(_dev, "Offset=0x%08x\n", offset);
526 + if (offset < SZ_256K ) {
527 + otg_dev->reg_offset = offset;
528 + }
529 + else {
530 + dev_err( _dev, "invalid offset\n" );
531 + }
532 +
533 + return count;
534 +}
535 +DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, regoffset_show, regoffset_store);
536 +
537 +/**
538 + * Show the value of the register at the offset in the reg_offset
539 + * attribute.
540 + */
541 +static ssize_t regvalue_show( struct device *_dev, struct device_attribute *attr, char *buf)
542 +{
543 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
544 + uint32_t val;
545 + volatile uint32_t *addr;
546 +
547 + if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
548 + /* Calculate the address */
549 + addr = (uint32_t*)(otg_dev->reg_offset +
550 + (uint8_t*)otg_dev->base);
551 + //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
552 + val = dwc_read_reg32( addr );
553 + return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
554 + "Reg@0x%06x = 0x%08x\n",
555 + otg_dev->reg_offset, val);
556 + }
557 + else {
558 + dev_err(_dev, "Invalid offset (0x%0x)\n",
559 + otg_dev->reg_offset);
560 + return sprintf(buf, "invalid offset\n" );
561 + }
562 +}
563 +
564 +/**
565 + * Store the value in the register at the offset in the reg_offset
566 + * attribute.
567 + *
568 + */
569 +static ssize_t regvalue_store( struct device *_dev, struct device_attribute *attr, const char *buf,
570 + size_t count )
571 +{
572 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
573 + volatile uint32_t * addr;
574 + uint32_t val = simple_strtoul(buf, NULL, 16);
575 + //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
576 + if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
577 + /* Calculate the address */
578 + addr = (uint32_t*)(otg_dev->reg_offset +
579 + (uint8_t*)otg_dev->base);
580 + //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
581 + dwc_write_reg32( addr, val );
582 + }
583 + else {
584 + dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
585 + otg_dev->reg_offset);
586 + }
587 + return count;
588 +}
589 +DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store);
590 +
591 +/*
592 + * Attributes
593 + */
594 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
595 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
596 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
597 +
598 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
599 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
600 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
601 +
602 +DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
603 +DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
604 +DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
605 +DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
606 +DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
607 +DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
608 +DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
609 +DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
610 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
611 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
612 +
613 +DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
614 +DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
615 +
616 +
617 +/**
618 + * @todo Add code to initiate the HNP.
619 + */
620 +/**
621 + * Show the HNP status bit
622 + */
623 +static ssize_t hnp_show( struct device *_dev, struct device_attribute *attr, char *buf)
624 +{
625 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
626 + gotgctl_data_t val;
627 + val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
628 + return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
629 +}
630 +
631 +/**
632 + * Set the HNP Request bit
633 + */
634 +static ssize_t hnp_store( struct device *_dev, struct device_attribute *attr, const char *buf,
635 + size_t count )
636 +{
637 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
638 + uint32_t in = simple_strtoul(buf, NULL, 16);
639 + uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
640 + gotgctl_data_t mem;
641 + mem.d32 = dwc_read_reg32(addr);
642 + mem.b.hnpreq = in;
643 + dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
644 + dwc_write_reg32(addr, mem.d32);
645 + return count;
646 +}
647 +DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
648 +
649 +/**
650 + * @todo Add code to initiate the SRP.
651 + */
652 +/**
653 + * Show the SRP status bit
654 + */
655 +static ssize_t srp_show( struct device *_dev, struct device_attribute *attr, char *buf)
656 +{
657 +#ifndef DWC_HOST_ONLY
658 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
659 + gotgctl_data_t val;
660 + val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
661 + return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
662 +#else
663 + return sprintf(buf, "Host Only Mode!\n");
664 +#endif
665 +}
666 +
667 +/**
668 + * Set the SRP Request bit
669 + */
670 +static ssize_t srp_store( struct device *_dev, struct device_attribute *attr, const char *buf,
671 + size_t count )
672 +{
673 +#ifndef DWC_HOST_ONLY
674 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
675 + dwc_otg_pcd_initiate_srp(otg_dev->pcd);
676 +#endif
677 + return count;
678 +}
679 +DEVICE_ATTR(srp, 0644, srp_show, srp_store);
680 +
681 +/**
682 + * @todo Need to do more for power on/off?
683 + */
684 +/**
685 + * Show the Bus Power status
686 + */
687 +static ssize_t buspower_show( struct device *_dev, struct device_attribute *attr, char *buf)
688 +{
689 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
690 + hprt0_data_t val;
691 + val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
692 + return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
693 +}
694 +
695 +
696 +/**
697 + * Set the Bus Power status
698 + */
699 +static ssize_t buspower_store( struct device *_dev, struct device_attribute *attr, const char *buf,
700 + size_t count )
701 +{
702 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
703 + uint32_t on = simple_strtoul(buf, NULL, 16);
704 + uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
705 + hprt0_data_t mem;
706 +
707 + mem.d32 = dwc_read_reg32(addr);
708 + mem.b.prtpwr = on;
709 +
710 + //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
711 + dwc_write_reg32(addr, mem.d32);
712 +
713 + return count;
714 +}
715 +DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
716 +
717 +/**
718 + * @todo Need to do more for suspend?
719 + */
720 +/**
721 + * Show the Bus Suspend status
722 + */
723 +static ssize_t bussuspend_show( struct device *_dev, struct device_attribute *attr, char *buf)
724 +{
725 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
726 + hprt0_data_t val;
727 + val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
728 + return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
729 +}
730 +
731 +/**
732 + * Set the Bus Suspend status
733 + */
734 +static ssize_t bussuspend_store( struct device *_dev, struct device_attribute *attr, const char *buf,
735 + size_t count )
736 +{
737 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
738 + uint32_t in = simple_strtoul(buf, NULL, 16);
739 + uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
740 + hprt0_data_t mem;
741 + mem.d32 = dwc_read_reg32(addr);
742 + mem.b.prtsusp = in;
743 + dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
744 + dwc_write_reg32(addr, mem.d32);
745 + return count;
746 +}
747 +DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
748 +
749 +/**
750 + * Show the status of Remote Wakeup.
751 + */
752 +static ssize_t remote_wakeup_show( struct device *_dev, struct device_attribute *attr, char *buf)
753 +{
754 +#ifndef DWC_HOST_ONLY
755 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
756 + dctl_data_t val;
757 + val.d32 = dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
758 + return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
759 + val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
760 +#else
761 + return sprintf(buf, "Host Only Mode!\n");
762 +#endif
763 +}
764 +
765 +/**
766 + * Initiate a remote wakeup of the host. The Device control register
767 + * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
768 + * flag is set.
769 + *
770 + */
771 +static ssize_t remote_wakeup_store( struct device *_dev, struct device_attribute *attr, const char *buf,
772 + size_t count )
773 +{
774 +#ifndef DWC_HOST_ONLY
775 + uint32_t val = simple_strtoul(buf, NULL, 16);
776 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
777 + if (val&1) {
778 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
779 + }
780 + else {
781 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
782 + }
783 +#endif
784 + return count;
785 +}
786 +DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show,
787 + remote_wakeup_store);
788 +
789 +/**
790 + * Dump global registers and either host or device registers (depending on the
791 + * current mode of the core).
792 + */
793 +static ssize_t regdump_show( struct device *_dev, struct device_attribute *attr, char *buf)
794 +{
795 +#ifdef DEBUG
796 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
797 + printk("%s otg_dev=0x%p\n", __FUNCTION__, otg_dev);
798 +
799 + dwc_otg_dump_global_registers( otg_dev->core_if);
800 + if (dwc_otg_is_host_mode(otg_dev->core_if)) {
801 + dwc_otg_dump_host_registers( otg_dev->core_if);
802 + } else {
803 + dwc_otg_dump_dev_registers( otg_dev->core_if);
804 + }
805 +#endif
806 +
807 + return sprintf( buf, "Register Dump\n" );
808 +}
809 +
810 +DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
811 +
812 +/**
813 + * Dump the current hcd state.
814 + */
815 +static ssize_t hcddump_show( struct device *_dev, struct device_attribute *attr, char *buf)
816 +{
817 +#ifndef DWC_DEVICE_ONLY
818 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
819 + dwc_otg_hcd_dump_state(otg_dev->hcd);
820 +#endif
821 + return sprintf( buf, "HCD Dump\n" );
822 +}
823 +
824 +DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
825 +
826 +/**
827 + * Dump the average frame remaining at SOF. This can be used to
828 + * determine average interrupt latency. Frame remaining is also shown for
829 + * start transfer and two additional sample points.
830 + */
831 +static ssize_t hcd_frrem_show( struct device *_dev, struct device_attribute *attr, char *buf)
832 +{
833 +#ifndef DWC_DEVICE_ONLY
834 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
835 + dwc_otg_hcd_dump_frrem(otg_dev->hcd);
836 +#endif
837 + return sprintf( buf, "HCD Dump Frame Remaining\n" );
838 +}
839 +
840 +DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
841 +
842 +/**
843 + * Displays the time required to read the GNPTXFSIZ register many times (the
844 + * output shows the number of times the register is read).
845 + */
846 +#define RW_REG_COUNT 10000000
847 +#define MSEC_PER_JIFFIE 1000/HZ
848 +static ssize_t rd_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf)
849 +{
850 + int i;
851 + int time;
852 + int start_jiffies;
853 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
854 +
855 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
856 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
857 + start_jiffies = jiffies;
858 + for (i = 0; i < RW_REG_COUNT; i++) {
859 + dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
860 + }
861 + time = jiffies - start_jiffies;
862 + return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
863 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
864 +}
865 +
866 +DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
867 +
868 +/**
869 + * Displays the time required to write the GNPTXFSIZ register many times (the
870 + * output shows the number of times the register is written).
871 + */
872 +static ssize_t wr_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf)
873 +{
874 + int i;
875 + int time;
876 + int start_jiffies;
877 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
878 + uint32_t reg_val;
879 +
880 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
881 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
882 + reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
883 + start_jiffies = jiffies;
884 + for (i = 0; i < RW_REG_COUNT; i++) {
885 + dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
886 + }
887 + time = jiffies - start_jiffies;
888 + return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
889 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
890 +}
891 +
892 +DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
893 +/**@}*/
894 +
895 +/**
896 + * Create the device files
897 + */
898 +void dwc_otg_attr_create (struct device *_dev)
899 +{
900 + int retval;
901 +
902 + retval = device_create_file(_dev, &dev_attr_regoffset);
903 + retval += device_create_file(_dev, &dev_attr_regvalue);
904 + retval += device_create_file(_dev, &dev_attr_mode);
905 + retval += device_create_file(_dev, &dev_attr_hnpcapable);
906 + retval += device_create_file(_dev, &dev_attr_srpcapable);
907 + retval += device_create_file(_dev, &dev_attr_hnp);
908 + retval += device_create_file(_dev, &dev_attr_srp);
909 + retval += device_create_file(_dev, &dev_attr_buspower);
910 + retval += device_create_file(_dev, &dev_attr_bussuspend);
911 + retval += device_create_file(_dev, &dev_attr_busconnected);
912 + retval += device_create_file(_dev, &dev_attr_gotgctl);
913 + retval += device_create_file(_dev, &dev_attr_gusbcfg);
914 + retval += device_create_file(_dev, &dev_attr_grxfsiz);
915 + retval += device_create_file(_dev, &dev_attr_gnptxfsiz);
916 + retval += device_create_file(_dev, &dev_attr_gpvndctl);
917 + retval += device_create_file(_dev, &dev_attr_ggpio);
918 + retval += device_create_file(_dev, &dev_attr_guid);
919 + retval += device_create_file(_dev, &dev_attr_gsnpsid);
920 + retval += device_create_file(_dev, &dev_attr_devspeed);
921 + retval += device_create_file(_dev, &dev_attr_enumspeed);
922 + retval += device_create_file(_dev, &dev_attr_hptxfsiz);
923 + retval += device_create_file(_dev, &dev_attr_hprt0);
924 + retval += device_create_file(_dev, &dev_attr_remote_wakeup);
925 + retval += device_create_file(_dev, &dev_attr_regdump);
926 + retval += device_create_file(_dev, &dev_attr_hcddump);
927 + retval += device_create_file(_dev, &dev_attr_hcd_frrem);
928 + retval += device_create_file(_dev, &dev_attr_rd_reg_test);
929 + retval += device_create_file(_dev, &dev_attr_wr_reg_test);
930 +
931 + if(retval != 0)
932 + {
933 + DWC_PRINT("cannot create sysfs device files.\n");
934 + // DWC_PRINT("killing own sysfs device files!\n");
935 + dwc_otg_attr_remove(_dev);
936 + }
937 +}
938 +
939 +/**
940 + * Remove the device files
941 + */
942 +void dwc_otg_attr_remove (struct device *_dev)
943 +{
944 + device_remove_file(_dev, &dev_attr_regoffset);
945 + device_remove_file(_dev, &dev_attr_regvalue);
946 + device_remove_file(_dev, &dev_attr_mode);
947 + device_remove_file(_dev, &dev_attr_hnpcapable);
948 + device_remove_file(_dev, &dev_attr_srpcapable);
949 + device_remove_file(_dev, &dev_attr_hnp);
950 + device_remove_file(_dev, &dev_attr_srp);
951 + device_remove_file(_dev, &dev_attr_buspower);
952 + device_remove_file(_dev, &dev_attr_bussuspend);
953 + device_remove_file(_dev, &dev_attr_busconnected);
954 + device_remove_file(_dev, &dev_attr_gotgctl);
955 + device_remove_file(_dev, &dev_attr_gusbcfg);
956 + device_remove_file(_dev, &dev_attr_grxfsiz);
957 + device_remove_file(_dev, &dev_attr_gnptxfsiz);
958 + device_remove_file(_dev, &dev_attr_gpvndctl);
959 + device_remove_file(_dev, &dev_attr_ggpio);
960 + device_remove_file(_dev, &dev_attr_guid);
961 + device_remove_file(_dev, &dev_attr_gsnpsid);
962 + device_remove_file(_dev, &dev_attr_devspeed);
963 + device_remove_file(_dev, &dev_attr_enumspeed);
964 + device_remove_file(_dev, &dev_attr_hptxfsiz);
965 + device_remove_file(_dev, &dev_attr_hprt0);
966 + device_remove_file(_dev, &dev_attr_remote_wakeup);
967 + device_remove_file(_dev, &dev_attr_regdump);
968 + device_remove_file(_dev, &dev_attr_hcddump);
969 + device_remove_file(_dev, &dev_attr_hcd_frrem);
970 + device_remove_file(_dev, &dev_attr_rd_reg_test);
971 + device_remove_file(_dev, &dev_attr_wr_reg_test);
972 +}
973 --- /dev/null
974 +++ b/drivers/usb/dwc_otg/dwc_otg_attr.h
975 @@ -0,0 +1,67 @@
976 +/* ==========================================================================
977 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.h $
978 + * $Revision: 1.1.1.1 $
979 + * $Date: 2009-04-17 06:15:34 $
980 + * $Change: 510275 $
981 + *
982 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
983 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
984 + * otherwise expressly agreed to in writing between Synopsys and you.
985 + *
986 + * The Software IS NOT an item of Licensed Software or Licensed Product under
987 + * any End User Software License Agreement or Agreement for Licensed Product
988 + * with Synopsys or any supplement thereto. You are permitted to use and
989 + * redistribute this Software in source and binary forms, with or without
990 + * modification, provided that redistributions of source code must retain this
991 + * notice. You may not view, use, disclose, copy or distribute this file or
992 + * any information contained herein except pursuant to this license grant from
993 + * Synopsys. If you do not agree with this notice, including the disclaimer
994 + * below, then you are not authorized to use the Software.
995 + *
996 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
997 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
998 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
999 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
1000 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1001 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
1002 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
1003 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
1004 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1005 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
1006 + * DAMAGE.
1007 + * ========================================================================== */
1008 +
1009 +#if !defined(__DWC_OTG_ATTR_H__)
1010 +#define __DWC_OTG_ATTR_H__
1011 +
1012 +/** @file
1013 + * This file contains the interface to the Linux device attributes.
1014 + */
1015 +extern struct device_attribute dev_attr_regoffset;
1016 +extern struct device_attribute dev_attr_regvalue;
1017 +
1018 +extern struct device_attribute dev_attr_mode;
1019 +extern struct device_attribute dev_attr_hnpcapable;
1020 +extern struct device_attribute dev_attr_srpcapable;
1021 +extern struct device_attribute dev_attr_hnp;
1022 +extern struct device_attribute dev_attr_srp;
1023 +extern struct device_attribute dev_attr_buspower;
1024 +extern struct device_attribute dev_attr_bussuspend;
1025 +extern struct device_attribute dev_attr_busconnected;
1026 +extern struct device_attribute dev_attr_gotgctl;
1027 +extern struct device_attribute dev_attr_gusbcfg;
1028 +extern struct device_attribute dev_attr_grxfsiz;
1029 +extern struct device_attribute dev_attr_gnptxfsiz;
1030 +extern struct device_attribute dev_attr_gpvndctl;
1031 +extern struct device_attribute dev_attr_ggpio;
1032 +extern struct device_attribute dev_attr_guid;
1033 +extern struct device_attribute dev_attr_gsnpsid;
1034 +extern struct device_attribute dev_attr_devspeed;
1035 +extern struct device_attribute dev_attr_enumspeed;
1036 +extern struct device_attribute dev_attr_hptxfsiz;
1037 +extern struct device_attribute dev_attr_hprt0;
1038 +
1039 +void dwc_otg_attr_create (struct device *_dev);
1040 +void dwc_otg_attr_remove (struct device *_dev);
1041 +
1042 +#endif
1043 --- /dev/null
1044 +++ b/drivers/usb/dwc_otg/dwc_otg_cil.c
1045 @@ -0,0 +1,3025 @@
1046 +/* ==========================================================================
1047 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.c $
1048 + * $Revision: 1.1.1.1 $
1049 + * $Date: 2009-04-17 06:15:34 $
1050 + * $Change: 631780 $
1051 + *
1052 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
1053 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
1054 + * otherwise expressly agreed to in writing between Synopsys and you.
1055 + *
1056 + * The Software IS NOT an item of Licensed Software or Licensed Product under
1057 + * any End User Software License Agreement or Agreement for Licensed Product
1058 + * with Synopsys or any supplement thereto. You are permitted to use and
1059 + * redistribute this Software in source and binary forms, with or without
1060 + * modification, provided that redistributions of source code must retain this
1061 + * notice. You may not view, use, disclose, copy or distribute this file or
1062 + * any information contained herein except pursuant to this license grant from
1063 + * Synopsys. If you do not agree with this notice, including the disclaimer
1064 + * below, then you are not authorized to use the Software.
1065 + *
1066 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
1067 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1068 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1069 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
1070 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1071 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
1072 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
1073 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
1074 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1075 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
1076 + * DAMAGE.
1077 + * ========================================================================== */
1078 +
1079 +/** @file
1080 + *
1081 + * The Core Interface Layer provides basic services for accessing and
1082 + * managing the DWC_otg hardware. These services are used by both the
1083 + * Host Controller Driver and the Peripheral Controller Driver.
1084 + *
1085 + * The CIL manages the memory map for the core so that the HCD and PCD
1086 + * don't have to do this separately. It also handles basic tasks like
1087 + * reading/writing the registers and data FIFOs in the controller.
1088 + * Some of the data access functions provide encapsulation of several
1089 + * operations required to perform a task, such as writing multiple
1090 + * registers to start a transfer. Finally, the CIL performs basic
1091 + * services that are not specific to either the host or device modes
1092 + * of operation. These services include management of the OTG Host
1093 + * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
1094 + * Diagnostic API is also provided to allow testing of the controller
1095 + * hardware.
1096 + *
1097 + * The Core Interface Layer has the following requirements:
1098 + * - Provides basic controller operations.
1099 + * - Minimal use of OS services.
1100 + * - The OS services used will be abstracted by using inline functions
1101 + * or macros.
1102 + *
1103 + */
1104 +#include <asm/unaligned.h>
1105 +
1106 +#ifdef DEBUG
1107 +#include <linux/jiffies.h>
1108 +#endif
1109 +
1110 +#include "dwc_otg_plat.h"
1111 +
1112 +#include "dwc_otg_regs.h"
1113 +#include "dwc_otg_cil.h"
1114 +
1115 +/**
1116 + * This function is called to initialize the DWC_otg CSR data
1117 + * structures. The register addresses in the device and host
1118 + * structures are initialized from the base address supplied by the
1119 + * caller. The calling function must make the OS calls to get the
1120 + * base address of the DWC_otg controller registers. The core_params
1121 + * argument holds the parameters that specify how the core should be
1122 + * configured.
1123 + *
1124 + * @param[in] _reg_base_addr Base address of DWC_otg core registers
1125 + * @param[in] _core_params Pointer to the core configuration parameters
1126 + *
1127 + */
1128 +dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
1129 + dwc_otg_core_params_t *_core_params)
1130 +{
1131 + dwc_otg_core_if_t *core_if = 0;
1132 + dwc_otg_dev_if_t *dev_if = 0;
1133 + dwc_otg_host_if_t *host_if = 0;
1134 + uint8_t *reg_base = (uint8_t *)_reg_base_addr;
1135 + int i = 0;
1136 +
1137 + DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, _reg_base_addr, _core_params);
1138 +
1139 + core_if = kmalloc( sizeof(dwc_otg_core_if_t), GFP_KERNEL);
1140 + if (core_if == 0) {
1141 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n");
1142 + return 0;
1143 + }
1144 + memset(core_if, 0, sizeof(dwc_otg_core_if_t));
1145 +
1146 + core_if->core_params = _core_params;
1147 + core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base;
1148 + /*
1149 + * Allocate the Device Mode structures.
1150 + */
1151 + dev_if = kmalloc( sizeof(dwc_otg_dev_if_t), GFP_KERNEL);
1152 + if (dev_if == 0) {
1153 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
1154 + kfree( core_if );
1155 + return 0;
1156 + }
1157 +
1158 + dev_if->dev_global_regs =
1159 + (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET);
1160 +
1161 + for (i=0; i<MAX_EPS_CHANNELS; i++) {
1162 + dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
1163 + (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
1164 + (i * DWC_EP_REG_OFFSET));
1165 +
1166 + dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
1167 + (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
1168 + (i * DWC_EP_REG_OFFSET));
1169 + DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
1170 + i, &dev_if->in_ep_regs[i]->diepctl);
1171 + DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
1172 + i, &dev_if->out_ep_regs[i]->doepctl);
1173 + }
1174 + dev_if->speed = 0; // unknown
1175 + //dev_if->num_eps = MAX_EPS_CHANNELS;
1176 + //dev_if->num_perio_eps = 0;
1177 +
1178 + core_if->dev_if = dev_if;
1179 + /*
1180 + * Allocate the Host Mode structures.
1181 + */
1182 + host_if = kmalloc( sizeof(dwc_otg_host_if_t), GFP_KERNEL);
1183 + if (host_if == 0) {
1184 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n");
1185 + kfree( dev_if );
1186 + kfree( core_if );
1187 + return 0;
1188 + }
1189 +
1190 + host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
1191 + (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
1192 + host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
1193 + for (i=0; i<MAX_EPS_CHANNELS; i++) {
1194 + host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
1195 + (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
1196 + (i * DWC_OTG_CHAN_REGS_OFFSET));
1197 + DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
1198 + i, &host_if->hc_regs[i]->hcchar);
1199 + }
1200 + host_if->num_host_channels = MAX_EPS_CHANNELS;
1201 + core_if->host_if = host_if;
1202 +
1203 + for (i=0; i<MAX_EPS_CHANNELS; i++) {
1204 + core_if->data_fifo[i] =
1205 + (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET +
1206 + (i * DWC_OTG_DATA_FIFO_SIZE));
1207 + DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
1208 + i, (unsigned)core_if->data_fifo[i]);
1209 + } // for loop.
1210 +
1211 + core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET);
1212 +
1213 + /*
1214 + * Store the contents of the hardware configuration registers here for
1215 + * easy access later.
1216 + */
1217 + core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
1218 + core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
1219 + core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
1220 + core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
1221 +
1222 + DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32);
1223 + DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32);
1224 + DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32);
1225 + DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32);
1226 +
1227 +
1228 + DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode);
1229 + DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture);
1230 + DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep);
1231 + DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan);
1232 + DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth);
1233 + DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth);
1234 + DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth);
1235 +
1236 + DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth);
1237 + DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width);
1238 +
1239 + /*
1240 + * Set the SRP sucess bit for FS-I2c
1241 + */
1242 + core_if->srp_success = 0;
1243 + core_if->srp_timer_started = 0;
1244 +
1245 + return core_if;
1246 +}
1247 +/**
1248 + * This function frees the structures allocated by dwc_otg_cil_init().
1249 + *
1250 + * @param[in] _core_if The core interface pointer returned from
1251 + * dwc_otg_cil_init().
1252 + *
1253 + */
1254 +void dwc_otg_cil_remove( dwc_otg_core_if_t *_core_if )
1255 +{
1256 + /* Disable all interrupts */
1257 + dwc_modify_reg32( &_core_if->core_global_regs->gahbcfg, 1, 0);
1258 + dwc_write_reg32( &_core_if->core_global_regs->gintmsk, 0);
1259 +
1260 + if ( _core_if->dev_if ) {
1261 + kfree( _core_if->dev_if );
1262 + }
1263 + if ( _core_if->host_if ) {
1264 + kfree( _core_if->host_if );
1265 + }
1266 + kfree( _core_if );
1267 +}
1268 +
1269 +/**
1270 + * This function enables the controller's Global Interrupt in the AHB Config
1271 + * register.
1272 + *
1273 + * @param[in] _core_if Programming view of DWC_otg controller.
1274 + */
1275 +extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if )
1276 +{
1277 + gahbcfg_data_t ahbcfg = { .d32 = 0};
1278 + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
1279 + dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
1280 +}
1281 +/**
1282 + * This function disables the controller's Global Interrupt in the AHB Config
1283 + * register.
1284 + *
1285 + * @param[in] _core_if Programming view of DWC_otg controller.
1286 + */
1287 +extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if )
1288 +{
1289 + gahbcfg_data_t ahbcfg = { .d32 = 0};
1290 + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
1291 + dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
1292 +}
1293 +
1294 +/**
1295 + * This function initializes the commmon interrupts, used in both
1296 + * device and host modes.
1297 + *
1298 + * @param[in] _core_if Programming view of the DWC_otg controller
1299 + *
1300 + */
1301 +static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *_core_if)
1302 +{
1303 + dwc_otg_core_global_regs_t *global_regs =
1304 + _core_if->core_global_regs;
1305 + gintmsk_data_t intr_mask = { .d32 = 0};
1306 + /* Clear any pending OTG Interrupts */
1307 + dwc_write_reg32( &global_regs->gotgint, 0xFFFFFFFF);
1308 + /* Clear any pending interrupts */
1309 + dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF);
1310 + /*
1311 + * Enable the interrupts in the GINTMSK.
1312 + */
1313 + intr_mask.b.modemismatch = 1;
1314 + intr_mask.b.otgintr = 1;
1315 + if (!_core_if->dma_enable) {
1316 + intr_mask.b.rxstsqlvl = 1;
1317 + }
1318 + intr_mask.b.conidstschng = 1;
1319 + intr_mask.b.wkupintr = 1;
1320 + intr_mask.b.disconnect = 1;
1321 + intr_mask.b.usbsuspend = 1;
1322 + intr_mask.b.sessreqintr = 1;
1323 + dwc_write_reg32( &global_regs->gintmsk, intr_mask.d32);
1324 +}
1325 +
1326 +/**
1327 + * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
1328 + * type.
1329 + */
1330 +static void init_fslspclksel(dwc_otg_core_if_t *_core_if)
1331 +{
1332 + uint32_t val;
1333 + hcfg_data_t hcfg;
1334 +
1335 + if (((_core_if->hwcfg2.b.hs_phy_type == 2) &&
1336 + (_core_if->hwcfg2.b.fs_phy_type == 1) &&
1337 + (_core_if->core_params->ulpi_fs_ls)) ||
1338 + (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS))
1339 + {
1340 + /* Full speed PHY */
1341 + val = DWC_HCFG_48_MHZ;
1342 + } else {
1343 + /* High speed PHY running at full speed or high speed */
1344 + val = DWC_HCFG_30_60_MHZ;
1345 + }
1346 +
1347 + DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
1348 + hcfg.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hcfg);
1349 + hcfg.b.fslspclksel = val;
1350 + dwc_write_reg32(&_core_if->host_if->host_global_regs->hcfg, hcfg.d32);
1351 +}
1352 +
1353 +/**
1354 + * Initializes the DevSpd field of the DCFG register depending on the PHY type
1355 + * and the enumeration speed of the device.
1356 + */
1357 +static void init_devspd(dwc_otg_core_if_t *_core_if)
1358 +{
1359 + uint32_t val;
1360 + dcfg_data_t dcfg;
1361 +
1362 + if (((_core_if->hwcfg2.b.hs_phy_type == 2) &&
1363 + (_core_if->hwcfg2.b.fs_phy_type == 1) &&
1364 + (_core_if->core_params->ulpi_fs_ls)) ||
1365 + (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS))
1366 + {
1367 + /* Full speed PHY */
1368 + val = 0x3;
1369 + } else if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
1370 + /* High speed PHY running at full speed */
1371 + val = 0x1;
1372 + } else {
1373 + /* High speed PHY running at high speed */
1374 + val = 0x0;
1375 + }
1376 +
1377 + DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
1378 + dcfg.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dcfg);
1379 + dcfg.b.devspd = val;
1380 + dwc_write_reg32(&_core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
1381 +}
1382 +
1383 +/**
1384 + * This function calculates the number of IN EPS
1385 + * using GHWCFG1 and GHWCFG2 registers values
1386 + *
1387 + * @param _pcd the pcd structure.
1388 + */
1389 +static uint32_t calc_num_in_eps(dwc_otg_core_if_t * _core_if)
1390 +{
1391 + uint32_t num_in_eps = 0;
1392 + uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep;
1393 + uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2;
1394 + uint32_t num_tx_fifos = _core_if->hwcfg4.b.num_in_eps;
1395 + int i;
1396 + for (i = 0; i < num_eps; ++i) {
1397 + if (!(hwcfg1 & 0x1))
1398 + num_in_eps++;
1399 + hwcfg1 >>= 2;
1400 + }
1401 + if (_core_if->hwcfg4.b.ded_fifo_en) {
1402 + num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
1403 + }
1404 + return num_in_eps;
1405 +}
1406 +
1407 +
1408 +/**
1409 + * This function calculates the number of OUT EPS
1410 + * using GHWCFG1 and GHWCFG2 registers values
1411 + *
1412 + * @param _pcd the pcd structure.
1413 + */
1414 +static uint32_t calc_num_out_eps(dwc_otg_core_if_t * _core_if)
1415 +{
1416 + uint32_t num_out_eps = 0;
1417 + uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep;
1418 + uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2;
1419 + int i;
1420 + for (i = 0; i < num_eps; ++i) {
1421 + if (!(hwcfg1 & 0x2))
1422 + num_out_eps++;
1423 + hwcfg1 >>= 2;
1424 + }
1425 + return num_out_eps;
1426 +}
1427 +/**
1428 + * This function initializes the DWC_otg controller registers and
1429 + * prepares the core for device mode or host mode operation.
1430 + *
1431 + * @param _core_if Programming view of the DWC_otg controller
1432 + *
1433 + */
1434 +void dwc_otg_core_init(dwc_otg_core_if_t *_core_if)
1435 +{
1436 + dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs;
1437 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
1438 + int i = 0;
1439 + gahbcfg_data_t ahbcfg = { .d32 = 0};
1440 + gusbcfg_data_t usbcfg = { .d32 = 0 };
1441 + gi2cctl_data_t i2cctl = {.d32 = 0};
1442 +
1443 + DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n",_core_if);
1444 +
1445 + /* Common Initialization */
1446 +
1447 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1448 + DWC_DEBUGPL(DBG_CIL, "USB config register: 0x%08x\n", usbcfg.d32);
1449 +
1450 + /* Program the ULPI External VBUS bit if needed */
1451 + //usbcfg.b.ulpi_ext_vbus_drv = 1;
1452 + //usbcfg.b.ulpi_ext_vbus_drv = 0;
1453 + usbcfg.b.ulpi_ext_vbus_drv =
1454 + (_core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
1455 +
1456 + /* Set external TS Dline pulsing */
1457 + usbcfg.b.term_sel_dl_pulse = (_core_if->core_params->ts_dline == 1) ? 1 : 0;
1458 + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1459 +
1460 + /* Reset the Controller */
1461 + dwc_otg_core_reset( _core_if );
1462 +
1463 + /* Initialize parameters from Hardware configuration registers. */
1464 +#if 0
1465 + dev_if->num_eps = _core_if->hwcfg2.b.num_dev_ep;
1466 + dev_if->num_perio_eps = _core_if->hwcfg4.b.num_dev_perio_in_ep;
1467 +#else
1468 + dev_if->num_in_eps = calc_num_in_eps(_core_if);
1469 + dev_if->num_out_eps = calc_num_out_eps(_core_if);
1470 +#endif
1471 + DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
1472 + _core_if->hwcfg4.b.num_dev_perio_in_ep);
1473 + DWC_DEBUGPL(DBG_CIL, "Is power optimization enabled? %s\n",
1474 + _core_if->hwcfg4.b.power_optimiz ? "Yes" : "No");
1475 + DWC_DEBUGPL(DBG_CIL, "vbus_valid filter enabled? %s\n",
1476 + _core_if->hwcfg4.b.vbus_valid_filt_en ? "Yes" : "No");
1477 + DWC_DEBUGPL(DBG_CIL, "iddig filter enabled? %s\n",
1478 + _core_if->hwcfg4.b.iddig_filt_en ? "Yes" : "No");
1479 +
1480 + DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",_core_if->hwcfg4.b.num_dev_perio_in_ep);
1481 + for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
1482 + dev_if->perio_tx_fifo_size[i] =
1483 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
1484 + DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", i,
1485 + dev_if->perio_tx_fifo_size[i]);
1486 + }
1487 + for (i = 0; i < _core_if->hwcfg4.b.num_in_eps; i++) {
1488 + dev_if->tx_fifo_size[i] =
1489 + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
1490 + DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", i,
1491 + dev_if->perio_tx_fifo_size[i]);
1492 + }
1493 +
1494 + _core_if->total_fifo_size = _core_if->hwcfg3.b.dfifo_depth;
1495 + _core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz);
1496 + _core_if->nperio_tx_fifo_size = dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
1497 +
1498 + DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", _core_if->total_fifo_size);
1499 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", _core_if->rx_fifo_size);
1500 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", _core_if->nperio_tx_fifo_size);
1501 +
1502 + /* This programming sequence needs to happen in FS mode before any other
1503 + * programming occurs */
1504 + if ((_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
1505 + (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1506 + /* If FS mode with FS PHY */
1507 +
1508 + /* core_init() is now called on every switch so only call the
1509 + * following for the first time through. */
1510 + if (!_core_if->phy_init_done) {
1511 + _core_if->phy_init_done = 1;
1512 + DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
1513 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1514 + usbcfg.b.physel = 1;
1515 + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1516 +
1517 + /* Reset after a PHY select */
1518 + dwc_otg_core_reset( _core_if );
1519 + }
1520 +
1521 + /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1522 + * do this on HNP Dev/Host mode switches (done in dev_init and
1523 + * host_init). */
1524 + if (dwc_otg_is_host_mode(_core_if)) {
1525 + DWC_DEBUGPL(DBG_CIL, "host mode\n");
1526 + init_fslspclksel(_core_if);
1527 + } else {
1528 + DWC_DEBUGPL(DBG_CIL, "device mode\n");
1529 + init_devspd(_core_if);
1530 + }
1531 +
1532 + if (_core_if->core_params->i2c_enable) {
1533 + DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
1534 + /* Program GUSBCFG.OtgUtmifsSel to I2C */
1535 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1536 + usbcfg.b.otgutmifssel = 1;
1537 + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1538 +
1539 + /* Program GI2CCTL.I2CEn */
1540 + i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
1541 + i2cctl.b.i2cdevaddr = 1;
1542 + i2cctl.b.i2cen = 0;
1543 + dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
1544 + i2cctl.b.i2cen = 1;
1545 + dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
1546 + }
1547 +
1548 + } /* endif speed == DWC_SPEED_PARAM_FULL */
1549 + else {
1550 + /* High speed PHY. */
1551 + if (!_core_if->phy_init_done) {
1552 + _core_if->phy_init_done = 1;
1553 + DWC_DEBUGPL(DBG_CIL, "High spped PHY\n");
1554 + /* HS PHY parameters. These parameters are preserved
1555 + * during soft reset so only program the first time. Do
1556 + * a soft reset immediately after setting phyif. */
1557 + usbcfg.b.ulpi_utmi_sel = _core_if->core_params->phy_type;
1558 + if (usbcfg.b.ulpi_utmi_sel == 2) { // winder
1559 + DWC_DEBUGPL(DBG_CIL, "ULPI\n");
1560 + /* ULPI interface */
1561 + usbcfg.b.phyif = 0;
1562 + usbcfg.b.ddrsel = _core_if->core_params->phy_ulpi_ddr;
1563 + } else {
1564 + /* UTMI+ interface */
1565 + if (_core_if->core_params->phy_utmi_width == 16) {
1566 + usbcfg.b.phyif = 1;
1567 + DWC_DEBUGPL(DBG_CIL, "UTMI+ 16\n");
1568 + } else {
1569 + DWC_DEBUGPL(DBG_CIL, "UTMI+ 8\n");
1570 + usbcfg.b.phyif = 0;
1571 + }
1572 + }
1573 + dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32);
1574 +
1575 + /* Reset after setting the PHY parameters */
1576 + dwc_otg_core_reset( _core_if );
1577 + }
1578 + }
1579 +
1580 + if ((_core_if->hwcfg2.b.hs_phy_type == 2) &&
1581 + (_core_if->hwcfg2.b.fs_phy_type == 1) &&
1582 + (_core_if->core_params->ulpi_fs_ls))
1583 + {
1584 + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
1585 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1586 + usbcfg.b.ulpi_fsls = 1;
1587 + usbcfg.b.ulpi_clk_sus_m = 1;
1588 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1589 + } else {
1590 + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS=0\n");
1591 + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1592 + usbcfg.b.ulpi_fsls = 0;
1593 + usbcfg.b.ulpi_clk_sus_m = 0;
1594 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1595 + }
1596 +
1597 + /* Program the GAHBCFG Register.*/
1598 + switch (_core_if->hwcfg2.b.architecture){
1599 +
1600 + case DWC_SLAVE_ONLY_ARCH:
1601 + DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
1602 + ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1603 + ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1604 + _core_if->dma_enable = 0;
1605 + break;
1606 +
1607 + case DWC_EXT_DMA_ARCH:
1608 + DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
1609 + ahbcfg.b.hburstlen = _core_if->core_params->dma_burst_size;
1610 + _core_if->dma_enable = (_core_if->core_params->dma_enable != 0);
1611 + break;
1612 +
1613 + case DWC_INT_DMA_ARCH:
1614 + DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
1615 + //ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR;
1616 + ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR4;
1617 + _core_if->dma_enable = (_core_if->core_params->dma_enable != 0);
1618 + break;
1619 + }
1620 + ahbcfg.b.dmaenable = _core_if->dma_enable;
1621 + dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
1622 + _core_if->en_multiple_tx_fifo = _core_if->hwcfg4.b.ded_fifo_en;
1623 +
1624 + /*
1625 + * Program the GUSBCFG register.
1626 + */
1627 + usbcfg.d32 = dwc_read_reg32( &global_regs->gusbcfg );
1628 +
1629 + switch (_core_if->hwcfg2.b.op_mode) {
1630 + case DWC_MODE_HNP_SRP_CAPABLE:
1631 + usbcfg.b.hnpcap = (_core_if->core_params->otg_cap ==
1632 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1633 + usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
1634 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1635 + break;
1636 +
1637 + case DWC_MODE_SRP_ONLY_CAPABLE:
1638 + usbcfg.b.hnpcap = 0;
1639 + usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
1640 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1641 + break;
1642 +
1643 + case DWC_MODE_NO_HNP_SRP_CAPABLE:
1644 + usbcfg.b.hnpcap = 0;
1645 + usbcfg.b.srpcap = 0;
1646 + break;
1647 +
1648 + case DWC_MODE_SRP_CAPABLE_DEVICE:
1649 + usbcfg.b.hnpcap = 0;
1650 + usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
1651 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1652 + break;
1653 +
1654 + case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
1655 + usbcfg.b.hnpcap = 0;
1656 + usbcfg.b.srpcap = 0;
1657 + break;
1658 +
1659 + case DWC_MODE_SRP_CAPABLE_HOST:
1660 + usbcfg.b.hnpcap = 0;
1661 + usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
1662 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1663 + break;
1664 +
1665 + case DWC_MODE_NO_SRP_CAPABLE_HOST:
1666 + usbcfg.b.hnpcap = 0;
1667 + usbcfg.b.srpcap = 0;
1668 + break;
1669 + }
1670 +
1671 + dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32);
1672 +
1673 + /* Enable common interrupts */
1674 + dwc_otg_enable_common_interrupts( _core_if );
1675 +
1676 + /* Do device or host intialization based on mode during PCD
1677 + * and HCD initialization */
1678 + if (dwc_otg_is_host_mode( _core_if )) {
1679 + DWC_DEBUGPL(DBG_ANY, "Host Mode\n" );
1680 + _core_if->op_state = A_HOST;
1681 + } else {
1682 + DWC_DEBUGPL(DBG_ANY, "Device Mode\n" );
1683 + _core_if->op_state = B_PERIPHERAL;
1684 +#ifdef DWC_DEVICE_ONLY
1685 + dwc_otg_core_dev_init( _core_if );
1686 +#endif
1687 + }
1688 +}
1689 +
1690 +
1691 +/**
1692 + * This function enables the Device mode interrupts.
1693 + *
1694 + * @param _core_if Programming view of DWC_otg controller
1695 + */
1696 +void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if)
1697 +{
1698 + gintmsk_data_t intr_mask = { .d32 = 0};
1699 + dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs;
1700 +
1701 + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
1702 +
1703 + /* Disable all interrupts. */
1704 + dwc_write_reg32( &global_regs->gintmsk, 0);
1705 +
1706 + /* Clear any pending interrupts */
1707 + dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF);
1708 +
1709 + /* Enable the common interrupts */
1710 + dwc_otg_enable_common_interrupts( _core_if );
1711 +
1712 + /* Enable interrupts */
1713 + intr_mask.b.usbreset = 1;
1714 + intr_mask.b.enumdone = 1;
1715 + //intr_mask.b.epmismatch = 1;
1716 + intr_mask.b.inepintr = 1;
1717 + intr_mask.b.outepintr = 1;
1718 + intr_mask.b.erlysuspend = 1;
1719 + if (_core_if->en_multiple_tx_fifo == 0) {
1720 + intr_mask.b.epmismatch = 1;
1721 + }
1722 +
1723 + /** @todo NGS: Should this be a module parameter? */
1724 + intr_mask.b.isooutdrop = 1;
1725 + intr_mask.b.eopframe = 1;
1726 + intr_mask.b.incomplisoin = 1;
1727 + intr_mask.b.incomplisoout = 1;
1728 +
1729 + dwc_modify_reg32( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1730 +
1731 + DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
1732 + dwc_read_reg32( &global_regs->gintmsk));
1733 +}
1734 +
1735 +/**
1736 + * This function initializes the DWC_otg controller registers for
1737 + * device mode.
1738 + *
1739 + * @param _core_if Programming view of DWC_otg controller
1740 + *
1741 + */
1742 +void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if)
1743 +{
1744 + dwc_otg_core_global_regs_t *global_regs =
1745 + _core_if->core_global_regs;
1746 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
1747 + dwc_otg_core_params_t *params = _core_if->core_params;
1748 + dcfg_data_t dcfg = {.d32 = 0};
1749 + grstctl_t resetctl = { .d32=0 };
1750 + int i;
1751 + uint32_t rx_fifo_size;
1752 + fifosize_data_t nptxfifosize;
1753 + fifosize_data_t txfifosize;
1754 + dthrctl_data_t dthrctl;
1755 +
1756 + fifosize_data_t ptxfifosize;
1757 +
1758 + /* Restart the Phy Clock */
1759 + dwc_write_reg32(_core_if->pcgcctl, 0);
1760 +
1761 + /* Device configuration register */
1762 + init_devspd(_core_if);
1763 + dcfg.d32 = dwc_read_reg32( &dev_if->dev_global_regs->dcfg);
1764 + dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
1765 + dwc_write_reg32( &dev_if->dev_global_regs->dcfg, dcfg.d32 );
1766 +
1767 + /* Configure data FIFO sizes */
1768 + if ( _core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo ) {
1769 +
1770 + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", _core_if->total_fifo_size);
1771 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size);
1772 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size);
1773 +
1774 + /* Rx FIFO */
1775 + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
1776 + dwc_read_reg32(&global_regs->grxfsiz));
1777 + rx_fifo_size = params->dev_rx_fifo_size;
1778 + dwc_write_reg32( &global_regs->grxfsiz, rx_fifo_size );
1779 + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
1780 + dwc_read_reg32(&global_regs->grxfsiz));
1781 +
1782 + /** Set Periodic Tx FIFO Mask all bits 0 */
1783 + _core_if->p_tx_msk = 0;
1784 +
1785 + /** Set Tx FIFO Mask all bits 0 */
1786 + _core_if->tx_msk = 0;
1787 + if (_core_if->en_multiple_tx_fifo == 0) {
1788 + /* Non-periodic Tx FIFO */
1789 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
1790 + dwc_read_reg32(&global_regs->gnptxfsiz));
1791 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
1792 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
1793 + dwc_write_reg32( &global_regs->gnptxfsiz, nptxfifosize.d32 );
1794 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
1795 + dwc_read_reg32(&global_regs->gnptxfsiz));
1796 +
1797 +
1798 + /**@todo NGS: Fix Periodic FIFO Sizing! */
1799 + /*
1800 + * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
1801 + * Indexes of the FIFO size module parameters in the
1802 + * dev_perio_tx_fifo_size array and the FIFO size registers in
1803 + * the dptxfsiz array run from 0 to 14.
1804 + */
1805 + /** @todo Finish debug of this */
1806 + ptxfifosize.b.startaddr =
1807 + nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1808 + for (i = 0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) {
1809 + ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i];
1810 + DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n",
1811 + i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
1812 + dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],ptxfifosize.d32);
1813 + DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n",
1814 + i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
1815 + ptxfifosize.b.startaddr += ptxfifosize.b.depth;
1816 + }
1817 + } else {
1818 +
1819 + /*
1820 + * Tx FIFOs These FIFOs are numbered from 1 to 15.
1821 + * Indexes of the FIFO size module parameters in the
1822 + * dev_tx_fifo_size array and the FIFO size registers in
1823 + * the dptxfsiz_dieptxf array run from 0 to 14.
1824 + */
1825 +
1826 + /* Non-periodic Tx FIFO */
1827 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
1828 + dwc_read_reg32(&global_regs->gnptxfsiz));
1829 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
1830 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
1831 + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
1832 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
1833 + dwc_read_reg32(&global_regs->gnptxfsiz));
1834 + txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1835 + for (i = 1;i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) {
1836 + txfifosize.b.depth = params->dev_tx_fifo_size[i];
1837 + DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n",
1838 + i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
1839 + dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i - 1],txfifosize.d32);
1840 + DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n",
1841 + i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1]));
1842 + txfifosize.b.startaddr += txfifosize.b.depth;
1843 + }
1844 + }
1845 + }
1846 + /* Flush the FIFOs */
1847 + dwc_otg_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */
1848 + dwc_otg_flush_rx_fifo(_core_if);
1849 +
1850 + /* Flush the Learning Queue. */
1851 + resetctl.b.intknqflsh = 1;
1852 + dwc_write_reg32( &_core_if->core_global_regs->grstctl, resetctl.d32);
1853 +
1854 + /* Clear all pending Device Interrupts */
1855 + dwc_write_reg32( &dev_if->dev_global_regs->diepmsk, 0 );
1856 + dwc_write_reg32( &dev_if->dev_global_regs->doepmsk, 0 );
1857 + dwc_write_reg32( &dev_if->dev_global_regs->daint, 0xFFFFFFFF );
1858 + dwc_write_reg32( &dev_if->dev_global_regs->daintmsk, 0 );
1859 +
1860 + for (i = 0; i <= dev_if->num_in_eps; i++) {
1861 + depctl_data_t depctl;
1862 + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
1863 + if (depctl.b.epena) {
1864 + depctl.d32 = 0;
1865 + depctl.b.epdis = 1;
1866 + depctl.b.snak = 1;
1867 + } else {
1868 + depctl.d32 = 0;
1869 + }
1870 + dwc_write_reg32( &dev_if->in_ep_regs[i]->diepctl, depctl.d32);
1871 +
1872 + dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
1873 + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
1874 + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
1875 + }
1876 + for (i = 0; i <= dev_if->num_out_eps; i++) {
1877 + depctl_data_t depctl;
1878 + depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
1879 + if (depctl.b.epena) {
1880 + depctl.d32 = 0;
1881 + depctl.b.epdis = 1;
1882 + depctl.b.snak = 1;
1883 + } else {
1884 + depctl.d32 = 0;
1885 + }
1886 + dwc_write_reg32( &dev_if->out_ep_regs[i]->doepctl, depctl.d32);
1887 +
1888 + //dwc_write_reg32( &dev_if->in_ep_regs[i]->dieptsiz, 0);
1889 + dwc_write_reg32( &dev_if->out_ep_regs[i]->doeptsiz, 0);
1890 + //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepdma, 0);
1891 + dwc_write_reg32( &dev_if->out_ep_regs[i]->doepdma, 0);
1892 + //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepint, 0xFF);
1893 + dwc_write_reg32( &dev_if->out_ep_regs[i]->doepint, 0xFF);
1894 + }
1895 +
1896 + if (_core_if->en_multiple_tx_fifo && _core_if->dma_enable) {
1897 + dev_if->non_iso_tx_thr_en = _core_if->core_params->thr_ctl & 0x1;
1898 + dev_if->iso_tx_thr_en = (_core_if->core_params->thr_ctl >> 1) & 0x1;
1899 + dev_if->rx_thr_en = (_core_if->core_params->thr_ctl >> 2) & 0x1;
1900 + dev_if->rx_thr_length = _core_if->core_params->rx_thr_length;
1901 + dev_if->tx_thr_length = _core_if->core_params->tx_thr_length;
1902 + dthrctl.d32 = 0;
1903 + dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
1904 + dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
1905 + dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
1906 + dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
1907 + dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
1908 + dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl,dthrctl.d32);
1909 + DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\n"
1910 + "Rx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
1911 + dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
1912 + dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
1913 + dthrctl.b.rx_thr_len);
1914 + }
1915 + dwc_otg_enable_device_interrupts( _core_if );
1916 + {
1917 + diepmsk_data_t msk = {.d32 = 0};
1918 + msk.b.txfifoundrn = 1;
1919 + dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32,msk.d32);
1920 +}
1921 +}
1922 +
1923 +/**
1924 + * This function enables the Host mode interrupts.
1925 + *
1926 + * @param _core_if Programming view of DWC_otg controller
1927 + */
1928 +void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if)
1929 +{
1930 + dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
1931 + gintmsk_data_t intr_mask = {.d32 = 0};
1932 +
1933 + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
1934 +
1935 + /* Disable all interrupts. */
1936 + dwc_write_reg32(&global_regs->gintmsk, 0);
1937 +
1938 + /* Clear any pending interrupts. */
1939 + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
1940 +
1941 + /* Enable the common interrupts */
1942 + dwc_otg_enable_common_interrupts(_core_if);
1943 +
1944 + /*
1945 + * Enable host mode interrupts without disturbing common
1946 + * interrupts.
1947 + */
1948 + intr_mask.b.sofintr = 1;
1949 + intr_mask.b.portintr = 1;
1950 + intr_mask.b.hcintr = 1;
1951 +
1952 + //dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1953 + //dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
1954 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1955 +}
1956 +
1957 +/**
1958 + * This function disables the Host Mode interrupts.
1959 + *
1960 + * @param _core_if Programming view of DWC_otg controller
1961 + */
1962 +void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if)
1963 +{
1964 + dwc_otg_core_global_regs_t *global_regs =
1965 + _core_if->core_global_regs;
1966 + gintmsk_data_t intr_mask = {.d32 = 0};
1967 +
1968 + DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
1969 +
1970 + /*
1971 + * Disable host mode interrupts without disturbing common
1972 + * interrupts.
1973 + */
1974 + intr_mask.b.sofintr = 1;
1975 + intr_mask.b.portintr = 1;
1976 + intr_mask.b.hcintr = 1;
1977 + intr_mask.b.ptxfempty = 1;
1978 + intr_mask.b.nptxfempty = 1;
1979 +
1980 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
1981 +}
1982 +
1983 +#if 0
1984 +/* currently not used, keep it here as if needed later */
1985 +static int phy_read(dwc_otg_core_if_t * _core_if, int addr)
1986 +{
1987 + u32 val;
1988 + int timeout = 10;
1989 +
1990 + dwc_write_reg32(&_core_if->core_global_regs->gpvndctl,
1991 + 0x02000000 | (addr << 16));
1992 + val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl);
1993 + while (((val & 0x08000000) == 0) && (timeout--)) {
1994 + udelay(1000);
1995 + val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl);
1996 + }
1997 + val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl);
1998 + printk("%s: addr=%02x regval=%02x\n", __func__, addr, val & 0x000000ff);
1999 +
2000 + return 0;
2001 +}
2002 +#endif
2003 +
2004 +/**
2005 + * This function initializes the DWC_otg controller registers for
2006 + * host mode.
2007 + *
2008 + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
2009 + * request queues. Host channels are reset to ensure that they are ready for
2010 + * performing transfers.
2011 + *
2012 + * @param _core_if Programming view of DWC_otg controller
2013 + *
2014 + */
2015 +void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if)
2016 +{
2017 + dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
2018 + dwc_otg_host_if_t *host_if = _core_if->host_if;
2019 + dwc_otg_core_params_t *params = _core_if->core_params;
2020 + hprt0_data_t hprt0 = {.d32 = 0};
2021 + fifosize_data_t nptxfifosize;
2022 + fifosize_data_t ptxfifosize;
2023 + int i;
2024 + hcchar_data_t hcchar;
2025 + hcfg_data_t hcfg;
2026 + dwc_otg_hc_regs_t *hc_regs;
2027 + int num_channels;
2028 + gotgctl_data_t gotgctl = {.d32 = 0};
2029 +
2030 + DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, _core_if);
2031 +
2032 + /* Restart the Phy Clock */
2033 + dwc_write_reg32(_core_if->pcgcctl, 0);
2034 +
2035 + /* Initialize Host Configuration Register */
2036 + init_fslspclksel(_core_if);
2037 + if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
2038 + hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
2039 + hcfg.b.fslssupp = 1;
2040 + dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
2041 + }
2042 +
2043 + /* Configure data FIFO sizes */
2044 + if (_core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
2045 + DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", _core_if->total_fifo_size);
2046 + DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size);
2047 + DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size);
2048 + DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size);
2049 +
2050 + /* Rx FIFO */
2051 + DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
2052 + dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size);
2053 + DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
2054 +
2055 + /* Non-periodic Tx FIFO */
2056 + DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
2057 + nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
2058 + nptxfifosize.b.startaddr = params->host_rx_fifo_size;
2059 + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
2060 + DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
2061 +
2062 + /* Periodic Tx FIFO */
2063 + DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
2064 + ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
2065 + ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
2066 + dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
2067 + DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
2068 + }
2069 +
2070 + /* Clear Host Set HNP Enable in the OTG Control Register */
2071 + gotgctl.b.hstsethnpen = 1;
2072 + dwc_modify_reg32( &global_regs->gotgctl, gotgctl.d32, 0);
2073 +
2074 + /* Make sure the FIFOs are flushed. */
2075 + dwc_otg_flush_tx_fifo(_core_if, 0x10 /* all Tx FIFOs */);
2076 + dwc_otg_flush_rx_fifo(_core_if);
2077 +
2078 + /* Flush out any leftover queued requests. */
2079 + num_channels = _core_if->core_params->host_channels;
2080 + for (i = 0; i < num_channels; i++) {
2081 + hc_regs = _core_if->host_if->hc_regs[i];
2082 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2083 + hcchar.b.chen = 0;
2084 + hcchar.b.chdis = 1;
2085 + hcchar.b.epdir = 0;
2086 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2087 + }
2088 +
2089 + /* Halt all channels to put them into a known state. */
2090 + for (i = 0; i < num_channels; i++) {
2091 + int count = 0;
2092 + hc_regs = _core_if->host_if->hc_regs[i];
2093 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2094 + hcchar.b.chen = 1;
2095 + hcchar.b.chdis = 1;
2096 + hcchar.b.epdir = 0;
2097 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2098 + DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
2099 + do {
2100 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2101 + if (++count > 200) {
2102 + DWC_ERROR("%s: Unable to clear halt on channel %d\n",
2103 + __func__, i);
2104 + break;
2105 + }
2106 + udelay(100);
2107 + } while (hcchar.b.chen);
2108 + }
2109 +
2110 + /* Turn on the vbus power. */
2111 + DWC_PRINT("Init: Port Power? op_state=%d\n", _core_if->op_state);
2112 + if (_core_if->op_state == A_HOST){
2113 + hprt0.d32 = dwc_otg_read_hprt0(_core_if);
2114 + DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2115 + if (hprt0.b.prtpwr == 0 ) {
2116 + hprt0.b.prtpwr = 1;
2117 + dwc_write_reg32(host_if->hprt0, hprt0.d32);
2118 + }
2119 + }
2120 +
2121 + dwc_otg_enable_host_interrupts( _core_if );
2122 +}
2123 +
2124 +/**
2125 + * Prepares a host channel for transferring packets to/from a specific
2126 + * endpoint. The HCCHARn register is set up with the characteristics specified
2127 + * in _hc. Host channel interrupts that may need to be serviced while this
2128 + * transfer is in progress are enabled.
2129 + *
2130 + * @param _core_if Programming view of DWC_otg controller
2131 + * @param _hc Information needed to initialize the host channel
2132 + */
2133 +void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2134 +{
2135 + uint32_t intr_enable;
2136 + hcintmsk_data_t hc_intr_mask;
2137 + gintmsk_data_t gintmsk = {.d32 = 0};
2138 + hcchar_data_t hcchar;
2139 + hcsplt_data_t hcsplt;
2140 +
2141 + uint8_t hc_num = _hc->hc_num;
2142 + dwc_otg_host_if_t *host_if = _core_if->host_if;
2143 + dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
2144 +
2145 + /* Clear old interrupt conditions for this host channel. */
2146 + hc_intr_mask.d32 = 0xFFFFFFFF;
2147 + hc_intr_mask.b.reserved = 0;
2148 + dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
2149 +
2150 + /* Enable channel interrupts required for this transfer. */
2151 + hc_intr_mask.d32 = 0;
2152 + hc_intr_mask.b.chhltd = 1;
2153 + if (_core_if->dma_enable) {
2154 + hc_intr_mask.b.ahberr = 1;
2155 + if (_hc->error_state && !_hc->do_split &&
2156 + _hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
2157 + hc_intr_mask.b.ack = 1;
2158 + if (_hc->ep_is_in) {
2159 + hc_intr_mask.b.datatglerr = 1;
2160 + if (_hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
2161 + hc_intr_mask.b.nak = 1;
2162 + }
2163 + }
2164 + }
2165 + } else {
2166 + switch (_hc->ep_type) {
2167 + case DWC_OTG_EP_TYPE_CONTROL:
2168 + case DWC_OTG_EP_TYPE_BULK:
2169 + hc_intr_mask.b.xfercompl = 1;
2170 + hc_intr_mask.b.stall = 1;
2171 + hc_intr_mask.b.xacterr = 1;
2172 + hc_intr_mask.b.datatglerr = 1;
2173 + if (_hc->ep_is_in) {
2174 + hc_intr_mask.b.bblerr = 1;
2175 + } else {
2176 + hc_intr_mask.b.nak = 1;
2177 + hc_intr_mask.b.nyet = 1;
2178 + if (_hc->do_ping) {
2179 + hc_intr_mask.b.ack = 1;
2180 + }
2181 + }
2182 +
2183 + if (_hc->do_split) {
2184 + hc_intr_mask.b.nak = 1;
2185 + if (_hc->complete_split) {
2186 + hc_intr_mask.b.nyet = 1;
2187 + }
2188 + else {
2189 + hc_intr_mask.b.ack = 1;
2190 + }
2191 + }
2192 +
2193 + if (_hc->error_state) {
2194 + hc_intr_mask.b.ack = 1;
2195 + }
2196 + break;
2197 + case DWC_OTG_EP_TYPE_INTR:
2198 + hc_intr_mask.b.xfercompl = 1;
2199 + hc_intr_mask.b.nak = 1;
2200 + hc_intr_mask.b.stall = 1;
2201 + hc_intr_mask.b.xacterr = 1;
2202 + hc_intr_mask.b.datatglerr = 1;
2203 + hc_intr_mask.b.frmovrun = 1;
2204 +
2205 + if (_hc->ep_is_in) {
2206 + hc_intr_mask.b.bblerr = 1;
2207 + }
2208 + if (_hc->error_state) {
2209 + hc_intr_mask.b.ack = 1;
2210 + }
2211 + if (_hc->do_split) {
2212 + if (_hc->complete_split) {
2213 + hc_intr_mask.b.nyet = 1;
2214 + }
2215 + else {
2216 + hc_intr_mask.b.ack = 1;
2217 + }
2218 + }
2219 + break;
2220 + case DWC_OTG_EP_TYPE_ISOC:
2221 + hc_intr_mask.b.xfercompl = 1;
2222 + hc_intr_mask.b.frmovrun = 1;
2223 + hc_intr_mask.b.ack = 1;
2224 +
2225 + if (_hc->ep_is_in) {
2226 + hc_intr_mask.b.xacterr = 1;
2227 + hc_intr_mask.b.bblerr = 1;
2228 + }
2229 + break;
2230 + }
2231 + }
2232 + dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
2233 +
2234 + /* Enable the top level host channel interrupt. */
2235 + intr_enable = (1 << hc_num);
2236 + dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
2237 +
2238 + /* Make sure host channel interrupts are enabled. */
2239 + gintmsk.b.hcintr = 1;
2240 + dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
2241 +
2242 + /*
2243 + * Program the HCCHARn register with the endpoint characteristics for
2244 + * the current transfer.
2245 + */
2246 + hcchar.d32 = 0;
2247 + hcchar.b.devaddr = _hc->dev_addr;
2248 + hcchar.b.epnum = _hc->ep_num;
2249 + hcchar.b.epdir = _hc->ep_is_in;
2250 + hcchar.b.lspddev = (_hc->speed == DWC_OTG_EP_SPEED_LOW);
2251 + hcchar.b.eptype = _hc->ep_type;
2252 + hcchar.b.mps = _hc->max_packet;
2253 +
2254 + dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
2255 +
2256 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
2257 + DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr);
2258 + DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum);
2259 + DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir);
2260 + DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev);
2261 + DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype);
2262 + DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
2263 + DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt);
2264 +
2265 + /*
2266 + * Program the HCSPLIT register for SPLITs
2267 + */
2268 + hcsplt.d32 = 0;
2269 + if (_hc->do_split) {
2270 + DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", _hc->hc_num,
2271 + _hc->complete_split ? "CSPLIT" : "SSPLIT");
2272 + hcsplt.b.compsplt = _hc->complete_split;
2273 + hcsplt.b.xactpos = _hc->xact_pos;
2274 + hcsplt.b.hubaddr = _hc->hub_addr;
2275 + hcsplt.b.prtaddr = _hc->port_addr;
2276 + DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", _hc->complete_split);
2277 + DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", _hc->xact_pos);
2278 + DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", _hc->hub_addr);
2279 + DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", _hc->port_addr);
2280 + DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", _hc->ep_is_in);
2281 + DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
2282 + DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", _hc->xfer_len);
2283 + }
2284 + dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
2285 +
2286 +}
2287 +
2288 +/**
2289 + * Attempts to halt a host channel. This function should only be called in
2290 + * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
2291 + * normal circumstances in DMA mode, the controller halts the channel when the
2292 + * transfer is complete or a condition occurs that requires application
2293 + * intervention.
2294 + *
2295 + * In slave mode, checks for a free request queue entry, then sets the Channel
2296 + * Enable and Channel Disable bits of the Host Channel Characteristics
2297 + * register of the specified channel to intiate the halt. If there is no free
2298 + * request queue entry, sets only the Channel Disable bit of the HCCHARn
2299 + * register to flush requests for this channel. In the latter case, sets a
2300 + * flag to indicate that the host channel needs to be halted when a request
2301 + * queue slot is open.
2302 + *
2303 + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
2304 + * HCCHARn register. The controller ensures there is space in the request
2305 + * queue before submitting the halt request.
2306 + *
2307 + * Some time may elapse before the core flushes any posted requests for this
2308 + * host channel and halts. The Channel Halted interrupt handler completes the
2309 + * deactivation of the host channel.
2310 + *
2311 + * @param _core_if Controller register interface.
2312 + * @param _hc Host channel to halt.
2313 + * @param _halt_status Reason for halting the channel.
2314 + */
2315 +void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
2316 + dwc_hc_t *_hc,
2317 + dwc_otg_halt_status_e _halt_status)
2318 +{
2319 + gnptxsts_data_t nptxsts;
2320 + hptxsts_data_t hptxsts;
2321 + hcchar_data_t hcchar;
2322 + dwc_otg_hc_regs_t *hc_regs;
2323 + dwc_otg_core_global_regs_t *global_regs;
2324 + dwc_otg_host_global_regs_t *host_global_regs;
2325 +
2326 + hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2327 + global_regs = _core_if->core_global_regs;
2328 + host_global_regs = _core_if->host_if->host_global_regs;
2329 +
2330 + WARN_ON(_halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS);
2331 +
2332 + if (_halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
2333 + _halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
2334 + /*
2335 + * Disable all channel interrupts except Ch Halted. The QTD
2336 + * and QH state associated with this transfer has been cleared
2337 + * (in the case of URB_DEQUEUE), so the channel needs to be
2338 + * shut down carefully to prevent crashes.
2339 + */
2340 + hcintmsk_data_t hcintmsk;
2341 + hcintmsk.d32 = 0;
2342 + hcintmsk.b.chhltd = 1;
2343 + dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
2344 +
2345 + /*
2346 + * Make sure no other interrupts besides halt are currently
2347 + * pending. Handling another interrupt could cause a crash due
2348 + * to the QTD and QH state.
2349 + */
2350 + dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
2351 +
2352 + /*
2353 + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
2354 + * even if the channel was already halted for some other
2355 + * reason.
2356 + */
2357 + _hc->halt_status = _halt_status;
2358 +
2359 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2360 + if (hcchar.b.chen == 0) {
2361 + /*
2362 + * The channel is either already halted or it hasn't
2363 + * started yet. In DMA mode, the transfer may halt if
2364 + * it finishes normally or a condition occurs that
2365 + * requires driver intervention. Don't want to halt
2366 + * the channel again. In either Slave or DMA mode,
2367 + * it's possible that the transfer has been assigned
2368 + * to a channel, but not started yet when an URB is
2369 + * dequeued. Don't want to halt a channel that hasn't
2370 + * started yet.
2371 + */
2372 + return;
2373 + }
2374 + }
2375 +
2376 + if (_hc->halt_pending) {
2377 + /*
2378 + * A halt has already been issued for this channel. This might
2379 + * happen when a transfer is aborted by a higher level in
2380 + * the stack.
2381 + */
2382 +#ifdef DEBUG
2383 + DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n",
2384 + __func__, _hc->hc_num);
2385 +
2386 +/* dwc_otg_dump_global_registers(_core_if); */
2387 +/* dwc_otg_dump_host_registers(_core_if); */
2388 +#endif
2389 + return;
2390 + }
2391 +
2392 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2393 + hcchar.b.chen = 1;
2394 + hcchar.b.chdis = 1;
2395 +
2396 + if (!_core_if->dma_enable) {
2397 + /* Check for space in the request queue to issue the halt. */
2398 + if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
2399 + _hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
2400 + nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2401 + if (nptxsts.b.nptxqspcavail == 0) {
2402 + hcchar.b.chen = 0;
2403 + }
2404 + } else {
2405 + hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts);
2406 + if ((hptxsts.b.ptxqspcavail == 0) || (_core_if->queuing_high_bandwidth)) {
2407 + hcchar.b.chen = 0;
2408 + }
2409 + }
2410 + }
2411 +
2412 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2413 +
2414 + _hc->halt_status = _halt_status;
2415 +
2416 + if (hcchar.b.chen) {
2417 + _hc->halt_pending = 1;
2418 + _hc->halt_on_queue = 0;
2419 + } else {
2420 + _hc->halt_on_queue = 1;
2421 + }
2422 +
2423 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
2424 + DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
2425 + DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", _hc->halt_pending);
2426 + DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", _hc->halt_on_queue);
2427 + DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", _hc->halt_status);
2428 +
2429 + return;
2430 +}
2431 +
2432 +/**
2433 + * Clears the transfer state for a host channel. This function is normally
2434 + * called after a transfer is done and the host channel is being released.
2435 + *
2436 + * @param _core_if Programming view of DWC_otg controller.
2437 + * @param _hc Identifies the host channel to clean up.
2438 + */
2439 +void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2440 +{
2441 + dwc_otg_hc_regs_t *hc_regs;
2442 +
2443 + _hc->xfer_started = 0;
2444 +
2445 + /*
2446 + * Clear channel interrupt enables and any unhandled channel interrupt
2447 + * conditions.
2448 + */
2449 + hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2450 + dwc_write_reg32(&hc_regs->hcintmsk, 0);
2451 + dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
2452 +
2453 +#ifdef DEBUG
2454 + del_timer(&_core_if->hc_xfer_timer[_hc->hc_num]);
2455 + {
2456 + hcchar_data_t hcchar;
2457 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2458 + if (hcchar.b.chdis) {
2459 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2460 + __func__, _hc->hc_num, hcchar.d32);
2461 + }
2462 + }
2463 +#endif
2464 +}
2465 +
2466 +/**
2467 + * Sets the channel property that indicates in which frame a periodic transfer
2468 + * should occur. This is always set to the _next_ frame. This function has no
2469 + * effect on non-periodic transfers.
2470 + *
2471 + * @param _core_if Programming view of DWC_otg controller.
2472 + * @param _hc Identifies the host channel to set up and its properties.
2473 + * @param _hcchar Current value of the HCCHAR register for the specified host
2474 + * channel.
2475 + */
2476 +static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *_core_if,
2477 + dwc_hc_t *_hc,
2478 + hcchar_data_t *_hcchar)
2479 +{
2480 + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2481 + _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2482 + hfnum_data_t hfnum;
2483 + hfnum.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hfnum);
2484 + /* 1 if _next_ frame is odd, 0 if it's even */
2485 + _hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
2486 +#ifdef DEBUG
2487 + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR && _hc->do_split && !_hc->complete_split) {
2488 + switch (hfnum.b.frnum & 0x7) {
2489 + case 7:
2490 + _core_if->hfnum_7_samples++;
2491 + _core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
2492 + break;
2493 + case 0:
2494 + _core_if->hfnum_0_samples++;
2495 + _core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
2496 + break;
2497 + default:
2498 + _core_if->hfnum_other_samples++;
2499 + _core_if->hfnum_other_frrem_accum += hfnum.b.frrem;
2500 + break;
2501 + }
2502 + }
2503 +#endif
2504 + }
2505 +}
2506 +
2507 +#ifdef DEBUG
2508 +static void hc_xfer_timeout(unsigned long _ptr)
2509 +{
2510 + hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)_ptr;
2511 + int hc_num = xfer_info->hc->hc_num;
2512 + DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
2513 + DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]);
2514 +}
2515 +#endif
2516 +
2517 +/*
2518 + * This function does the setup for a data transfer for a host channel and
2519 + * starts the transfer. May be called in either Slave mode or DMA mode. In
2520 + * Slave mode, the caller must ensure that there is sufficient space in the
2521 + * request queue and Tx Data FIFO.
2522 + *
2523 + * For an OUT transfer in Slave mode, it loads a data packet into the
2524 + * appropriate FIFO. If necessary, additional data packets will be loaded in
2525 + * the Host ISR.
2526 + *
2527 + * For an IN transfer in Slave mode, a data packet is requested. The data
2528 + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
2529 + * additional data packets are requested in the Host ISR.
2530 + *
2531 + * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
2532 + * register along with a packet count of 1 and the channel is enabled. This
2533 + * causes a single PING transaction to occur. Other fields in HCTSIZ are
2534 + * simply set to 0 since no data transfer occurs in this case.
2535 + *
2536 + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
2537 + * all the information required to perform the subsequent data transfer. In
2538 + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
2539 + * controller performs the entire PING protocol, then starts the data
2540 + * transfer.
2541 + *
2542 + * @param _core_if Programming view of DWC_otg controller.
2543 + * @param _hc Information needed to initialize the host channel. The xfer_len
2544 + * value may be reduced to accommodate the max widths of the XferSize and
2545 + * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
2546 + * to reflect the final xfer_len value.
2547 + */
2548 +void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2549 +{
2550 + hcchar_data_t hcchar;
2551 + hctsiz_data_t hctsiz;
2552 + uint16_t num_packets;
2553 + uint32_t max_hc_xfer_size = _core_if->core_params->max_transfer_size;
2554 + uint16_t max_hc_pkt_count = _core_if->core_params->max_packet_count;
2555 + dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2556 +
2557 + hctsiz.d32 = 0;
2558 +
2559 + if (_hc->do_ping) {
2560 + if (!_core_if->dma_enable) {
2561 + dwc_otg_hc_do_ping(_core_if, _hc);
2562 + _hc->xfer_started = 1;
2563 + return;
2564 + } else {
2565 + hctsiz.b.dopng = 1;
2566 + }
2567 + }
2568 +
2569 + if (_hc->do_split) {
2570 + num_packets = 1;
2571 +
2572 + if (_hc->complete_split && !_hc->ep_is_in) {
2573 + /* For CSPLIT OUT Transfer, set the size to 0 so the
2574 + * core doesn't expect any data written to the FIFO */
2575 + _hc->xfer_len = 0;
2576 + } else if (_hc->ep_is_in || (_hc->xfer_len > _hc->max_packet)) {
2577 + _hc->xfer_len = _hc->max_packet;
2578 + } else if (!_hc->ep_is_in && (_hc->xfer_len > 188)) {
2579 + _hc->xfer_len = 188;
2580 + }
2581 +
2582 + hctsiz.b.xfersize = _hc->xfer_len;
2583 + } else {
2584 + /*
2585 + * Ensure that the transfer length and packet count will fit
2586 + * in the widths allocated for them in the HCTSIZn register.
2587 + */
2588 + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2589 + _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2590 + /*
2591 + * Make sure the transfer size is no larger than one
2592 + * (micro)frame's worth of data. (A check was done
2593 + * when the periodic transfer was accepted to ensure
2594 + * that a (micro)frame's worth of data can be
2595 + * programmed into a channel.)
2596 + */
2597 + uint32_t max_periodic_len = _hc->multi_count * _hc->max_packet;
2598 + if (_hc->xfer_len > max_periodic_len) {
2599 + _hc->xfer_len = max_periodic_len;
2600 + } else {
2601 + }
2602 + } else if (_hc->xfer_len > max_hc_xfer_size) {
2603 + /* Make sure that xfer_len is a multiple of max packet size. */
2604 + _hc->xfer_len = max_hc_xfer_size - _hc->max_packet + 1;
2605 + }
2606 +
2607 + if (_hc->xfer_len > 0) {
2608 + num_packets = (_hc->xfer_len + _hc->max_packet - 1) / _hc->max_packet;
2609 + if (num_packets > max_hc_pkt_count) {
2610 + num_packets = max_hc_pkt_count;
2611 + _hc->xfer_len = num_packets * _hc->max_packet;
2612 + }
2613 + } else {
2614 + /* Need 1 packet for transfer length of 0. */
2615 + num_packets = 1;
2616 + }
2617 +
2618 + if (_hc->ep_is_in) {
2619 + /* Always program an integral # of max packets for IN transfers. */
2620 + _hc->xfer_len = num_packets * _hc->max_packet;
2621 + }
2622 +
2623 + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2624 + _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2625 + /*
2626 + * Make sure that the multi_count field matches the
2627 + * actual transfer length.
2628 + */
2629 + _hc->multi_count = num_packets;
2630 +
2631 + }
2632 +
2633 + if (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2634 + /* Set up the initial PID for the transfer. */
2635 + if (_hc->speed == DWC_OTG_EP_SPEED_HIGH) {
2636 + if (_hc->ep_is_in) {
2637 + if (_hc->multi_count == 1) {
2638 + _hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2639 + } else if (_hc->multi_count == 2) {
2640 + _hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2641 + } else {
2642 + _hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
2643 + }
2644 + } else {
2645 + if (_hc->multi_count == 1) {
2646 + _hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2647 + } else {
2648 + _hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
2649 + }
2650 + }
2651 + } else {
2652 + _hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2653 + }
2654 + }
2655 +
2656 + hctsiz.b.xfersize = _hc->xfer_len;
2657 + }
2658 +
2659 + _hc->start_pkt_count = num_packets;
2660 + hctsiz.b.pktcnt = num_packets;
2661 + hctsiz.b.pid = _hc->data_pid_start;
2662 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2663 +
2664 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
2665 + DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
2666 + DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
2667 + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
2668 +
2669 + if (_core_if->dma_enable) {
2670 +#ifdef DEBUG
2671 +if(((uint32_t)_hc->xfer_buff)%4)
2672 +printk("dwc_otg_hc_start_transfer _hc->xfer_buff not 4 byte alignment\n");
2673 +#endif
2674 + dwc_write_reg32(&hc_regs->hcdma, (uint32_t)_hc->xfer_buff);
2675 + }
2676 +
2677 + /* Start the split */
2678 + if (_hc->do_split) {
2679 + hcsplt_data_t hcsplt;
2680 + hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt);
2681 + hcsplt.b.spltena = 1;
2682 + dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
2683 + }
2684 +
2685 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2686 + hcchar.b.multicnt = _hc->multi_count;
2687 + hc_set_even_odd_frame(_core_if, _hc, &hcchar);
2688 +#ifdef DEBUG
2689 + _core_if->start_hcchar_val[_hc->hc_num] = hcchar.d32;
2690 + if (hcchar.b.chdis) {
2691 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2692 + __func__, _hc->hc_num, hcchar.d32);
2693 + }
2694 +#endif
2695 +
2696 + /* Set host channel enable after all other setup is complete. */
2697 + hcchar.b.chen = 1;
2698 + hcchar.b.chdis = 0;
2699 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2700 +
2701 + _hc->xfer_started = 1;
2702 + _hc->requests++;
2703 +
2704 + if (!_core_if->dma_enable && !_hc->ep_is_in && _hc->xfer_len > 0) {
2705 + /* Load OUT packet into the appropriate Tx FIFO. */
2706 + dwc_otg_hc_write_packet(_core_if, _hc);
2707 + }
2708 +
2709 +#ifdef DEBUG
2710 + /* Start a timer for this transfer. */
2711 + _core_if->hc_xfer_timer[_hc->hc_num].function = hc_xfer_timeout;
2712 + _core_if->hc_xfer_info[_hc->hc_num].core_if = _core_if;
2713 + _core_if->hc_xfer_info[_hc->hc_num].hc = _hc;
2714 + _core_if->hc_xfer_timer[_hc->hc_num].data = (unsigned long)(&_core_if->hc_xfer_info[_hc->hc_num]);
2715 + _core_if->hc_xfer_timer[_hc->hc_num].expires = jiffies + (HZ*10);
2716 + add_timer(&_core_if->hc_xfer_timer[_hc->hc_num]);
2717 +#endif
2718 +}
2719 +
2720 +/**
2721 + * This function continues a data transfer that was started by previous call
2722 + * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
2723 + * sufficient space in the request queue and Tx Data FIFO. This function
2724 + * should only be called in Slave mode. In DMA mode, the controller acts
2725 + * autonomously to complete transfers programmed to a host channel.
2726 + *
2727 + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
2728 + * if there is any data remaining to be queued. For an IN transfer, another
2729 + * data packet is always requested. For the SETUP phase of a control transfer,
2730 + * this function does nothing.
2731 + *
2732 + * @return 1 if a new request is queued, 0 if no more requests are required
2733 + * for this transfer.
2734 + */
2735 +int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2736 +{
2737 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
2738 +
2739 + if (_hc->do_split) {
2740 + /* SPLITs always queue just once per channel */
2741 + return 0;
2742 + } else if (_hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
2743 + /* SETUPs are queued only once since they can't be NAKed. */
2744 + return 0;
2745 + } else if (_hc->ep_is_in) {
2746 + /*
2747 + * Always queue another request for other IN transfers. If
2748 + * back-to-back INs are issued and NAKs are received for both,
2749 + * the driver may still be processing the first NAK when the
2750 + * second NAK is received. When the interrupt handler clears
2751 + * the NAK interrupt for the first NAK, the second NAK will
2752 + * not be seen. So we can't depend on the NAK interrupt
2753 + * handler to requeue a NAKed request. Instead, IN requests
2754 + * are issued each time this function is called. When the
2755 + * transfer completes, the extra requests for the channel will
2756 + * be flushed.
2757 + */
2758 + hcchar_data_t hcchar;
2759 + dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2760 +
2761 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2762 + hc_set_even_odd_frame(_core_if, _hc, &hcchar);
2763 + hcchar.b.chen = 1;
2764 + hcchar.b.chdis = 0;
2765 + DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32);
2766 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2767 + _hc->requests++;
2768 + return 1;
2769 + } else {
2770 + /* OUT transfers. */
2771 + if (_hc->xfer_count < _hc->xfer_len) {
2772 + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2773 + _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2774 + hcchar_data_t hcchar;
2775 + dwc_otg_hc_regs_t *hc_regs;
2776 + hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2777 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2778 + hc_set_even_odd_frame(_core_if, _hc, &hcchar);
2779 + }
2780 +
2781 + /* Load OUT packet into the appropriate Tx FIFO. */
2782 + dwc_otg_hc_write_packet(_core_if, _hc);
2783 + _hc->requests++;
2784 + return 1;
2785 + } else {
2786 + return 0;
2787 + }
2788 + }
2789 +}
2790 +
2791 +/**
2792 + * Starts a PING transfer. This function should only be called in Slave mode.
2793 + * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
2794 + */
2795 +void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2796 +{
2797 + hcchar_data_t hcchar;
2798 + hctsiz_data_t hctsiz;
2799 + dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2800 +
2801 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
2802 +
2803 + hctsiz.d32 = 0;
2804 + hctsiz.b.dopng = 1;
2805 + hctsiz.b.pktcnt = 1;
2806 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2807 +
2808 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2809 + hcchar.b.chen = 1;
2810 + hcchar.b.chdis = 0;
2811 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2812 +}
2813 +
2814 +/*
2815 + * This function writes a packet into the Tx FIFO associated with the Host
2816 + * Channel. For a channel associated with a non-periodic EP, the non-periodic
2817 + * Tx FIFO is written. For a channel associated with a periodic EP, the
2818 + * periodic Tx FIFO is written. This function should only be called in Slave
2819 + * mode.
2820 + *
2821 + * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
2822 + * then number of bytes written to the Tx FIFO.
2823 + */
2824 +void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2825 +{
2826 + uint32_t i;
2827 + uint32_t remaining_count;
2828 + uint32_t byte_count;
2829 + uint32_t dword_count;
2830 +
2831 + uint32_t *data_buff = (uint32_t *)(_hc->xfer_buff);
2832 + uint32_t *data_fifo = _core_if->data_fifo[_hc->hc_num];
2833 +
2834 + remaining_count = _hc->xfer_len - _hc->xfer_count;
2835 + if (remaining_count > _hc->max_packet) {
2836 + byte_count = _hc->max_packet;
2837 + } else {
2838 + byte_count = remaining_count;
2839 + }
2840 +
2841 + dword_count = (byte_count + 3) / 4;
2842 +
2843 + if ((((unsigned long)data_buff) & 0x3) == 0) {
2844 + /* xfer_buff is DWORD aligned. */
2845 + for (i = 0; i < dword_count; i++, data_buff++) {
2846 + dwc_write_reg32(data_fifo, *data_buff);
2847 + }
2848 + } else {
2849 + /* xfer_buff is not DWORD aligned. */
2850 + for (i = 0; i < dword_count; i++, data_buff++) {
2851 + dwc_write_reg32(data_fifo, get_unaligned(data_buff));
2852 + }
2853 + }
2854 +
2855 + _hc->xfer_count += byte_count;
2856 + _hc->xfer_buff += byte_count;
2857 +}
2858 +
2859 +/**
2860 + * Gets the current USB frame number. This is the frame number from the last
2861 + * SOF packet.
2862 + */
2863 +uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if)
2864 +{
2865 + dsts_data_t dsts;
2866 + dsts.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dsts);
2867 +
2868 + /* read current frame/microfreme number from DSTS register */
2869 + return dsts.b.soffn;
2870 +}
2871 +
2872 +/**
2873 + * This function reads a setup packet from the Rx FIFO into the destination
2874 + * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
2875 + * Interrupt routine when a SETUP packet has been received in Slave mode.
2876 + *
2877 + * @param _core_if Programming view of DWC_otg controller.
2878 + * @param _dest Destination buffer for packet data.
2879 + */
2880 +void dwc_otg_read_setup_packet(dwc_otg_core_if_t *_core_if, uint32_t *_dest)
2881 +{
2882 + /* Get the 8 bytes of a setup transaction data */
2883 +
2884 + /* Pop 2 DWORDS off the receive data FIFO into memory */
2885 + _dest[0] = dwc_read_reg32(_core_if->data_fifo[0]);
2886 + _dest[1] = dwc_read_reg32(_core_if->data_fifo[0]);
2887 + //_dest[0] = dwc_read_datafifo32(_core_if->data_fifo[0]);
2888 + //_dest[1] = dwc_read_datafifo32(_core_if->data_fifo[0]);
2889 +}
2890 +
2891 +
2892 +/**
2893 + * This function enables EP0 OUT to receive SETUP packets and configures EP0
2894 + * IN for transmitting packets. It is normally called when the
2895 + * "Enumeration Done" interrupt occurs.
2896 + *
2897 + * @param _core_if Programming view of DWC_otg controller.
2898 + * @param _ep The EP0 data.
2899 + */
2900 +void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
2901 +{
2902 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
2903 + dsts_data_t dsts;
2904 + depctl_data_t diepctl;
2905 + depctl_data_t doepctl;
2906 + dctl_data_t dctl ={.d32=0};
2907 +
2908 + /* Read the Device Status and Endpoint 0 Control registers */
2909 + dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
2910 + diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
2911 + doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
2912 +
2913 + /* Set the MPS of the IN EP based on the enumeration speed */
2914 + switch (dsts.b.enumspd) {
2915 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
2916 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
2917 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
2918 + diepctl.b.mps = DWC_DEP0CTL_MPS_64;
2919 + break;
2920 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
2921 + diepctl.b.mps = DWC_DEP0CTL_MPS_8;
2922 + break;
2923 + }
2924 +
2925 + dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
2926 +
2927 + /* Enable OUT EP for receive */
2928 + doepctl.b.epena = 1;
2929 + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
2930 +
2931 +#ifdef VERBOSE
2932 + DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
2933 + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
2934 + DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
2935 + dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
2936 +#endif
2937 + dctl.b.cgnpinnak = 1;
2938 + dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
2939 + DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n",
2940 + dwc_read_reg32(&dev_if->dev_global_regs->dctl));
2941 +}
2942 +
2943 +/**
2944 + * This function activates an EP. The Device EP control register for
2945 + * the EP is configured as defined in the ep structure. Note: This
2946 + * function is not used for EP0.
2947 + *
2948 + * @param _core_if Programming view of DWC_otg controller.
2949 + * @param _ep The EP to activate.
2950 + */
2951 +void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
2952 +{
2953 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
2954 + depctl_data_t depctl;
2955 + volatile uint32_t *addr;
2956 + daint_data_t daintmsk = {.d32=0};
2957 +
2958 + DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, _ep->num,
2959 + (_ep->is_in?"IN":"OUT"));
2960 +
2961 + /* Read DEPCTLn register */
2962 + if (_ep->is_in == 1) {
2963 + addr = &dev_if->in_ep_regs[_ep->num]->diepctl;
2964 + daintmsk.ep.in = 1<<_ep->num;
2965 + } else {
2966 + addr = &dev_if->out_ep_regs[_ep->num]->doepctl;
2967 + daintmsk.ep.out = 1<<_ep->num;
2968 + }
2969 +
2970 + /* If the EP is already active don't change the EP Control
2971 + * register. */
2972 + depctl.d32 = dwc_read_reg32(addr);
2973 + if (!depctl.b.usbactep) {
2974 + depctl.b.mps = _ep->maxpacket;
2975 + depctl.b.eptype = _ep->type;
2976 + depctl.b.txfnum = _ep->tx_fifo_num;
2977 +
2978 + if (_ep->type == DWC_OTG_EP_TYPE_ISOC) {
2979 + depctl.b.setd0pid = 1; // ???
2980 + } else {
2981 + depctl.b.setd0pid = 1;
2982 + }
2983 + depctl.b.usbactep = 1;
2984 +
2985 + dwc_write_reg32(addr, depctl.d32);
2986 + DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr));
2987 + }
2988 +
2989 +
2990 + /* Enable the Interrupt for this EP */
2991 + dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
2992 + 0, daintmsk.d32);
2993 + DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n",
2994 + dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
2995 + _ep->stall_clear_flag = 0;
2996 + return;
2997 +}
2998 +
2999 +/**
3000 + * This function deactivates an EP. This is done by clearing the USB Active
3001 + * EP bit in the Device EP control register. Note: This function is not used
3002 + * for EP0. EP0 cannot be deactivated.
3003 + *
3004 + * @param _core_if Programming view of DWC_otg controller.
3005 + * @param _ep The EP to deactivate.
3006 + */
3007 +void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
3008 +{
3009 + depctl_data_t depctl ={.d32 = 0};
3010 + volatile uint32_t *addr;
3011 + daint_data_t daintmsk = {.d32=0};
3012 +
3013 + /* Read DEPCTLn register */
3014 + if (_ep->is_in == 1) {
3015 + addr = &_core_if->dev_if->in_ep_regs[_ep->num]->diepctl;
3016 + daintmsk.ep.in = 1<<_ep->num;
3017 + } else {
3018 + addr = &_core_if->dev_if->out_ep_regs[_ep->num]->doepctl;
3019 + daintmsk.ep.out = 1<<_ep->num;
3020 + }
3021 +
3022 + depctl.b.usbactep = 0;
3023 + dwc_write_reg32(addr, depctl.d32);
3024 +
3025 + /* Disable the Interrupt for this EP */
3026 + dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->daintmsk,
3027 + daintmsk.d32, 0);
3028 +
3029 + return;
3030 +}
3031 +
3032 +/**
3033 + * This function does the setup for a data transfer for an EP and
3034 + * starts the transfer. For an IN transfer, the packets will be
3035 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
3036 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
3037 + *
3038 + * @param _core_if Programming view of DWC_otg controller.
3039 + * @param _ep The EP to start the transfer on.
3040 + */
3041 +void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
3042 +{
3043 + /** @todo Refactor this funciton to check the transfer size
3044 + * count value does not execed the number bits in the Transfer
3045 + * count register. */
3046 + depctl_data_t depctl;
3047 + deptsiz_data_t deptsiz;
3048 + gintmsk_data_t intr_mask = { .d32 = 0};
3049 +
3050 +#ifdef CHECK_PACKET_COUNTER_WIDTH
3051 + const uint32_t MAX_XFER_SIZE =
3052 + _core_if->core_params->max_transfer_size;
3053 + const uint32_t MAX_PKT_COUNT =
3054 + _core_if->core_params->max_packet_count;
3055 + uint32_t num_packets;
3056 + uint32_t transfer_len;
3057 + dwc_otg_dev_out_ep_regs_t *out_regs =
3058 + _core_if->dev_if->out_ep_regs[_ep->num];
3059 + dwc_otg_dev_in_ep_regs_t *in_regs =
3060 + _core_if->dev_if->in_ep_regs[_ep->num];
3061 + gnptxsts_data_t txstatus;
3062 +
3063 + int lvl = SET_DEBUG_LEVEL(DBG_PCD);
3064 +
3065 +
3066 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3067 + "xfer_buff=%p start_xfer_buff=%p\n",
3068 + _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len,
3069 + _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff);
3070 +
3071 + transfer_len = _ep->xfer_len - _ep->xfer_count;
3072 + if (transfer_len > MAX_XFER_SIZE) {
3073 + transfer_len = MAX_XFER_SIZE;
3074 + }
3075 + if (transfer_len == 0) {
3076 + num_packets = 1;
3077 + /* OUT EP to recieve Zero-length packet set transfer
3078 + * size to maxpacket size. */
3079 + if (!_ep->is_in) {
3080 + transfer_len = _ep->maxpacket;
3081 + }
3082 + } else {
3083 + num_packets =
3084 + (transfer_len + _ep->maxpacket - 1) / _ep->maxpacket;
3085 + if (num_packets > MAX_PKT_COUNT) {
3086 + num_packets = MAX_PKT_COUNT;
3087 + }
3088 + }
3089 + DWC_DEBUGPL(DBG_PCD, "transfer_len=%d #pckt=%d\n", transfer_len,
3090 + num_packets);
3091 +
3092 + deptsiz.b.xfersize = transfer_len;
3093 + deptsiz.b.pktcnt = num_packets;
3094 +
3095 + /* IN endpoint */
3096 + if (_ep->is_in == 1) {
3097 + depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
3098 + } else {/* OUT endpoint */
3099 + depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
3100 + }
3101 +
3102 + /* EP enable, IN data in FIFO */
3103 + depctl.b.cnak = 1;
3104 + depctl.b.epena = 1;
3105 + /* IN endpoint */
3106 + if (_ep->is_in == 1) {
3107 + txstatus.d32 =
3108 + dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
3109 + if (txstatus.b.nptxqspcavail == 0) {
3110 + DWC_DEBUGPL(DBG_ANY, "TX Queue Full (0x%0x)\n",
3111 + txstatus.d32);
3112 + return;
3113 + }
3114 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3115 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3116 + /**
3117 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
3118 + * data will be written into the fifo by the ISR.
3119 + */
3120 + if (_core_if->dma_enable) {
3121 + dwc_write_reg32(&in_regs->diepdma, (uint32_t) _ep->xfer_buff);
3122 + } else {
3123 + if (_core_if->en_multiple_tx_fifo == 0) {
3124 + intr_mask.b.nptxfempty = 1;
3125 + dwc_modify_reg32( &_core_if->core_global_regs->gintsts,
3126 + intr_mask.d32, 0);
3127 + dwc_modify_reg32( &_core_if->core_global_regs->gintmsk,
3128 + intr_mask.d32, intr_mask.d32);
3129 + } else {
3130 + /* Enable the Tx FIFO Empty Interrupt for this EP */
3131 + if (_ep->xfer_len > 0 &&
3132 + _ep->type != DWC_OTG_EP_TYPE_ISOC) {
3133 + uint32_t fifoemptymsk = 0;
3134 + fifoemptymsk = (0x1 << _ep->num);
3135 + dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->
3136 + dtknqr4_fifoemptymsk,0, fifoemptymsk);
3137 + }
3138 + }
3139 + }
3140 + } else { /* OUT endpoint */
3141 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3142 + dwc_write_reg32(&out_regs->doepctl, depctl.d32);
3143 + if (_core_if->dma_enable) {
3144 + dwc_write_reg32(&out_regs->doepdma,(uint32_t) _ep->xfer_buff);
3145 + }
3146 + }
3147 + DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
3148 + dwc_read_reg32(&out_regs->doepctl),
3149 + dwc_read_reg32(&out_regs->doeptsiz));
3150 + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3151 + dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk),
3152 + dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
3153 +
3154 + SET_DEBUG_LEVEL(lvl);
3155 +#endif
3156 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
3157 +
3158 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3159 + "xfer_buff=%p start_xfer_buff=%p\n",
3160 + _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len,
3161 + _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff);
3162 +
3163 + /* IN endpoint */
3164 + if (_ep->is_in == 1) {
3165 + dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[_ep->num];
3166 + gnptxsts_data_t gtxstatus;
3167 + gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
3168 + if (_core_if->en_multiple_tx_fifo == 0 &&
3169 + gtxstatus.b.nptxqspcavail == 0) {
3170 +#ifdef DEBUG
3171 + DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32);
3172 +#endif
3173 + //return;
3174 + MDELAY(100); //james
3175 + }
3176 +
3177 + depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
3178 + deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
3179 +
3180 + /* Zero Length Packet? */
3181 + if (_ep->xfer_len == 0) {
3182 + deptsiz.b.xfersize = 0;
3183 + deptsiz.b.pktcnt = 1;
3184 + } else {
3185 +
3186 + /* Program the transfer size and packet count
3187 + * as follows: xfersize = N * maxpacket +
3188 + * short_packet pktcnt = N + (short_packet
3189 + * exist ? 1 : 0)
3190 + */
3191 + deptsiz.b.xfersize = _ep->xfer_len;
3192 + deptsiz.b.pktcnt = (_ep->xfer_len - 1 + _ep->maxpacket) / _ep->maxpacket;
3193 + }
3194 +
3195 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3196 +
3197 + /* Write the DMA register */
3198 + if (_core_if->dma_enable) {
3199 +#if 1 // winder
3200 + dma_cache_wback_inv((unsigned long) _ep->xfer_buff, _ep->xfer_len); // winder
3201 + dwc_write_reg32 (&(in_regs->diepdma),
3202 + CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder
3203 +#else
3204 + dwc_write_reg32 (&(in_regs->diepdma),
3205 + (uint32_t)_ep->dma_addr);
3206 +#endif
3207 + } else {
3208 + if (_ep->type != DWC_OTG_EP_TYPE_ISOC) {
3209 + /**
3210 + * Enable the Non-Periodic Tx FIFO empty interrupt,
3211 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
3212 + * the data will be written into the fifo by the ISR.
3213 + */
3214 + if (_core_if->en_multiple_tx_fifo == 0) {
3215 + intr_mask.b.nptxfempty = 1;
3216 + dwc_modify_reg32( &_core_if->core_global_regs->gintsts,
3217 + intr_mask.d32, 0);
3218 + dwc_modify_reg32( &_core_if->core_global_regs->gintmsk,
3219 + intr_mask.d32, intr_mask.d32);
3220 + } else {
3221 + /* Enable the Tx FIFO Empty Interrupt for this EP */
3222 + if (_ep->xfer_len > 0) {
3223 + uint32_t fifoemptymsk = 0;
3224 + fifoemptymsk = 1 << _ep->num;
3225 + dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->
3226 + dtknqr4_fifoemptymsk,0,fifoemptymsk);
3227 + }
3228 + }
3229 + }
3230 + }
3231 +
3232 + /* EP enable, IN data in FIFO */
3233 + depctl.b.cnak = 1;
3234 + depctl.b.epena = 1;
3235 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3236 +
3237 + if (_core_if->dma_enable) {
3238 + depctl.d32 = dwc_read_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl);
3239 + depctl.b.nextep = _ep->num;
3240 + dwc_write_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
3241 +
3242 + }
3243 + } else {
3244 + /* OUT endpoint */
3245 + dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num];
3246 +
3247 + depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
3248 + deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
3249 +
3250 + /* Program the transfer size and packet count as follows:
3251 + *
3252 + * pktcnt = N
3253 + * xfersize = N * maxpacket
3254 + */
3255 + if (_ep->xfer_len == 0) {
3256 + /* Zero Length Packet */
3257 + deptsiz.b.xfersize = _ep->maxpacket;
3258 + deptsiz.b.pktcnt = 1;
3259 + } else {
3260 + deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket;
3261 + deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket;
3262 + }
3263 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3264 +
3265 + DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
3266 + _ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
3267 +
3268 + if (_core_if->dma_enable) {
3269 +#if 1 // winder
3270 + dwc_write_reg32 (&(out_regs->doepdma),
3271 + CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder
3272 +#else
3273 + dwc_write_reg32 (&(out_regs->doepdma),
3274 + (uint32_t)_ep->dma_addr);
3275 +#endif
3276 + }
3277 +
3278 + if (_ep->type == DWC_OTG_EP_TYPE_ISOC) {
3279 + /** @todo NGS: dpid is read-only. Use setd0pid
3280 + * or setd1pid. */
3281 + if (_ep->even_odd_frame) {
3282 + depctl.b.setd1pid = 1;
3283 + } else {
3284 + depctl.b.setd0pid = 1;
3285 + }
3286 + }
3287 +
3288 + /* EP enable */
3289 + depctl.b.cnak = 1;
3290 + depctl.b.epena = 1;
3291 +
3292 + dwc_write_reg32(&out_regs->doepctl, depctl.d32);
3293 +
3294 + DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
3295 + dwc_read_reg32(&out_regs->doepctl),
3296 + dwc_read_reg32(&out_regs->doeptsiz));
3297 + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3298 + dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk),
3299 + dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
3300 + }
3301 +}
3302 +
3303 +
3304 +/**
3305 + * This function does the setup for a data transfer for EP0 and starts
3306 + * the transfer. For an IN transfer, the packets will be loaded into
3307 + * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
3308 + * unloaded from the Rx FIFO in the ISR.
3309 + *
3310 + * @param _core_if Programming view of DWC_otg controller.
3311 + * @param _ep The EP0 data.
3312 + */
3313 +void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
3314 +{
3315 + volatile depctl_data_t depctl;
3316 + volatile deptsiz0_data_t deptsiz;
3317 + gintmsk_data_t intr_mask = { .d32 = 0};
3318 +
3319 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3320 + "xfer_buff=%p start_xfer_buff=%p total_len=%d\n",
3321 + _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len,
3322 + _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff,
3323 + _ep->total_len);
3324 + _ep->total_len = _ep->xfer_len;
3325 +
3326 + /* IN endpoint */
3327 + if (_ep->is_in == 1) {
3328 + dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[0];
3329 + gnptxsts_data_t gtxstatus;
3330 + gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
3331 + if (_core_if->en_multiple_tx_fifo == 0 &&
3332 + gtxstatus.b.nptxqspcavail == 0) {
3333 +#ifdef DEBUG
3334 + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3335 + DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n",
3336 + dwc_read_reg32(&in_regs->diepctl));
3337 + DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
3338 + deptsiz.d32, deptsiz.b.xfersize,deptsiz.b.pktcnt);
3339 + DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n", gtxstatus.d32);
3340 +#endif /* */
3341 + printk("TX Queue or FIFO Full!!!!\n"); // test-only
3342 + //return;
3343 + MDELAY(100); //james
3344 + }
3345 +
3346 + depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
3347 + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3348 +
3349 + /* Zero Length Packet? */
3350 + if (_ep->xfer_len == 0) {
3351 + deptsiz.b.xfersize = 0;
3352 + deptsiz.b.pktcnt = 1;
3353 + } else {
3354 + /* Program the transfer size and packet count
3355 + * as follows: xfersize = N * maxpacket +
3356 + * short_packet pktcnt = N + (short_packet
3357 + * exist ? 1 : 0)
3358 + */
3359 + if (_ep->xfer_len > _ep->maxpacket) {
3360 + _ep->xfer_len = _ep->maxpacket;
3361 + deptsiz.b.xfersize = _ep->maxpacket;
3362 + }
3363 + else {
3364 + deptsiz.b.xfersize = _ep->xfer_len;
3365 + }
3366 + deptsiz.b.pktcnt = 1;
3367 +
3368 + }
3369 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3370 + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
3371 + _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt, deptsiz.d32);
3372 +
3373 + /* Write the DMA register */
3374 + if (_core_if->dma_enable) {
3375 + dwc_write_reg32(&(in_regs->diepdma), (uint32_t) _ep->dma_addr);
3376 + }
3377 +
3378 + /* EP enable, IN data in FIFO */
3379 + depctl.b.cnak = 1;
3380 + depctl.b.epena = 1;
3381 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3382 +
3383 + /**
3384 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
3385 + * data will be written into the fifo by the ISR.
3386 + */
3387 + if (!_core_if->dma_enable) {
3388 + if (_core_if->en_multiple_tx_fifo == 0) {
3389 + intr_mask.b.nptxfempty = 1;
3390 + dwc_modify_reg32(&_core_if->core_global_regs->gintsts, intr_mask.d32, 0);
3391 + dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, intr_mask.d32,
3392 + intr_mask.d32);
3393 + } else {
3394 + /* Enable the Tx FIFO Empty Interrupt for this EP */
3395 + if (_ep->xfer_len > 0) {
3396 + uint32_t fifoemptymsk = 0;
3397 + fifoemptymsk |= 1 << _ep->num;
3398 + dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3399 + 0, fifoemptymsk);
3400 + }
3401 +
3402 + }
3403 + }
3404 + } else {
3405 + /* OUT endpoint */
3406 + dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num];
3407 +
3408 + depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
3409 + deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
3410 +
3411 + /* Program the transfer size and packet count as follows:
3412 + * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
3413 + * pktcnt = N */
3414 + if (_ep->xfer_len == 0) {
3415 + /* Zero Length Packet */
3416 + deptsiz.b.xfersize = _ep->maxpacket;
3417 + deptsiz.b.pktcnt = 1;
3418 + } else {
3419 + deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket;
3420 + deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket;
3421 + }
3422 +
3423 + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3424 + DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
3425 + _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt);
3426 +
3427 + if (_core_if->dma_enable) {
3428 + dwc_write_reg32(&(out_regs->doepdma), (uint32_t) _ep->dma_addr);
3429 + }
3430 +
3431 + /* EP enable */
3432 + depctl.b.cnak = 1;
3433 + depctl.b.epena = 1;
3434 + dwc_write_reg32 (&(out_regs->doepctl), depctl.d32);
3435 + }
3436 +}
3437 +
3438 +/**
3439 + * This function continues control IN transfers started by
3440 + * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
3441 + * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
3442 + * bit for the packet count.
3443 + *
3444 + * @param _core_if Programming view of DWC_otg controller.
3445 + * @param _ep The EP0 data.
3446 + */
3447 +void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
3448 +{
3449 + depctl_data_t depctl;
3450 + deptsiz0_data_t deptsiz;
3451 + gintmsk_data_t intr_mask = { .d32 = 0};
3452 +
3453 + if (_ep->is_in == 1) {
3454 + dwc_otg_dev_in_ep_regs_t *in_regs =
3455 + _core_if->dev_if->in_ep_regs[0];
3456 + gnptxsts_data_t tx_status = {.d32 = 0};
3457 +
3458 + tx_status.d32 = dwc_read_reg32( &_core_if->core_global_regs->gnptxsts );
3459 + /** @todo Should there be check for room in the Tx
3460 + * Status Queue. If not remove the code above this comment. */
3461 +
3462 + depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
3463 + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3464 +
3465 + /* Program the transfer size and packet count
3466 + * as follows: xfersize = N * maxpacket +
3467 + * short_packet pktcnt = N + (short_packet
3468 + * exist ? 1 : 0)
3469 + */
3470 + deptsiz.b.xfersize = (_ep->total_len - _ep->xfer_count) > _ep->maxpacket ? _ep->maxpacket :
3471 + (_ep->total_len - _ep->xfer_count);
3472 + deptsiz.b.pktcnt = 1;
3473 + _ep->xfer_len += deptsiz.b.xfersize;
3474 +
3475 + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3476 + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
3477 + _ep->xfer_len,
3478 + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
3479 +
3480 + /* Write the DMA register */
3481 + if (_core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
3482 + dwc_write_reg32 (&(in_regs->diepdma),
3483 + CPHYSADDR((uint32_t)_ep->dma_addr)); // winder
3484 + }
3485 +
3486 + /* EP enable, IN data in FIFO */
3487 + depctl.b.cnak = 1;
3488 + depctl.b.epena = 1;
3489 + dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3490 +
3491 + /**
3492 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
3493 + * data will be written into the fifo by the ISR.
3494 + */
3495 + if (!_core_if->dma_enable) {
3496 + /* First clear it from GINTSTS */
3497 + intr_mask.b.nptxfempty = 1;
3498 + dwc_write_reg32( &_core_if->core_global_regs->gintsts,
3499 + intr_mask.d32 );
3500 +
3501 + dwc_modify_reg32( &_core_if->core_global_regs->gintmsk,
3502 + intr_mask.d32, intr_mask.d32);
3503 + }
3504 +
3505 + }
3506 +
3507 +}
3508 +
3509 +#ifdef DEBUG
3510 +void dump_msg(const u8 *buf, unsigned int length)
3511 +{
3512 + unsigned int start, num, i;
3513 + char line[52], *p;
3514 +
3515 + if (length >= 512)
3516 + return;
3517 + start = 0;
3518 + while (length > 0) {
3519 + num = min(length, 16u);
3520 + p = line;
3521 + for (i = 0; i < num; ++i) {
3522 + if (i == 8)
3523 + *p++ = ' ';
3524 + sprintf(p, " %02x", buf[i]);
3525 + p += 3;
3526 + }
3527 + *p = 0;
3528 + DWC_PRINT( "%6x: %s\n", start, line);
3529 + buf += num;
3530 + start += num;
3531 + length -= num;
3532 + }
3533 +}
3534 +#else
3535 +static inline void dump_msg(const u8 *buf, unsigned int length)
3536 +{
3537 +}
3538 +#endif
3539 +
3540 +/**
3541 + * This function writes a packet into the Tx FIFO associated with the
3542 + * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
3543 + * periodic EPs the periodic Tx FIFO associated with the EP is written
3544 + * with all packets for the next micro-frame.
3545 + *
3546 + * @param _core_if Programming view of DWC_otg controller.
3547 + * @param _ep The EP to write packet for.
3548 + * @param _dma Indicates if DMA is being used.
3549 + */
3550 +void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma)
3551 +{
3552 + /**
3553 + * The buffer is padded to DWORD on a per packet basis in
3554 + * slave/dma mode if the MPS is not DWORD aligned. The last
3555 + * packet, if short, is also padded to a multiple of DWORD.
3556 + *
3557 + * ep->xfer_buff always starts DWORD aligned in memory and is a
3558 + * multiple of DWORD in length
3559 + *
3560 + * ep->xfer_len can be any number of bytes
3561 + *
3562 + * ep->xfer_count is a multiple of ep->maxpacket until the last
3563 + * packet
3564 + *
3565 + * FIFO access is DWORD */
3566 +
3567 + uint32_t i;
3568 + uint32_t byte_count;
3569 + uint32_t dword_count;
3570 + uint32_t *fifo;
3571 + uint32_t *data_buff = (uint32_t *)_ep->xfer_buff;
3572 +
3573 + //DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, _core_if, _ep);
3574 + if (_ep->xfer_count >= _ep->xfer_len) {
3575 + DWC_WARN("%s() No data for EP%d!!!\n", __func__, _ep->num);
3576 + return;
3577 + }
3578 +
3579 + /* Find the byte length of the packet either short packet or MPS */
3580 + if ((_ep->xfer_len - _ep->xfer_count) < _ep->maxpacket) {
3581 + byte_count = _ep->xfer_len - _ep->xfer_count;
3582 + }
3583 + else {
3584 + byte_count = _ep->maxpacket;
3585 + }
3586 +
3587 + /* Find the DWORD length, padded by extra bytes as neccessary if MPS
3588 + * is not a multiple of DWORD */
3589 + dword_count = (byte_count + 3) / 4;
3590 +
3591 +#ifdef VERBOSE
3592 + dump_msg(_ep->xfer_buff, byte_count);
3593 +#endif
3594 + if (_ep->type == DWC_OTG_EP_TYPE_ISOC) {
3595 + /**@todo NGS Where are the Periodic Tx FIFO addresses
3596 + * intialized? What should this be? */
3597 + fifo = _core_if->data_fifo[_ep->tx_fifo_num];
3598 + } else {
3599 + fifo = _core_if->data_fifo[_ep->num];
3600 + }
3601 +
3602 + DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
3603 + fifo, data_buff, *data_buff, byte_count);
3604 +
3605 +
3606 + if (!_dma) {
3607 + for (i=0; i<dword_count; i++, data_buff++) {
3608 + dwc_write_reg32( fifo, *data_buff );
3609 + }
3610 + }
3611 +
3612 + _ep->xfer_count += byte_count;
3613 + _ep->xfer_buff += byte_count;
3614 +#if 1 // winder, why do we need this??
3615 + _ep->dma_addr += byte_count;
3616 +#endif
3617 +}
3618 +
3619 +/**
3620 + * Set the EP STALL.
3621 + *
3622 + * @param _core_if Programming view of DWC_otg controller.
3623 + * @param _ep The EP to set the stall on.
3624 + */
3625 +void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
3626 +{
3627 + depctl_data_t depctl;
3628 + volatile uint32_t *depctl_addr;
3629 +
3630 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num,
3631 + (_ep->is_in?"IN":"OUT"));
3632 +
3633 + if (_ep->is_in == 1) {
3634 + depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl);
3635 + depctl.d32 = dwc_read_reg32(depctl_addr);
3636 +
3637 + /* set the disable and stall bits */
3638 + if (depctl.b.epena) {
3639 + depctl.b.epdis = 1;
3640 + }
3641 + depctl.b.stall = 1;
3642 + dwc_write_reg32(depctl_addr, depctl.d32);
3643 +
3644 + } else {
3645 + depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl);
3646 + depctl.d32 = dwc_read_reg32(depctl_addr);
3647 +
3648 + /* set the stall bit */
3649 + depctl.b.stall = 1;
3650 + dwc_write_reg32(depctl_addr, depctl.d32);
3651 + }
3652 + DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
3653 + return;
3654 +}
3655 +
3656 +/**
3657 + * Clear the EP STALL.
3658 + *
3659 + * @param _core_if Programming view of DWC_otg controller.
3660 + * @param _ep The EP to clear stall from.
3661 + */
3662 +void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
3663 +{
3664 + depctl_data_t depctl;
3665 + volatile uint32_t *depctl_addr;
3666 +
3667 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num,
3668 + (_ep->is_in?"IN":"OUT"));
3669 +
3670 + if (_ep->is_in == 1) {
3671 + depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl);
3672 + } else {
3673 + depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl);
3674 + }
3675 +
3676 + depctl.d32 = dwc_read_reg32(depctl_addr);
3677 +
3678 + /* clear the stall bits */
3679 + depctl.b.stall = 0;
3680 +
3681 + /*
3682 + * USB Spec 9.4.5: For endpoints using data toggle, regardless
3683 + * of whether an endpoint has the Halt feature set, a
3684 + * ClearFeature(ENDPOINT_HALT) request always results in the
3685 + * data toggle being reinitialized to DATA0.
3686 + */
3687 + if (_ep->type == DWC_OTG_EP_TYPE_INTR ||
3688 + _ep->type == DWC_OTG_EP_TYPE_BULK) {
3689 + depctl.b.setd0pid = 1; /* DATA0 */
3690 + }
3691 +
3692 + dwc_write_reg32(depctl_addr, depctl.d32);
3693 + DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
3694 + return;
3695 +}
3696 +
3697 +/**
3698 + * This function reads a packet from the Rx FIFO into the destination
3699 + * buffer. To read SETUP data use dwc_otg_read_setup_packet.
3700 + *
3701 + * @param _core_if Programming view of DWC_otg controller.
3702 + * @param _dest Destination buffer for the packet.
3703 + * @param _bytes Number of bytes to copy to the destination.
3704 + */
3705 +void dwc_otg_read_packet(dwc_otg_core_if_t *_core_if,
3706 + uint8_t *_dest,
3707 + uint16_t _bytes)
3708 +{
3709 + int i;
3710 + int word_count = (_bytes + 3) / 4;
3711 +
3712 + volatile uint32_t *fifo = _core_if->data_fifo[0];
3713 + uint32_t *data_buff = (uint32_t *)_dest;
3714 +
3715 + /**
3716 + * @todo Account for the case where _dest is not dword aligned. This
3717 + * requires reading data from the FIFO into a uint32_t temp buffer,
3718 + * then moving it into the data buffer.
3719 + */
3720 +
3721 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
3722 + _core_if, _dest, _bytes);
3723 +
3724 + for (i=0; i<word_count; i++, data_buff++) {
3725 + *data_buff = dwc_read_reg32(fifo);
3726 + }
3727 +
3728 + return;
3729 +}
3730 +
3731 +
3732 +#ifdef DEBUG
3733 +/**
3734 + * This functions reads the device registers and prints them
3735 + *
3736 + * @param _core_if Programming view of DWC_otg controller.
3737 + */
3738 +void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if)
3739 +{
3740 + int i;
3741 + volatile uint32_t *addr;
3742 +
3743 + DWC_PRINT("Device Global Registers\n");
3744 + addr=&_core_if->dev_if->dev_global_regs->dcfg;
3745 + DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3746 + addr=&_core_if->dev_if->dev_global_regs->dctl;
3747 + DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3748 + addr=&_core_if->dev_if->dev_global_regs->dsts;
3749 + DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3750 + addr=&_core_if->dev_if->dev_global_regs->diepmsk;
3751 + DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3752 + addr=&_core_if->dev_if->dev_global_regs->doepmsk;
3753 + DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3754 + addr=&_core_if->dev_if->dev_global_regs->daint;
3755 + DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3756 + addr=&_core_if->dev_if->dev_global_regs->dtknqr1;
3757 + DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3758 + if (_core_if->hwcfg2.b.dev_token_q_depth > 6) {
3759 + addr=&_core_if->dev_if->dev_global_regs->dtknqr2;
3760 + DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n",
3761 + (uint32_t)addr,dwc_read_reg32(addr));
3762 + }
3763 +
3764 + addr=&_core_if->dev_if->dev_global_regs->dvbusdis;
3765 + DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3766 +
3767 + addr=&_core_if->dev_if->dev_global_regs->dvbuspulse;
3768 + DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n",
3769 + (uint32_t)addr,dwc_read_reg32(addr));
3770 +
3771 + if (_core_if->hwcfg2.b.dev_token_q_depth > 14) {
3772 + addr = &_core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
3773 + DWC_PRINT("DTKNQR3 @0x%08X : 0x%08X\n",
3774 + (uint32_t)addr, dwc_read_reg32(addr));
3775 + }
3776 +
3777 + if (_core_if->hwcfg2.b.dev_token_q_depth > 22) {
3778 + addr = &_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
3779 + DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", (uint32_t) addr,
3780 + dwc_read_reg32(addr));
3781 + }
3782 + for (i = 0; i <= _core_if->dev_if->num_in_eps; i++) {
3783 + DWC_PRINT("Device IN EP %d Registers\n", i);
3784 + addr=&_core_if->dev_if->in_ep_regs[i]->diepctl;
3785 + DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3786 + addr=&_core_if->dev_if->in_ep_regs[i]->diepint;
3787 + DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3788 + addr=&_core_if->dev_if->in_ep_regs[i]->dieptsiz;
3789 + DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3790 + addr=&_core_if->dev_if->in_ep_regs[i]->diepdma;
3791 + DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3792 +
3793 +addr = &_core_if->dev_if->in_ep_regs[i]->dtxfsts;
3794 + DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n", (uint32_t) addr,
3795 + dwc_read_reg32(addr));
3796 + }
3797 + for (i = 0; i <= _core_if->dev_if->num_out_eps; i++) {
3798 + DWC_PRINT("Device OUT EP %d Registers\n", i);
3799 + addr=&_core_if->dev_if->out_ep_regs[i]->doepctl;
3800 + DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3801 + addr=&_core_if->dev_if->out_ep_regs[i]->doepfn;
3802 + DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3803 + addr=&_core_if->dev_if->out_ep_regs[i]->doepint;
3804 + DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3805 + addr=&_core_if->dev_if->out_ep_regs[i]->doeptsiz;
3806 + DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3807 + addr=&_core_if->dev_if->out_ep_regs[i]->doepdma;
3808 + DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3809 + }
3810 + return;
3811 +}
3812 +
3813 +/**
3814 + * This function reads the host registers and prints them
3815 + *
3816 + * @param _core_if Programming view of DWC_otg controller.
3817 + */
3818 +void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if)
3819 +{
3820 + int i;
3821 + volatile uint32_t *addr;
3822 +
3823 + DWC_PRINT("Host Global Registers\n");
3824 + addr=&_core_if->host_if->host_global_regs->hcfg;
3825 + DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3826 + addr=&_core_if->host_if->host_global_regs->hfir;
3827 + DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3828 + addr=&_core_if->host_if->host_global_regs->hfnum;
3829 + DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3830 + addr=&_core_if->host_if->host_global_regs->hptxsts;
3831 + DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3832 + addr=&_core_if->host_if->host_global_regs->haint;
3833 + DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3834 + addr=&_core_if->host_if->host_global_regs->haintmsk;
3835 + DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3836 + addr=_core_if->host_if->hprt0;
3837 + DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3838 +
3839 + for (i=0; i<_core_if->core_params->host_channels; i++) {
3840 + DWC_PRINT("Host Channel %d Specific Registers\n", i);
3841 + addr=&_core_if->host_if->hc_regs[i]->hcchar;
3842 + DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3843 + addr=&_core_if->host_if->hc_regs[i]->hcsplt;
3844 + DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3845 + addr=&_core_if->host_if->hc_regs[i]->hcint;
3846 + DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3847 + addr=&_core_if->host_if->hc_regs[i]->hcintmsk;
3848 + DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3849 + addr=&_core_if->host_if->hc_regs[i]->hctsiz;
3850 + DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3851 + addr=&_core_if->host_if->hc_regs[i]->hcdma;
3852 + DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3853 +
3854 + }
3855 + return;
3856 +}
3857 +
3858 +/**
3859 + * This function reads the core global registers and prints them
3860 + *
3861 + * @param _core_if Programming view of DWC_otg controller.
3862 + */
3863 +void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if)
3864 +{
3865 + int i;
3866 + volatile uint32_t *addr;
3867 +
3868 + DWC_PRINT("Core Global Registers\n");
3869 + addr=&_core_if->core_global_regs->gotgctl;
3870 + DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3871 + addr=&_core_if->core_global_regs->gotgint;
3872 + DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3873 + addr=&_core_if->core_global_regs->gahbcfg;
3874 + DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3875 + addr=&_core_if->core_global_regs->gusbcfg;
3876 + DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3877 + addr=&_core_if->core_global_regs->grstctl;
3878 + DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3879 + addr=&_core_if->core_global_regs->gintsts;
3880 + DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3881 + addr=&_core_if->core_global_regs->gintmsk;
3882 + DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3883 + addr=&_core_if->core_global_regs->grxstsr;
3884 + DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3885 + //addr=&_core_if->core_global_regs->grxstsp;
3886 + //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3887 + addr=&_core_if->core_global_regs->grxfsiz;
3888 + DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3889 + addr=&_core_if->core_global_regs->gnptxfsiz;
3890 + DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3891 + addr=&_core_if->core_global_regs->gnptxsts;
3892 + DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3893 + addr=&_core_if->core_global_regs->gi2cctl;
3894 + DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3895 + addr=&_core_if->core_global_regs->gpvndctl;
3896 + DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3897 + addr=&_core_if->core_global_regs->ggpio;
3898 + DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3899 + addr=&_core_if->core_global_regs->guid;
3900 + DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3901 + addr=&_core_if->core_global_regs->gsnpsid;
3902 + DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3903 + addr=&_core_if->core_global_regs->ghwcfg1;
3904 + DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3905 + addr=&_core_if->core_global_regs->ghwcfg2;
3906 + DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3907 + addr=&_core_if->core_global_regs->ghwcfg3;
3908 + DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3909 + addr=&_core_if->core_global_regs->ghwcfg4;
3910 + DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3911 + addr=&_core_if->core_global_regs->hptxfsiz;
3912 + DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3913 +
3914 + for (i=0; i<_core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
3915 + addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i];
3916 + DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr));
3917 + }
3918 +
3919 +}
3920 +#endif
3921 +
3922 +/**
3923 + * Flush a Tx FIFO.
3924 + *
3925 + * @param _core_if Programming view of DWC_otg controller.
3926 + * @param _num Tx FIFO to flush.
3927 + */
3928 +extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
3929 + const int _num )
3930 +{
3931 + dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
3932 + volatile grstctl_t greset = { .d32 = 0};
3933 + int count = 0;
3934 +
3935 + DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num);
3936 +
3937 + greset.b.txfflsh = 1;
3938 + greset.b.txfnum = _num;
3939 + dwc_write_reg32( &global_regs->grstctl, greset.d32 );
3940 +
3941 + do {
3942 + greset.d32 = dwc_read_reg32( &global_regs->grstctl);
3943 + if (++count > 10000){
3944 + DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
3945 + __func__, greset.d32,
3946 + dwc_read_reg32( &global_regs->gnptxsts));
3947 + break;
3948 + }
3949 +
3950 + udelay(1);
3951 + } while (greset.b.txfflsh == 1);
3952 + /* Wait for 3 PHY Clocks*/
3953 + UDELAY(1);
3954 +}
3955 +
3956 +/**
3957 + * Flush Rx FIFO.
3958 + *
3959 + * @param _core_if Programming view of DWC_otg controller.
3960 + */
3961 +extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if )
3962 +{
3963 + dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
3964 + volatile grstctl_t greset = { .d32 = 0};
3965 + int count = 0;
3966 +
3967 + DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
3968 + /*
3969 + *
3970 + */
3971 + greset.b.rxfflsh = 1;
3972 + dwc_write_reg32( &global_regs->grstctl, greset.d32 );
3973 +
3974 + do {
3975 + greset.d32 = dwc_read_reg32( &global_regs->grstctl);
3976 + if (++count > 10000){
3977 + DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
3978 + greset.d32);
3979 + break;
3980 + }
3981 + } while (greset.b.rxfflsh == 1);
3982 + /* Wait for 3 PHY Clocks*/
3983 + UDELAY(1);
3984 +}
3985 +
3986 +/**
3987 + * Do core a soft reset of the core. Be careful with this because it
3988 + * resets all the internal state machines of the core.
3989 + */
3990 +
3991 +void dwc_otg_core_reset(dwc_otg_core_if_t *_core_if)
3992 +{
3993 + dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
3994 + volatile grstctl_t greset = { .d32 = 0};
3995 + int count = 0;
3996 +
3997 + DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
3998 + /* Wait for AHB master IDLE state. */
3999 + do {
4000 + UDELAY(10);
4001 + greset.d32 = dwc_read_reg32( &global_regs->grstctl);
4002 + if (++count > 100000){
4003 + DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__,
4004 + greset.d32, greset.b.ahbidle);
4005 + return;
4006 + }
4007 + } while (greset.b.ahbidle == 0);
4008 +
4009 +// winder add.
4010 +#if 1
4011 + /* Note: Actually, I don't exactly why we need to put delay here. */
4012 + MDELAY(100);
4013 +#endif
4014 + /* Core Soft Reset */
4015 + count = 0;
4016 + greset.b.csftrst = 1;
4017 + dwc_write_reg32( &global_regs->grstctl, greset.d32 );
4018 +// winder add.
4019 +#if 1
4020 + /* Note: Actually, I don't exactly why we need to put delay here. */
4021 + MDELAY(100);
4022 +#endif
4023 + do {
4024 + greset.d32 = dwc_read_reg32( &global_regs->grstctl);
4025 + if (++count > 10000){
4026 + DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__,
4027 + greset.d32);
4028 + break;
4029 + }
4030 + udelay(1);
4031 + } while (greset.b.csftrst == 1);
4032 + /* Wait for 3 PHY Clocks*/
4033 + //DWC_PRINT("100ms\n");
4034 + MDELAY(100);
4035 +}
4036 +
4037 +
4038 +
4039 +/**
4040 + * Register HCD callbacks. The callbacks are used to start and stop
4041 + * the HCD for interrupt processing.
4042 + *
4043 + * @param _core_if Programming view of DWC_otg controller.
4044 + * @param _cb the HCD callback structure.
4045 + * @param _p pointer to be passed to callback function (usb_hcd*).
4046 + */
4047 +extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
4048 + dwc_otg_cil_callbacks_t *_cb,
4049 + void *_p)
4050 +{
4051 + _core_if->hcd_cb = _cb;
4052 + _cb->p = _p;
4053 +}
4054 +
4055 +/**
4056 + * Register PCD callbacks. The callbacks are used to start and stop
4057 + * the PCD for interrupt processing.
4058 + *
4059 + * @param _core_if Programming view of DWC_otg controller.
4060 + * @param _cb the PCD callback structure.
4061 + * @param _p pointer to be passed to callback function (pcd*).
4062 + */
4063 +extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
4064 + dwc_otg_cil_callbacks_t *_cb,
4065 + void *_p)
4066 +{
4067 + _core_if->pcd_cb = _cb;
4068 + _cb->p = _p;
4069 +}
4070 +
4071 --- /dev/null
4072 +++ b/drivers/usb/dwc_otg/dwc_otg_cil.h
4073 @@ -0,0 +1,911 @@
4074 +/* ==========================================================================
4075 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.h $
4076 + * $Revision: 1.1.1.1 $
4077 + * $Date: 2009-04-17 06:15:34 $
4078 + * $Change: 631780 $
4079 + *
4080 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
4081 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
4082 + * otherwise expressly agreed to in writing between Synopsys and you.
4083 + *
4084 + * The Software IS NOT an item of Licensed Software or Licensed Product under
4085 + * any End User Software License Agreement or Agreement for Licensed Product
4086 + * with Synopsys or any supplement thereto. You are permitted to use and
4087 + * redistribute this Software in source and binary forms, with or without
4088 + * modification, provided that redistributions of source code must retain this
4089 + * notice. You may not view, use, disclose, copy or distribute this file or
4090 + * any information contained herein except pursuant to this license grant from
4091 + * Synopsys. If you do not agree with this notice, including the disclaimer
4092 + * below, then you are not authorized to use the Software.
4093 + *
4094 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
4095 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
4096 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4097 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
4098 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
4099 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
4100 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
4101 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
4102 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
4103 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
4104 + * DAMAGE.
4105 + * ========================================================================== */
4106 +
4107 +#if !defined(__DWC_CIL_H__)
4108 +#define __DWC_CIL_H__
4109 +
4110 +#include "dwc_otg_plat.h"
4111 +
4112 +#include "dwc_otg_regs.h"
4113 +#ifdef DEBUG
4114 +#include "linux/timer.h"
4115 +#endif
4116 +
4117 +/* the OTG capabilities. */
4118 +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
4119 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
4120 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
4121 +/* the maximum speed of operation in host and device mode. */
4122 +#define DWC_SPEED_PARAM_HIGH 0
4123 +#define DWC_SPEED_PARAM_FULL 1
4124 +/* the PHY clock rate in low power mode when connected to a
4125 + * Low Speed device in host mode. */
4126 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
4127 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
4128 +/* the type of PHY interface to use. */
4129 +#define DWC_PHY_TYPE_PARAM_FS 0
4130 +#define DWC_PHY_TYPE_PARAM_UTMI 1
4131 +#define DWC_PHY_TYPE_PARAM_ULPI 2
4132 +/* whether to use the internal or external supply to
4133 + * drive the vbus with a ULPI phy. */
4134 +#define DWC_PHY_ULPI_INTERNAL_VBUS 0
4135 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
4136 +/* EP type. */
4137 +
4138 +/**
4139 + * @file
4140 + * This file contains the interface to the Core Interface Layer.
4141 + */
4142 +
4143 +/**
4144 + * The <code>dwc_ep</code> structure represents the state of a single
4145 + * endpoint when acting in device mode. It contains the data items
4146 + * needed for an endpoint to be activated and transfer packets.
4147 + */
4148 +typedef struct dwc_ep {
4149 + /** EP number used for register address lookup */
4150 + uint8_t num;
4151 + /** EP direction 0 = OUT */
4152 + unsigned is_in : 1;
4153 + /** EP active. */
4154 + unsigned active : 1;
4155 +
4156 + /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
4157 + If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
4158 + unsigned tx_fifo_num : 4;
4159 + /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
4160 + unsigned type : 2;
4161 +#define DWC_OTG_EP_TYPE_CONTROL 0
4162 +#define DWC_OTG_EP_TYPE_ISOC 1
4163 +#define DWC_OTG_EP_TYPE_BULK 2
4164 +#define DWC_OTG_EP_TYPE_INTR 3
4165 +
4166 + /** DATA start PID for INTR and BULK EP */
4167 + unsigned data_pid_start : 1;
4168 + /** Frame (even/odd) for ISOC EP */
4169 + unsigned even_odd_frame : 1;
4170 + /** Max Packet bytes */
4171 + unsigned maxpacket : 11;
4172 +
4173 + /** @name Transfer state */
4174 + /** @{ */
4175 +
4176 + /**
4177 + * Pointer to the beginning of the transfer buffer -- do not modify
4178 + * during transfer.
4179 + */
4180 +
4181 + uint32_t dma_addr;
4182 +
4183 + uint8_t *start_xfer_buff;
4184 + /** pointer to the transfer buffer */
4185 + uint8_t *xfer_buff;
4186 + /** Number of bytes to transfer */
4187 + unsigned xfer_len : 19;
4188 + /** Number of bytes transferred. */
4189 + unsigned xfer_count : 19;
4190 + /** Sent ZLP */
4191 + unsigned sent_zlp : 1;
4192 + /** Total len for control transfer */
4193 + unsigned total_len : 19;
4194 +
4195 + /** stall clear flag */
4196 + unsigned stall_clear_flag : 1;
4197 +
4198 + /** @} */
4199 +} dwc_ep_t;
4200 +
4201 +/*
4202 + * Reasons for halting a host channel.
4203 + */
4204 +typedef enum dwc_otg_halt_status {
4205 + DWC_OTG_HC_XFER_NO_HALT_STATUS,
4206 + DWC_OTG_HC_XFER_COMPLETE,
4207 + DWC_OTG_HC_XFER_URB_COMPLETE,
4208 + DWC_OTG_HC_XFER_ACK,
4209 + DWC_OTG_HC_XFER_NAK,
4210 + DWC_OTG_HC_XFER_NYET,
4211 + DWC_OTG_HC_XFER_STALL,
4212 + DWC_OTG_HC_XFER_XACT_ERR,
4213 + DWC_OTG_HC_XFER_FRAME_OVERRUN,
4214 + DWC_OTG_HC_XFER_BABBLE_ERR,
4215 + DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
4216 + DWC_OTG_HC_XFER_AHB_ERR,
4217 + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
4218 + DWC_OTG_HC_XFER_URB_DEQUEUE
4219 +} dwc_otg_halt_status_e;
4220 +
4221 +/**
4222 + * Host channel descriptor. This structure represents the state of a single
4223 + * host channel when acting in host mode. It contains the data items needed to
4224 + * transfer packets to an endpoint via a host channel.
4225 + */
4226 +typedef struct dwc_hc {
4227 + /** Host channel number used for register address lookup */
4228 + uint8_t hc_num;
4229 +
4230 + /** Device to access */
4231 + unsigned dev_addr : 7;
4232 +
4233 + /** EP to access */
4234 + unsigned ep_num : 4;
4235 +
4236 + /** EP direction. 0: OUT, 1: IN */
4237 + unsigned ep_is_in : 1;
4238 +
4239 + /**
4240 + * EP speed.
4241 + * One of the following values:
4242 + * - DWC_OTG_EP_SPEED_LOW
4243 + * - DWC_OTG_EP_SPEED_FULL
4244 + * - DWC_OTG_EP_SPEED_HIGH
4245 + */
4246 + unsigned speed : 2;
4247 +#define DWC_OTG_EP_SPEED_LOW 0
4248 +#define DWC_OTG_EP_SPEED_FULL 1
4249 +#define DWC_OTG_EP_SPEED_HIGH 2
4250 +
4251 + /**
4252 + * Endpoint type.
4253 + * One of the following values:
4254 + * - DWC_OTG_EP_TYPE_CONTROL: 0
4255 + * - DWC_OTG_EP_TYPE_ISOC: 1
4256 + * - DWC_OTG_EP_TYPE_BULK: 2
4257 + * - DWC_OTG_EP_TYPE_INTR: 3
4258 + */
4259 + unsigned ep_type : 2;
4260 +
4261 + /** Max packet size in bytes */
4262 + unsigned max_packet : 11;
4263 +
4264 + /**
4265 + * PID for initial transaction.
4266 + * 0: DATA0,<br>
4267 + * 1: DATA2,<br>
4268 + * 2: DATA1,<br>
4269 + * 3: MDATA (non-Control EP),
4270 + * SETUP (Control EP)
4271 + */
4272 + unsigned data_pid_start : 2;
4273 +#define DWC_OTG_HC_PID_DATA0 0
4274 +#define DWC_OTG_HC_PID_DATA2 1
4275 +#define DWC_OTG_HC_PID_DATA1 2
4276 +#define DWC_OTG_HC_PID_MDATA 3
4277 +#define DWC_OTG_HC_PID_SETUP 3
4278 +
4279 + /** Number of periodic transactions per (micro)frame */
4280 + unsigned multi_count: 2;
4281 +
4282 + /** @name Transfer State */
4283 + /** @{ */
4284 +
4285 + /** Pointer to the current transfer buffer position. */
4286 + uint8_t *xfer_buff;
4287 + /** Total number of bytes to transfer. */
4288 + uint32_t xfer_len;
4289 + /** Number of bytes transferred so far. */
4290 + uint32_t xfer_count;
4291 + /** Packet count at start of transfer.*/
4292 + uint16_t start_pkt_count;
4293 +
4294 + /**
4295 + * Flag to indicate whether the transfer has been started. Set to 1 if
4296 + * it has been started, 0 otherwise.
4297 + */
4298 + uint8_t xfer_started;
4299 +
4300 + /**
4301 + * Set to 1 to indicate that a PING request should be issued on this
4302 + * channel. If 0, process normally.
4303 + */
4304 + uint8_t do_ping;
4305 +
4306 + /**
4307 + * Set to 1 to indicate that the error count for this transaction is
4308 + * non-zero. Set to 0 if the error count is 0.
4309 + */
4310 + uint8_t error_state;
4311 +
4312 + /**
4313 + * Set to 1 to indicate that this channel should be halted the next
4314 + * time a request is queued for the channel. This is necessary in
4315 + * slave mode if no request queue space is available when an attempt
4316 + * is made to halt the channel.
4317 + */
4318 + uint8_t halt_on_queue;
4319 +
4320 + /**
4321 + * Set to 1 if the host channel has been halted, but the core is not
4322 + * finished flushing queued requests. Otherwise 0.
4323 + */
4324 + uint8_t halt_pending;
4325 +
4326 + /**
4327 + * Reason for halting the host channel.
4328 + */
4329 + dwc_otg_halt_status_e halt_status;
4330 +
4331 + /*
4332 + * Split settings for the host channel
4333 + */
4334 + uint8_t do_split; /**< Enable split for the channel */
4335 + uint8_t complete_split; /**< Enable complete split */
4336 + uint8_t hub_addr; /**< Address of high speed hub */
4337 +
4338 + uint8_t port_addr; /**< Port of the low/full speed device */
4339 + /** Split transaction position
4340 + * One of the following values:
4341 + * - DWC_HCSPLIT_XACTPOS_MID
4342 + * - DWC_HCSPLIT_XACTPOS_BEGIN
4343 + * - DWC_HCSPLIT_XACTPOS_END
4344 + * - DWC_HCSPLIT_XACTPOS_ALL */
4345 + uint8_t xact_pos;
4346 +
4347 + /** Set when the host channel does a short read. */
4348 + uint8_t short_read;
4349 +
4350 + /**
4351 + * Number of requests issued for this channel since it was assigned to
4352 + * the current transfer (not counting PINGs).
4353 + */
4354 + uint8_t requests;
4355 +
4356 + /**
4357 + * Queue Head for the transfer being processed by this channel.
4358 + */
4359 + struct dwc_otg_qh *qh;
4360 +
4361 + /** @} */
4362 +
4363 + /** Entry in list of host channels. */
4364 + struct list_head hc_list_entry;
4365 +} dwc_hc_t;
4366 +
4367 +/**
4368 + * The following parameters may be specified when starting the module. These
4369 + * parameters define how the DWC_otg controller should be configured.
4370 + * Parameter values are passed to the CIL initialization function
4371 + * dwc_otg_cil_init.
4372 + */
4373 +
4374 +typedef struct dwc_otg_core_params
4375 +{
4376 + int32_t opt;
4377 +//#define dwc_param_opt_default 1
4378 + /**
4379 + * Specifies the OTG capabilities. The driver will automatically
4380 + * detect the value for this parameter if none is specified.
4381 + * 0 - HNP and SRP capable (default)
4382 + * 1 - SRP Only capable
4383 + * 2 - No HNP/SRP capable
4384 + */
4385 + int32_t otg_cap;
4386 +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
4387 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
4388 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
4389 +//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
4390 + /**
4391 + * Specifies whether to use slave or DMA mode for accessing the data
4392 + * FIFOs. The driver will automatically detect the value for this
4393 + * parameter if none is specified.
4394 + * 0 - Slave
4395 + * 1 - DMA (default, if available)
4396 + */
4397 + int32_t dma_enable;
4398 +//#define dwc_param_dma_enable_default 1
4399 + /** The DMA Burst size (applicable only for External DMA
4400 + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
4401 + */
4402 + int32_t dma_burst_size; /* Translate this to GAHBCFG values */
4403 +//#define dwc_param_dma_burst_size_default 32
4404 + /**
4405 + * Specifies the maximum speed of operation in host and device mode.
4406 + * The actual speed depends on the speed of the attached device and
4407 + * the value of phy_type. The actual speed depends on the speed of the
4408 + * attached device.
4409 + * 0 - High Speed (default)
4410 + * 1 - Full Speed
4411 + */
4412 + int32_t speed;
4413 +//#define dwc_param_speed_default 0
4414 +#define DWC_SPEED_PARAM_HIGH 0
4415 +#define DWC_SPEED_PARAM_FULL 1
4416 +
4417 + /** Specifies whether low power mode is supported when attached
4418 + * to a Full Speed or Low Speed device in host mode.
4419 + * 0 - Don't support low power mode (default)
4420 + * 1 - Support low power mode
4421 + */
4422 + int32_t host_support_fs_ls_low_power;
4423 +//#define dwc_param_host_support_fs_ls_low_power_default 0
4424 + /** Specifies the PHY clock rate in low power mode when connected to a
4425 + * Low Speed device in host mode. This parameter is applicable only if
4426 + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
4427 + * then defaults to 6 MHZ otherwise 48 MHZ.
4428 + *
4429 + * 0 - 48 MHz
4430 + * 1 - 6 MHz
4431 + */
4432 + int32_t host_ls_low_power_phy_clk;
4433 +//#define dwc_param_host_ls_low_power_phy_clk_default 0
4434 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
4435 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
4436 + /**
4437 + * 0 - Use cC FIFO size parameters
4438 + * 1 - Allow dynamic FIFO sizing (default)
4439 + */
4440 + int32_t enable_dynamic_fifo;
4441 +//#define dwc_param_enable_dynamic_fifo_default 1
4442 + /** Total number of 4-byte words in the data FIFO memory. This
4443 + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
4444 + * Tx FIFOs.
4445 + * 32 to 32768 (default 8192)
4446 + * Note: The total FIFO memory depth in the FPGA configuration is 8192.
4447 + */
4448 + int32_t data_fifo_size;
4449 +//#define dwc_param_data_fifo_size_default 8192
4450 + /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
4451 + * FIFO sizing is enabled.
4452 + * 16 to 32768 (default 1064)
4453 + */
4454 + int32_t dev_rx_fifo_size;
4455 +//#define dwc_param_dev_rx_fifo_size_default 1064
4456 + /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
4457 + * when dynamic FIFO sizing is enabled.
4458 + * 16 to 32768 (default 1024)
4459 + */
4460 + int32_t dev_nperio_tx_fifo_size;
4461 +//#define dwc_param_dev_nperio_tx_fifo_size_default 1024
4462 + /** Number of 4-byte words in each of the periodic Tx FIFOs in device
4463 + * mode when dynamic FIFO sizing is enabled.
4464 + * 4 to 768 (default 256)
4465 + */
4466 + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
4467 +//#define dwc_param_dev_perio_tx_fifo_size_default 256
4468 + /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
4469 + * FIFO sizing is enabled.
4470 + * 16 to 32768 (default 1024)
4471 + */
4472 + int32_t host_rx_fifo_size;
4473 +//#define dwc_param_host_rx_fifo_size_default 1024
4474 + /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
4475 + * when Dynamic FIFO sizing is enabled in the core.
4476 + * 16 to 32768 (default 1024)
4477 + */
4478 + int32_t host_nperio_tx_fifo_size;
4479 +//#define dwc_param_host_nperio_tx_fifo_size_default 1024
4480 + /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
4481 + * FIFO sizing is enabled.
4482 + * 16 to 32768 (default 1024)
4483 + */
4484 + int32_t host_perio_tx_fifo_size;
4485 +//#define dwc_param_host_perio_tx_fifo_size_default 1024
4486 + /** The maximum transfer size supported in bytes.
4487 + * 2047 to 65,535 (default 65,535)
4488 + */
4489 + int32_t max_transfer_size;
4490 +//#define dwc_param_max_transfer_size_default 65535
4491 + /** The maximum number of packets in a transfer.
4492 + * 15 to 511 (default 511)
4493 + */
4494 + int32_t max_packet_count;
4495 +//#define dwc_param_max_packet_count_default 511
4496 + /** The number of host channel registers to use.
4497 + * 1 to 16 (default 12)
4498 + * Note: The FPGA configuration supports a maximum of 12 host channels.
4499 + */
4500 + int32_t host_channels;
4501 +//#define dwc_param_host_channels_default 12
4502 + /** The number of endpoints in addition to EP0 available for device
4503 + * mode operations.
4504 + * 1 to 15 (default 6 IN and OUT)
4505 + * Note: The FPGA configuration supports a maximum of 6 IN and OUT
4506 + * endpoints in addition to EP0.
4507 + */
4508 + int32_t dev_endpoints;
4509 +//#define dwc_param_dev_endpoints_default 6
4510 + /**
4511 + * Specifies the type of PHY interface to use. By default, the driver
4512 + * will automatically detect the phy_type.
4513 + *
4514 + * 0 - Full Speed PHY
4515 + * 1 - UTMI+ (default)
4516 + * 2 - ULPI
4517 + */
4518 + int32_t phy_type;
4519 +#define DWC_PHY_TYPE_PARAM_FS 0
4520 +#define DWC_PHY_TYPE_PARAM_UTMI 1
4521 +#define DWC_PHY_TYPE_PARAM_ULPI 2
4522 +//#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
4523 + /**
4524 + * Specifies the UTMI+ Data Width. This parameter is
4525 + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
4526 + * PHY_TYPE, this parameter indicates the data width between
4527 + * the MAC and the ULPI Wrapper.) Also, this parameter is
4528 + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
4529 + * to "8 and 16 bits", meaning that the core has been
4530 + * configured to work at either data path width.
4531 + *
4532 + * 8 or 16 bits (default 16)
4533 + */
4534 + int32_t phy_utmi_width;
4535 +//#define dwc_param_phy_utmi_width_default 16
4536 + /**
4537 + * Specifies whether the ULPI operates at double or single
4538 + * data rate. This parameter is only applicable if PHY_TYPE is
4539 + * ULPI.
4540 + *
4541 + * 0 - single data rate ULPI interface with 8 bit wide data
4542 + * bus (default)
4543 + * 1 - double data rate ULPI interface with 4 bit wide data
4544 + * bus
4545 + */
4546 + int32_t phy_ulpi_ddr;
4547 +//#define dwc_param_phy_ulpi_ddr_default 0
4548 + /**
4549 + * Specifies whether to use the internal or external supply to
4550 + * drive the vbus with a ULPI phy.
4551 + */
4552 + int32_t phy_ulpi_ext_vbus;
4553 +#define DWC_PHY_ULPI_INTERNAL_VBUS 0
4554 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
4555 +//#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
4556 + /**
4557 + * Specifies whether to use the I2Cinterface for full speed PHY. This
4558 + * parameter is only applicable if PHY_TYPE is FS.
4559 + * 0 - No (default)
4560 + * 1 - Yes
4561 + */
4562 + int32_t i2c_enable;
4563 +//#define dwc_param_i2c_enable_default 0
4564 +
4565 + int32_t ulpi_fs_ls;
4566 +//#define dwc_param_ulpi_fs_ls_default 0
4567 +
4568 + int32_t ts_dline;
4569 +//#define dwc_param_ts_dline_default 0
4570 +
4571 + /**
4572 + * Specifies whether dedicated transmit FIFOs are
4573 + * enabled for non periodic IN endpoints in device mode
4574 + * 0 - No
4575 + * 1 - Yes
4576 + */
4577 + int32_t en_multiple_tx_fifo;
4578 +#define dwc_param_en_multiple_tx_fifo_default 1
4579 +
4580 + /** Number of 4-byte words in each of the Tx FIFOs in device
4581 + * mode when dynamic FIFO sizing is enabled.
4582 + * 4 to 768 (default 256)
4583 + */
4584 + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
4585 +#define dwc_param_dev_tx_fifo_size_default 256
4586 +
4587 + /** Thresholding enable flag-
4588 + * bit 0 - enable non-ISO Tx thresholding
4589 + * bit 1 - enable ISO Tx thresholding
4590 + * bit 2 - enable Rx thresholding
4591 + */
4592 + uint32_t thr_ctl;
4593 +#define dwc_param_thr_ctl_default 0
4594 +
4595 + /** Thresholding length for Tx
4596 + * FIFOs in 32 bit DWORDs
4597 + */
4598 + uint32_t tx_thr_length;
4599 +#define dwc_param_tx_thr_length_default 64
4600 +
4601 + /** Thresholding length for Rx
4602 + * FIFOs in 32 bit DWORDs
4603 + */
4604 + uint32_t rx_thr_length;
4605 +#define dwc_param_rx_thr_length_default 64
4606 +} dwc_otg_core_params_t;
4607 +
4608 +#ifdef DEBUG
4609 +struct dwc_otg_core_if;
4610 +typedef struct hc_xfer_info
4611 +{
4612 + struct dwc_otg_core_if *core_if;
4613 + dwc_hc_t *hc;
4614 +} hc_xfer_info_t;
4615 +#endif
4616 +
4617 +/**
4618 + * The <code>dwc_otg_core_if</code> structure contains information needed to manage
4619 + * the DWC_otg controller acting in either host or device mode. It
4620 + * represents the programming view of the controller as a whole.
4621 + */
4622 +typedef struct dwc_otg_core_if
4623 +{
4624 + /** Parameters that define how the core should be configured.*/
4625 + dwc_otg_core_params_t *core_params;
4626 +
4627 + /** Core Global registers starting at offset 000h. */
4628 + dwc_otg_core_global_regs_t *core_global_regs;
4629 +
4630 + /** Device-specific information */
4631 + dwc_otg_dev_if_t *dev_if;
4632 + /** Host-specific information */
4633 + dwc_otg_host_if_t *host_if;
4634 +
4635 + /*
4636 + * Set to 1 if the core PHY interface bits in USBCFG have been
4637 + * initialized.
4638 + */
4639 + uint8_t phy_init_done;
4640 +
4641 + /*
4642 + * SRP Success flag, set by srp success interrupt in FS I2C mode
4643 + */
4644 + uint8_t srp_success;
4645 + uint8_t srp_timer_started;
4646 +
4647 + /* Common configuration information */
4648 + /** Power and Clock Gating Control Register */
4649 + volatile uint32_t *pcgcctl;
4650 +#define DWC_OTG_PCGCCTL_OFFSET 0xE00
4651 +
4652 + /** Push/pop addresses for endpoints or host channels.*/
4653 + uint32_t *data_fifo[MAX_EPS_CHANNELS];
4654 +#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
4655 +#define DWC_OTG_DATA_FIFO_SIZE 0x1000
4656 +
4657 + /** Total RAM for FIFOs (Bytes) */
4658 + uint16_t total_fifo_size;
4659 + /** Size of Rx FIFO (Bytes) */
4660 + uint16_t rx_fifo_size;
4661 + /** Size of Non-periodic Tx FIFO (Bytes) */
4662 + uint16_t nperio_tx_fifo_size;
4663 +
4664 + /** 1 if DMA is enabled, 0 otherwise. */
4665 + uint8_t dma_enable;
4666 +
4667 + /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
4668 + uint8_t en_multiple_tx_fifo;
4669 +
4670 + /** Set to 1 if multiple packets of a high-bandwidth transfer is in
4671 + * process of being queued */
4672 + uint8_t queuing_high_bandwidth;
4673 +
4674 + /** Hardware Configuration -- stored here for convenience.*/
4675 + hwcfg1_data_t hwcfg1;
4676 + hwcfg2_data_t hwcfg2;
4677 + hwcfg3_data_t hwcfg3;
4678 + hwcfg4_data_t hwcfg4;
4679 +
4680 + /** The operational State, during transations
4681 + * (a_host>>a_peripherial and b_device=>b_host) this may not
4682 + * match the core but allows the software to determine
4683 + * transitions.
4684 + */
4685 + uint8_t op_state;
4686 +
4687 + /**
4688 + * Set to 1 if the HCD needs to be restarted on a session request
4689 + * interrupt. This is required if no connector ID status change has
4690 + * occurred since the HCD was last disconnected.
4691 + */
4692 + uint8_t restart_hcd_on_session_req;
4693 +
4694 + /** HCD callbacks */
4695 + /** A-Device is a_host */
4696 +#define A_HOST (1)
4697 + /** A-Device is a_suspend */
4698 +#define A_SUSPEND (2)
4699 + /** A-Device is a_peripherial */
4700 +#define A_PERIPHERAL (3)
4701 + /** B-Device is operating as a Peripheral. */
4702 +#define B_PERIPHERAL (4)
4703 + /** B-Device is operating as a Host. */
4704 +#define B_HOST (5)
4705 +
4706 + /** HCD callbacks */
4707 + struct dwc_otg_cil_callbacks *hcd_cb;
4708 + /** PCD callbacks */
4709 + struct dwc_otg_cil_callbacks *pcd_cb;
4710 +
4711 + /** Device mode Periodic Tx FIFO Mask */
4712 + uint32_t p_tx_msk;
4713 + /** Device mode Periodic Tx FIFO Mask */
4714 + uint32_t tx_msk;
4715 +
4716 +#ifdef DEBUG
4717 + uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
4718 +
4719 + hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
4720 + struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
4721 +
4722 +#if 1 // winder
4723 + uint32_t hfnum_7_samples;
4724 + uint32_t hfnum_7_frrem_accum;
4725 + uint32_t hfnum_0_samples;
4726 + uint32_t hfnum_0_frrem_accum;
4727 + uint32_t hfnum_other_samples;
4728 + uint32_t hfnum_other_frrem_accum;
4729 +#else
4730 + uint32_t hfnum_7_samples;
4731 + uint64_t hfnum_7_frrem_accum;
4732 + uint32_t hfnum_0_samples;
4733 + uint64_t hfnum_0_frrem_accum;
4734 + uint32_t hfnum_other_samples;
4735 + uint64_t hfnum_other_frrem_accum;
4736 +#endif
4737 + resource_size_t phys_addr; /* Added to support PLB DMA : phys-virt mapping */
4738 +#endif
4739 +
4740 +} dwc_otg_core_if_t;
4741 +
4742 +/*
4743 + * The following functions support initialization of the CIL driver component
4744 + * and the DWC_otg controller.
4745 + */
4746 +extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
4747 + dwc_otg_core_params_t *_core_params);
4748 +extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
4749 +extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
4750 +extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
4751 +extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
4752 +extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
4753 +extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
4754 +
4755 +/** @name Device CIL Functions
4756 + * The following functions support managing the DWC_otg controller in device
4757 + * mode.
4758 + */
4759 +/**@{*/
4760 +extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
4761 +extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
4762 +extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
4763 +extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4764 +extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4765 +extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4766 +extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4767 +extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4768 +extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4769 +extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
4770 +extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4771 +extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4772 +extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
4773 +extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
4774 +/**@}*/
4775 +
4776 +/** @name Host CIL Functions
4777 + * The following functions support managing the DWC_otg controller in host
4778 + * mode.
4779 + */
4780 +/**@{*/
4781 +extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4782 +extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
4783 + dwc_hc_t *_hc,
4784 + dwc_otg_halt_status_e _halt_status);
4785 +extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4786 +extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4787 +extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4788 +extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4789 +extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4790 +extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
4791 +extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
4792 +
4793 +/**
4794 + * This function Reads HPRT0 in preparation to modify. It keeps the
4795 + * WC bits 0 so that if they are read as 1, they won't clear when you
4796 + * write it back
4797 + */
4798 +static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
4799 +{
4800 + hprt0_data_t hprt0;
4801 + hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
4802 + hprt0.b.prtena = 0;
4803 + hprt0.b.prtconndet = 0;
4804 + hprt0.b.prtenchng = 0;
4805 + hprt0.b.prtovrcurrchng = 0;
4806 + return hprt0.d32;
4807 +}
4808 +
4809 +extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
4810 +/**@}*/
4811 +
4812 +/** @name Common CIL Functions
4813 + * The following functions support managing the DWC_otg controller in either
4814 + * device or host mode.
4815 + */
4816 +/**@{*/
4817 +
4818 +extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
4819 + uint8_t *dest,
4820 + uint16_t bytes);
4821 +
4822 +extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
4823 +
4824 +extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
4825 + const int _num );
4826 +extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
4827 +extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
4828 +
4829 +#define NP_TXFIFO_EMPTY -1
4830 +#define MAX_NP_TXREQUEST_Q_SLOTS 8
4831 +/**
4832 + * This function returns the endpoint number of the request at
4833 + * the top of non-periodic TX FIFO, or -1 if the request FIFO is
4834 + * empty.
4835 + */
4836 +static inline int dwc_otg_top_nptxfifo_epnum(dwc_otg_core_if_t *_core_if) {
4837 + gnptxsts_data_t txstatus = {.d32 = 0};
4838 +
4839 + txstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
4840 + return (txstatus.b.nptxqspcavail == MAX_NP_TXREQUEST_Q_SLOTS ?
4841 + -1 : txstatus.b.nptxqtop_chnep);
4842 +}
4843 +/**
4844 + * This function returns the Core Interrupt register.
4845 + */
4846 +static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) {
4847 + return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
4848 + dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
4849 +}
4850 +
4851 +/**
4852 + * This function returns the OTG Interrupt register.
4853 + */
4854 +static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) {
4855 + return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
4856 +}
4857 +
4858 +/**
4859 + * This function reads the Device All Endpoints Interrupt register and
4860 + * returns the IN endpoint interrupt bits.
4861 + */
4862 +static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *_core_if) {
4863 + uint32_t v;
4864 + v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
4865 + dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
4866 + return (v & 0xffff);
4867 +
4868 +}
4869 +
4870 +/**
4871 + * This function reads the Device All Endpoints Interrupt register and
4872 + * returns the OUT endpoint interrupt bits.
4873 + */
4874 +static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *_core_if) {
4875 + uint32_t v;
4876 + v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
4877 + dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
4878 + return ((v & 0xffff0000) >> 16);
4879 +}
4880 +
4881 +/**
4882 + * This function returns the Device IN EP Interrupt register
4883 + */
4884 +static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *_core_if,
4885 + dwc_ep_t *_ep)
4886 +{
4887 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
4888 + uint32_t v, msk, emp;
4889 + msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
4890 + emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
4891 + msk |= ((emp >> _ep->num) & 0x1) << 7;
4892 + v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & msk;
4893 +/*
4894 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
4895 + uint32_t v;
4896 + v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) &
4897 + dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
4898 +*/
4899 + return v;
4900 +}
4901 +/**
4902 + * This function returns the Device OUT EP Interrupt register
4903 + */
4904 +static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
4905 + dwc_ep_t *_ep)
4906 +{
4907 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
4908 + uint32_t v;
4909 + v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) &
4910 + dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
4911 + return v;
4912 +}
4913 +
4914 +/**
4915 + * This function returns the Host All Channel Interrupt register
4916 + */
4917 +static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
4918 +{
4919 + return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
4920 +}
4921 +
4922 +static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
4923 +{
4924 + return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
4925 +}
4926 +
4927 +
4928 +/**
4929 + * This function returns the mode of the operation, host or device.
4930 + *
4931 + * @return 0 - Device Mode, 1 - Host Mode
4932 + */
4933 +static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) {
4934 + return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
4935 +}
4936 +
4937 +static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
4938 +{
4939 + return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
4940 +}
4941 +static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
4942 +{
4943 + return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
4944 +}
4945 +
4946 +extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
4947 +
4948 +
4949 +/**@}*/
4950 +
4951 +/**
4952 + * DWC_otg CIL callback structure. This structure allows the HCD and
4953 + * PCD to register functions used for starting and stopping the PCD
4954 + * and HCD for role change on for a DRD.
4955 + */
4956 +typedef struct dwc_otg_cil_callbacks
4957 +{
4958 + /** Start function for role change */
4959 + int (*start) (void *_p);
4960 + /** Stop Function for role change */
4961 + int (*stop) (void *_p);
4962 + /** Disconnect Function for role change */
4963 + int (*disconnect) (void *_p);
4964 + /** Resume/Remote wakeup Function */
4965 + int (*resume_wakeup) (void *_p);
4966 + /** Suspend function */
4967 + int (*suspend) (void *_p);
4968 + /** Session Start (SRP) */
4969 + int (*session_start) (void *_p);
4970 + /** Pointer passed to start() and stop() */
4971 + void *p;
4972 +} dwc_otg_cil_callbacks_t;
4973 +
4974 +
4975 +
4976 +extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
4977 + dwc_otg_cil_callbacks_t *_cb,
4978 + void *_p);
4979 +extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
4980 + dwc_otg_cil_callbacks_t *_cb,
4981 + void *_p);
4982 +
4983 +
4984 +#endif
4985 --- /dev/null
4986 +++ b/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h
4987 @@ -0,0 +1,58 @@
4988 +/******************************************************************************
4989 +**
4990 +** FILE NAME : dwc_otg_cil_ifx.h
4991 +** PROJECT : Twinpass/Danube
4992 +** MODULES : DWC OTG USB
4993 +**
4994 +** DATE : 07 Sep. 2007
4995 +** AUTHOR : Sung Winder
4996 +** DESCRIPTION : Default param value.
4997 +** COPYRIGHT : Copyright (c) 2007
4998 +** Infineon Technologies AG
4999 +** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
5000 +** Hsin-chu City, 300 Taiwan.
5001 +**
5002 +** This program is free software; you can redistribute it and/or modify
5003 +** it under the terms of the GNU General Public License as published by
5004 +** the Free Software Foundation; either version 2 of the License, or
5005 +** (at your option) any later version.
5006 +**
5007 +** HISTORY
5008 +** $Date $Author $Comment
5009 +** 12 April 2007 Sung Winder Initiate Version
5010 +*******************************************************************************/
5011 +#if !defined(__DWC_OTG_CIL_IFX_H__)
5012 +#define __DWC_OTG_CIL_IFX_H__
5013 +
5014 +/* ================ Default param value ================== */
5015 +#define dwc_param_opt_default 1
5016 +#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
5017 +#define dwc_param_dma_enable_default 1
5018 +#define dwc_param_dma_burst_size_default 32
5019 +#define dwc_param_speed_default DWC_SPEED_PARAM_HIGH
5020 +#define dwc_param_host_support_fs_ls_low_power_default 0
5021 +#define dwc_param_host_ls_low_power_phy_clk_default DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ
5022 +#define dwc_param_enable_dynamic_fifo_default 1
5023 +#define dwc_param_data_fifo_size_default 2048
5024 +#define dwc_param_dev_rx_fifo_size_default 1024
5025 +#define dwc_param_dev_nperio_tx_fifo_size_default 1024
5026 +#define dwc_param_dev_perio_tx_fifo_size_default 768
5027 +#define dwc_param_host_rx_fifo_size_default 640
5028 +#define dwc_param_host_nperio_tx_fifo_size_default 640
5029 +#define dwc_param_host_perio_tx_fifo_size_default 768
5030 +#define dwc_param_max_transfer_size_default 65535
5031 +#define dwc_param_max_packet_count_default 511
5032 +#define dwc_param_host_channels_default 16
5033 +#define dwc_param_dev_endpoints_default 6
5034 +#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
5035 +#define dwc_param_phy_utmi_width_default 16
5036 +#define dwc_param_phy_ulpi_ddr_default 0
5037 +#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
5038 +#define dwc_param_i2c_enable_default 0
5039 +#define dwc_param_ulpi_fs_ls_default 0
5040 +#define dwc_param_ts_dline_default 0
5041 +
5042 +/* ======================================================= */
5043 +
5044 +#endif // __DWC_OTG_CIL_IFX_H__
5045 +
5046 --- /dev/null
5047 +++ b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c
5048 @@ -0,0 +1,708 @@
5049 +/* ==========================================================================
5050 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil_intr.c $
5051 + * $Revision: 1.1.1.1 $
5052 + * $Date: 2009-04-17 06:15:34 $
5053 + * $Change: 553126 $
5054 + *
5055 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
5056 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
5057 + * otherwise expressly agreed to in writing between Synopsys and you.
5058 + *
5059 + * The Software IS NOT an item of Licensed Software or Licensed Product under
5060 + * any End User Software License Agreement or Agreement for Licensed Product
5061 + * with Synopsys or any supplement thereto. You are permitted to use and
5062 + * redistribute this Software in source and binary forms, with or without
5063 + * modification, provided that redistributions of source code must retain this
5064 + * notice. You may not view, use, disclose, copy or distribute this file or
5065 + * any information contained herein except pursuant to this license grant from
5066 + * Synopsys. If you do not agree with this notice, including the disclaimer
5067 + * below, then you are not authorized to use the Software.
5068 + *
5069 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
5070 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
5071 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
5072 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
5073 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5074 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
5075 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
5076 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
5077 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
5078 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
5079 + * DAMAGE.
5080 + * ========================================================================== */
5081 +
5082 +/** @file
5083 + *
5084 + * The Core Interface Layer provides basic services for accessing and
5085 + * managing the DWC_otg hardware. These services are used by both the
5086 + * Host Controller Driver and the Peripheral Controller Driver.
5087 + *
5088 + * This file contains the Common Interrupt handlers.
5089 + */
5090 +#include "dwc_otg_plat.h"
5091 +#include "dwc_otg_regs.h"
5092 +#include "dwc_otg_cil.h"
5093 +
5094 +#ifdef DEBUG
5095 +inline const char *op_state_str( dwc_otg_core_if_t *_core_if )
5096 +{
5097 + return (_core_if->op_state==A_HOST?"a_host":
5098 + (_core_if->op_state==A_SUSPEND?"a_suspend":
5099 + (_core_if->op_state==A_PERIPHERAL?"a_peripheral":
5100 + (_core_if->op_state==B_PERIPHERAL?"b_peripheral":
5101 + (_core_if->op_state==B_HOST?"b_host":
5102 + "unknown")))));
5103 +}
5104 +#endif
5105 +
5106 +/** This function will log a debug message
5107 + *
5108 + * @param _core_if Programming view of DWC_otg controller.
5109 + */
5110 +int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *_core_if)
5111 +{
5112 + gintsts_data_t gintsts;
5113 + DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
5114 + dwc_otg_mode(_core_if) ? "Host" : "Device");
5115 +
5116 + /* Clear interrupt */
5117 + gintsts.d32 = 0;
5118 + gintsts.b.modemismatch = 1;
5119 + dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
5120 + return 1;
5121 +}
5122 +
5123 +/** Start the HCD. Helper function for using the HCD callbacks.
5124 + *
5125 + * @param _core_if Programming view of DWC_otg controller.
5126 + */
5127 +static inline void hcd_start( dwc_otg_core_if_t *_core_if )
5128 +{
5129 + if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
5130 + _core_if->hcd_cb->start( _core_if->hcd_cb->p );
5131 + }
5132 +}
5133 +/** Stop the HCD. Helper function for using the HCD callbacks.
5134 + *
5135 + * @param _core_if Programming view of DWC_otg controller.
5136 + */
5137 +static inline void hcd_stop( dwc_otg_core_if_t *_core_if )
5138 +{
5139 + if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
5140 + _core_if->hcd_cb->stop( _core_if->hcd_cb->p );
5141 + }
5142 +}
5143 +/** Disconnect the HCD. Helper function for using the HCD callbacks.
5144 + *
5145 + * @param _core_if Programming view of DWC_otg controller.
5146 + */
5147 +static inline void hcd_disconnect( dwc_otg_core_if_t *_core_if )
5148 +{
5149 + if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
5150 + _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
5151 + }
5152 +}
5153 +/** Inform the HCD the a New Session has begun. Helper function for
5154 + * using the HCD callbacks.
5155 + *
5156 + * @param _core_if Programming view of DWC_otg controller.
5157 + */
5158 +static inline void hcd_session_start( dwc_otg_core_if_t *_core_if )
5159 +{
5160 + if (_core_if->hcd_cb && _core_if->hcd_cb->session_start) {
5161 + _core_if->hcd_cb->session_start( _core_if->hcd_cb->p );
5162 + }
5163 +}
5164 +
5165 +/** Start the PCD. Helper function for using the PCD callbacks.
5166 + *
5167 + * @param _core_if Programming view of DWC_otg controller.
5168 + */
5169 +static inline void pcd_start( dwc_otg_core_if_t *_core_if )
5170 +{
5171 + if (_core_if->pcd_cb && _core_if->pcd_cb->start ) {
5172 + _core_if->pcd_cb->start( _core_if->pcd_cb->p );
5173 + }
5174 +}
5175 +/** Stop the PCD. Helper function for using the PCD callbacks.
5176 + *
5177 + * @param _core_if Programming view of DWC_otg controller.
5178 + */
5179 +static inline void pcd_stop( dwc_otg_core_if_t *_core_if )
5180 +{
5181 + if (_core_if->pcd_cb && _core_if->pcd_cb->stop ) {
5182 + _core_if->pcd_cb->stop( _core_if->pcd_cb->p );
5183 + }
5184 +}
5185 +/** Suspend the PCD. Helper function for using the PCD callbacks.
5186 + *
5187 + * @param _core_if Programming view of DWC_otg controller.
5188 + */
5189 +static inline void pcd_suspend( dwc_otg_core_if_t *_core_if )
5190 +{
5191 + if (_core_if->pcd_cb && _core_if->pcd_cb->suspend ) {
5192 + _core_if->pcd_cb->suspend( _core_if->pcd_cb->p );
5193 + }
5194 +}
5195 +/** Resume the PCD. Helper function for using the PCD callbacks.
5196 + *
5197 + * @param _core_if Programming view of DWC_otg controller.
5198 + */
5199 +static inline void pcd_resume( dwc_otg_core_if_t *_core_if )
5200 +{
5201 + if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup ) {
5202 + _core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p );
5203 + }
5204 +}
5205 +
5206 +/**
5207 + * This function handles the OTG Interrupts. It reads the OTG
5208 + * Interrupt Register (GOTGINT) to determine what interrupt has
5209 + * occurred.
5210 + *
5211 + * @param _core_if Programming view of DWC_otg controller.
5212 + */
5213 +int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *_core_if)
5214 +{
5215 + dwc_otg_core_global_regs_t *global_regs =
5216 + _core_if->core_global_regs;
5217 + gotgint_data_t gotgint;
5218 + gotgctl_data_t gotgctl;
5219 + gintmsk_data_t gintmsk;
5220 +
5221 + gotgint.d32 = dwc_read_reg32( &global_regs->gotgint);
5222 + gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
5223 + DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
5224 + op_state_str(_core_if));
5225 + //DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32 );
5226 +
5227 + if (gotgint.b.sesenddet) {
5228 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
5229 + "Session End Detected++ (%s)\n",
5230 + op_state_str(_core_if));
5231 + gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
5232 +
5233 + if (_core_if->op_state == B_HOST) {
5234 + pcd_start( _core_if );
5235 + _core_if->op_state = B_PERIPHERAL;
5236 + } else {
5237 + /* If not B_HOST and Device HNP still set. HNP
5238 + * Did not succeed!*/
5239 + if (gotgctl.b.devhnpen) {
5240 + DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
5241 + DWC_ERROR( "Device Not Connected/Responding!\n" );
5242 + }
5243 +
5244 + /* If Session End Detected the B-Cable has
5245 + * been disconnected. */
5246 + /* Reset PCD and Gadget driver to a
5247 + * clean state. */
5248 + pcd_stop(_core_if);
5249 + }
5250 + gotgctl.d32 = 0;
5251 + gotgctl.b.devhnpen = 1;
5252 + dwc_modify_reg32( &global_regs->gotgctl,
5253 + gotgctl.d32, 0);
5254 + }
5255 + if (gotgint.b.sesreqsucstschng) {
5256 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
5257 + "Session Reqeust Success Status Change++\n");
5258 + gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
5259 + if (gotgctl.b.sesreqscs) {
5260 + if ((_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
5261 + (_core_if->core_params->i2c_enable)) {
5262 + _core_if->srp_success = 1;
5263 + }
5264 + else {
5265 + pcd_resume( _core_if );
5266 + /* Clear Session Request */
5267 + gotgctl.d32 = 0;
5268 + gotgctl.b.sesreq = 1;
5269 + dwc_modify_reg32( &global_regs->gotgctl,
5270 + gotgctl.d32, 0);
5271 + }
5272 + }
5273 + }
5274 + if (gotgint.b.hstnegsucstschng) {
5275 + /* Print statements during the HNP interrupt handling
5276 + * can cause it to fail.*/
5277 + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
5278 + if (gotgctl.b.hstnegscs) {
5279 + if (dwc_otg_is_host_mode(_core_if) ) {
5280 + _core_if->op_state = B_HOST;
5281 + /*
5282 + * Need to disable SOF interrupt immediately.
5283 + * When switching from device to host, the PCD
5284 + * interrupt handler won't handle the
5285 + * interrupt if host mode is already set. The
5286 + * HCD interrupt handler won't get called if
5287 + * the HCD state is HALT. This means that the
5288 + * interrupt does not get handled and Linux
5289 + * complains loudly.
5290 + */
5291 + gintmsk.d32 = 0;
5292 + gintmsk.b.sofintr = 1;
5293 + dwc_modify_reg32(&global_regs->gintmsk,
5294 + gintmsk.d32, 0);
5295 + pcd_stop(_core_if);
5296 + /*
5297 + * Initialize the Core for Host mode.
5298 + */
5299 + hcd_start( _core_if );
5300 + _core_if->op_state = B_HOST;
5301 + }
5302 + } else {
5303 + gotgctl.d32 = 0;
5304 + gotgctl.b.hnpreq = 1;
5305 + gotgctl.b.devhnpen = 1;
5306 + dwc_modify_reg32( &global_regs->gotgctl,
5307 + gotgctl.d32, 0);
5308 + DWC_DEBUGPL( DBG_ANY, "HNP Failed\n");
5309 + DWC_ERROR( "Device Not Connected/Responding\n" );
5310 + }
5311 + }
5312 + if (gotgint.b.hstnegdet) {
5313 + /* The disconnect interrupt is set at the same time as
5314 + * Host Negotiation Detected. During the mode
5315 + * switch all interrupts are cleared so the disconnect
5316 + * interrupt handler will not get executed.
5317 + */
5318 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
5319 + "Host Negotiation Detected++ (%s)\n",
5320 + (dwc_otg_is_host_mode(_core_if)?"Host":"Device"));
5321 + if (dwc_otg_is_device_mode(_core_if)){
5322 + DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",_core_if->op_state);
5323 + hcd_disconnect( _core_if );
5324 + pcd_start( _core_if );
5325 + _core_if->op_state = A_PERIPHERAL;
5326 + } else {
5327 + /*
5328 + * Need to disable SOF interrupt immediately. When
5329 + * switching from device to host, the PCD interrupt
5330 + * handler won't handle the interrupt if host mode is
5331 + * already set. The HCD interrupt handler won't get
5332 + * called if the HCD state is HALT. This means that
5333 + * the interrupt does not get handled and Linux
5334 + * complains loudly.
5335 + */
5336 + gintmsk.d32 = 0;
5337 + gintmsk.b.sofintr = 1;
5338 + dwc_modify_reg32(&global_regs->gintmsk,
5339 + gintmsk.d32, 0);
5340 + pcd_stop( _core_if );
5341 + hcd_start( _core_if );
5342 + _core_if->op_state = A_HOST;
5343 + }
5344 + }
5345 + if (gotgint.b.adevtoutchng) {
5346 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
5347 + "A-Device Timeout Change++\n");
5348 + }
5349 + if (gotgint.b.debdone) {
5350 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
5351 + "Debounce Done++\n");
5352 + }
5353 +
5354 + /* Clear GOTGINT */
5355 + dwc_write_reg32 (&_core_if->core_global_regs->gotgint, gotgint.d32);
5356 +
5357 + return 1;
5358 +}
5359 +
5360 +/**
5361 + * This function handles the Connector ID Status Change Interrupt. It
5362 + * reads the OTG Interrupt Register (GOTCTL) to determine whether this
5363 + * is a Device to Host Mode transition or a Host Mode to Device
5364 + * Transition.
5365 + *
5366 + * This only occurs when the cable is connected/removed from the PHY
5367 + * connector.
5368 + *
5369 + * @param _core_if Programming view of DWC_otg controller.
5370 + */
5371 +int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *_core_if)
5372 +{
5373 + uint32_t count = 0;
5374 +
5375 + gintsts_data_t gintsts = { .d32 = 0 };
5376 + gintmsk_data_t gintmsk = { .d32 = 0 };
5377 + gotgctl_data_t gotgctl = { .d32 = 0 };
5378 +
5379 + /*
5380 + * Need to disable SOF interrupt immediately. If switching from device
5381 + * to host, the PCD interrupt handler won't handle the interrupt if
5382 + * host mode is already set. The HCD interrupt handler won't get
5383 + * called if the HCD state is HALT. This means that the interrupt does
5384 + * not get handled and Linux complains loudly.
5385 + */
5386 + gintmsk.b.sofintr = 1;
5387 + dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
5388 +
5389 + DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n",
5390 + (dwc_otg_is_host_mode(_core_if)?"Host":"Device"));
5391 + gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
5392 + DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
5393 + DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
5394 +
5395 + /* B-Device connector (Device Mode) */
5396 + if (gotgctl.b.conidsts) {
5397 + /* Wait for switch to device mode. */
5398 + while (!dwc_otg_is_device_mode(_core_if) ){
5399 + DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
5400 + (dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral"));
5401 + MDELAY(100);
5402 + if (++count > 10000) *(uint32_t*)NULL=0;
5403 + }
5404 + _core_if->op_state = B_PERIPHERAL;
5405 + dwc_otg_core_init(_core_if);
5406 + dwc_otg_enable_global_interrupts(_core_if);
5407 + pcd_start( _core_if );
5408 + } else {
5409 + /* A-Device connector (Host Mode) */
5410 + while (!dwc_otg_is_host_mode(_core_if) ) {
5411 + DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
5412 + (dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral"));
5413 + MDELAY(100);
5414 + if (++count > 10000) *(uint32_t*)NULL=0;
5415 + }
5416 + _core_if->op_state = A_HOST;
5417 + /*
5418 + * Initialize the Core for Host mode.
5419 + */
5420 + dwc_otg_core_init(_core_if);
5421 + dwc_otg_enable_global_interrupts(_core_if);
5422 + hcd_start( _core_if );
5423 + }
5424 +
5425 + /* Set flag and clear interrupt */
5426 + gintsts.b.conidstschng = 1;
5427 + dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
5428 +
5429 + return 1;
5430 +}
5431 +
5432 +/**
5433 + * This interrupt indicates that a device is initiating the Session
5434 + * Request Protocol to request the host to turn on bus power so a new
5435 + * session can begin. The handler responds by turning on bus power. If
5436 + * the DWC_otg controller is in low power mode, the handler brings the
5437 + * controller out of low power mode before turning on bus power.
5438 + *
5439 + * @param _core_if Programming view of DWC_otg controller.
5440 + */
5441 +int32_t dwc_otg_handle_session_req_intr( dwc_otg_core_if_t *_core_if )
5442 +{
5443 +#ifndef DWC_HOST_ONLY // winder
5444 + hprt0_data_t hprt0;
5445 +#endif
5446 + gintsts_data_t gintsts;
5447 +
5448 +#ifndef DWC_HOST_ONLY
5449 + DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
5450 +
5451 + if (dwc_otg_is_device_mode(_core_if) ) {
5452 + DWC_PRINT("SRP: Device mode\n");
5453 + } else {
5454 + DWC_PRINT("SRP: Host mode\n");
5455 +
5456 + /* Turn on the port power bit. */
5457 + hprt0.d32 = dwc_otg_read_hprt0( _core_if );
5458 + hprt0.b.prtpwr = 1;
5459 + dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
5460 +
5461 + /* Start the Connection timer. So a message can be displayed
5462 + * if connect does not occur within 10 seconds. */
5463 + hcd_session_start( _core_if );
5464 + }
5465 +#endif
5466 +
5467 + /* Clear interrupt */
5468 + gintsts.d32 = 0;
5469 + gintsts.b.sessreqintr = 1;
5470 + dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
5471 +
5472 + return 1;
5473 +}
5474 +
5475 +/**
5476 + * This interrupt indicates that the DWC_otg controller has detected a
5477 + * resume or remote wakeup sequence. If the DWC_otg controller is in
5478 + * low power mode, the handler must brings the controller out of low
5479 + * power mode. The controller automatically begins resume
5480 + * signaling. The handler schedules a time to stop resume signaling.
5481 + */
5482 +int32_t dwc_otg_handle_wakeup_detected_intr( dwc_otg_core_if_t *_core_if )
5483 +{
5484 + gintsts_data_t gintsts;
5485 +
5486 + DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
5487 +
5488 + if (dwc_otg_is_device_mode(_core_if) ) {
5489 + dctl_data_t dctl = {.d32=0};
5490 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
5491 + dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts));
5492 +#ifdef PARTIAL_POWER_DOWN
5493 + if (_core_if->hwcfg4.b.power_optimiz) {
5494 + pcgcctl_data_t power = {.d32=0};
5495 +
5496 + power.d32 = dwc_read_reg32( _core_if->pcgcctl );
5497 + DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
5498 +
5499 + power.b.stoppclk = 0;
5500 + dwc_write_reg32( _core_if->pcgcctl, power.d32);
5501 +
5502 + power.b.pwrclmp = 0;
5503 + dwc_write_reg32( _core_if->pcgcctl, power.d32);
5504 +
5505 + power.b.rstpdwnmodule = 0;
5506 + dwc_write_reg32( _core_if->pcgcctl, power.d32);
5507 + }
5508 +#endif
5509 + /* Clear the Remote Wakeup Signalling */
5510 + dctl.b.rmtwkupsig = 1;
5511 + dwc_modify_reg32( &_core_if->dev_if->dev_global_regs->dctl,
5512 + dctl.d32, 0 );
5513 +
5514 + if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup) {
5515 + _core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p );
5516 + }
5517 +
5518 + } else {
5519 + /*
5520 + * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
5521 + * so that OPT tests pass with all PHYs).
5522 + */
5523 + hprt0_data_t hprt0 = {.d32=0};
5524 + pcgcctl_data_t pcgcctl = {.d32=0};
5525 + /* Restart the Phy Clock */
5526 + pcgcctl.b.stoppclk = 1;
5527 + dwc_modify_reg32(_core_if->pcgcctl, pcgcctl.d32, 0);
5528 + UDELAY(10);
5529 +
5530 + /* Now wait for 70 ms. */
5531 + hprt0.d32 = dwc_otg_read_hprt0( _core_if );
5532 + DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
5533 + MDELAY(70);
5534 + hprt0.b.prtres = 0; /* Resume */
5535 + dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
5536 + DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(_core_if->host_if->hprt0));
5537 + }
5538 +
5539 + /* Clear interrupt */
5540 + gintsts.d32 = 0;
5541 + gintsts.b.wkupintr = 1;
5542 + dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
5543 +
5544 + return 1;
5545 +}
5546 +
5547 +/**
5548 + * This interrupt indicates that a device has been disconnected from
5549 + * the root port.
5550 + */
5551 +int32_t dwc_otg_handle_disconnect_intr( dwc_otg_core_if_t *_core_if)
5552 +{
5553 + gintsts_data_t gintsts;
5554 +
5555 + DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
5556 + (dwc_otg_is_host_mode(_core_if)?"Host":"Device"),
5557 + op_state_str(_core_if));
5558 +
5559 +/** @todo Consolidate this if statement. */
5560 +#ifndef DWC_HOST_ONLY
5561 + if (_core_if->op_state == B_HOST) {
5562 + /* If in device mode Disconnect and stop the HCD, then
5563 + * start the PCD. */
5564 + hcd_disconnect( _core_if );
5565 + pcd_start( _core_if );
5566 + _core_if->op_state = B_PERIPHERAL;
5567 + } else if (dwc_otg_is_device_mode(_core_if)) {
5568 + gotgctl_data_t gotgctl = { .d32 = 0 };
5569 + gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
5570 + if (gotgctl.b.hstsethnpen==1) {
5571 + /* Do nothing, if HNP in process the OTG
5572 + * interrupt "Host Negotiation Detected"
5573 + * interrupt will do the mode switch.
5574 + */
5575 + } else if (gotgctl.b.devhnpen == 0) {
5576 + /* If in device mode Disconnect and stop the HCD, then
5577 + * start the PCD. */
5578 + hcd_disconnect( _core_if );
5579 + pcd_start( _core_if );
5580 + _core_if->op_state = B_PERIPHERAL;
5581 + } else {
5582 + DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
5583 + }
5584 + } else {
5585 + if (_core_if->op_state == A_HOST) {
5586 + /* A-Cable still connected but device disconnected. */
5587 + hcd_disconnect( _core_if );
5588 + }
5589 + }
5590 +#endif
5591 +/* Without OTG, we should use the disconnect function!? winder added.*/
5592 +#if 1 // NO OTG, so host only!!
5593 + hcd_disconnect( _core_if );
5594 +#endif
5595 +
5596 + gintsts.d32 = 0;
5597 + gintsts.b.disconnect = 1;
5598 + dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
5599 + return 1;
5600 +}
5601 +/**
5602 + * This interrupt indicates that SUSPEND state has been detected on
5603 + * the USB.
5604 + *
5605 + * For HNP the USB Suspend interrupt signals the change from
5606 + * "a_peripheral" to "a_host".
5607 + *
5608 + * When power management is enabled the core will be put in low power
5609 + * mode.
5610 + */
5611 +int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *_core_if )
5612 +{
5613 + dsts_data_t dsts;
5614 + gintsts_data_t gintsts;
5615 +
5616 + //805141:<IFTW-fchang>.removed DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
5617 +
5618 + if (dwc_otg_is_device_mode( _core_if ) ) {
5619 + /* Check the Device status register to determine if the Suspend
5620 + * state is active. */
5621 + dsts.d32 = dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts);
5622 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
5623 + DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
5624 + "HWCFG4.power Optimize=%d\n",
5625 + dsts.b.suspsts, _core_if->hwcfg4.b.power_optimiz);
5626 +
5627 +
5628 +#ifdef PARTIAL_POWER_DOWN
5629 +/** @todo Add a module parameter for power management. */
5630 +
5631 + if (dsts.b.suspsts && _core_if->hwcfg4.b.power_optimiz) {
5632 + pcgcctl_data_t power = {.d32=0};
5633 + DWC_DEBUGPL(DBG_CIL, "suspend\n");
5634 +
5635 + power.b.pwrclmp = 1;
5636 + dwc_write_reg32( _core_if->pcgcctl, power.d32);
5637 +
5638 + power.b.rstpdwnmodule = 1;
5639 + dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32);
5640 +
5641 + power.b.stoppclk = 1;
5642 + dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32);
5643 +
5644 + } else {
5645 + DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
5646 + }
5647 +#endif
5648 + /* PCD callback for suspend. */
5649 + pcd_suspend(_core_if);
5650 + } else {
5651 + if (_core_if->op_state == A_PERIPHERAL) {
5652 + DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
5653 + /* Clear the a_peripheral flag, back to a_host. */
5654 + pcd_stop( _core_if );
5655 + hcd_start( _core_if );
5656 + _core_if->op_state = A_HOST;
5657 + }
5658 + }
5659 +
5660 + /* Clear interrupt */
5661 + gintsts.d32 = 0;
5662 + gintsts.b.usbsuspend = 1;
5663 + dwc_write_reg32( &_core_if->core_global_regs->gintsts, gintsts.d32);
5664 +
5665 + return 1;
5666 +}
5667 +
5668 +
5669 +/**
5670 + * This function returns the Core Interrupt register.
5671 + */
5672 +static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *_core_if)
5673 +{
5674 + gintsts_data_t gintsts;
5675 + gintmsk_data_t gintmsk;
5676 + gintmsk_data_t gintmsk_common = {.d32=0};
5677 + gintmsk_common.b.wkupintr = 1;
5678 + gintmsk_common.b.sessreqintr = 1;
5679 + gintmsk_common.b.conidstschng = 1;
5680 + gintmsk_common.b.otgintr = 1;
5681 + gintmsk_common.b.modemismatch = 1;
5682 + gintmsk_common.b.disconnect = 1;
5683 + gintmsk_common.b.usbsuspend = 1;
5684 + /** @todo: The port interrupt occurs while in device
5685 + * mode. Added code to CIL to clear the interrupt for now!
5686 + */
5687 + gintmsk_common.b.portintr = 1;
5688 +
5689 + gintsts.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintsts);
5690 + gintmsk.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintmsk);
5691 +#ifdef DEBUG
5692 + /* if any common interrupts set */
5693 + if (gintsts.d32 & gintmsk_common.d32) {
5694 + DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
5695 + gintsts.d32, gintmsk.d32);
5696 + }
5697 +#endif
5698 +
5699 + return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32);
5700 +
5701 +}
5702 +
5703 +/**
5704 + * Common interrupt handler.
5705 + *
5706 + * The common interrupts are those that occur in both Host and Device mode.
5707 + * This handler handles the following interrupts:
5708 + * - Mode Mismatch Interrupt
5709 + * - Disconnect Interrupt
5710 + * - OTG Interrupt
5711 + * - Connector ID Status Change Interrupt
5712 + * - Session Request Interrupt.
5713 + * - Resume / Remote Wakeup Detected Interrupt.
5714 + *
5715 + */
5716 +extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if )
5717 +{
5718 + int retval = 0;
5719 + gintsts_data_t gintsts;
5720 +
5721 + gintsts.d32 = dwc_otg_read_common_intr(_core_if);
5722 +
5723 + if (gintsts.b.modemismatch) {
5724 + retval |= dwc_otg_handle_mode_mismatch_intr( _core_if );
5725 + }
5726 + if (gintsts.b.otgintr) {
5727 + retval |= dwc_otg_handle_otg_intr( _core_if );
5728 + }
5729 + if (gintsts.b.conidstschng) {
5730 + retval |= dwc_otg_handle_conn_id_status_change_intr( _core_if );
5731 + }
5732 + if (gintsts.b.disconnect) {
5733 + retval |= dwc_otg_handle_disconnect_intr( _core_if );
5734 + }
5735 + if (gintsts.b.sessreqintr) {
5736 + retval |= dwc_otg_handle_session_req_intr( _core_if );
5737 + }
5738 + if (gintsts.b.wkupintr) {
5739 + retval |= dwc_otg_handle_wakeup_detected_intr( _core_if );
5740 + }
5741 + if (gintsts.b.usbsuspend) {
5742 + retval |= dwc_otg_handle_usb_suspend_intr( _core_if );
5743 + }
5744 + if (gintsts.b.portintr && dwc_otg_is_device_mode(_core_if)) {
5745 + /* The port interrupt occurs while in device mode with HPRT0
5746 + * Port Enable/Disable.
5747 + */
5748 + gintsts.d32 = 0;
5749 + gintsts.b.portintr = 1;
5750 + dwc_write_reg32(&_core_if->core_global_regs->gintsts,
5751 + gintsts.d32);
5752 + retval |= 1;
5753 +
5754 + }
5755 + return retval;
5756 +}
5757 --- /dev/null
5758 +++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
5759 @@ -0,0 +1,1274 @@
5760 +/* ==========================================================================
5761 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
5762 + * $Revision: 1.1.1.1 $
5763 + * $Date: 2009-04-17 06:15:34 $
5764 + * $Change: 631780 $
5765 + *
5766 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
5767 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
5768 + * otherwise expressly agreed to in writing between Synopsys and you.
5769 + *
5770 + * The Software IS NOT an item of Licensed Software or Licensed Product under
5771 + * any End User Software License Agreement or Agreement for Licensed Product
5772 + * with Synopsys or any supplement thereto. You are permitted to use and
5773 + * redistribute this Software in source and binary forms, with or without
5774 + * modification, provided that redistributions of source code must retain this
5775 + * notice. You may not view, use, disclose, copy or distribute this file or
5776 + * any information contained herein except pursuant to this license grant from
5777 + * Synopsys. If you do not agree with this notice, including the disclaimer
5778 + * below, then you are not authorized to use the Software.
5779 + *
5780 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
5781 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
5782 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
5783 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
5784 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5785 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
5786 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
5787 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
5788 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
5789 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
5790 + * DAMAGE.
5791 + * ========================================================================== */
5792 +
5793 +/** @file
5794 + * The dwc_otg_driver module provides the initialization and cleanup entry
5795 + * points for the DWC_otg driver. This module will be dynamically installed
5796 + * after Linux is booted using the insmod command. When the module is
5797 + * installed, the dwc_otg_init function is called. When the module is
5798 + * removed (using rmmod), the dwc_otg_cleanup function is called.
5799 + *
5800 + * This module also defines a data structure for the dwc_otg_driver, which is
5801 + * used in conjunction with the standard ARM lm_device structure. These
5802 + * structures allow the OTG driver to comply with the standard Linux driver
5803 + * model in which devices and drivers are registered with a bus driver. This
5804 + * has the benefit that Linux can expose attributes of the driver and device
5805 + * in its special sysfs file system. Users can then read or write files in
5806 + * this file system to perform diagnostics on the driver components or the
5807 + * device.
5808 + */
5809 +
5810 +#include <linux/kernel.h>
5811 +#include <linux/module.h>
5812 +#include <linux/moduleparam.h>
5813 +#include <linux/init.h>
5814 +#include <linux/gpio.h>
5815 +
5816 +#include <linux/device.h>
5817 +#include <linux/platform_device.h>
5818 +
5819 +#include <linux/errno.h>
5820 +#include <linux/types.h>
5821 +#include <linux/stat.h> /* permission constants */
5822 +#include <linux/irq.h>
5823 +#include <asm/io.h>
5824 +
5825 +#include "dwc_otg_plat.h"
5826 +#include "dwc_otg_attr.h"
5827 +#include "dwc_otg_driver.h"
5828 +#include "dwc_otg_cil.h"
5829 +#include "dwc_otg_cil_ifx.h"
5830 +
5831 +// #include "dwc_otg_pcd.h" // device
5832 +#include "dwc_otg_hcd.h" // host
5833 +
5834 +#include "dwc_otg_ifx.h" // for Infineon platform specific.
5835 +
5836 +#define DWC_DRIVER_VERSION "2.60a 22-NOV-2006"
5837 +#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
5838 +
5839 +const char dwc_driver_name[] = "dwc_otg";
5840 +
5841 +static unsigned long dwc_iomem_base = IFX_USB_IOMEM_BASE;
5842 +int dwc_irq = LTQ_USB_INT;
5843 +//int dwc_irq = 54;
5844 +//int dwc_irq = IFXMIPS_USB_OC_INT;
5845 +
5846 +extern int ifx_usb_hc_init(unsigned long base_addr, int irq);
5847 +extern void ifx_usb_hc_remove(void);
5848 +
5849 +/*-------------------------------------------------------------------------*/
5850 +/* Encapsulate the module parameter settings */
5851 +
5852 +static dwc_otg_core_params_t dwc_otg_module_params = {
5853 + .opt = -1,
5854 + .otg_cap = -1,
5855 + .dma_enable = -1,
5856 + .dma_burst_size = -1,
5857 + .speed = -1,
5858 + .host_support_fs_ls_low_power = -1,
5859 + .host_ls_low_power_phy_clk = -1,
5860 + .enable_dynamic_fifo = -1,
5861 + .data_fifo_size = -1,
5862 + .dev_rx_fifo_size = -1,
5863 + .dev_nperio_tx_fifo_size = -1,
5864 + .dev_perio_tx_fifo_size = /* dev_perio_tx_fifo_size_1 */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 15 */
5865 + .host_rx_fifo_size = -1,
5866 + .host_nperio_tx_fifo_size = -1,
5867 + .host_perio_tx_fifo_size = -1,
5868 + .max_transfer_size = -1,
5869 + .max_packet_count = -1,
5870 + .host_channels = -1,
5871 + .dev_endpoints = -1,
5872 + .phy_type = -1,
5873 + .phy_utmi_width = -1,
5874 + .phy_ulpi_ddr = -1,
5875 + .phy_ulpi_ext_vbus = -1,
5876 + .i2c_enable = -1,
5877 + .ulpi_fs_ls = -1,
5878 + .ts_dline = -1,
5879 + .en_multiple_tx_fifo = -1,
5880 + .dev_tx_fifo_size = { /* dev_tx_fifo_size */
5881 + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
5882 + }, /* 15 */
5883 + .thr_ctl = -1,
5884 + .tx_thr_length = -1,
5885 + .rx_thr_length = -1,
5886 +};
5887 +
5888 +/**
5889 + * This function shows the Driver Version.
5890 + */
5891 +static ssize_t version_show(struct device_driver *dev, char *buf)
5892 +{
5893 + return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2,"%s\n",
5894 + DWC_DRIVER_VERSION);
5895 +}
5896 +static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
5897 +
5898 +/**
5899 + * Global Debug Level Mask.
5900 + */
5901 +uint32_t g_dbg_lvl = 0xff; /* OFF */
5902 +
5903 +/**
5904 + * This function shows the driver Debug Level.
5905 + */
5906 +static ssize_t dbg_level_show(struct device_driver *_drv, char *_buf)
5907 +{
5908 + return sprintf(_buf, "0x%0x\n", g_dbg_lvl);
5909 +}
5910 +/**
5911 + * This function stores the driver Debug Level.
5912 + */
5913 +static ssize_t dbg_level_store(struct device_driver *_drv, const char *_buf,
5914 + size_t _count)
5915 +{
5916 + g_dbg_lvl = simple_strtoul(_buf, NULL, 16);
5917 + return _count;
5918 +}
5919 +static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
5920 +
5921 +/**
5922 + * This function is called during module intialization to verify that
5923 + * the module parameters are in a valid state.
5924 + */
5925 +static int check_parameters(dwc_otg_core_if_t *core_if)
5926 +{
5927 + int i;
5928 + int retval = 0;
5929 +
5930 +/* Checks if the parameter is outside of its valid range of values */
5931 +#define DWC_OTG_PARAM_TEST(_param_,_low_,_high_) \
5932 + ((dwc_otg_module_params._param_ < (_low_)) || \
5933 + (dwc_otg_module_params._param_ > (_high_)))
5934 +
5935 +/* If the parameter has been set by the user, check that the parameter value is
5936 + * within the value range of values. If not, report a module error. */
5937 +#define DWC_OTG_PARAM_ERR(_param_,_low_,_high_,_string_) \
5938 + do { \
5939 + if (dwc_otg_module_params._param_ != -1) { \
5940 + if (DWC_OTG_PARAM_TEST(_param_,(_low_),(_high_))) { \
5941 + DWC_ERROR("`%d' invalid for parameter `%s'\n", \
5942 + dwc_otg_module_params._param_, _string_); \
5943 + dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
5944 + retval ++; \
5945 + } \
5946 + } \
5947 + } while (0)
5948 +
5949 + DWC_OTG_PARAM_ERR(opt,0,1,"opt");
5950 + DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
5951 + DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
5952 + DWC_OTG_PARAM_ERR(speed,0,1,"speed");
5953 + DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
5954 + DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
5955 + DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
5956 + DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
5957 + DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
5958 + DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
5959 + DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
5960 + DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
5961 + DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
5962 + DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
5963 + DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
5964 + DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
5965 + DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
5966 + DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
5967 + DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
5968 + DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
5969 + DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
5970 + DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
5971 + DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
5972 +
5973 + if (dwc_otg_module_params.dma_burst_size != -1) {
5974 + if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
5975 + DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
5976 + DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
5977 + DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
5978 + DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
5979 + DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
5980 + DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
5981 + DWC_OTG_PARAM_TEST(dma_burst_size,256,256))
5982 + {
5983 + DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
5984 + dwc_otg_module_params.dma_burst_size);
5985 + dwc_otg_module_params.dma_burst_size = 32;
5986 + retval ++;
5987 + }
5988 + }
5989 +
5990 + if (dwc_otg_module_params.phy_utmi_width != -1) {
5991 + if (DWC_OTG_PARAM_TEST(phy_utmi_width,8,8) &&
5992 + DWC_OTG_PARAM_TEST(phy_utmi_width,16,16))
5993 + {
5994 + DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
5995 + dwc_otg_module_params.phy_utmi_width);
5996 + //dwc_otg_module_params.phy_utmi_width = 16;
5997 + dwc_otg_module_params.phy_utmi_width = 8;
5998 + retval ++;
5999 + }
6000 + }
6001 +
6002 + for (i=0; i<15; i++) {
6003 + /** @todo should be like above */
6004 + //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i],4,768,"dev_perio_tx_fifo_size");
6005 + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
6006 + if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i],4,768)) {
6007 + DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
6008 + dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
6009 + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
6010 + retval ++;
6011 + }
6012 + }
6013 + }
6014 +
6015 + DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
6016 + for (i = 0; i < 15; i++) {
6017 + /** @todo should be like above */
6018 + //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i],4,768,"dev_tx_fifo_size");
6019 + if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
6020 + if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
6021 + DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
6022 + dwc_otg_module_params.dev_tx_fifo_size[i],
6023 + "dev_tx_fifo_size", i);
6024 + dwc_otg_module_params.dev_tx_fifo_size[i] =
6025 + dwc_param_dev_tx_fifo_size_default;
6026 + retval++;
6027 + }
6028 + }
6029 + }
6030 + DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
6031 + DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
6032 + DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
6033 +
6034 + /* At this point, all module parameters that have been set by the user
6035 + * are valid, and those that have not are left unset. Now set their
6036 + * default values and/or check the parameters against the hardware
6037 + * configurations of the OTG core. */
6038 +
6039 +
6040 +
6041 +/* This sets the parameter to the default value if it has not been set by the
6042 + * user */
6043 +#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
6044 + ({ \
6045 + int changed = 1; \
6046 + if (dwc_otg_module_params._param_ == -1) { \
6047 + changed = 0; \
6048 + dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
6049 + } \
6050 + changed; \
6051 + })
6052 +
6053 +/* This checks the macro agains the hardware configuration to see if it is
6054 + * valid. It is possible that the default value could be invalid. In this
6055 + * case, it will report a module error if the user touched the parameter.
6056 + * Otherwise it will adjust the value without any error. */
6057 +#define DWC_OTG_PARAM_CHECK_VALID(_param_,_str_,_is_valid_,_set_valid_) \
6058 + ({ \
6059 + int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
6060 + int error = 0; \
6061 + if (!(_is_valid_)) { \
6062 + if (changed) { \
6063 + DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_,_str_); \
6064 + error = 1; \
6065 + } \
6066 + dwc_otg_module_params._param_ = (_set_valid_); \
6067 + } \
6068 + error; \
6069 + })
6070 +
6071 + /* OTG Cap */
6072 + retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap,"otg_cap",
6073 + ({
6074 + int valid;
6075 + valid = 1;
6076 + switch (dwc_otg_module_params.otg_cap) {
6077 + case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
6078 + if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) valid = 0;
6079 + break;
6080 + case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
6081 + if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
6082 + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
6083 + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
6084 + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST))
6085 + {
6086 + valid = 0;
6087 + }
6088 + break;
6089 + case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
6090 + /* always valid */
6091 + break;
6092 + }
6093 + valid;
6094 + }),
6095 + (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
6096 + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
6097 + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
6098 + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
6099 + DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
6100 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
6101 +
6102 + retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable,"dma_enable",
6103 + ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
6104 + 0);
6105 +
6106 + retval += DWC_OTG_PARAM_CHECK_VALID(opt,"opt",
6107 + 1,
6108 + 0);
6109 +
6110 + DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
6111 +
6112 + retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
6113 + "host_support_fs_ls_low_power",
6114 + 1, 0);
6115 +
6116 + retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
6117 + "enable_dynamic_fifo",
6118 + ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
6119 + (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
6120 +
6121 +
6122 + retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
6123 + "data_fifo_size",
6124 + (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
6125 + core_if->hwcfg3.b.dfifo_depth);
6126 +
6127 + retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
6128 + "dev_rx_fifo_size",
6129 + (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
6130 + dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
6131 +
6132 + retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
6133 + "dev_nperio_tx_fifo_size",
6134 + (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
6135 + (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
6136 +
6137 + retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
6138 + "host_rx_fifo_size",
6139 + (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
6140 + dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
6141 +
6142 +
6143 + retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
6144 + "host_nperio_tx_fifo_size",
6145 + (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
6146 + (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
6147 +
6148 + retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
6149 + "host_perio_tx_fifo_size",
6150 + (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
6151 + ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
6152 +
6153 + retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
6154 + "max_transfer_size",
6155 + (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
6156 + ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
6157 +
6158 + retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
6159 + "max_packet_count",
6160 + (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
6161 + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
6162 +
6163 + retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
6164 + "host_channels",
6165 + (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
6166 + (core_if->hwcfg2.b.num_host_chan + 1));
6167 +
6168 + retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
6169 + "dev_endpoints",
6170 + (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
6171 + core_if->hwcfg2.b.num_dev_ep);
6172 +
6173 +/*
6174 + * Define the following to disable the FS PHY Hardware checking. This is for
6175 + * internal testing only.
6176 + *
6177 + * #define NO_FS_PHY_HW_CHECKS
6178 + */
6179 +
6180 +#ifdef NO_FS_PHY_HW_CHECKS
6181 + retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
6182 + "phy_type", 1, 0);
6183 +#else
6184 + retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
6185 + "phy_type",
6186 + ({
6187 + int valid = 0;
6188 + if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
6189 + ((core_if->hwcfg2.b.hs_phy_type == 1) ||
6190 + (core_if->hwcfg2.b.hs_phy_type == 3)))
6191 + {
6192 + valid = 1;
6193 + }
6194 + else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
6195 + ((core_if->hwcfg2.b.hs_phy_type == 2) ||
6196 + (core_if->hwcfg2.b.hs_phy_type == 3)))
6197 + {
6198 + valid = 1;
6199 + }
6200 + else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
6201 + (core_if->hwcfg2.b.fs_phy_type == 1))
6202 + {
6203 + valid = 1;
6204 + }
6205 + valid;
6206 + }),
6207 + ({
6208 + int set = DWC_PHY_TYPE_PARAM_FS;
6209 + if (core_if->hwcfg2.b.hs_phy_type) {
6210 + if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
6211 + (core_if->hwcfg2.b.hs_phy_type == 1)) {
6212 + set = DWC_PHY_TYPE_PARAM_UTMI;
6213 + }
6214 + else {
6215 + set = DWC_PHY_TYPE_PARAM_ULPI;
6216 + }
6217 + }
6218 + set;
6219 + }));
6220 +#endif
6221 +
6222 + retval += DWC_OTG_PARAM_CHECK_VALID(speed,"speed",
6223 + (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
6224 + dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
6225 +
6226 + retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
6227 + "host_ls_low_power_phy_clk",
6228 + ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
6229 + ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
6230 +
6231 + DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
6232 + DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
6233 + DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
6234 + DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
6235 + DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
6236 +
6237 +#ifdef NO_FS_PHY_HW_CHECKS
6238 + retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
6239 + "i2c_enable", 1, 0);
6240 +#else
6241 + retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
6242 + "i2c_enable",
6243 + (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
6244 + 0);
6245 +#endif
6246 +
6247 + for (i=0; i<16; i++) {
6248 +
6249 + int changed = 1;
6250 + int error = 0;
6251 +
6252 + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
6253 + changed = 0;
6254 + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
6255 + }
6256 + if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
6257 + if (changed) {
6258 + DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i],i);
6259 + error = 1;
6260 + }
6261 + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
6262 + }
6263 + retval += error;
6264 + }
6265 +
6266 + retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo,
6267 + "en_multiple_tx_fifo",
6268 + ((dwc_otg_module_params.en_multiple_tx_fifo == 1) &&
6269 + (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1, 0);
6270 +
6271 + for (i = 0; i < 16; i++) {
6272 + int changed = 1;
6273 + int error = 0;
6274 + if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
6275 + changed = 0;
6276 + dwc_otg_module_params.dev_tx_fifo_size[i] =
6277 + dwc_param_dev_tx_fifo_size_default;
6278 + }
6279 + if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <=
6280 + (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
6281 + if (changed) {
6282 + DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'."
6283 + "Check HW configuration.\n",dwc_otg_module_params.dev_tx_fifo_size[i],i);
6284 + error = 1;
6285 + }
6286 + dwc_otg_module_params.dev_tx_fifo_size[i] =
6287 + dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
6288 + }
6289 + retval += error;
6290 + }
6291 + DWC_OTG_PARAM_SET_DEFAULT(thr_ctl);
6292 + DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
6293 + DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
6294 + return retval;
6295 +} // check_parameters
6296 +
6297 +
6298 +/**
6299 + * This function is the top level interrupt handler for the Common
6300 + * (Device and host modes) interrupts.
6301 + */
6302 +static irqreturn_t dwc_otg_common_irq(int _irq, void *_dev)
6303 +{
6304 + dwc_otg_device_t *otg_dev = _dev;
6305 + int32_t retval = IRQ_NONE;
6306 +
6307 + retval = dwc_otg_handle_common_intr( otg_dev->core_if );
6308 +
6309 + mask_and_ack_ifx_irq (_irq);
6310 +
6311 + return IRQ_RETVAL(retval);
6312 +}
6313 +
6314 +
6315 +/**
6316 + * This function is called when a DWC_OTG device is unregistered with the
6317 + * dwc_otg_driver. This happens, for example, when the rmmod command is
6318 + * executed. The device may or may not be electrically present. If it is
6319 + * present, the driver stops device processing. Any resources used on behalf
6320 + * of this device are freed.
6321 + *
6322 + * @return
6323 + */
6324 +static int
6325 +dwc_otg_driver_remove(struct platform_device *_dev)
6326 +{
6327 + //dwc_otg_device_t *otg_dev = dev_get_drvdata(&_dev->dev);
6328 + dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
6329 +
6330 + DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
6331 +
6332 + if (otg_dev == NULL) {
6333 + /* Memory allocation for the dwc_otg_device failed. */
6334 + return 0;
6335 + }
6336 +
6337 + /*
6338 + * Free the IRQ
6339 + */
6340 + if (otg_dev->common_irq_installed) {
6341 + free_irq( otg_dev->irq, otg_dev );
6342 + }
6343 +
6344 +#ifndef DWC_DEVICE_ONLY
6345 + if (otg_dev->hcd != NULL) {
6346 + dwc_otg_hcd_remove(&_dev->dev);
6347 + }
6348 +#endif
6349 + printk("after removehcd\n");
6350 +
6351 +// Note: Integrate HOST and DEVICE(Gadget) is not planned yet.
6352 +#ifndef DWC_HOST_ONLY
6353 + if (otg_dev->pcd != NULL) {
6354 + dwc_otg_pcd_remove(otg_dev);
6355 + }
6356 +#endif
6357 + if (otg_dev->core_if != NULL) {
6358 + dwc_otg_cil_remove( otg_dev->core_if );
6359 + }
6360 + printk("after removecil\n");
6361 +
6362 + /*
6363 + * Remove the device attributes
6364 + */
6365 + dwc_otg_attr_remove(&_dev->dev);
6366 + printk("after removeattr\n");
6367 +
6368 + /*
6369 + * Return the memory.
6370 + */
6371 + if (otg_dev->base != NULL) {
6372 + iounmap(otg_dev->base);
6373 + }
6374 + if (otg_dev->phys_addr != 0) {
6375 + release_mem_region(otg_dev->phys_addr, otg_dev->base_len);
6376 + }
6377 + kfree(otg_dev);
6378 +
6379 + /*
6380 + * Clear the drvdata pointer.
6381 + */
6382 + //dev_set_drvdata(&_dev->dev, 0);
6383 + platform_set_drvdata(_dev, 0);
6384 + return 0;
6385 +}
6386 +
6387 +/**
6388 + * This function is called when an DWC_OTG device is bound to a
6389 + * dwc_otg_driver. It creates the driver components required to
6390 + * control the device (CIL, HCD, and PCD) and it initializes the
6391 + * device. The driver components are stored in a dwc_otg_device
6392 + * structure. A reference to the dwc_otg_device is saved in the
6393 + * lm_device. This allows the driver to access the dwc_otg_device
6394 + * structure on subsequent calls to driver methods for this device.
6395 + *
6396 + * @return
6397 + */
6398 +static int __devinit
6399 +dwc_otg_driver_probe(struct platform_device *_dev)
6400 +{
6401 + int retval = 0;
6402 + dwc_otg_device_t *dwc_otg_device;
6403 + int pin = (int)_dev->dev.platform_data;
6404 + int32_t snpsid;
6405 + struct resource *res;
6406 + gusbcfg_data_t usbcfg = {.d32 = 0};
6407 +
6408 + // GPIOs
6409 + if(pin >= 0)
6410 + {
6411 + gpio_request(pin, "usb_power");
6412 + gpio_direction_output(pin, 1);
6413 + gpio_set_value(pin, 1);
6414 + gpio_export(pin, 0);
6415 + }
6416 + dev_dbg(&_dev->dev, "dwc_otg_driver_probe (%p)\n", _dev);
6417 +
6418 + dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
6419 + if (dwc_otg_device == 0) {
6420 + dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
6421 + retval = -ENOMEM;
6422 + goto fail;
6423 + }
6424 + memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
6425 + dwc_otg_device->reg_offset = 0xFFFFFFFF;
6426 +
6427 + /*
6428 + * Retrieve the memory and IRQ resources.
6429 + */
6430 + dwc_otg_device->irq = platform_get_irq(_dev, 0);
6431 + if (dwc_otg_device->irq == 0) {
6432 + dev_err(&_dev->dev, "no device irq\n");
6433 + retval = -ENODEV;
6434 + goto fail;
6435 + }
6436 + dev_dbg(&_dev->dev, "OTG - device irq: %d\n", dwc_otg_device->irq);
6437 + res = platform_get_resource(_dev, IORESOURCE_MEM, 0);
6438 + if (res == NULL) {
6439 + dev_err(&_dev->dev, "no CSR address\n");
6440 + retval = -ENODEV;
6441 + goto fail;
6442 + }
6443 + dev_dbg(&_dev->dev, "OTG - ioresource_mem start0x%08x: end:0x%08x\n",
6444 + (unsigned)res->start, (unsigned)res->end);
6445 + dwc_otg_device->phys_addr = res->start;
6446 + dwc_otg_device->base_len = res->end - res->start + 1;
6447 + if (request_mem_region(dwc_otg_device->phys_addr, dwc_otg_device->base_len,
6448 + dwc_driver_name) == NULL) {
6449 + dev_err(&_dev->dev, "request_mem_region failed\n");
6450 + retval = -EBUSY;
6451 + goto fail;
6452 + }
6453 +
6454 + /*
6455 + * Map the DWC_otg Core memory into virtual address space.
6456 + */
6457 + dwc_otg_device->base = ioremap_nocache(dwc_otg_device->phys_addr, dwc_otg_device->base_len);
6458 + if (dwc_otg_device->base == NULL) {
6459 + dev_err(&_dev->dev, "ioremap() failed\n");
6460 + retval = -ENOMEM;
6461 + goto fail;
6462 + }
6463 + dev_dbg(&_dev->dev, "mapped base=0x%08x\n", (unsigned)dwc_otg_device->base);
6464 +
6465 + /*
6466 + * Attempt to ensure this device is really a DWC_otg Controller.
6467 + * Read and verify the SNPSID register contents. The value should be
6468 + * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
6469 + */
6470 + snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
6471 + if ((snpsid & 0xFFFFF000) != 0x4F542000) {
6472 + dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
6473 + retval = -EINVAL;
6474 + goto fail;
6475 + }
6476 +
6477 + /*
6478 + * Initialize driver data to point to the global DWC_otg
6479 + * Device structure.
6480 + */
6481 + platform_set_drvdata(_dev, dwc_otg_device);
6482 + dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
6483 + dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base, &dwc_otg_module_params);
6484 + if (dwc_otg_device->core_if == 0) {
6485 + dev_err(&_dev->dev, "CIL initialization failed!\n");
6486 + retval = -ENOMEM;
6487 + goto fail;
6488 + }
6489 +
6490 + /*
6491 + * Validate parameter values.
6492 + */
6493 + if (check_parameters(dwc_otg_device->core_if) != 0) {
6494 + retval = -EINVAL;
6495 + goto fail;
6496 + }
6497 +
6498 + /* Added for PLB DMA phys virt mapping */
6499 + //dwc_otg_device->core_if->phys_addr = dwc_otg_device->phys_addr;
6500 + /*
6501 + * Create Device Attributes in sysfs
6502 + */
6503 + dwc_otg_attr_create (&_dev->dev);
6504 +
6505 + /*
6506 + * Disable the global interrupt until all the interrupt
6507 + * handlers are installed.
6508 + */
6509 + dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
6510 + /*
6511 + * Install the interrupt handler for the common interrupts before
6512 + * enabling common interrupts in core_init below.
6513 + */
6514 + DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n", dwc_otg_device->irq);
6515 +
6516 + retval = request_irq((unsigned int)dwc_otg_device->irq, dwc_otg_common_irq,
6517 + //SA_INTERRUPT|SA_SHIRQ, "dwc_otg", (void *)dwc_otg_device );
6518 + IRQF_SHARED, "dwc_otg", (void *)dwc_otg_device );
6519 + //IRQF_DISABLED, "dwc_otg", (void *)dwc_otg_device );
6520 + if (retval != 0) {
6521 + DWC_ERROR("request of irq%d failed retval: %d\n", dwc_otg_device->irq, retval);
6522 + retval = -EBUSY;
6523 + goto fail;
6524 + } else {
6525 + dwc_otg_device->common_irq_installed = 1;
6526 + }
6527 +
6528 + /*
6529 + * Initialize the DWC_otg core.
6530 + */
6531 + dwc_otg_core_init( dwc_otg_device->core_if );
6532 +
6533 +
6534 +#ifndef DWC_HOST_ONLY // otg device mode. (gadget.)
6535 + /*
6536 + * Initialize the PCD
6537 + */
6538 + retval = dwc_otg_pcd_init(dwc_otg_device);
6539 + if (retval != 0) {
6540 + DWC_ERROR("dwc_otg_pcd_init failed\n");
6541 + dwc_otg_device->pcd = NULL;
6542 + goto fail;
6543 + }
6544 +#endif // DWC_HOST_ONLY
6545 +
6546 +#ifndef DWC_DEVICE_ONLY // otg host mode. (HCD)
6547 + /*
6548 + * Initialize the HCD
6549 + */
6550 +#if 1 /*fscz*/
6551 + /* force_host_mode */
6552 + usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg);
6553 + usbcfg.b.force_host_mode = 1;
6554 + dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32);
6555 +#endif
6556 + retval = dwc_otg_hcd_init(&_dev->dev, dwc_otg_device);
6557 + if (retval != 0) {
6558 + DWC_ERROR("dwc_otg_hcd_init failed\n");
6559 + dwc_otg_device->hcd = NULL;
6560 + goto fail;
6561 + }
6562 +#endif // DWC_DEVICE_ONLY
6563 +
6564 + /*
6565 + * Enable the global interrupt after all the interrupt
6566 + * handlers are installed.
6567 + */
6568 + dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
6569 +#if 0 /*fscz*/
6570 + usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg);
6571 + usbcfg.b.force_host_mode = 0;
6572 + dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32);
6573 +#endif
6574 +
6575 +
6576 + return 0;
6577 +
6578 +fail:
6579 + dwc_otg_driver_remove(_dev);
6580 + return retval;
6581 +}
6582 +
6583 +/**
6584 + * This structure defines the methods to be called by a bus driver
6585 + * during the lifecycle of a device on that bus. Both drivers and
6586 + * devices are registered with a bus driver. The bus driver matches
6587 + * devices to drivers based on information in the device and driver
6588 + * structures.
6589 + *
6590 + * The probe function is called when the bus driver matches a device
6591 + * to this driver. The remove function is called when a device is
6592 + * unregistered with the bus driver.
6593 + */
6594 +struct platform_driver dwc_otg_driver = {
6595 + .probe = dwc_otg_driver_probe,
6596 + .remove = dwc_otg_driver_remove,
6597 +// .suspend = dwc_otg_driver_suspend,
6598 +// .resume = dwc_otg_driver_resume,
6599 + .driver = {
6600 + .name = dwc_driver_name,
6601 + .owner = THIS_MODULE,
6602 + },
6603 +};
6604 +EXPORT_SYMBOL(dwc_otg_driver);
6605 +
6606 +/**
6607 + * This function is called when the dwc_otg_driver is installed with the
6608 + * insmod command. It registers the dwc_otg_driver structure with the
6609 + * appropriate bus driver. This will cause the dwc_otg_driver_probe function
6610 + * to be called. In addition, the bus driver will automatically expose
6611 + * attributes defined for the device and driver in the special sysfs file
6612 + * system.
6613 + *
6614 + * @return
6615 + */
6616 +static int __init dwc_otg_init(void)
6617 +{
6618 + int retval = 0;
6619 +
6620 + printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
6621 +
6622 + // ifxmips setup
6623 + retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq);
6624 + if (retval < 0)
6625 + {
6626 + printk(KERN_ERR "%s retval=%d\n", __func__, retval);
6627 + return retval;
6628 + }
6629 + dwc_otg_power_on(); // ifx only!!
6630 +
6631 +
6632 + retval = platform_driver_register(&dwc_otg_driver);
6633 +
6634 + if (retval < 0) {
6635 + printk(KERN_ERR "%s retval=%d\n", __func__, retval);
6636 + goto error1;
6637 + }
6638 +
6639 + retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
6640 + if (retval < 0)
6641 + {
6642 + printk(KERN_ERR "%s retval=%d\n", __func__, retval);
6643 + goto error2;
6644 + }
6645 + retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
6646 + if (retval < 0)
6647 + {
6648 + printk(KERN_ERR "%s retval=%d\n", __func__, retval);
6649 + goto error3;
6650 + }
6651 + return retval;
6652 +
6653 +
6654 +error3:
6655 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
6656 +error2:
6657 + driver_unregister(&dwc_otg_driver.driver);
6658 +error1:
6659 + ifx_usb_hc_remove();
6660 + return retval;
6661 +}
6662 +module_init(dwc_otg_init);
6663 +
6664 +/**
6665 + * This function is called when the driver is removed from the kernel
6666 + * with the rmmod command. The driver unregisters itself with its bus
6667 + * driver.
6668 + *
6669 + */
6670 +static void __exit dwc_otg_cleanup(void)
6671 +{
6672 + printk(KERN_DEBUG "dwc_otg_cleanup()\n");
6673 +
6674 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
6675 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
6676 +
6677 + platform_driver_unregister(&dwc_otg_driver);
6678 + ifx_usb_hc_remove();
6679 +
6680 + printk(KERN_INFO "%s module removed\n", dwc_driver_name);
6681 +}
6682 +module_exit(dwc_otg_cleanup);
6683 +
6684 +MODULE_DESCRIPTION(DWC_DRIVER_DESC);
6685 +MODULE_AUTHOR("Synopsys Inc.");
6686 +MODULE_LICENSE("GPL");
6687 +
6688 +module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
6689 +MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
6690 +module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
6691 +MODULE_PARM_DESC(opt, "OPT Mode");
6692 +module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
6693 +MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
6694 +module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
6695 +MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
6696 +module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
6697 +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
6698 +module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
6699 +MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
6700 +module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
6701 +MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
6702 +module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
6703 +MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
6704 +module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
6705 +MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
6706 +module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
6707 +MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
6708 +module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
6709 +MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
6710 +module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
6711 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
6712 +module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
6713 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
6714 +module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
6715 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
6716 +module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
6717 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
6718 +module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
6719 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
6720 +module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
6721 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
6722 +module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
6723 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
6724 +module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
6725 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
6726 +module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
6727 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
6728 +module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
6729 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
6730 +module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
6731 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
6732 +module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
6733 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
6734 +module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
6735 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
6736 +module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
6737 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
6738 +module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
6739 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
6740 +module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
6741 +MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
6742 +module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
6743 +MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
6744 +module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
6745 +MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
6746 +module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
6747 +/** @todo Set the max to 512K, modify checks */
6748 +MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
6749 +module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
6750 +MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
6751 +module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
6752 +MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
6753 +module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
6754 +MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
6755 +module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
6756 +MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
6757 +module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
6758 +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
6759 +module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
6760 +MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
6761 +module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
6762 +MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
6763 +module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
6764 +MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
6765 +module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
6766 +MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
6767 +module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
6768 +MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
6769 +module_param_named(debug, g_dbg_lvl, int, 0444);
6770 +MODULE_PARM_DESC(debug, "0");
6771 +module_param_named(en_multiple_tx_fifo,
6772 + dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
6773 +MODULE_PARM_DESC(en_multiple_tx_fifo,
6774 + "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
6775 +module_param_named(dev_tx_fifo_size_1,
6776 + dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
6777 +MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
6778 +module_param_named(dev_tx_fifo_size_2,
6779 + dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
6780 +MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
6781 +module_param_named(dev_tx_fifo_size_3,
6782 + dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
6783 +MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
6784 +module_param_named(dev_tx_fifo_size_4,
6785 + dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
6786 +MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
6787 +module_param_named(dev_tx_fifo_size_5,
6788 + dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
6789 +MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
6790 +module_param_named(dev_tx_fifo_size_6,
6791 + dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
6792 +MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
6793 +module_param_named(dev_tx_fifo_size_7,
6794 + dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
6795 +MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
6796 +module_param_named(dev_tx_fifo_size_8,
6797 + dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
6798 +MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
6799 +module_param_named(dev_tx_fifo_size_9,
6800 + dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
6801 +MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
6802 +module_param_named(dev_tx_fifo_size_10,
6803 + dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
6804 +MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
6805 +module_param_named(dev_tx_fifo_size_11,
6806 + dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
6807 +MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
6808 +module_param_named(dev_tx_fifo_size_12,
6809 + dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
6810 +MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
6811 +module_param_named(dev_tx_fifo_size_13,
6812 + dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
6813 +MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
6814 +module_param_named(dev_tx_fifo_size_14,
6815 + dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
6816 +MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
6817 +module_param_named(dev_tx_fifo_size_15,
6818 + dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
6819 +MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
6820 +module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
6821 +MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit"
6822 + "0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
6823 +module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
6824 +MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
6825 +module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
6826 +MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
6827 +module_param_named (iomem_base, dwc_iomem_base, ulong, 0444);
6828 +MODULE_PARM_DESC (dwc_iomem_base, "The base address of the DWC_OTG register.");
6829 +module_param_named (irq, dwc_irq, int, 0444);
6830 +MODULE_PARM_DESC (dwc_irq, "The interrupt number");
6831 +
6832 +/** @page "Module Parameters"
6833 + *
6834 + * The following parameters may be specified when starting the module.
6835 + * These parameters define how the DWC_otg controller should be
6836 + * configured. Parameter values are passed to the CIL initialization
6837 + * function dwc_otg_cil_init
6838 + *
6839 + * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
6840 + *
6841 +
6842 + <table>
6843 + <tr><td>Parameter Name</td><td>Meaning</td></tr>
6844 +
6845 + <tr>
6846 + <td>otg_cap</td>
6847 + <td>Specifies the OTG capabilities. The driver will automatically detect the
6848 + value for this parameter if none is specified.
6849 + - 0: HNP and SRP capable (default, if available)
6850 + - 1: SRP Only capable
6851 + - 2: No HNP/SRP capable
6852 + </td></tr>
6853 +
6854 + <tr>
6855 + <td>dma_enable</td>
6856 + <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
6857 + The driver will automatically detect the value for this parameter if none is
6858 + specified.
6859 + - 0: Slave
6860 + - 1: DMA (default, if available)
6861 + </td></tr>
6862 +
6863 + <tr>
6864 + <td>dma_burst_size</td>
6865 + <td>The DMA Burst size (applicable only for External DMA Mode).
6866 + - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
6867 + </td></tr>
6868 +
6869 + <tr>
6870 + <td>speed</td>
6871 + <td>Specifies the maximum speed of operation in host and device mode. The
6872 + actual speed depends on the speed of the attached device and the value of
6873 + phy_type.
6874 + - 0: High Speed (default)
6875 + - 1: Full Speed
6876 + </td></tr>
6877 +
6878 + <tr>
6879 + <td>host_support_fs_ls_low_power</td>
6880 + <td>Specifies whether low power mode is supported when attached to a Full
6881 + Speed or Low Speed device in host mode.
6882 + - 0: Don't support low power mode (default)
6883 + - 1: Support low power mode
6884 + </td></tr>
6885 +
6886 + <tr>
6887 + <td>host_ls_low_power_phy_clk</td>
6888 + <td>Specifies the PHY clock rate in low power mode when connected to a Low
6889 + Speed device in host mode. This parameter is applicable only if
6890 + HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
6891 + - 0: 48 MHz (default)
6892 + - 1: 6 MHz
6893 + </td></tr>
6894 +
6895 + <tr>
6896 + <td>enable_dynamic_fifo</td>
6897 + <td> Specifies whether FIFOs may be resized by the driver software.
6898 + - 0: Use cC FIFO size parameters
6899 + - 1: Allow dynamic FIFO sizing (default)
6900 + </td></tr>
6901 +
6902 + <tr>
6903 + <td>data_fifo_size</td>
6904 + <td>Total number of 4-byte words in the data FIFO memory. This memory
6905 + includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
6906 + - Values: 32 to 32768 (default 8192)
6907 +
6908 + Note: The total FIFO memory depth in the FPGA configuration is 8192.
6909 + </td></tr>
6910 +
6911 + <tr>
6912 + <td>dev_rx_fifo_size</td>
6913 + <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
6914 + FIFO sizing is enabled.
6915 + - Values: 16 to 32768 (default 1064)
6916 + </td></tr>
6917 +
6918 + <tr>
6919 + <td>dev_nperio_tx_fifo_size</td>
6920 + <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
6921 + dynamic FIFO sizing is enabled.
6922 + - Values: 16 to 32768 (default 1024)
6923 + </td></tr>
6924 +
6925 + <tr>
6926 + <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
6927 + <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
6928 + when dynamic FIFO sizing is enabled.
6929 + - Values: 4 to 768 (default 256)
6930 + </td></tr>
6931 +
6932 + <tr>
6933 + <td>host_rx_fifo_size</td>
6934 + <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
6935 + sizing is enabled.
6936 + - Values: 16 to 32768 (default 1024)
6937 + </td></tr>
6938 +
6939 + <tr>
6940 + <td>host_nperio_tx_fifo_size</td>
6941 + <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
6942 + dynamic FIFO sizing is enabled in the core.
6943 + - Values: 16 to 32768 (default 1024)
6944 + </td></tr>
6945 +
6946 + <tr>
6947 + <td>host_perio_tx_fifo_size</td>
6948 + <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
6949 + sizing is enabled.
6950 + - Values: 16 to 32768 (default 1024)
6951 + </td></tr>
6952 +
6953 + <tr>
6954 + <td>max_transfer_size</td>
6955 + <td>The maximum transfer size supported in bytes.
6956 + - Values: 2047 to 65,535 (default 65,535)
6957 + </td></tr>
6958 +
6959 + <tr>
6960 + <td>max_packet_count</td>
6961 + <td>The maximum number of packets in a transfer.
6962 + - Values: 15 to 511 (default 511)
6963 + </td></tr>
6964 +
6965 + <tr>
6966 + <td>host_channels</td>
6967 + <td>The number of host channel registers to use.
6968 + - Values: 1 to 16 (default 12)
6969 +
6970 + Note: The FPGA configuration supports a maximum of 12 host channels.
6971 + </td></tr>
6972 +
6973 + <tr>
6974 + <td>dev_endpoints</td>
6975 + <td>The number of endpoints in addition to EP0 available for device mode
6976 + operations.
6977 + - Values: 1 to 15 (default 6 IN and OUT)
6978 +
6979 + Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
6980 + addition to EP0.
6981 + </td></tr>
6982 +
6983 + <tr>
6984 + <td>phy_type</td>
6985 + <td>Specifies the type of PHY interface to use. By default, the driver will
6986 + automatically detect the phy_type.
6987 + - 0: Full Speed
6988 + - 1: UTMI+ (default, if available)
6989 + - 2: ULPI
6990 + </td></tr>
6991 +
6992 + <tr>
6993 + <td>phy_utmi_width</td>
6994 + <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
6995 + phy_type of UTMI+. Also, this parameter is applicable only if the
6996 + OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
6997 + core has been configured to work at either data path width.
6998 + - Values: 8 or 16 bits (default 16)
6999 + </td></tr>
7000 +
7001 + <tr>
7002 + <td>phy_ulpi_ddr</td>
7003 + <td>Specifies whether the ULPI operates at double or single data rate. This
7004 + parameter is only applicable if phy_type is ULPI.
7005 + - 0: single data rate ULPI interface with 8 bit wide data bus (default)
7006 + - 1: double data rate ULPI interface with 4 bit wide data bus
7007 + </td></tr>
7008 +
7009 + <tr>
7010 + <td>i2c_enable</td>
7011 + <td>Specifies whether to use the I2C interface for full speed PHY. This
7012 + parameter is only applicable if PHY_TYPE is FS.
7013 + - 0: Disabled (default)
7014 + - 1: Enabled
7015 + </td></tr>
7016 +
7017 + <tr>
7018 + <td>otg_en_multiple_tx_fifo</td>
7019 + <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
7020 + The driver will automatically detect the value for this parameter if none is
7021 + specified.
7022 + - 0: Disabled
7023 + - 1: Enabled (default, if available)
7024 + </td></tr>
7025 +
7026 + <tr>
7027 + <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
7028 + <td>Number of 4-byte words in each of the Tx FIFOs in device mode
7029 + when dynamic FIFO sizing is enabled.
7030 + - Values: 4 to 768 (default 256)
7031 + </td></tr>
7032 +
7033 +*/
7034 --- /dev/null
7035 +++ b/drivers/usb/dwc_otg/dwc_otg_driver.h
7036 @@ -0,0 +1,84 @@
7037 +/* ==========================================================================
7038 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.h $
7039 + * $Revision: 1.1.1.1 $
7040 + * $Date: 2009-04-17 06:15:34 $
7041 + * $Change: 510275 $
7042 + *
7043 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
7044 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
7045 + * otherwise expressly agreed to in writing between Synopsys and you.
7046 + *
7047 + * The Software IS NOT an item of Licensed Software or Licensed Product under
7048 + * any End User Software License Agreement or Agreement for Licensed Product
7049 + * with Synopsys or any supplement thereto. You are permitted to use and
7050 + * redistribute this Software in source and binary forms, with or without
7051 + * modification, provided that redistributions of source code must retain this
7052 + * notice. You may not view, use, disclose, copy or distribute this file or
7053 + * any information contained herein except pursuant to this license grant from
7054 + * Synopsys. If you do not agree with this notice, including the disclaimer
7055 + * below, then you are not authorized to use the Software.
7056 + *
7057 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
7058 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7059 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7060 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
7061 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7062 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
7063 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7064 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
7065 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
7066 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7067 + * DAMAGE.
7068 + * ========================================================================== */
7069 +
7070 +#if !defined(__DWC_OTG_DRIVER_H__)
7071 +#define __DWC_OTG_DRIVER_H__
7072 +
7073 +/** @file
7074 + * This file contains the interface to the Linux driver.
7075 + */
7076 +#include "dwc_otg_cil.h"
7077 +
7078 +/* Type declarations */
7079 +struct dwc_otg_pcd;
7080 +struct dwc_otg_hcd;
7081 +
7082 +/**
7083 + * This structure is a wrapper that encapsulates the driver components used to
7084 + * manage a single DWC_otg controller.
7085 + */
7086 +typedef struct dwc_otg_device
7087 +{
7088 + /** Base address returned from ioremap() */
7089 + void *base;
7090 +
7091 + /** Pointer to the core interface structure. */
7092 + dwc_otg_core_if_t *core_if;
7093 +
7094 + /** Register offset for Diagnostic API.*/
7095 + uint32_t reg_offset;
7096 +
7097 + /** Pointer to the PCD structure. */
7098 + struct dwc_otg_pcd *pcd;
7099 +
7100 + /** Pointer to the HCD structure. */
7101 + struct dwc_otg_hcd *hcd;
7102 +
7103 + /** Flag to indicate whether the common IRQ handler is installed. */
7104 + uint8_t common_irq_installed;
7105 +
7106 + /** Interrupt request number. */
7107 + unsigned int irq;
7108 +
7109 + /** Physical address of Control and Status registers, used by
7110 + * release_mem_region().
7111 + */
7112 + resource_size_t phys_addr;
7113 +
7114 + /** Length of memory region, used by release_mem_region(). */
7115 + unsigned long base_len;
7116 +} dwc_otg_device_t;
7117 +
7118 +//#define dev_dbg(fake, format, arg...) printk(KERN_CRIT __FILE__ ":%d: " format "\n" , __LINE__, ## arg)
7119 +
7120 +#endif
7121 --- /dev/null
7122 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd.c
7123 @@ -0,0 +1,2870 @@
7124 +/* ==========================================================================
7125 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $
7126 + * $Revision: 1.1.1.1 $
7127 + * $Date: 2009-04-17 06:15:34 $
7128 + * $Change: 631780 $
7129 + *
7130 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
7131 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
7132 + * otherwise expressly agreed to in writing between Synopsys and you.
7133 + *
7134 + * The Software IS NOT an item of Licensed Software or Licensed Product under
7135 + * any End User Software License Agreement or Agreement for Licensed Product
7136 + * with Synopsys or any supplement thereto. You are permitted to use and
7137 + * redistribute this Software in source and binary forms, with or without
7138 + * modification, provided that redistributions of source code must retain this
7139 + * notice. You may not view, use, disclose, copy or distribute this file or
7140 + * any information contained herein except pursuant to this license grant from
7141 + * Synopsys. If you do not agree with this notice, including the disclaimer
7142 + * below, then you are not authorized to use the Software.
7143 + *
7144 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
7145 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7146 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7147 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
7148 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7149 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
7150 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7151 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
7152 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
7153 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7154 + * DAMAGE.
7155 + * ========================================================================== */
7156 +#ifndef DWC_DEVICE_ONLY
7157 +
7158 +/**
7159 + * @file
7160 + *
7161 + * This file contains the implementation of the HCD. In Linux, the HCD
7162 + * implements the hc_driver API.
7163 + */
7164 +#include <linux/kernel.h>
7165 +#include <linux/module.h>
7166 +#include <linux/moduleparam.h>
7167 +#include <linux/init.h>
7168 +
7169 +#include <linux/device.h>
7170 +
7171 +#include <linux/errno.h>
7172 +#include <linux/list.h>
7173 +#include <linux/interrupt.h>
7174 +#include <linux/string.h>
7175 +
7176 +#include <linux/dma-mapping.h>
7177 +
7178 +#include "dwc_otg_driver.h"
7179 +#include "dwc_otg_hcd.h"
7180 +#include "dwc_otg_regs.h"
7181 +
7182 +#include <asm/irq.h>
7183 +#include "dwc_otg_ifx.h" // for Infineon platform specific.
7184 +extern atomic_t release_later;
7185 +
7186 +static u64 dma_mask = DMA_BIT_MASK(32);
7187 +
7188 +static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";
7189 +static const struct hc_driver dwc_otg_hc_driver =
7190 +{
7191 + .description = dwc_otg_hcd_name,
7192 + .product_desc = "DWC OTG Controller",
7193 + .hcd_priv_size = sizeof(dwc_otg_hcd_t),
7194 + .irq = dwc_otg_hcd_irq,
7195 + .flags = HCD_MEMORY | HCD_USB2,
7196 + //.reset =
7197 + .start = dwc_otg_hcd_start,
7198 + //.suspend =
7199 + //.resume =
7200 + .stop = dwc_otg_hcd_stop,
7201 + .urb_enqueue = dwc_otg_hcd_urb_enqueue,
7202 + .urb_dequeue = dwc_otg_hcd_urb_dequeue,
7203 + .endpoint_disable = dwc_otg_hcd_endpoint_disable,
7204 + .get_frame_number = dwc_otg_hcd_get_frame_number,
7205 + .hub_status_data = dwc_otg_hcd_hub_status_data,
7206 + .hub_control = dwc_otg_hcd_hub_control,
7207 + //.hub_suspend =
7208 + //.hub_resume =
7209 +};
7210 +
7211 +
7212 +/**
7213 + * Work queue function for starting the HCD when A-Cable is connected.
7214 + * The dwc_otg_hcd_start() must be called in a process context.
7215 + */
7216 +static void hcd_start_func(struct work_struct *work)
7217 +{
7218 + struct dwc_otg_hcd *priv =
7219 + container_of(work, struct dwc_otg_hcd, start_work);
7220 + struct usb_hcd *usb_hcd = (struct usb_hcd *)priv->_p;
7221 + DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd);
7222 + if (usb_hcd) {
7223 + dwc_otg_hcd_start(usb_hcd);
7224 + }
7225 +}
7226 +
7227 +
7228 +/**
7229 + * HCD Callback function for starting the HCD when A-Cable is
7230 + * connected.
7231 + *
7232 + * @param _p void pointer to the <code>struct usb_hcd</code>
7233 + */
7234 +static int32_t dwc_otg_hcd_start_cb(void *_p)
7235 +{
7236 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);
7237 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
7238 + hprt0_data_t hprt0;
7239 + if (core_if->op_state == B_HOST) {
7240 + /*
7241 + * Reset the port. During a HNP mode switch the reset
7242 + * needs to occur within 1ms and have a duration of at
7243 + * least 50ms.
7244 + */
7245 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
7246 + hprt0.b.prtrst = 1;
7247 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
7248 + ((struct usb_hcd *)_p)->self.is_b_host = 1;
7249 + } else {
7250 + ((struct usb_hcd *)_p)->self.is_b_host = 0;
7251 + }
7252 + /* Need to start the HCD in a non-interrupt context. */
7253 + INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
7254 + dwc_otg_hcd->_p = _p;
7255 + schedule_work(&dwc_otg_hcd->start_work);
7256 + return 1;
7257 +}
7258 +
7259 +
7260 +/**
7261 + * HCD Callback function for stopping the HCD.
7262 + *
7263 + * @param _p void pointer to the <code>struct usb_hcd</code>
7264 + */
7265 +static int32_t dwc_otg_hcd_stop_cb( void *_p )
7266 +{
7267 + struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;
7268 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
7269 + dwc_otg_hcd_stop( usb_hcd );
7270 + return 1;
7271 +}
7272 +static void del_xfer_timers(dwc_otg_hcd_t *_hcd)
7273 +{
7274 +#ifdef DEBUG
7275 + int i;
7276 + int num_channels = _hcd->core_if->core_params->host_channels;
7277 + for (i = 0; i < num_channels; i++) {
7278 + del_timer(&_hcd->core_if->hc_xfer_timer[i]);
7279 + }
7280 +#endif /* */
7281 +}
7282 +
7283 +static void del_timers(dwc_otg_hcd_t *_hcd)
7284 +{
7285 + del_xfer_timers(_hcd);
7286 + del_timer(&_hcd->conn_timer);
7287 +}
7288 +
7289 +/**
7290 + * Processes all the URBs in a single list of QHs. Completes them with
7291 + * -ETIMEDOUT and frees the QTD.
7292 + */
7293 +static void kill_urbs_in_qh_list(dwc_otg_hcd_t * _hcd,
7294 + struct list_head *_qh_list)
7295 +{
7296 + struct list_head *qh_item;
7297 + dwc_otg_qh_t *qh;
7298 + struct list_head *qtd_item;
7299 + dwc_otg_qtd_t *qtd;
7300 +
7301 + list_for_each(qh_item, _qh_list) {
7302 + qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
7303 + for (qtd_item = qh->qtd_list.next; qtd_item != &qh->qtd_list;
7304 + qtd_item = qh->qtd_list.next) {
7305 + qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
7306 + if (qtd->urb != NULL) {
7307 + dwc_otg_hcd_complete_urb(_hcd, qtd->urb,-ETIMEDOUT);
7308 + }
7309 + dwc_otg_hcd_qtd_remove_and_free(qtd);
7310 + }
7311 + }
7312 +}
7313 +
7314 +/**
7315 + * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
7316 + * and periodic schedules. The QTD associated with each URB is removed from
7317 + * the schedule and freed. This function may be called when a disconnect is
7318 + * detected or when the HCD is being stopped.
7319 + */
7320 +static void kill_all_urbs(dwc_otg_hcd_t *_hcd)
7321 +{
7322 + kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_deferred);
7323 + kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive);
7324 + kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active);
7325 + kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive);
7326 + kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready);
7327 + kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned);
7328 + kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued);
7329 +}
7330 +
7331 +/**
7332 + * HCD Callback function for disconnect of the HCD.
7333 + *
7334 + * @param _p void pointer to the <code>struct usb_hcd</code>
7335 + */
7336 +static int32_t dwc_otg_hcd_disconnect_cb( void *_p )
7337 +{
7338 + gintsts_data_t intr;
7339 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
7340 +
7341 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
7342 +
7343 + /*
7344 + * Set status flags for the hub driver.
7345 + */
7346 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
7347 + dwc_otg_hcd->flags.b.port_connect_status = 0;
7348 +
7349 + /*
7350 + * Shutdown any transfers in process by clearing the Tx FIFO Empty
7351 + * interrupt mask and status bits and disabling subsequent host
7352 + * channel interrupts.
7353 + */
7354 + intr.d32 = 0;
7355 + intr.b.nptxfempty = 1;
7356 + intr.b.ptxfempty = 1;
7357 + intr.b.hcintr = 1;
7358 + dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
7359 + dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
7360 +
7361 + del_timers(dwc_otg_hcd);
7362 +
7363 + /*
7364 + * Turn off the vbus power only if the core has transitioned to device
7365 + * mode. If still in host mode, need to keep power on to detect a
7366 + * reconnection.
7367 + */
7368 + if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
7369 + if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
7370 + hprt0_data_t hprt0 = { .d32=0 };
7371 + DWC_PRINT("Disconnect: PortPower off\n");
7372 + hprt0.b.prtpwr = 0;
7373 + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
7374 + }
7375 +
7376 + dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
7377 + }
7378 +
7379 + /* Respond with an error status to all URBs in the schedule. */
7380 + kill_all_urbs(dwc_otg_hcd);
7381 +
7382 + if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
7383 + /* Clean up any host channels that were in use. */
7384 + int num_channels;
7385 + int i;
7386 + dwc_hc_t *channel;
7387 + dwc_otg_hc_regs_t *hc_regs;
7388 + hcchar_data_t hcchar;
7389 +
7390 + num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
7391 +
7392 + if (!dwc_otg_hcd->core_if->dma_enable) {
7393 + /* Flush out any channel requests in slave mode. */
7394 + for (i = 0; i < num_channels; i++) {
7395 + channel = dwc_otg_hcd->hc_ptr_array[i];
7396 + if (list_empty(&channel->hc_list_entry)) {
7397 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
7398 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
7399 + if (hcchar.b.chen) {
7400 + hcchar.b.chen = 0;
7401 + hcchar.b.chdis = 1;
7402 + hcchar.b.epdir = 0;
7403 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
7404 + }
7405 + }
7406 + }
7407 + }
7408 +
7409 + for (i = 0; i < num_channels; i++) {
7410 + channel = dwc_otg_hcd->hc_ptr_array[i];
7411 + if (list_empty(&channel->hc_list_entry)) {
7412 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
7413 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
7414 + if (hcchar.b.chen) {
7415 + /* Halt the channel. */
7416 + hcchar.b.chdis = 1;
7417 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
7418 + }
7419 +
7420 + dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
7421 + list_add_tail(&channel->hc_list_entry,
7422 + &dwc_otg_hcd->free_hc_list);
7423 + }
7424 + }
7425 + }
7426 +
7427 + /* A disconnect will end the session so the B-Device is no
7428 + * longer a B-host. */
7429 + ((struct usb_hcd *)_p)->self.is_b_host = 0;
7430 +
7431 + return 1;
7432 +}
7433 +
7434 +/**
7435 + * Connection timeout function. An OTG host is required to display a
7436 + * message if the device does not connect within 10 seconds.
7437 + */
7438 +void dwc_otg_hcd_connect_timeout( unsigned long _ptr )
7439 +{
7440 + DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr);
7441 + DWC_PRINT( "Connect Timeout\n");
7442 + DWC_ERROR( "Device Not Connected/Responding\n" );
7443 +}
7444 +
7445 +/**
7446 + * Start the connection timer. An OTG host is required to display a
7447 + * message if the device does not connect within 10 seconds. The
7448 + * timer is deleted if a port connect interrupt occurs before the
7449 + * timer expires.
7450 + */
7451 +static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)
7452 +{
7453 + init_timer( &_hcd->conn_timer );
7454 + _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
7455 + _hcd->conn_timer.data = (unsigned long)0;
7456 + _hcd->conn_timer.expires = jiffies + (HZ*10);
7457 + add_timer( &_hcd->conn_timer );
7458 +}
7459 +
7460 +/**
7461 + * HCD Callback function for disconnect of the HCD.
7462 + *
7463 + * @param _p void pointer to the <code>struct usb_hcd</code>
7464 + */
7465 +static int32_t dwc_otg_hcd_session_start_cb( void *_p )
7466 +{
7467 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
7468 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
7469 + dwc_otg_hcd_start_connect_timer( dwc_otg_hcd );
7470 + return 1;
7471 +}
7472 +
7473 +/**
7474 + * HCD Callback structure for handling mode switching.
7475 + */
7476 +static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
7477 + .start = dwc_otg_hcd_start_cb,
7478 + .stop = dwc_otg_hcd_stop_cb,
7479 + .disconnect = dwc_otg_hcd_disconnect_cb,
7480 + .session_start = dwc_otg_hcd_session_start_cb,
7481 + .p = 0,
7482 +};
7483 +
7484 +
7485 +/**
7486 + * Reset tasklet function
7487 + */
7488 +static void reset_tasklet_func (unsigned long data)
7489 +{
7490 + dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
7491 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
7492 + hprt0_data_t hprt0;
7493 +
7494 + DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
7495 +
7496 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
7497 + hprt0.b.prtrst = 1;
7498 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
7499 + mdelay (60);
7500 +
7501 + hprt0.b.prtrst = 0;
7502 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
7503 + dwc_otg_hcd->flags.b.port_reset_change = 1;
7504 +
7505 + return;
7506 +}
7507 +
7508 +static struct tasklet_struct reset_tasklet = {
7509 + .next = NULL,
7510 + .state = 0,
7511 + .count = ATOMIC_INIT(0),
7512 + .func = reset_tasklet_func,
7513 + .data = 0,
7514 +};
7515 +
7516 +/**
7517 + * Initializes the HCD. This function allocates memory for and initializes the
7518 + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
7519 + * USB bus with the core and calls the hc_driver->start() function. It returns
7520 + * a negative error on failure.
7521 + */
7522 +int init_hcd_usecs(dwc_otg_hcd_t *_hcd);
7523 +
7524 +int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device)
7525 +{
7526 + struct usb_hcd *hcd = NULL;
7527 + dwc_otg_hcd_t *dwc_otg_hcd = NULL;
7528 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
7529 +
7530 + int num_channels;
7531 + int i;
7532 + dwc_hc_t *channel;
7533 +
7534 + int retval = 0;
7535 +
7536 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
7537 +
7538 + /*
7539 + * Allocate memory for the base HCD plus the DWC OTG HCD.
7540 + * Initialize the base HCD.
7541 + */
7542 + hcd = usb_create_hcd(&dwc_otg_hc_driver, _dev, dev_name(_dev));
7543 + if (hcd == NULL) {
7544 + retval = -ENOMEM;
7545 + goto error1;
7546 + }
7547 + dev_set_drvdata(_dev, dwc_otg_device); /* fscz restore */
7548 + hcd->regs = otg_dev->base;
7549 + hcd->rsrc_start = (int)otg_dev->base;
7550 +
7551 + hcd->self.otg_port = 1;
7552 +
7553 + /* Initialize the DWC OTG HCD. */
7554 + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
7555 + dwc_otg_hcd->core_if = otg_dev->core_if;
7556 + otg_dev->hcd = dwc_otg_hcd;
7557 +
7558 + /* Register the HCD CIL Callbacks */
7559 + dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
7560 + &hcd_cil_callbacks, hcd);
7561 +
7562 + /* Initialize the non-periodic schedule. */
7563 + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
7564 + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
7565 + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_deferred);
7566 +
7567 + /* Initialize the periodic schedule. */
7568 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
7569 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
7570 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
7571 + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
7572 +
7573 + /*
7574 + * Create a host channel descriptor for each host channel implemented
7575 + * in the controller. Initialize the channel descriptor array.
7576 + */
7577 + INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
7578 + num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
7579 + for (i = 0; i < num_channels; i++) {
7580 + channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
7581 + if (channel == NULL) {
7582 + retval = -ENOMEM;
7583 + DWC_ERROR("%s: host channel allocation failed\n", __func__);
7584 + goto error2;
7585 + }
7586 + memset(channel, 0, sizeof(dwc_hc_t));
7587 + channel->hc_num = i;
7588 + dwc_otg_hcd->hc_ptr_array[i] = channel;
7589 +#ifdef DEBUG
7590 + init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
7591 +#endif
7592 +
7593 + DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
7594 + }
7595 +
7596 + /* Initialize the Connection timeout timer. */
7597 + init_timer( &dwc_otg_hcd->conn_timer );
7598 +
7599 + /* Initialize reset tasklet. */
7600 + reset_tasklet.data = (unsigned long) dwc_otg_hcd;
7601 + dwc_otg_hcd->reset_tasklet = &reset_tasklet;
7602 +
7603 + /* Set device flags indicating whether the HCD supports DMA. */
7604 + if (otg_dev->core_if->dma_enable) {
7605 + DWC_PRINT("Using DMA mode\n");
7606 + //_dev->dma_mask = (void *)~0;
7607 + //_dev->coherent_dma_mask = ~0;
7608 + _dev->dma_mask = &dma_mask;
7609 + _dev->coherent_dma_mask = DMA_BIT_MASK(32);
7610 + } else {
7611 + DWC_PRINT("Using Slave mode\n");
7612 + _dev->dma_mask = (void *)0;
7613 + _dev->coherent_dma_mask = 0;
7614 + }
7615 +
7616 + init_hcd_usecs(dwc_otg_hcd);
7617 + /*
7618 + * Finish generic HCD initialization and start the HCD. This function
7619 + * allocates the DMA buffer pool, registers the USB bus, requests the
7620 + * IRQ line, and calls dwc_otg_hcd_start method.
7621 + */
7622 + retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED);
7623 + if (retval < 0) {
7624 + goto error2;
7625 + }
7626 +
7627 + /*
7628 + * Allocate space for storing data on status transactions. Normally no
7629 + * data is sent, but this space acts as a bit bucket. This must be
7630 + * done after usb_add_hcd since that function allocates the DMA buffer
7631 + * pool.
7632 + */
7633 + if (otg_dev->core_if->dma_enable) {
7634 + dwc_otg_hcd->status_buf =
7635 + dma_alloc_coherent(_dev,
7636 + DWC_OTG_HCD_STATUS_BUF_SIZE,
7637 + &dwc_otg_hcd->status_buf_dma,
7638 + GFP_KERNEL | GFP_DMA);
7639 + } else {
7640 + dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
7641 + GFP_KERNEL);
7642 + }
7643 + if (dwc_otg_hcd->status_buf == NULL) {
7644 + retval = -ENOMEM;
7645 + DWC_ERROR("%s: status_buf allocation failed\n", __func__);
7646 + goto error3;
7647 + }
7648 +
7649 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
7650 + dev_name(_dev), hcd->self.busnum);
7651 +
7652 + return 0;
7653 +
7654 + /* Error conditions */
7655 +error3:
7656 + usb_remove_hcd(hcd);
7657 +error2:
7658 + dwc_otg_hcd_free(hcd);
7659 + usb_put_hcd(hcd);
7660 +error1:
7661 + return retval;
7662 +}
7663 +
7664 +/**
7665 + * Removes the HCD.
7666 + * Frees memory and resources associated with the HCD and deregisters the bus.
7667 + */
7668 +void dwc_otg_hcd_remove(struct device *_dev)
7669 +{
7670 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
7671 + dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
7672 + struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
7673 +
7674 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
7675 +
7676 + /* Turn off all interrupts */
7677 + dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
7678 + dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
7679 +
7680 + usb_remove_hcd(hcd);
7681 +
7682 + dwc_otg_hcd_free(hcd);
7683 +
7684 + usb_put_hcd(hcd);
7685 +
7686 + return;
7687 +}
7688 +
7689 +
7690 +/* =========================================================================
7691 + * Linux HC Driver Functions
7692 + * ========================================================================= */
7693 +
7694 +/**
7695 + * Initializes dynamic portions of the DWC_otg HCD state.
7696 + */
7697 +static void hcd_reinit(dwc_otg_hcd_t *_hcd)
7698 +{
7699 + struct list_head *item;
7700 + int num_channels;
7701 + int i;
7702 + dwc_hc_t *channel;
7703 +
7704 + _hcd->flags.d32 = 0;
7705 +
7706 + _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;
7707 + _hcd->available_host_channels = _hcd->core_if->core_params->host_channels;
7708 +
7709 + /*
7710 + * Put all channels in the free channel list and clean up channel
7711 + * states.
7712 + */
7713 + item = _hcd->free_hc_list.next;
7714 + while (item != &_hcd->free_hc_list) {
7715 + list_del(item);
7716 + item = _hcd->free_hc_list.next;
7717 + }
7718 + num_channels = _hcd->core_if->core_params->host_channels;
7719 + for (i = 0; i < num_channels; i++) {
7720 + channel = _hcd->hc_ptr_array[i];
7721 + list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list);
7722 + dwc_otg_hc_cleanup(_hcd->core_if, channel);
7723 + }
7724 +
7725 + /* Initialize the DWC core for host mode operation. */
7726 + dwc_otg_core_host_init(_hcd->core_if);
7727 +}
7728 +
7729 +/** Initializes the DWC_otg controller and its root hub and prepares it for host
7730 + * mode operation. Activates the root port. Returns 0 on success and a negative
7731 + * error code on failure. */
7732 +int dwc_otg_hcd_start(struct usb_hcd *_hcd)
7733 +{
7734 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
7735 + dwc_otg_core_if_t * core_if = dwc_otg_hcd->core_if;
7736 + struct usb_bus *bus;
7737 +
7738 + // int retval;
7739 +
7740 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
7741 +
7742 + bus = hcd_to_bus(_hcd);
7743 +
7744 + /* Initialize the bus state. If the core is in Device Mode
7745 + * HALT the USB bus and return. */
7746 + if (dwc_otg_is_device_mode (core_if)) {
7747 + _hcd->state = HC_STATE_HALT;
7748 + return 0;
7749 + }
7750 + _hcd->state = HC_STATE_RUNNING;
7751 +
7752 + /* Initialize and connect root hub if one is not already attached */
7753 + if (bus->root_hub) {
7754 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
7755 + /* Inform the HUB driver to resume. */
7756 + usb_hcd_resume_root_hub(_hcd);
7757 + }
7758 + else {
7759 +#if 0
7760 + struct usb_device *udev;
7761 + udev = usb_alloc_dev(NULL, bus, 0);
7762 + if (!udev) {
7763 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
7764 + return -ENODEV;
7765 + }
7766 + udev->speed = USB_SPEED_HIGH;
7767 + /* Not needed - VJ
7768 + if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) {
7769 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
7770 + return -ENODEV;
7771 + }
7772 + */
7773 +#else
7774 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
7775 +#endif
7776 + }
7777 +
7778 + hcd_reinit(dwc_otg_hcd);
7779 +
7780 + return 0;
7781 +}
7782 +
7783 +static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
7784 +{
7785 + struct list_head *item;
7786 + dwc_otg_qh_t *qh;
7787 +
7788 + if (_qh_list->next == NULL) {
7789 + /* The list hasn't been initialized yet. */
7790 + return;
7791 + }
7792 +
7793 + /* Ensure there are no QTDs or URBs left. */
7794 + kill_urbs_in_qh_list(_hcd, _qh_list);
7795 +
7796 + for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {
7797 + qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
7798 + dwc_otg_hcd_qh_remove_and_free(_hcd, qh);
7799 + }
7800 +}
7801 +
7802 +/**
7803 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
7804 + * stopped.
7805 + */
7806 +void dwc_otg_hcd_stop(struct usb_hcd *_hcd)
7807 +{
7808 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
7809 + hprt0_data_t hprt0 = { .d32=0 };
7810 +
7811 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
7812 +
7813 + /* Turn off all host-specific interrupts. */
7814 + dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
7815 +
7816 + /*
7817 + * The root hub should be disconnected before this function is called.
7818 + * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
7819 + * and the QH lists (via ..._hcd_endpoint_disable).
7820 + */
7821 +
7822 + /* Turn off the vbus power */
7823 + DWC_PRINT("PortPower off\n");
7824 + hprt0.b.prtpwr = 0;
7825 + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
7826 +
7827 + return;
7828 +}
7829 +
7830 +
7831 +/** Returns the current frame number. */
7832 +int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd)
7833 +{
7834 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
7835 + hfnum_data_t hfnum;
7836 +
7837 + hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
7838 + host_if->host_global_regs->hfnum);
7839 +
7840 +#ifdef DEBUG_SOF
7841 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
7842 +#endif
7843 + return hfnum.b.frnum;
7844 +}
7845 +
7846 +/**
7847 + * Frees secondary storage associated with the dwc_otg_hcd structure contained
7848 + * in the struct usb_hcd field.
7849 + */
7850 +void dwc_otg_hcd_free(struct usb_hcd *_hcd)
7851 +{
7852 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
7853 + int i;
7854 +
7855 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
7856 +
7857 + del_timers(dwc_otg_hcd);
7858 +
7859 + /* Free memory for QH/QTD lists */
7860 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
7861 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_deferred);
7862 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
7863 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
7864 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
7865 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
7866 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
7867 +
7868 + /* Free memory for the host channels. */
7869 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
7870 + dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
7871 + if (hc != NULL) {
7872 + DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
7873 + kfree(hc);
7874 + }
7875 + }
7876 +
7877 + if (dwc_otg_hcd->core_if->dma_enable) {
7878 + if (dwc_otg_hcd->status_buf_dma) {
7879 + dma_free_coherent(_hcd->self.controller,
7880 + DWC_OTG_HCD_STATUS_BUF_SIZE,
7881 + dwc_otg_hcd->status_buf,
7882 + dwc_otg_hcd->status_buf_dma);
7883 + }
7884 + } else if (dwc_otg_hcd->status_buf != NULL) {
7885 + kfree(dwc_otg_hcd->status_buf);
7886 + }
7887 +
7888 + return;
7889 +}
7890 +
7891 +
7892 +#ifdef DEBUG
7893 +static void dump_urb_info(struct urb *_urb, char* _fn_name)
7894 +{
7895 + DWC_PRINT("%s, urb %p\n", _fn_name, _urb);
7896 + DWC_PRINT(" Device address: %d\n", usb_pipedevice(_urb->pipe));
7897 + DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe),
7898 + (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
7899 + DWC_PRINT(" Endpoint type: %s\n",
7900 + ({char *pipetype;
7901 + switch (usb_pipetype(_urb->pipe)) {
7902 + case PIPE_CONTROL: pipetype = "CONTROL"; break;
7903 + case PIPE_BULK: pipetype = "BULK"; break;
7904 + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
7905 + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
7906 + default: pipetype = "UNKNOWN"; break;
7907 + }; pipetype;}));
7908 + DWC_PRINT(" Speed: %s\n",
7909 + ({char *speed;
7910 + switch (_urb->dev->speed) {
7911 + case USB_SPEED_HIGH: speed = "HIGH"; break;
7912 + case USB_SPEED_FULL: speed = "FULL"; break;
7913 + case USB_SPEED_LOW: speed = "LOW"; break;
7914 + default: speed = "UNKNOWN"; break;
7915 + }; speed;}));
7916 + DWC_PRINT(" Max packet size: %d\n",
7917 + usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
7918 + DWC_PRINT(" Data buffer length: %d\n", _urb->transfer_buffer_length);
7919 + DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n",
7920 + _urb->transfer_buffer, (void *)_urb->transfer_dma);
7921 + DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n",
7922 + _urb->setup_packet, (void *)_urb->setup_dma);
7923 + DWC_PRINT(" Interval: %d\n", _urb->interval);
7924 + if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
7925 + int i;
7926 + for (i = 0; i < _urb->number_of_packets; i++) {
7927 + DWC_PRINT(" ISO Desc %d:\n", i);
7928 + DWC_PRINT(" offset: %d, length %d\n",
7929 + _urb->iso_frame_desc[i].offset,
7930 + _urb->iso_frame_desc[i].length);
7931 + }
7932 + }
7933 +}
7934 +
7935 +static void dump_channel_info(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *qh)
7936 +{
7937 + if (qh->channel != NULL) {
7938 + dwc_hc_t *hc = qh->channel;
7939 + struct list_head *item;
7940 + dwc_otg_qh_t *qh_item;
7941 + int num_channels = _hcd->core_if->core_params->host_channels;
7942 + int i;
7943 +
7944 + dwc_otg_hc_regs_t *hc_regs;
7945 + hcchar_data_t hcchar;
7946 + hcsplt_data_t hcsplt;
7947 + hctsiz_data_t hctsiz;
7948 + uint32_t hcdma;
7949 +
7950 + hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];
7951 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
7952 + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
7953 + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
7954 + hcdma = dwc_read_reg32(&hc_regs->hcdma);
7955 +
7956 + DWC_PRINT(" Assigned to channel %p:\n", hc);
7957 + DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
7958 + DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
7959 + DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
7960 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
7961 + DWC_PRINT(" ep_type: %d\n", hc->ep_type);
7962 + DWC_PRINT(" max_packet: %d\n", hc->max_packet);
7963 + DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
7964 + DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
7965 + DWC_PRINT(" halt_status: %d\n", hc->halt_status);
7966 + DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
7967 + DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
7968 + DWC_PRINT(" qh: %p\n", hc->qh);
7969 + DWC_PRINT(" NP inactive sched:\n");
7970 + list_for_each(item, &_hcd->non_periodic_sched_inactive) {
7971 + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
7972 + DWC_PRINT(" %p\n", qh_item);
7973 + } DWC_PRINT(" NP active sched:\n");
7974 + list_for_each(item, &_hcd->non_periodic_sched_deferred) {
7975 + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
7976 + DWC_PRINT(" %p\n", qh_item);
7977 + } DWC_PRINT(" NP deferred sched:\n");
7978 + list_for_each(item, &_hcd->non_periodic_sched_active) {
7979 + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
7980 + DWC_PRINT(" %p\n", qh_item);
7981 + } DWC_PRINT(" Channels: \n");
7982 + for (i = 0; i < num_channels; i++) {
7983 + dwc_hc_t *hc = _hcd->hc_ptr_array[i];
7984 + DWC_PRINT(" %2d: %p\n", i, hc);
7985 + }
7986 + }
7987 +}
7988 +#endif // DEBUG
7989 +
7990 +/** Starts processing a USB transfer request specified by a USB Request Block
7991 + * (URB). mem_flags indicates the type of memory allocation to use while
7992 + * processing this URB. */
7993 +int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
7994 + struct urb *_urb,
7995 + gfp_t _mem_flags)
7996 +{
7997 + unsigned long flags;
7998 + int retval;
7999 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
8000 + dwc_otg_qtd_t *qtd;
8001 +
8002 + local_irq_save(flags);
8003 + retval = usb_hcd_link_urb_to_ep(_hcd, _urb);
8004 + if (retval) {
8005 + local_irq_restore(flags);
8006 + return retval;
8007 + }
8008 +#ifdef DEBUG
8009 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8010 + dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
8011 + }
8012 +#endif // DEBUG
8013 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
8014 + /* No longer connected. */
8015 + local_irq_restore(flags);
8016 + return -ENODEV;
8017 + }
8018 +
8019 + qtd = dwc_otg_hcd_qtd_create (_urb);
8020 + if (qtd == NULL) {
8021 + local_irq_restore(flags);
8022 + DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
8023 + return -ENOMEM;
8024 + }
8025 +
8026 + retval = dwc_otg_hcd_qtd_add (qtd, dwc_otg_hcd);
8027 + if (retval < 0) {
8028 + DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
8029 + "Error status %d\n", retval);
8030 + dwc_otg_hcd_qtd_free(qtd);
8031 + }
8032 +
8033 + local_irq_restore (flags);
8034 + return retval;
8035 +}
8036 +
8037 +/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
8038 + * success. */
8039 +int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status)
8040 +{
8041 + unsigned long flags;
8042 + dwc_otg_hcd_t *dwc_otg_hcd;
8043 + dwc_otg_qtd_t *urb_qtd;
8044 + dwc_otg_qh_t *qh;
8045 + int retval;
8046 + //struct usb_host_endpoint *_ep = NULL;
8047 +
8048 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
8049 +
8050 + local_irq_save(flags);
8051 +
8052 + retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status);
8053 + if (retval) {
8054 + local_irq_restore(flags);
8055 + return retval;
8056 + }
8057 +
8058 + dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
8059 + urb_qtd = (dwc_otg_qtd_t *)_urb->hcpriv;
8060 + if (urb_qtd == NULL) {
8061 + printk("urb_qtd is NULL for _urb %08x\n",(unsigned)_urb);
8062 + goto done;
8063 + }
8064 + qh = (dwc_otg_qh_t *) urb_qtd->qtd_qh_ptr;
8065 + if (qh == NULL) {
8066 + goto done;
8067 + }
8068 +
8069 +#ifdef DEBUG
8070 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8071 + dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue");
8072 + if (urb_qtd == qh->qtd_in_process) {
8073 + dump_channel_info(dwc_otg_hcd, qh);
8074 + }
8075 + }
8076 +#endif // DEBUG
8077 +
8078 + if (urb_qtd == qh->qtd_in_process) {
8079 + /* The QTD is in process (it has been assigned to a channel). */
8080 +
8081 + if (dwc_otg_hcd->flags.b.port_connect_status) {
8082 + /*
8083 + * If still connected (i.e. in host mode), halt the
8084 + * channel so it can be used for other transfers. If
8085 + * no longer connected, the host registers can't be
8086 + * written to halt the channel since the core is in
8087 + * device mode.
8088 + */
8089 + dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
8090 + DWC_OTG_HC_XFER_URB_DEQUEUE);
8091 + }
8092 + }
8093 +
8094 + /*
8095 + * Free the QTD and clean up the associated QH. Leave the QH in the
8096 + * schedule if it has any remaining QTDs.
8097 + */
8098 + dwc_otg_hcd_qtd_remove_and_free(urb_qtd);
8099 + if (urb_qtd == qh->qtd_in_process) {
8100 + dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
8101 + qh->channel = NULL;
8102 + qh->qtd_in_process = NULL;
8103 + } else if (list_empty(&qh->qtd_list)) {
8104 + dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
8105 + }
8106 +
8107 +done:
8108 + local_irq_restore(flags);
8109 + _urb->hcpriv = NULL;
8110 +
8111 + /* Higher layer software sets URB status. */
8112 + usb_hcd_unlink_urb_from_ep(_hcd, _urb);
8113 + usb_hcd_giveback_urb(_hcd, _urb, _status);
8114 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8115 + DWC_PRINT("Called usb_hcd_giveback_urb()\n");
8116 + DWC_PRINT(" urb->status = %d\n", _urb->status);
8117 + }
8118 +
8119 + return 0;
8120 +}
8121 +
8122 +
8123 +/** Frees resources in the DWC_otg controller related to a given endpoint. Also
8124 + * clears state in the HCD related to the endpoint. Any URBs for the endpoint
8125 + * must already be dequeued. */
8126 +void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd,
8127 + struct usb_host_endpoint *_ep)
8128 +
8129 +{
8130 + dwc_otg_qh_t *qh;
8131 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
8132 +
8133 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
8134 + "endpoint=%d\n", _ep->desc.bEndpointAddress,
8135 + dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
8136 +
8137 + qh = (dwc_otg_qh_t *)(_ep->hcpriv);
8138 + if (qh != NULL) {
8139 +#ifdef DEBUG
8140 + /** Check that the QTD list is really empty */
8141 + if (!list_empty(&qh->qtd_list)) {
8142 + DWC_WARN("DWC OTG HCD EP DISABLE:"
8143 + " QTD List for this endpoint is not empty\n");
8144 + }
8145 +#endif // DEBUG
8146 +
8147 + dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
8148 + _ep->hcpriv = NULL;
8149 + }
8150 +
8151 + return;
8152 +}
8153 +extern int dwc_irq;
8154 +/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
8155 + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
8156 + * interrupt.
8157 + *
8158 + * This function is called by the USB core when an interrupt occurs */
8159 +irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
8160 +{
8161 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
8162 +
8163 + mask_and_ack_ifx_irq (dwc_irq);
8164 + return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
8165 +}
8166 +
8167 +/** Creates Status Change bitmap for the root hub and root port. The bitmap is
8168 + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
8169 + * is the status change indicator for the single root port. Returns 1 if either
8170 + * change indicator is 1, otherwise returns 0. */
8171 +int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd, char *_buf)
8172 +{
8173 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
8174 +
8175 + _buf[0] = 0;
8176 + _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
8177 + dwc_otg_hcd->flags.b.port_reset_change ||
8178 + dwc_otg_hcd->flags.b.port_enable_change ||
8179 + dwc_otg_hcd->flags.b.port_suspend_change ||
8180 + dwc_otg_hcd->flags.b.port_over_current_change) << 1;
8181 +
8182 +#ifdef DEBUG
8183 + if (_buf[0]) {
8184 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
8185 + " Root port status changed\n");
8186 + DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
8187 + dwc_otg_hcd->flags.b.port_connect_status_change);
8188 + DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
8189 + dwc_otg_hcd->flags.b.port_reset_change);
8190 + DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
8191 + dwc_otg_hcd->flags.b.port_enable_change);
8192 + DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
8193 + dwc_otg_hcd->flags.b.port_suspend_change);
8194 + DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
8195 + dwc_otg_hcd->flags.b.port_over_current_change);
8196 + }
8197 +#endif // DEBUG
8198 + return (_buf[0] != 0);
8199 +}
8200 +
8201 +#ifdef DWC_HS_ELECT_TST
8202 +/*
8203 + * Quick and dirty hack to implement the HS Electrical Test
8204 + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
8205 + *
8206 + * This code was copied from our userspace app "hset". It sends a
8207 + * Get Device Descriptor control sequence in two parts, first the
8208 + * Setup packet by itself, followed some time later by the In and
8209 + * Ack packets. Rather than trying to figure out how to add this
8210 + * functionality to the normal driver code, we just hijack the
8211 + * hardware, using these two function to drive the hardware
8212 + * directly.
8213 + */
8214 +
8215 +dwc_otg_core_global_regs_t *global_regs;
8216 +dwc_otg_host_global_regs_t *hc_global_regs;
8217 +dwc_otg_hc_regs_t *hc_regs;
8218 +uint32_t *data_fifo;
8219 +
8220 +static void do_setup(void)
8221 +{
8222 + gintsts_data_t gintsts;
8223 + hctsiz_data_t hctsiz;
8224 + hcchar_data_t hcchar;
8225 + haint_data_t haint;
8226 + hcint_data_t hcint;
8227 +
8228 + /* Enable HAINTs */
8229 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
8230 +
8231 + /* Enable HCINTs */
8232 + dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
8233 +
8234 + /* Read GINTSTS */
8235 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8236 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8237 +
8238 + /* Read HAINT */
8239 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8240 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8241 +
8242 + /* Read HCINT */
8243 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8244 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8245 +
8246 + /* Read HCCHAR */
8247 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8248 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8249 +
8250 + /* Clear HCINT */
8251 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8252 +
8253 + /* Clear HAINT */
8254 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8255 +
8256 + /* Clear GINTSTS */
8257 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8258 +
8259 + /* Read GINTSTS */
8260 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8261 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8262 +
8263 + /*
8264 + * Send Setup packet (Get Device Descriptor)
8265 + */
8266 +
8267 + /* Make sure channel is disabled */
8268 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8269 + if (hcchar.b.chen) {
8270 + //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
8271 + hcchar.b.chdis = 1;
8272 + // hcchar.b.chen = 1;
8273 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8274 + //sleep(1);
8275 + MDELAY(1000);
8276 +
8277 + /* Read GINTSTS */
8278 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8279 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8280 +
8281 + /* Read HAINT */
8282 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8283 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8284 +
8285 + /* Read HCINT */
8286 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8287 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8288 +
8289 + /* Read HCCHAR */
8290 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8291 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8292 +
8293 + /* Clear HCINT */
8294 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8295 +
8296 + /* Clear HAINT */
8297 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8298 +
8299 + /* Clear GINTSTS */
8300 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8301 +
8302 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8303 + //if (hcchar.b.chen) {
8304 + // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
8305 + //}
8306 + }
8307 +
8308 + /* Set HCTSIZ */
8309 + hctsiz.d32 = 0;
8310 + hctsiz.b.xfersize = 8;
8311 + hctsiz.b.pktcnt = 1;
8312 + hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
8313 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
8314 +
8315 + /* Set HCCHAR */
8316 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8317 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
8318 + hcchar.b.epdir = 0;
8319 + hcchar.b.epnum = 0;
8320 + hcchar.b.mps = 8;
8321 + hcchar.b.chen = 1;
8322 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8323 +
8324 + /* Fill FIFO with Setup data for Get Device Descriptor */
8325 + data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
8326 + dwc_write_reg32(data_fifo++, 0x01000680);
8327 + dwc_write_reg32(data_fifo++, 0x00080000);
8328 +
8329 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8330 + //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
8331 +
8332 + /* Wait for host channel interrupt */
8333 + do {
8334 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8335 + } while (gintsts.b.hcintr == 0);
8336 +
8337 + //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
8338 +
8339 + /* Disable HCINTs */
8340 + dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
8341 +
8342 + /* Disable HAINTs */
8343 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
8344 +
8345 + /* Read HAINT */
8346 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8347 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8348 +
8349 + /* Read HCINT */
8350 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8351 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8352 +
8353 + /* Read HCCHAR */
8354 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8355 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8356 +
8357 + /* Clear HCINT */
8358 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8359 +
8360 + /* Clear HAINT */
8361 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8362 +
8363 + /* Clear GINTSTS */
8364 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8365 +
8366 + /* Read GINTSTS */
8367 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8368 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8369 +}
8370 +
8371 +static void do_in_ack(void)
8372 +{
8373 + gintsts_data_t gintsts;
8374 + hctsiz_data_t hctsiz;
8375 + hcchar_data_t hcchar;
8376 + haint_data_t haint;
8377 + hcint_data_t hcint;
8378 + host_grxsts_data_t grxsts;
8379 +
8380 + /* Enable HAINTs */
8381 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
8382 +
8383 + /* Enable HCINTs */
8384 + dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
8385 +
8386 + /* Read GINTSTS */
8387 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8388 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8389 +
8390 + /* Read HAINT */
8391 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8392 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8393 +
8394 + /* Read HCINT */
8395 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8396 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8397 +
8398 + /* Read HCCHAR */
8399 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8400 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8401 +
8402 + /* Clear HCINT */
8403 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8404 +
8405 + /* Clear HAINT */
8406 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8407 +
8408 + /* Clear GINTSTS */
8409 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8410 +
8411 + /* Read GINTSTS */
8412 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8413 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8414 +
8415 + /*
8416 + * Receive Control In packet
8417 + */
8418 +
8419 + /* Make sure channel is disabled */
8420 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8421 + if (hcchar.b.chen) {
8422 + //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
8423 + hcchar.b.chdis = 1;
8424 + hcchar.b.chen = 1;
8425 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8426 + //sleep(1);
8427 + MDELAY(1000);
8428 +
8429 + /* Read GINTSTS */
8430 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8431 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8432 +
8433 + /* Read HAINT */
8434 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8435 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8436 +
8437 + /* Read HCINT */
8438 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8439 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8440 +
8441 + /* Read HCCHAR */
8442 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8443 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8444 +
8445 + /* Clear HCINT */
8446 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8447 +
8448 + /* Clear HAINT */
8449 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8450 +
8451 + /* Clear GINTSTS */
8452 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8453 +
8454 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8455 + //if (hcchar.b.chen) {
8456 + // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
8457 + //}
8458 + }
8459 +
8460 + /* Set HCTSIZ */
8461 + hctsiz.d32 = 0;
8462 + hctsiz.b.xfersize = 8;
8463 + hctsiz.b.pktcnt = 1;
8464 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
8465 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
8466 +
8467 + /* Set HCCHAR */
8468 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8469 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
8470 + hcchar.b.epdir = 1;
8471 + hcchar.b.epnum = 0;
8472 + hcchar.b.mps = 8;
8473 + hcchar.b.chen = 1;
8474 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8475 +
8476 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8477 + //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
8478 +
8479 + /* Wait for receive status queue interrupt */
8480 + do {
8481 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8482 + } while (gintsts.b.rxstsqlvl == 0);
8483 +
8484 + //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
8485 +
8486 + /* Read RXSTS */
8487 + grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
8488 + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
8489 +
8490 + /* Clear RXSTSQLVL in GINTSTS */
8491 + gintsts.d32 = 0;
8492 + gintsts.b.rxstsqlvl = 1;
8493 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8494 +
8495 + switch (grxsts.b.pktsts) {
8496 + case DWC_GRXSTS_PKTSTS_IN:
8497 + /* Read the data into the host buffer */
8498 + if (grxsts.b.bcnt > 0) {
8499 + int i;
8500 + int word_count = (grxsts.b.bcnt + 3) / 4;
8501 +
8502 + data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
8503 +
8504 + for (i = 0; i < word_count; i++) {
8505 + (void)dwc_read_reg32(data_fifo++);
8506 + }
8507 + }
8508 +
8509 + //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
8510 + break;
8511 +
8512 + default:
8513 + //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
8514 + break;
8515 + }
8516 +
8517 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8518 + //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
8519 +
8520 + /* Wait for receive status queue interrupt */
8521 + do {
8522 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8523 + } while (gintsts.b.rxstsqlvl == 0);
8524 +
8525 + //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
8526 +
8527 + /* Read RXSTS */
8528 + grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
8529 + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
8530 +
8531 + /* Clear RXSTSQLVL in GINTSTS */
8532 + gintsts.d32 = 0;
8533 + gintsts.b.rxstsqlvl = 1;
8534 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8535 +
8536 + switch (grxsts.b.pktsts) {
8537 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
8538 + break;
8539 +
8540 + default:
8541 + //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
8542 + break;
8543 + }
8544 +
8545 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8546 + //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
8547 +
8548 + /* Wait for host channel interrupt */
8549 + do {
8550 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8551 + } while (gintsts.b.hcintr == 0);
8552 +
8553 + //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
8554 +
8555 + /* Read HAINT */
8556 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8557 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8558 +
8559 + /* Read HCINT */
8560 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8561 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8562 +
8563 + /* Read HCCHAR */
8564 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8565 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8566 +
8567 + /* Clear HCINT */
8568 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8569 +
8570 + /* Clear HAINT */
8571 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8572 +
8573 + /* Clear GINTSTS */
8574 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8575 +
8576 + /* Read GINTSTS */
8577 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8578 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8579 +
8580 + // usleep(100000);
8581 + // mdelay(100);
8582 + MDELAY(1);
8583 +
8584 + /*
8585 + * Send handshake packet
8586 + */
8587 +
8588 + /* Read HAINT */
8589 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8590 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8591 +
8592 + /* Read HCINT */
8593 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8594 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8595 +
8596 + /* Read HCCHAR */
8597 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8598 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8599 +
8600 + /* Clear HCINT */
8601 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8602 +
8603 + /* Clear HAINT */
8604 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8605 +
8606 + /* Clear GINTSTS */
8607 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8608 +
8609 + /* Read GINTSTS */
8610 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8611 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8612 +
8613 + /* Make sure channel is disabled */
8614 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8615 + if (hcchar.b.chen) {
8616 + //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
8617 + hcchar.b.chdis = 1;
8618 + hcchar.b.chen = 1;
8619 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8620 + //sleep(1);
8621 + MDELAY(1000);
8622 +
8623 + /* Read GINTSTS */
8624 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8625 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8626 +
8627 + /* Read HAINT */
8628 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8629 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8630 +
8631 + /* Read HCINT */
8632 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8633 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8634 +
8635 + /* Read HCCHAR */
8636 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8637 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8638 +
8639 + /* Clear HCINT */
8640 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8641 +
8642 + /* Clear HAINT */
8643 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8644 +
8645 + /* Clear GINTSTS */
8646 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8647 +
8648 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8649 + //if (hcchar.b.chen) {
8650 + // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
8651 + //}
8652 + }
8653 +
8654 + /* Set HCTSIZ */
8655 + hctsiz.d32 = 0;
8656 + hctsiz.b.xfersize = 0;
8657 + hctsiz.b.pktcnt = 1;
8658 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
8659 + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
8660 +
8661 + /* Set HCCHAR */
8662 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8663 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
8664 + hcchar.b.epdir = 0;
8665 + hcchar.b.epnum = 0;
8666 + hcchar.b.mps = 8;
8667 + hcchar.b.chen = 1;
8668 + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8669 +
8670 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8671 + //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
8672 +
8673 + /* Wait for host channel interrupt */
8674 + do {
8675 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8676 + } while (gintsts.b.hcintr == 0);
8677 +
8678 + //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
8679 +
8680 + /* Disable HCINTs */
8681 + dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
8682 +
8683 + /* Disable HAINTs */
8684 + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
8685 +
8686 + /* Read HAINT */
8687 + haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8688 + //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8689 +
8690 + /* Read HCINT */
8691 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8692 + //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8693 +
8694 + /* Read HCCHAR */
8695 + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8696 + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8697 +
8698 + /* Clear HCINT */
8699 + dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8700 +
8701 + /* Clear HAINT */
8702 + dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8703 +
8704 + /* Clear GINTSTS */
8705 + dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8706 +
8707 + /* Read GINTSTS */
8708 + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8709 + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8710 +}
8711 +#endif /* DWC_HS_ELECT_TST */
8712 +
8713 +/** Handles hub class-specific requests.*/
8714 +int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd,
8715 + u16 _typeReq,
8716 + u16 _wValue,
8717 + u16 _wIndex,
8718 + char *_buf,
8719 + u16 _wLength)
8720 +{
8721 + int retval = 0;
8722 +
8723 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
8724 + dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
8725 + struct usb_hub_descriptor *desc;
8726 + hprt0_data_t hprt0 = {.d32 = 0};
8727 +
8728 + uint32_t port_status;
8729 +
8730 + switch (_typeReq) {
8731 + case ClearHubFeature:
8732 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8733 + "ClearHubFeature 0x%x\n", _wValue);
8734 + switch (_wValue) {
8735 + case C_HUB_LOCAL_POWER:
8736 + case C_HUB_OVER_CURRENT:
8737 + /* Nothing required here */
8738 + break;
8739 + default:
8740 + retval = -EINVAL;
8741 + DWC_ERROR ("DWC OTG HCD - "
8742 + "ClearHubFeature request %xh unknown\n", _wValue);
8743 + }
8744 + break;
8745 + case ClearPortFeature:
8746 + if (!_wIndex || _wIndex > 1)
8747 + goto error;
8748 +
8749 + switch (_wValue) {
8750 + case USB_PORT_FEAT_ENABLE:
8751 + DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "
8752 + "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
8753 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8754 + hprt0.b.prtena = 1;
8755 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8756 + break;
8757 + case USB_PORT_FEAT_SUSPEND:
8758 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8759 + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
8760 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8761 + hprt0.b.prtres = 1;
8762 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8763 + /* Clear Resume bit */
8764 + mdelay (100);
8765 + hprt0.b.prtres = 0;
8766 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8767 + break;
8768 + case USB_PORT_FEAT_POWER:
8769 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8770 + "ClearPortFeature USB_PORT_FEAT_POWER\n");
8771 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8772 + hprt0.b.prtpwr = 0;
8773 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8774 + break;
8775 + case USB_PORT_FEAT_INDICATOR:
8776 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8777 + "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
8778 + /* Port inidicator not supported */
8779 + break;
8780 + case USB_PORT_FEAT_C_CONNECTION:
8781 + /* Clears drivers internal connect status change
8782 + * flag */
8783 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8784 + "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
8785 + dwc_otg_hcd->flags.b.port_connect_status_change = 0;
8786 + break;
8787 + case USB_PORT_FEAT_C_RESET:
8788 + /* Clears the driver's internal Port Reset Change
8789 + * flag */
8790 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8791 + "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
8792 + dwc_otg_hcd->flags.b.port_reset_change = 0;
8793 + break;
8794 + case USB_PORT_FEAT_C_ENABLE:
8795 + /* Clears the driver's internal Port
8796 + * Enable/Disable Change flag */
8797 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8798 + "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
8799 + dwc_otg_hcd->flags.b.port_enable_change = 0;
8800 + break;
8801 + case USB_PORT_FEAT_C_SUSPEND:
8802 + /* Clears the driver's internal Port Suspend
8803 + * Change flag, which is set when resume signaling on
8804 + * the host port is complete */
8805 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8806 + "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
8807 + dwc_otg_hcd->flags.b.port_suspend_change = 0;
8808 + break;
8809 + case USB_PORT_FEAT_C_OVER_CURRENT:
8810 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8811 + "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
8812 + dwc_otg_hcd->flags.b.port_over_current_change = 0;
8813 + break;
8814 + default:
8815 + retval = -EINVAL;
8816 + DWC_ERROR ("DWC OTG HCD - "
8817 + "ClearPortFeature request %xh "
8818 + "unknown or unsupported\n", _wValue);
8819 + }
8820 + break;
8821 + case GetHubDescriptor:
8822 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8823 + "GetHubDescriptor\n");
8824 + desc = (struct usb_hub_descriptor *)_buf;
8825 + desc->bDescLength = 9;
8826 + desc->bDescriptorType = 0x29;
8827 + desc->bNbrPorts = 1;
8828 + desc->wHubCharacteristics = 0x08;
8829 + desc->bPwrOn2PwrGood = 1;
8830 + desc->bHubContrCurrent = 0;
8831 + desc->u.hs.DeviceRemovable[0] = 0;
8832 + desc->u.hs.DeviceRemovable[1] = 0xff;
8833 + break;
8834 + case GetHubStatus:
8835 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8836 + "GetHubStatus\n");
8837 + memset (_buf, 0, 4);
8838 + break;
8839 + case GetPortStatus:
8840 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8841 + "GetPortStatus\n");
8842 +
8843 + if (!_wIndex || _wIndex > 1)
8844 + goto error;
8845 +
8846 + port_status = 0;
8847 +
8848 + if (dwc_otg_hcd->flags.b.port_connect_status_change)
8849 + port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
8850 +
8851 + if (dwc_otg_hcd->flags.b.port_enable_change)
8852 + port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
8853 +
8854 + if (dwc_otg_hcd->flags.b.port_suspend_change)
8855 + port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
8856 +
8857 + if (dwc_otg_hcd->flags.b.port_reset_change)
8858 + port_status |= (1 << USB_PORT_FEAT_C_RESET);
8859 +
8860 + if (dwc_otg_hcd->flags.b.port_over_current_change) {
8861 + DWC_ERROR("Device Not Supported\n");
8862 + port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
8863 + }
8864 +
8865 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
8866 + printk("DISCONNECTED PORT\n");
8867 + /*
8868 + * The port is disconnected, which means the core is
8869 + * either in device mode or it soon will be. Just
8870 + * return 0's for the remainder of the port status
8871 + * since the port register can't be read if the core
8872 + * is in device mode.
8873 + */
8874 +#if 1 // winder.
8875 + *((u32 *) _buf) = cpu_to_le32(port_status);
8876 +#else
8877 + *((__le32 *) _buf) = cpu_to_le32(port_status);
8878 +#endif
8879 + break;
8880 + }
8881 +
8882 + hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
8883 + DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
8884 +
8885 + if (hprt0.b.prtconnsts)
8886 + port_status |= (1 << USB_PORT_FEAT_CONNECTION);
8887 +
8888 + if (hprt0.b.prtena)
8889 + port_status |= (1 << USB_PORT_FEAT_ENABLE);
8890 +
8891 + if (hprt0.b.prtsusp)
8892 + port_status |= (1 << USB_PORT_FEAT_SUSPEND);
8893 +
8894 + if (hprt0.b.prtovrcurract)
8895 + port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
8896 +
8897 + if (hprt0.b.prtrst)
8898 + port_status |= (1 << USB_PORT_FEAT_RESET);
8899 +
8900 + if (hprt0.b.prtpwr)
8901 + port_status |= (1 << USB_PORT_FEAT_POWER);
8902 +
8903 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
8904 + port_status |= USB_PORT_STAT_HIGH_SPEED;
8905 +
8906 + else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
8907 + port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
8908 +
8909 + if (hprt0.b.prttstctl)
8910 + port_status |= (1 << USB_PORT_FEAT_TEST);
8911 +
8912 + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
8913 +#if 1 // winder.
8914 + *((u32 *) _buf) = cpu_to_le32(port_status);
8915 +#else
8916 + *((__le32 *) _buf) = cpu_to_le32(port_status);
8917 +#endif
8918 +
8919 + break;
8920 + case SetHubFeature:
8921 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8922 + "SetHubFeature\n");
8923 + /* No HUB features supported */
8924 + break;
8925 + case SetPortFeature:
8926 + if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
8927 + goto error;
8928 +
8929 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
8930 + /*
8931 + * The port is disconnected, which means the core is
8932 + * either in device mode or it soon will be. Just
8933 + * return without doing anything since the port
8934 + * register can't be written if the core is in device
8935 + * mode.
8936 + */
8937 + break;
8938 + }
8939 +
8940 + switch (_wValue) {
8941 + case USB_PORT_FEAT_SUSPEND:
8942 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8943 + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
8944 + if (_hcd->self.otg_port == _wIndex
8945 + && _hcd->self.b_hnp_enable) {
8946 + gotgctl_data_t gotgctl = {.d32=0};
8947 + gotgctl.b.hstsethnpen = 1;
8948 + dwc_modify_reg32(&core_if->core_global_regs->
8949 + gotgctl, 0, gotgctl.d32);
8950 + core_if->op_state = A_SUSPEND;
8951 + }
8952 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8953 + hprt0.b.prtsusp = 1;
8954 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8955 + //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
8956 + /* Suspend the Phy Clock */
8957 + {
8958 + pcgcctl_data_t pcgcctl = {.d32=0};
8959 + pcgcctl.b.stoppclk = 1;
8960 + dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
8961 + }
8962 +
8963 + /* For HNP the bus must be suspended for at least 200ms.*/
8964 + if (_hcd->self.b_hnp_enable) {
8965 + mdelay(200);
8966 + //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state);
8967 + }
8968 + break;
8969 + case USB_PORT_FEAT_POWER:
8970 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8971 + "SetPortFeature - USB_PORT_FEAT_POWER\n");
8972 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8973 + hprt0.b.prtpwr = 1;
8974 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8975 + break;
8976 + case USB_PORT_FEAT_RESET:
8977 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8978 + "SetPortFeature - USB_PORT_FEAT_RESET\n");
8979 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8980 + /* TODO: Is this for OTG protocol??
8981 + * We shoudl remove OTG totally for Danube system.
8982 + * But, in the future, maybe we need this.
8983 + */
8984 +#if 1 // winder
8985 + hprt0.b.prtrst = 1;
8986 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8987 +#else
8988 + /* When B-Host the Port reset bit is set in
8989 + * the Start HCD Callback function, so that
8990 + * the reset is started within 1ms of the HNP
8991 + * success interrupt. */
8992 + if (!_hcd->self.is_b_host) {
8993 + hprt0.b.prtrst = 1;
8994 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8995 + }
8996 +#endif
8997 + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
8998 + MDELAY (60);
8999 + hprt0.b.prtrst = 0;
9000 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9001 + break;
9002 +
9003 +#ifdef DWC_HS_ELECT_TST
9004 + case USB_PORT_FEAT_TEST:
9005 + {
9006 + uint32_t t;
9007 + gintmsk_data_t gintmsk;
9008 +
9009 + t = (_wIndex >> 8); /* MSB wIndex USB */
9010 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9011 + "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
9012 + printk("USB_PORT_FEAT_TEST %d\n", t);
9013 + if (t < 6) {
9014 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
9015 + hprt0.b.prttstctl = t;
9016 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9017 + } else {
9018 + /* Setup global vars with reg addresses (quick and
9019 + * dirty hack, should be cleaned up)
9020 + */
9021 + global_regs = core_if->core_global_regs;
9022 + hc_global_regs = core_if->host_if->host_global_regs;
9023 + hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
9024 + data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
9025 +
9026 + if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
9027 + /* Save current interrupt mask */
9028 + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9029 +
9030 + /* Disable all interrupts while we muck with
9031 + * the hardware directly
9032 + */
9033 + dwc_write_reg32(&global_regs->gintmsk, 0);
9034 +
9035 + /* 15 second delay per the test spec */
9036 + mdelay(15000);
9037 +
9038 + /* Drive suspend on the root port */
9039 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
9040 + hprt0.b.prtsusp = 1;
9041 + hprt0.b.prtres = 0;
9042 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9043 +
9044 + /* 15 second delay per the test spec */
9045 + mdelay(15000);
9046 +
9047 + /* Drive resume on the root port */
9048 + hprt0.d32 = dwc_otg_read_hprt0 (core_if);
9049 + hprt0.b.prtsusp = 0;
9050 + hprt0.b.prtres = 1;
9051 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9052 + mdelay(100);
9053 +
9054 + /* Clear the resume bit */
9055 + hprt0.b.prtres = 0;
9056 + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9057 +
9058 + /* Restore interrupts */
9059 + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9060 + } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
9061 + /* Save current interrupt mask */
9062 + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9063 +
9064 + /* Disable all interrupts while we muck with
9065 + * the hardware directly
9066 + */
9067 + dwc_write_reg32(&global_regs->gintmsk, 0);
9068 +
9069 + /* 15 second delay per the test spec */
9070 + mdelay(15000);
9071 +
9072 + /* Send the Setup packet */
9073 + do_setup();
9074 +
9075 + /* 15 second delay so nothing else happens for awhile */
9076 + mdelay(15000);
9077 +
9078 + /* Restore interrupts */
9079 + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9080 + } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
9081 + /* Save current interrupt mask */
9082 + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9083 +
9084 + /* Disable all interrupts while we muck with
9085 + * the hardware directly
9086 + */
9087 + dwc_write_reg32(&global_regs->gintmsk, 0);
9088 +
9089 + /* Send the Setup packet */
9090 + do_setup();
9091 +
9092 + /* 15 second delay so nothing else happens for awhile */
9093 + mdelay(15000);
9094 +
9095 + /* Send the In and Ack packets */
9096 + do_in_ack();
9097 +
9098 + /* 15 second delay so nothing else happens for awhile */
9099 + mdelay(15000);
9100 +
9101 + /* Restore interrupts */
9102 + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9103 + }
9104 + }
9105 + break;
9106 + }
9107 +#endif /* DWC_HS_ELECT_TST */
9108 +
9109 + case USB_PORT_FEAT_INDICATOR:
9110 + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9111 + "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
9112 + /* Not supported */
9113 + break;
9114 + default:
9115 + retval = -EINVAL;
9116 + DWC_ERROR ("DWC OTG HCD - "
9117 + "SetPortFeature request %xh "
9118 + "unknown or unsupported\n", _wValue);
9119 + break;
9120 + }
9121 + break;
9122 + default:
9123 +error:
9124 + retval = -EINVAL;
9125 + DWC_WARN ("DWC OTG HCD - "
9126 + "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
9127 + _typeReq, _wIndex, _wValue);
9128 + break;
9129 + }
9130 +
9131 + return retval;
9132 +}
9133 +
9134 +
9135 +/**
9136 + * Assigns transactions from a QTD to a free host channel and initializes the
9137 + * host channel to perform the transactions. The host channel is removed from
9138 + * the free list.
9139 + *
9140 + * @param _hcd The HCD state structure.
9141 + * @param _qh Transactions from the first QTD for this QH are selected and
9142 + * assigned to a free host channel.
9143 + */
9144 +static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
9145 +{
9146 + dwc_hc_t *hc;
9147 + dwc_otg_qtd_t *qtd;
9148 + struct urb *urb;
9149 +
9150 + DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);
9151 +
9152 + hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
9153 +
9154 + /* Remove the host channel from the free list. */
9155 + list_del_init(&hc->hc_list_entry);
9156 +
9157 + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
9158 + urb = qtd->urb;
9159 + _qh->channel = hc;
9160 + _qh->qtd_in_process = qtd;
9161 +
9162 + /*
9163 + * Use usb_pipedevice to determine device address. This address is
9164 + * 0 before the SET_ADDRESS command and the correct address afterward.
9165 + */
9166 + hc->dev_addr = usb_pipedevice(urb->pipe);
9167 + hc->ep_num = usb_pipeendpoint(urb->pipe);
9168 +
9169 + if (urb->dev->speed == USB_SPEED_LOW) {
9170 + hc->speed = DWC_OTG_EP_SPEED_LOW;
9171 + } else if (urb->dev->speed == USB_SPEED_FULL) {
9172 + hc->speed = DWC_OTG_EP_SPEED_FULL;
9173 + } else {
9174 + hc->speed = DWC_OTG_EP_SPEED_HIGH;
9175 + }
9176 + hc->max_packet = dwc_max_packet(_qh->maxp);
9177 +
9178 + hc->xfer_started = 0;
9179 + hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
9180 + hc->error_state = (qtd->error_count > 0);
9181 + hc->halt_on_queue = 0;
9182 + hc->halt_pending = 0;
9183 + hc->requests = 0;
9184 +
9185 + /*
9186 + * The following values may be modified in the transfer type section
9187 + * below. The xfer_len value may be reduced when the transfer is
9188 + * started to accommodate the max widths of the XferSize and PktCnt
9189 + * fields in the HCTSIZn register.
9190 + */
9191 + hc->do_ping = _qh->ping_state;
9192 + hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
9193 + hc->data_pid_start = _qh->data_toggle;
9194 + hc->multi_count = 1;
9195 +
9196 + if (_hcd->core_if->dma_enable) {
9197 + hc->xfer_buff = (uint8_t *)(u32)urb->transfer_dma + urb->actual_length;
9198 + } else {
9199 + hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
9200 + }
9201 + hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
9202 + hc->xfer_count = 0;
9203 +
9204 + /*
9205 + * Set the split attributes
9206 + */
9207 + hc->do_split = 0;
9208 + if (_qh->do_split) {
9209 + hc->do_split = 1;
9210 + hc->xact_pos = qtd->isoc_split_pos;
9211 + hc->complete_split = qtd->complete_split;
9212 + hc->hub_addr = urb->dev->tt->hub->devnum;
9213 + hc->port_addr = urb->dev->ttport;
9214 + }
9215 +
9216 + switch (usb_pipetype(urb->pipe)) {
9217 + case PIPE_CONTROL:
9218 + hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
9219 + switch (qtd->control_phase) {
9220 + case DWC_OTG_CONTROL_SETUP:
9221 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
9222 + hc->do_ping = 0;
9223 + hc->ep_is_in = 0;
9224 + hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
9225 + if (_hcd->core_if->dma_enable) {
9226 + hc->xfer_buff = (uint8_t *)(u32)urb->setup_dma;
9227 + } else {
9228 + hc->xfer_buff = (uint8_t *)urb->setup_packet;
9229 + }
9230 + hc->xfer_len = 8;
9231 + break;
9232 + case DWC_OTG_CONTROL_DATA:
9233 + DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
9234 + hc->data_pid_start = qtd->data_toggle;
9235 + break;
9236 + case DWC_OTG_CONTROL_STATUS:
9237 + /*
9238 + * Direction is opposite of data direction or IN if no
9239 + * data.
9240 + */
9241 + DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
9242 + if (urb->transfer_buffer_length == 0) {
9243 + hc->ep_is_in = 1;
9244 + } else {
9245 + hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
9246 + }
9247 + if (hc->ep_is_in) {
9248 + hc->do_ping = 0;
9249 + }
9250 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
9251 + hc->xfer_len = 0;
9252 + if (_hcd->core_if->dma_enable) {
9253 + hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma;
9254 + } else {
9255 + hc->xfer_buff = (uint8_t *)_hcd->status_buf;
9256 + }
9257 + break;
9258 + }
9259 + break;
9260 + case PIPE_BULK:
9261 + hc->ep_type = DWC_OTG_EP_TYPE_BULK;
9262 + break;
9263 + case PIPE_INTERRUPT:
9264 + hc->ep_type = DWC_OTG_EP_TYPE_INTR;
9265 + break;
9266 + case PIPE_ISOCHRONOUS:
9267 + {
9268 + struct usb_iso_packet_descriptor *frame_desc;
9269 + frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
9270 + hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
9271 + if (_hcd->core_if->dma_enable) {
9272 + hc->xfer_buff = (uint8_t *)(u32)urb->transfer_dma;
9273 + } else {
9274 + hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
9275 + }
9276 + hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
9277 + hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
9278 +
9279 + if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
9280 + if (hc->xfer_len <= 188) {
9281 + hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
9282 + }
9283 + else {
9284 + hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
9285 + }
9286 + }
9287 + }
9288 + break;
9289 + }
9290 +
9291 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
9292 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
9293 + /*
9294 + * This value may be modified when the transfer is started to
9295 + * reflect the actual transfer length.
9296 + */
9297 + hc->multi_count = dwc_hb_mult(_qh->maxp);
9298 + }
9299 +
9300 + dwc_otg_hc_init(_hcd->core_if, hc);
9301 + hc->qh = _qh;
9302 +}
9303 +#define DEBUG_HOST_CHANNELS
9304 +#ifdef DEBUG_HOST_CHANNELS
9305 +static int last_sel_trans_num_per_scheduled = 0;
9306 +module_param(last_sel_trans_num_per_scheduled, int, 0444);
9307 +
9308 +static int last_sel_trans_num_nonper_scheduled = 0;
9309 +module_param(last_sel_trans_num_nonper_scheduled, int, 0444);
9310 +
9311 +static int last_sel_trans_num_avail_hc_at_start = 0;
9312 +module_param(last_sel_trans_num_avail_hc_at_start, int, 0444);
9313 +
9314 +static int last_sel_trans_num_avail_hc_at_end = 0;
9315 +module_param(last_sel_trans_num_avail_hc_at_end, int, 0444);
9316 +#endif /* DEBUG_HOST_CHANNELS */
9317 +
9318 +/**
9319 + * This function selects transactions from the HCD transfer schedule and
9320 + * assigns them to available host channels. It is called from HCD interrupt
9321 + * handler functions.
9322 + *
9323 + * @param _hcd The HCD state structure.
9324 + *
9325 + * @return The types of new transactions that were assigned to host channels.
9326 + */
9327 +dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd)
9328 +{
9329 + struct list_head *qh_ptr;
9330 + dwc_otg_qh_t *qh;
9331 + int num_channels;
9332 + unsigned long flags;
9333 + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
9334 +
9335 +#ifdef DEBUG_SOF
9336 + DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
9337 +#endif /* */
9338 +
9339 +#ifdef DEBUG_HOST_CHANNELS
9340 + last_sel_trans_num_per_scheduled = 0;
9341 + last_sel_trans_num_nonper_scheduled = 0;
9342 + last_sel_trans_num_avail_hc_at_start = _hcd->available_host_channels;
9343 +#endif /* DEBUG_HOST_CHANNELS */
9344 +
9345 + /* Process entries in the periodic ready list. */
9346 + num_channels = _hcd->core_if->core_params->host_channels;
9347 + qh_ptr = _hcd->periodic_sched_ready.next;
9348 + while (qh_ptr != &_hcd->periodic_sched_ready
9349 + && !list_empty(&_hcd->free_hc_list)) {
9350 +
9351 + // Make sure we leave one channel for non periodic transactions.
9352 + local_irq_save(flags);
9353 + if (_hcd->available_host_channels <= 1) {
9354 + local_irq_restore(flags);
9355 + break;
9356 + }
9357 + _hcd->available_host_channels--;
9358 + local_irq_restore(flags);
9359 +#ifdef DEBUG_HOST_CHANNELS
9360 + last_sel_trans_num_per_scheduled++;
9361 +#endif /* DEBUG_HOST_CHANNELS */
9362 +
9363 + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
9364 + assign_and_init_hc(_hcd, qh);
9365 +
9366 + /*
9367 + * Move the QH from the periodic ready schedule to the
9368 + * periodic assigned schedule.
9369 + */
9370 + qh_ptr = qh_ptr->next;
9371 + local_irq_save(flags);
9372 + list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
9373 + local_irq_restore(flags);
9374 + ret_val = DWC_OTG_TRANSACTION_PERIODIC;
9375 + }
9376 +
9377 + /*
9378 + * Process entries in the deferred portion of the non-periodic list.
9379 + * A NAK put them here and, at the right time, they need to be
9380 + * placed on the sched_inactive list.
9381 + */
9382 + qh_ptr = _hcd->non_periodic_sched_deferred.next;
9383 + while (qh_ptr != &_hcd->non_periodic_sched_deferred) {
9384 + uint16_t frame_number =
9385 + dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
9386 + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
9387 + qh_ptr = qh_ptr->next;
9388 +
9389 + if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
9390 + // NAK did this
9391 + /*
9392 + * Move the QH from the non periodic deferred schedule to
9393 + * the non periodic inactive schedule.
9394 + */
9395 + local_irq_save(flags);
9396 + list_move(&qh->qh_list_entry,
9397 + &_hcd->non_periodic_sched_inactive);
9398 + local_irq_restore(flags);
9399 + }
9400 + }
9401 +
9402 + /*
9403 + * Process entries in the inactive portion of the non-periodic
9404 + * schedule. Some free host channels may not be used if they are
9405 + * reserved for periodic transfers.
9406 + */
9407 + qh_ptr = _hcd->non_periodic_sched_inactive.next;
9408 + num_channels = _hcd->core_if->core_params->host_channels;
9409 + while (qh_ptr != &_hcd->non_periodic_sched_inactive
9410 + && !list_empty(&_hcd->free_hc_list)) {
9411 +
9412 + local_irq_save(flags);
9413 + if (_hcd->available_host_channels < 1) {
9414 + local_irq_restore(flags);
9415 + break;
9416 + }
9417 + _hcd->available_host_channels--;
9418 + local_irq_restore(flags);
9419 +#ifdef DEBUG_HOST_CHANNELS
9420 + last_sel_trans_num_nonper_scheduled++;
9421 +#endif /* DEBUG_HOST_CHANNELS */
9422 +
9423 + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
9424 + assign_and_init_hc(_hcd, qh);
9425 +
9426 + /*
9427 + * Move the QH from the non-periodic inactive schedule to the
9428 + * non-periodic active schedule.
9429 + */
9430 + qh_ptr = qh_ptr->next;
9431 + local_irq_save(flags);
9432 + list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
9433 + local_irq_restore(flags);
9434 +
9435 + if (ret_val == DWC_OTG_TRANSACTION_NONE) {
9436 + ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
9437 + } else {
9438 + ret_val = DWC_OTG_TRANSACTION_ALL;
9439 + }
9440 +
9441 + }
9442 +#ifdef DEBUG_HOST_CHANNELS
9443 + last_sel_trans_num_avail_hc_at_end = _hcd->available_host_channels;
9444 +#endif /* DEBUG_HOST_CHANNELS */
9445 +
9446 + return ret_val;
9447 +}
9448 +
9449 +/**
9450 + * Attempts to queue a single transaction request for a host channel
9451 + * associated with either a periodic or non-periodic transfer. This function
9452 + * assumes that there is space available in the appropriate request queue. For
9453 + * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
9454 + * is available in the appropriate Tx FIFO.
9455 + *
9456 + * @param _hcd The HCD state structure.
9457 + * @param _hc Host channel descriptor associated with either a periodic or
9458 + * non-periodic transfer.
9459 + * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx
9460 + * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
9461 + * transfers.
9462 + *
9463 + * @return 1 if a request is queued and more requests may be needed to
9464 + * complete the transfer, 0 if no more requests are required for this
9465 + * transfer, -1 if there is insufficient space in the Tx FIFO.
9466 + */
9467 +static int queue_transaction(dwc_otg_hcd_t *_hcd,
9468 + dwc_hc_t *_hc,
9469 + uint16_t _fifo_dwords_avail)
9470 +{
9471 + int retval;
9472 +
9473 + if (_hcd->core_if->dma_enable) {
9474 + if (!_hc->xfer_started) {
9475 + dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
9476 + _hc->qh->ping_state = 0;
9477 + }
9478 + retval = 0;
9479 + } else if (_hc->halt_pending) {
9480 + /* Don't queue a request if the channel has been halted. */
9481 + retval = 0;
9482 + } else if (_hc->halt_on_queue) {
9483 + dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status);
9484 + retval = 0;
9485 + } else if (_hc->do_ping) {
9486 + if (!_hc->xfer_started) {
9487 + dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
9488 + }
9489 + retval = 0;
9490 + } else if (!_hc->ep_is_in ||
9491 + _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
9492 + if ((_fifo_dwords_avail * 4) >= _hc->max_packet) {
9493 + if (!_hc->xfer_started) {
9494 + dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
9495 + retval = 1;
9496 + } else {
9497 + retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
9498 + }
9499 + } else {
9500 + retval = -1;
9501 + }
9502 + } else {
9503 + if (!_hc->xfer_started) {
9504 + dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
9505 + retval = 1;
9506 + } else {
9507 + retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
9508 + }
9509 + }
9510 +
9511 + return retval;
9512 +}
9513 +
9514 +/**
9515 + * Processes active non-periodic channels and queues transactions for these
9516 + * channels to the DWC_otg controller. After queueing transactions, the NP Tx
9517 + * FIFO Empty interrupt is enabled if there are more transactions to queue as
9518 + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
9519 + * FIFO Empty interrupt is disabled.
9520 + */
9521 +static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd)
9522 +{
9523 + gnptxsts_data_t tx_status;
9524 + struct list_head *orig_qh_ptr;
9525 + dwc_otg_qh_t *qh;
9526 + int status;
9527 + int no_queue_space = 0;
9528 + int no_fifo_space = 0;
9529 + int more_to_do = 0;
9530 +
9531 + dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;
9532 +
9533 + DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
9534 +#ifdef DEBUG
9535 + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
9536 + DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n",
9537 + tx_status.b.nptxqspcavail);
9538 + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
9539 + tx_status.b.nptxfspcavail);
9540 +#endif
9541 + /*
9542 + * Keep track of the starting point. Skip over the start-of-list
9543 + * entry.
9544 + */
9545 + if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
9546 + _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
9547 + }
9548 + orig_qh_ptr = _hcd->non_periodic_qh_ptr;
9549 +
9550 + /*
9551 + * Process once through the active list or until no more space is
9552 + * available in the request queue or the Tx FIFO.
9553 + */
9554 + do {
9555 + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
9556 + if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
9557 + no_queue_space = 1;
9558 + break;
9559 + }
9560 +
9561 + qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
9562 + status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail);
9563 +
9564 + if (status > 0) {
9565 + more_to_do = 1;
9566 + } else if (status < 0) {
9567 + no_fifo_space = 1;
9568 + break;
9569 + }
9570 +
9571 + /* Advance to next QH, skipping start-of-list entry. */
9572 + _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
9573 + if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
9574 + _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
9575 + }
9576 +
9577 + } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr);
9578 +
9579 + if (!_hcd->core_if->dma_enable) {
9580 + gintmsk_data_t intr_mask = {.d32 = 0};
9581 + intr_mask.b.nptxfempty = 1;
9582 +
9583 +#ifdef DEBUG
9584 + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
9585 + DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n",
9586 + tx_status.b.nptxqspcavail);
9587 + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n",
9588 + tx_status.b.nptxfspcavail);
9589 +#endif
9590 + if (more_to_do || no_queue_space || no_fifo_space) {
9591 + /*
9592 + * May need to queue more transactions as the request
9593 + * queue or Tx FIFO empties. Enable the non-periodic
9594 + * Tx FIFO empty interrupt. (Always use the half-empty
9595 + * level to ensure that new requests are loaded as
9596 + * soon as possible.)
9597 + */
9598 + dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
9599 + } else {
9600 + /*
9601 + * Disable the Tx FIFO empty interrupt since there are
9602 + * no more transactions that need to be queued right
9603 + * now. This function is called from interrupt
9604 + * handlers to queue more transactions as transfer
9605 + * states change.
9606 + */
9607 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
9608 + }
9609 + }
9610 +}
9611 +
9612 +/**
9613 + * Processes periodic channels for the next frame and queues transactions for
9614 + * these channels to the DWC_otg controller. After queueing transactions, the
9615 + * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
9616 + * to queue as Periodic Tx FIFO or request queue space becomes available.
9617 + * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
9618 + */
9619 +static void process_periodic_channels(dwc_otg_hcd_t *_hcd)
9620 +{
9621 + hptxsts_data_t tx_status;
9622 + struct list_head *qh_ptr;
9623 + dwc_otg_qh_t *qh;
9624 + int status;
9625 + int no_queue_space = 0;
9626 + int no_fifo_space = 0;
9627 +
9628 + dwc_otg_host_global_regs_t *host_regs;
9629 + host_regs = _hcd->core_if->host_if->host_global_regs;
9630 +
9631 + DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
9632 +#ifdef DEBUG
9633 + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
9634 + DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n",
9635 + tx_status.b.ptxqspcavail);
9636 + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
9637 + tx_status.b.ptxfspcavail);
9638 +#endif
9639 +
9640 + qh_ptr = _hcd->periodic_sched_assigned.next;
9641 + while (qh_ptr != &_hcd->periodic_sched_assigned) {
9642 + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
9643 + if (tx_status.b.ptxqspcavail == 0) {
9644 + no_queue_space = 1;
9645 + break;
9646 + }
9647 +
9648 + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
9649 +
9650 + /*
9651 + * Set a flag if we're queuing high-bandwidth in slave mode.
9652 + * The flag prevents any halts to get into the request queue in
9653 + * the middle of multiple high-bandwidth packets getting queued.
9654 + */
9655 + if ((!_hcd->core_if->dma_enable) &&
9656 + (qh->channel->multi_count > 1))
9657 + {
9658 + _hcd->core_if->queuing_high_bandwidth = 1;
9659 + }
9660 +
9661 + status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail);
9662 + if (status < 0) {
9663 + no_fifo_space = 1;
9664 + break;
9665 + }
9666 +
9667 + /*
9668 + * In Slave mode, stay on the current transfer until there is
9669 + * nothing more to do or the high-bandwidth request count is
9670 + * reached. In DMA mode, only need to queue one request. The
9671 + * controller automatically handles multiple packets for
9672 + * high-bandwidth transfers.
9673 + */
9674 + if (_hcd->core_if->dma_enable ||
9675 + (status == 0 ||
9676 + qh->channel->requests == qh->channel->multi_count)) {
9677 + qh_ptr = qh_ptr->next;
9678 + /*
9679 + * Move the QH from the periodic assigned schedule to
9680 + * the periodic queued schedule.
9681 + */
9682 + list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
9683 +
9684 + /* done queuing high bandwidth */
9685 + _hcd->core_if->queuing_high_bandwidth = 0;
9686 + }
9687 + }
9688 +
9689 + if (!_hcd->core_if->dma_enable) {
9690 + dwc_otg_core_global_regs_t *global_regs;
9691 + gintmsk_data_t intr_mask = {.d32 = 0};
9692 +
9693 + global_regs = _hcd->core_if->core_global_regs;
9694 + intr_mask.b.ptxfempty = 1;
9695 +#ifdef DEBUG
9696 + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
9697 + DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n",
9698 + tx_status.b.ptxqspcavail);
9699 + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n",
9700 + tx_status.b.ptxfspcavail);
9701 +#endif
9702 + if (!(list_empty(&_hcd->periodic_sched_assigned)) ||
9703 + no_queue_space || no_fifo_space) {
9704 + /*
9705 + * May need to queue more transactions as the request
9706 + * queue or Tx FIFO empties. Enable the periodic Tx
9707 + * FIFO empty interrupt. (Always use the half-empty
9708 + * level to ensure that new requests are loaded as
9709 + * soon as possible.)
9710 + */
9711 + dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
9712 + } else {
9713 + /*
9714 + * Disable the Tx FIFO empty interrupt since there are
9715 + * no more transactions that need to be queued right
9716 + * now. This function is called from interrupt
9717 + * handlers to queue more transactions as transfer
9718 + * states change.
9719 + */
9720 + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
9721 + }
9722 + }
9723 +}
9724 +
9725 +/**
9726 + * This function processes the currently active host channels and queues
9727 + * transactions for these channels to the DWC_otg controller. It is called
9728 + * from HCD interrupt handler functions.
9729 + *
9730 + * @param _hcd The HCD state structure.
9731 + * @param _tr_type The type(s) of transactions to queue (non-periodic,
9732 + * periodic, or both).
9733 + */
9734 +void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
9735 + dwc_otg_transaction_type_e _tr_type)
9736 +{
9737 +#ifdef DEBUG_SOF
9738 + DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
9739 +#endif
9740 + /* Process host channels associated with periodic transfers. */
9741 + if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
9742 + _tr_type == DWC_OTG_TRANSACTION_ALL) &&
9743 + !list_empty(&_hcd->periodic_sched_assigned)) {
9744 +
9745 + process_periodic_channels(_hcd);
9746 + }
9747 +
9748 + /* Process host channels associated with non-periodic transfers. */
9749 + if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
9750 + _tr_type == DWC_OTG_TRANSACTION_ALL)) {
9751 + if (!list_empty(&_hcd->non_periodic_sched_active)) {
9752 + process_non_periodic_channels(_hcd);
9753 + } else {
9754 + /*
9755 + * Ensure NP Tx FIFO empty interrupt is disabled when
9756 + * there are no non-periodic transfers to process.
9757 + */
9758 + gintmsk_data_t gintmsk = {.d32 = 0};
9759 + gintmsk.b.nptxfempty = 1;
9760 + dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
9761 + }
9762 + }
9763 +}
9764 +
9765 +/**
9766 + * Sets the final status of an URB and returns it to the device driver. Any
9767 + * required cleanup of the URB is performed.
9768 + */
9769 +void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb,
9770 + int _status)
9771 + __releases(_hcd->lock)
9772 +__acquires(_hcd->lock)
9773 +{
9774 +#ifdef DEBUG
9775 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
9776 + DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
9777 + __func__, _urb, usb_pipedevice(_urb->pipe),
9778 + usb_pipeendpoint(_urb->pipe),
9779 + usb_pipein(_urb->pipe) ? "IN" : "OUT", _status);
9780 + if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
9781 + int i;
9782 + for (i = 0; i < _urb->number_of_packets; i++) {
9783 + DWC_PRINT(" ISO Desc %d status: %d\n",
9784 + i, _urb->iso_frame_desc[i].status);
9785 + }
9786 + }
9787 + }
9788 +#endif
9789 +
9790 + _urb->status = _status;
9791 + _urb->hcpriv = NULL;
9792 + usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb);
9793 + spin_unlock(&_hcd->lock);
9794 + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
9795 + spin_lock(&_hcd->lock);
9796 +}
9797 +
9798 +/*
9799 + * Returns the Queue Head for an URB.
9800 + */
9801 +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb)
9802 +{
9803 + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
9804 + return (dwc_otg_qh_t *)ep->hcpriv;
9805 +}
9806 +
9807 +#ifdef DEBUG
9808 +void dwc_print_setup_data (uint8_t *setup)
9809 +{
9810 + int i;
9811 + if (CHK_DEBUG_LEVEL(DBG_HCD)){
9812 + DWC_PRINT("Setup Data = MSB ");
9813 + for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]);
9814 + DWC_PRINT("\n");
9815 + DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device");
9816 + DWC_PRINT(" bmRequestType Type = ");
9817 + switch ((setup[0]&0x60) >> 5) {
9818 + case 0: DWC_PRINT("Standard\n"); break;
9819 + case 1: DWC_PRINT("Class\n"); break;
9820 + case 2: DWC_PRINT("Vendor\n"); break;
9821 + case 3: DWC_PRINT("Reserved\n"); break;
9822 + }
9823 + DWC_PRINT(" bmRequestType Recipient = ");
9824 + switch (setup[0]&0x1f) {
9825 + case 0: DWC_PRINT("Device\n"); break;
9826 + case 1: DWC_PRINT("Interface\n"); break;
9827 + case 2: DWC_PRINT("Endpoint\n"); break;
9828 + case 3: DWC_PRINT("Other\n"); break;
9829 + default: DWC_PRINT("Reserved\n"); break;
9830 + }
9831 + DWC_PRINT(" bRequest = 0x%0x\n", setup[1]);
9832 + DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
9833 + DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
9834 + DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
9835 + }
9836 +}
9837 +#endif
9838 +
9839 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) {
9840 +#ifdef DEBUG
9841 +#if 0
9842 + DWC_PRINT("Frame remaining at SOF:\n");
9843 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9844 + _hcd->frrem_samples, _hcd->frrem_accum,
9845 + (_hcd->frrem_samples > 0) ?
9846 + _hcd->frrem_accum/_hcd->frrem_samples : 0);
9847 +
9848 + DWC_PRINT("\n");
9849 + DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
9850 + DWC_PRINT(" samples %u, accum %u, avg %u\n",
9851 + _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,
9852 + (_hcd->core_if->hfnum_7_samples > 0) ?
9853 + _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);
9854 + DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
9855 + DWC_PRINT(" samples %u, accum %u, avg %u\n",
9856 + _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,
9857 + (_hcd->core_if->hfnum_0_samples > 0) ?
9858 + _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);
9859 + DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
9860 + DWC_PRINT(" samples %u, accum %u, avg %u\n",
9861 + _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,
9862 + (_hcd->core_if->hfnum_other_samples > 0) ?
9863 + _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);
9864 +
9865 + DWC_PRINT("\n");
9866 + DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
9867 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9868 + _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,
9869 + (_hcd->hfnum_7_samples_a > 0) ?
9870 + _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);
9871 + DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
9872 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9873 + _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,
9874 + (_hcd->hfnum_0_samples_a > 0) ?
9875 + _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);
9876 + DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
9877 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9878 + _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,
9879 + (_hcd->hfnum_other_samples_a > 0) ?
9880 + _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);
9881 +
9882 + DWC_PRINT("\n");
9883 + DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
9884 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9885 + _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,
9886 + (_hcd->hfnum_7_samples_b > 0) ?
9887 + _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);
9888 + DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
9889 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9890 + _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,
9891 + (_hcd->hfnum_0_samples_b > 0) ?
9892 + _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);
9893 + DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
9894 + DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9895 + _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,
9896 + (_hcd->hfnum_other_samples_b > 0) ?
9897 + _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);
9898 +#endif
9899 +#endif
9900 +}
9901 +
9902 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd)
9903 +{
9904 +#ifdef DEBUG
9905 + int num_channels;
9906 + int i;
9907 + gnptxsts_data_t np_tx_status;
9908 + hptxsts_data_t p_tx_status;
9909 +
9910 + num_channels = _hcd->core_if->core_params->host_channels;
9911 + DWC_PRINT("\n");
9912 + DWC_PRINT("************************************************************\n");
9913 + DWC_PRINT("HCD State:\n");
9914 + DWC_PRINT(" Num channels: %d\n", num_channels);
9915 + for (i = 0; i < num_channels; i++) {
9916 + dwc_hc_t *hc = _hcd->hc_ptr_array[i];
9917 + DWC_PRINT(" Channel %d:\n", i);
9918 + DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
9919 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
9920 + DWC_PRINT(" speed: %d\n", hc->speed);
9921 + DWC_PRINT(" ep_type: %d\n", hc->ep_type);
9922 + DWC_PRINT(" max_packet: %d\n", hc->max_packet);
9923 + DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
9924 + DWC_PRINT(" multi_count: %d\n", hc->multi_count);
9925 + DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
9926 + DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
9927 + DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
9928 + DWC_PRINT(" xfer_count: %d\n", hc->xfer_count);
9929 + DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue);
9930 + DWC_PRINT(" halt_pending: %d\n", hc->halt_pending);
9931 + DWC_PRINT(" halt_status: %d\n", hc->halt_status);
9932 + DWC_PRINT(" do_split: %d\n", hc->do_split);
9933 + DWC_PRINT(" complete_split: %d\n", hc->complete_split);
9934 + DWC_PRINT(" hub_addr: %d\n", hc->hub_addr);
9935 + DWC_PRINT(" port_addr: %d\n", hc->port_addr);
9936 + DWC_PRINT(" xact_pos: %d\n", hc->xact_pos);
9937 + DWC_PRINT(" requests: %d\n", hc->requests);
9938 + DWC_PRINT(" qh: %p\n", hc->qh);
9939 + if (hc->xfer_started) {
9940 + hfnum_data_t hfnum;
9941 + hcchar_data_t hcchar;
9942 + hctsiz_data_t hctsiz;
9943 + hcint_data_t hcint;
9944 + hcintmsk_data_t hcintmsk;
9945 + hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
9946 + hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar);
9947 + hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz);
9948 + hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint);
9949 + hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk);
9950 + DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32);
9951 + DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32);
9952 + DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32);
9953 + DWC_PRINT(" hcint: 0x%08x\n", hcint.d32);
9954 + DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32);
9955 + }
9956 + if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {
9957 + dwc_otg_qtd_t *qtd;
9958 + struct urb *urb;
9959 + qtd = hc->qh->qtd_in_process;
9960 + urb = qtd->urb;
9961 + DWC_PRINT(" URB Info:\n");
9962 + DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb);
9963 + if (urb != NULL) {
9964 + DWC_PRINT(" Dev: %d, EP: %d %s\n",
9965 + usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
9966 + usb_pipein(urb->pipe) ? "IN" : "OUT");
9967 + DWC_PRINT(" Max packet size: %d\n",
9968 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
9969 + DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer);
9970 + DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma);
9971 + DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length);
9972 + DWC_PRINT(" actual_length: %d\n", urb->actual_length);
9973 + }
9974 + }
9975 + }
9976 + //DWC_PRINT(" non_periodic_channels: %d\n", _hcd->non_periodic_channels);
9977 + //DWC_PRINT(" periodic_channels: %d\n", _hcd->periodic_channels);
9978 + DWC_PRINT(" available_channels: %d\n", _hcd->available_host_channels);
9979 + DWC_PRINT(" periodic_usecs: %d\n", _hcd->periodic_usecs);
9980 + np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts);
9981 + DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
9982 + DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
9983 + p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts);
9984 + DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
9985 + DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
9986 + dwc_otg_hcd_dump_frrem(_hcd);
9987 + dwc_otg_dump_global_registers(_hcd->core_if);
9988 + dwc_otg_dump_host_registers(_hcd->core_if);
9989 + DWC_PRINT("************************************************************\n");
9990 + DWC_PRINT("\n");
9991 +#endif
9992 +}
9993 +#endif /* DWC_DEVICE_ONLY */
9994 --- /dev/null
9995 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd.h
9996 @@ -0,0 +1,676 @@
9997 +/* ==========================================================================
9998 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.h $
9999 + * $Revision: 1.1.1.1 $
10000 + * $Date: 2009-04-17 06:15:34 $
10001 + * $Change: 537387 $
10002 + *
10003 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
10004 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
10005 + * otherwise expressly agreed to in writing between Synopsys and you.
10006 + *
10007 + * The Software IS NOT an item of Licensed Software or Licensed Product under
10008 + * any End User Software License Agreement or Agreement for Licensed Product
10009 + * with Synopsys or any supplement thereto. You are permitted to use and
10010 + * redistribute this Software in source and binary forms, with or without
10011 + * modification, provided that redistributions of source code must retain this
10012 + * notice. You may not view, use, disclose, copy or distribute this file or
10013 + * any information contained herein except pursuant to this license grant from
10014 + * Synopsys. If you do not agree with this notice, including the disclaimer
10015 + * below, then you are not authorized to use the Software.
10016 + *
10017 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
10018 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10019 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10020 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
10021 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10022 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
10023 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
10024 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
10025 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
10026 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10027 + * DAMAGE.
10028 + * ========================================================================== */
10029 +#ifndef DWC_DEVICE_ONLY
10030 +#if !defined(__DWC_HCD_H__)
10031 +#define __DWC_HCD_H__
10032 +
10033 +#include <linux/list.h>
10034 +#include <linux/usb.h>
10035 +#include <linux/usb/hcd.h>
10036 +
10037 +struct lm_device;
10038 +struct dwc_otg_device;
10039 +
10040 +#include "dwc_otg_cil.h"
10041 +//#include "dwc_otg_ifx.h" // winder
10042 +
10043 +
10044 +/**
10045 + * @file
10046 + *
10047 + * This file contains the structures, constants, and interfaces for
10048 + * the Host Contoller Driver (HCD).
10049 + *
10050 + * The Host Controller Driver (HCD) is responsible for translating requests
10051 + * from the USB Driver into the appropriate actions on the DWC_otg controller.
10052 + * It isolates the USBD from the specifics of the controller by providing an
10053 + * API to the USBD.
10054 + */
10055 +
10056 +/**
10057 + * Phases for control transfers.
10058 + */
10059 +typedef enum dwc_otg_control_phase {
10060 + DWC_OTG_CONTROL_SETUP,
10061 + DWC_OTG_CONTROL_DATA,
10062 + DWC_OTG_CONTROL_STATUS
10063 +} dwc_otg_control_phase_e;
10064 +
10065 +/** Transaction types. */
10066 +typedef enum dwc_otg_transaction_type {
10067 + DWC_OTG_TRANSACTION_NONE,
10068 + DWC_OTG_TRANSACTION_PERIODIC,
10069 + DWC_OTG_TRANSACTION_NON_PERIODIC,
10070 + DWC_OTG_TRANSACTION_ALL
10071 +} dwc_otg_transaction_type_e;
10072 +
10073 +/**
10074 + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
10075 + * interrupt, or isochronous transfer. A single QTD is created for each URB
10076 + * (of one of these types) submitted to the HCD. The transfer associated with
10077 + * a QTD may require one or multiple transactions.
10078 + *
10079 + * A QTD is linked to a Queue Head, which is entered in either the
10080 + * non-periodic or periodic schedule for execution. When a QTD is chosen for
10081 + * execution, some or all of its transactions may be executed. After
10082 + * execution, the state of the QTD is updated. The QTD may be retired if all
10083 + * its transactions are complete or if an error occurred. Otherwise, it
10084 + * remains in the schedule so more transactions can be executed later.
10085 + */
10086 +struct dwc_otg_qh;
10087 +typedef struct dwc_otg_qtd {
10088 + /**
10089 + * Determines the PID of the next data packet for the data phase of
10090 + * control transfers. Ignored for other transfer types.<br>
10091 + * One of the following values:
10092 + * - DWC_OTG_HC_PID_DATA0
10093 + * - DWC_OTG_HC_PID_DATA1
10094 + */
10095 + uint8_t data_toggle;
10096 +
10097 + /** Current phase for control transfers (Setup, Data, or Status). */
10098 + dwc_otg_control_phase_e control_phase;
10099 +
10100 + /** Keep track of the current split type
10101 + * for FS/LS endpoints on a HS Hub */
10102 + uint8_t complete_split;
10103 +
10104 + /** How many bytes transferred during SSPLIT OUT */
10105 + uint32_t ssplit_out_xfer_count;
10106 +
10107 + /**
10108 + * Holds the number of bus errors that have occurred for a transaction
10109 + * within this transfer.
10110 + */
10111 + uint8_t error_count;
10112 +
10113 + /**
10114 + * Index of the next frame descriptor for an isochronous transfer. A
10115 + * frame descriptor describes the buffer position and length of the
10116 + * data to be transferred in the next scheduled (micro)frame of an
10117 + * isochronous transfer. It also holds status for that transaction.
10118 + * The frame index starts at 0.
10119 + */
10120 + int isoc_frame_index;
10121 +
10122 + /** Position of the ISOC split on full/low speed */
10123 + uint8_t isoc_split_pos;
10124 +
10125 + /** Position of the ISOC split in the buffer for the current frame */
10126 + uint16_t isoc_split_offset;
10127 +
10128 + /** URB for this transfer */
10129 + struct urb *urb;
10130 +
10131 + /** This list of QTDs */
10132 + struct list_head qtd_list_entry;
10133 +
10134 + /* Field to track the qh pointer */
10135 + struct dwc_otg_qh *qtd_qh_ptr;
10136 +} dwc_otg_qtd_t;
10137 +
10138 +/**
10139 + * A Queue Head (QH) holds the static characteristics of an endpoint and
10140 + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
10141 + * be entered in either the non-periodic or periodic schedule.
10142 + */
10143 +typedef struct dwc_otg_qh {
10144 + /**
10145 + * Endpoint type.
10146 + * One of the following values:
10147 + * - USB_ENDPOINT_XFER_CONTROL
10148 + * - USB_ENDPOINT_XFER_ISOC
10149 + * - USB_ENDPOINT_XFER_BULK
10150 + * - USB_ENDPOINT_XFER_INT
10151 + */
10152 + uint8_t ep_type;
10153 + uint8_t ep_is_in;
10154 +
10155 + /** wMaxPacketSize Field of Endpoint Descriptor. */
10156 + uint16_t maxp;
10157 +
10158 + /**
10159 + * Determines the PID of the next data packet for non-control
10160 + * transfers. Ignored for control transfers.<br>
10161 + * One of the following values:
10162 + * - DWC_OTG_HC_PID_DATA0
10163 + * - DWC_OTG_HC_PID_DATA1
10164 + */
10165 + uint8_t data_toggle;
10166 +
10167 + /** Ping state if 1. */
10168 + uint8_t ping_state;
10169 +
10170 + /**
10171 + * List of QTDs for this QH.
10172 + */
10173 + struct list_head qtd_list;
10174 +
10175 + /** Host channel currently processing transfers for this QH. */
10176 + dwc_hc_t *channel;
10177 +
10178 + /** QTD currently assigned to a host channel for this QH. */
10179 + dwc_otg_qtd_t *qtd_in_process;
10180 +
10181 + /** Full/low speed endpoint on high-speed hub requires split. */
10182 + uint8_t do_split;
10183 +
10184 + /** @name Periodic schedule information */
10185 + /** @{ */
10186 +
10187 + /** Bandwidth in microseconds per (micro)frame. */
10188 + uint8_t usecs;
10189 +
10190 + /** Interval between transfers in (micro)frames. */
10191 + uint16_t interval;
10192 +
10193 + /**
10194 + * (micro)frame to initialize a periodic transfer. The transfer
10195 + * executes in the following (micro)frame.
10196 + */
10197 + uint16_t sched_frame;
10198 +
10199 + /** (micro)frame at which last start split was initialized. */
10200 + uint16_t start_split_frame;
10201 +
10202 + /** @} */
10203 +
10204 + uint16_t speed;
10205 + uint16_t frame_usecs[8];
10206 + /** Entry for QH in either the periodic or non-periodic schedule. */
10207 + struct list_head qh_list_entry;
10208 +} dwc_otg_qh_t;
10209 +
10210 +/**
10211 + * This structure holds the state of the HCD, including the non-periodic and
10212 + * periodic schedules.
10213 + */
10214 +typedef struct dwc_otg_hcd {
10215 + spinlock_t lock;
10216 +
10217 + /** DWC OTG Core Interface Layer */
10218 + dwc_otg_core_if_t *core_if;
10219 +
10220 + /** Internal DWC HCD Flags */
10221 + volatile union dwc_otg_hcd_internal_flags {
10222 + uint32_t d32;
10223 + struct {
10224 + unsigned port_connect_status_change : 1;
10225 + unsigned port_connect_status : 1;
10226 + unsigned port_reset_change : 1;
10227 + unsigned port_enable_change : 1;
10228 + unsigned port_suspend_change : 1;
10229 + unsigned port_over_current_change : 1;
10230 + unsigned reserved : 27;
10231 + } b;
10232 + } flags;
10233 +
10234 + /**
10235 + * Inactive items in the non-periodic schedule. This is a list of
10236 + * Queue Heads. Transfers associated with these Queue Heads are not
10237 + * currently assigned to a host channel.
10238 + */
10239 + struct list_head non_periodic_sched_inactive;
10240 +
10241 + /**
10242 + * Deferred items in the non-periodic schedule. This is a list of
10243 + * Queue Heads. Transfers associated with these Queue Heads are not
10244 + * currently assigned to a host channel.
10245 + * When we get an NAK, the QH goes here.
10246 + */
10247 + struct list_head non_periodic_sched_deferred;
10248 +
10249 + /**
10250 + * Active items in the non-periodic schedule. This is a list of
10251 + * Queue Heads. Transfers associated with these Queue Heads are
10252 + * currently assigned to a host channel.
10253 + */
10254 + struct list_head non_periodic_sched_active;
10255 +
10256 + /**
10257 + * Pointer to the next Queue Head to process in the active
10258 + * non-periodic schedule.
10259 + */
10260 + struct list_head *non_periodic_qh_ptr;
10261 +
10262 + /**
10263 + * Inactive items in the periodic schedule. This is a list of QHs for
10264 + * periodic transfers that are _not_ scheduled for the next frame.
10265 + * Each QH in the list has an interval counter that determines when it
10266 + * needs to be scheduled for execution. This scheduling mechanism
10267 + * allows only a simple calculation for periodic bandwidth used (i.e.
10268 + * must assume that all periodic transfers may need to execute in the
10269 + * same frame). However, it greatly simplifies scheduling and should
10270 + * be sufficient for the vast majority of OTG hosts, which need to
10271 + * connect to a small number of peripherals at one time.
10272 + *
10273 + * Items move from this list to periodic_sched_ready when the QH
10274 + * interval counter is 0 at SOF.
10275 + */
10276 + struct list_head periodic_sched_inactive;
10277 +
10278 + /**
10279 + * List of periodic QHs that are ready for execution in the next
10280 + * frame, but have not yet been assigned to host channels.
10281 + *
10282 + * Items move from this list to periodic_sched_assigned as host
10283 + * channels become available during the current frame.
10284 + */
10285 + struct list_head periodic_sched_ready;
10286 +
10287 + /**
10288 + * List of periodic QHs to be executed in the next frame that are
10289 + * assigned to host channels.
10290 + *
10291 + * Items move from this list to periodic_sched_queued as the
10292 + * transactions for the QH are queued to the DWC_otg controller.
10293 + */
10294 + struct list_head periodic_sched_assigned;
10295 +
10296 + /**
10297 + * List of periodic QHs that have been queued for execution.
10298 + *
10299 + * Items move from this list to either periodic_sched_inactive or
10300 + * periodic_sched_ready when the channel associated with the transfer
10301 + * is released. If the interval for the QH is 1, the item moves to
10302 + * periodic_sched_ready because it must be rescheduled for the next
10303 + * frame. Otherwise, the item moves to periodic_sched_inactive.
10304 + */
10305 + struct list_head periodic_sched_queued;
10306 +
10307 + /**
10308 + * Total bandwidth claimed so far for periodic transfers. This value
10309 + * is in microseconds per (micro)frame. The assumption is that all
10310 + * periodic transfers may occur in the same (micro)frame.
10311 + */
10312 + uint16_t periodic_usecs;
10313 +
10314 + /**
10315 + * Total bandwidth claimed so far for all periodic transfers
10316 + * in a frame.
10317 + * This will include a mixture of HS and FS transfers.
10318 + * Units are microseconds per (micro)frame.
10319 + * We have a budget per frame and have to schedule
10320 + * transactions accordingly.
10321 + * Watch out for the fact that things are actually scheduled for the
10322 + * "next frame".
10323 + */
10324 + uint16_t frame_usecs[8];
10325 +
10326 + /**
10327 + * Frame number read from the core at SOF. The value ranges from 0 to
10328 + * DWC_HFNUM_MAX_FRNUM.
10329 + */
10330 + uint16_t frame_number;
10331 +
10332 + /**
10333 + * Free host channels in the controller. This is a list of
10334 + * dwc_hc_t items.
10335 + */
10336 + struct list_head free_hc_list;
10337 +
10338 + /**
10339 + * Number of available host channels.
10340 + */
10341 + int available_host_channels;
10342 +
10343 + /**
10344 + * Array of pointers to the host channel descriptors. Allows accessing
10345 + * a host channel descriptor given the host channel number. This is
10346 + * useful in interrupt handlers.
10347 + */
10348 + dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
10349 +
10350 + /**
10351 + * Buffer to use for any data received during the status phase of a
10352 + * control transfer. Normally no data is transferred during the status
10353 + * phase. This buffer is used as a bit bucket.
10354 + */
10355 + uint8_t *status_buf;
10356 +
10357 + /**
10358 + * DMA address for status_buf.
10359 + */
10360 + dma_addr_t status_buf_dma;
10361 +#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
10362 +
10363 + /**
10364 + * Structure to allow starting the HCD in a non-interrupt context
10365 + * during an OTG role change.
10366 + */
10367 + struct work_struct start_work;
10368 + struct usb_hcd *_p;
10369 +
10370 + /**
10371 + * Connection timer. An OTG host must display a message if the device
10372 + * does not connect. Started when the VBus power is turned on via
10373 + * sysfs attribute "buspower".
10374 + */
10375 + struct timer_list conn_timer;
10376 +
10377 + /* Tasket to do a reset */
10378 + struct tasklet_struct *reset_tasklet;
10379 +
10380 +#ifdef DEBUG
10381 + uint32_t frrem_samples;
10382 + uint64_t frrem_accum;
10383 +
10384 + uint32_t hfnum_7_samples_a;
10385 + uint64_t hfnum_7_frrem_accum_a;
10386 + uint32_t hfnum_0_samples_a;
10387 + uint64_t hfnum_0_frrem_accum_a;
10388 + uint32_t hfnum_other_samples_a;
10389 + uint64_t hfnum_other_frrem_accum_a;
10390 +
10391 + uint32_t hfnum_7_samples_b;
10392 + uint64_t hfnum_7_frrem_accum_b;
10393 + uint32_t hfnum_0_samples_b;
10394 + uint64_t hfnum_0_frrem_accum_b;
10395 + uint32_t hfnum_other_samples_b;
10396 + uint64_t hfnum_other_frrem_accum_b;
10397 +#endif
10398 +
10399 +} dwc_otg_hcd_t;
10400 +
10401 +/** Gets the dwc_otg_hcd from a struct usb_hcd */
10402 +static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
10403 +{
10404 + return (dwc_otg_hcd_t *)(hcd->hcd_priv);
10405 +}
10406 +
10407 +/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
10408 +static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
10409 +{
10410 + return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
10411 +}
10412 +
10413 +/** @name HCD Create/Destroy Functions */
10414 +/** @{ */
10415 +extern int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device);
10416 +extern void dwc_otg_hcd_remove(struct device *_dev);
10417 +/** @} */
10418 +
10419 +/** @name Linux HC Driver API Functions */
10420 +/** @{ */
10421 +
10422 +extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
10423 +extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
10424 +extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
10425 +extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
10426 +
10427 +extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
10428 + struct urb *urb,
10429 + gfp_t mem_flags);
10430 +extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
10431 + struct urb *urb,
10432 + int status);
10433 +extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
10434 +
10435 +extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
10436 + struct usb_host_endpoint *ep);
10437 +
10438 +extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
10439 + char *buf);
10440 +extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
10441 + u16 typeReq,
10442 + u16 wValue,
10443 + u16 wIndex,
10444 + char *buf,
10445 + u16 wLength);
10446 +
10447 +/** @} */
10448 +
10449 +/** @name Transaction Execution Functions */
10450 +/** @{ */
10451 +extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd);
10452 +extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
10453 + dwc_otg_transaction_type_e _tr_type);
10454 +extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *_urb,
10455 + int _status);
10456 +/** @} */
10457 +
10458 +/** @name Interrupt Handler Functions */
10459 +/** @{ */
10460 +extern int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10461 +extern int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10462 +extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10463 +extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10464 +extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10465 +extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *_dwc_otg_hcd);
10466 +extern int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10467 +extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10468 +extern int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10469 +extern int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10470 +extern int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num);
10471 +extern int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10472 +extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10473 +/** @} */
10474 +
10475 +
10476 +/** @name Schedule Queue Functions */
10477 +/** @{ */
10478 +
10479 +/* Implemented in dwc_otg_hcd_queue.c */
10480 +extern dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb);
10481 +extern void dwc_otg_hcd_qh_init (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb);
10482 +extern void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh);
10483 +extern int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh);
10484 +extern void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh);
10485 +extern void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_csplit);
10486 +extern int dwc_otg_hcd_qh_deferr (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int delay);
10487 +
10488 +/** Remove and free a QH */
10489 +static inline void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *_hcd,
10490 + dwc_otg_qh_t *_qh)
10491 +{
10492 + dwc_otg_hcd_qh_remove (_hcd, _qh);
10493 + dwc_otg_hcd_qh_free (_qh);
10494 +}
10495 +
10496 +/** Allocates memory for a QH structure.
10497 + * @return Returns the memory allocate or NULL on error. */
10498 +static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc (void)
10499 +{
10500 +#ifdef _SC_BUILD_
10501 + return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_ATOMIC);
10502 +#else
10503 + return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_KERNEL);
10504 +#endif
10505 +}
10506 +
10507 +extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb);
10508 +extern void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb);
10509 +extern int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
10510 +
10511 +/** Allocates memory for a QTD structure.
10512 + * @return Returns the memory allocate or NULL on error. */
10513 +static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc (void)
10514 +{
10515 +#ifdef _SC_BUILD_
10516 + return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_ATOMIC);
10517 +#else
10518 + return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_KERNEL);
10519 +#endif
10520 +}
10521 +
10522 +/** Frees the memory for a QTD structure. QTD should already be removed from
10523 + * list.
10524 + * @param[in] _qtd QTD to free.*/
10525 +static inline void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *_qtd)
10526 +{
10527 + kfree (_qtd);
10528 +}
10529 +
10530 +/** Removes a QTD from list.
10531 + * @param[in] _qtd QTD to remove from list. */
10532 +static inline void dwc_otg_hcd_qtd_remove (dwc_otg_qtd_t *_qtd)
10533 +{
10534 + unsigned long flags;
10535 + local_irq_save (flags);
10536 + list_del (&_qtd->qtd_list_entry);
10537 + local_irq_restore (flags);
10538 +}
10539 +
10540 +/** Remove and free a QTD */
10541 +static inline void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_qtd_t *_qtd)
10542 +{
10543 + dwc_otg_hcd_qtd_remove (_qtd);
10544 + dwc_otg_hcd_qtd_free (_qtd);
10545 +}
10546 +
10547 +/** @} */
10548 +
10549 +
10550 +/** @name Internal Functions */
10551 +/** @{ */
10552 +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb);
10553 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd);
10554 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd);
10555 +/** @} */
10556 +
10557 +
10558 +/** Gets the usb_host_endpoint associated with an URB. */
10559 +static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *_urb)
10560 +{
10561 + struct usb_device *dev = _urb->dev;
10562 + int ep_num = usb_pipeendpoint(_urb->pipe);
10563 + if (usb_pipein(_urb->pipe))
10564 + return dev->ep_in[ep_num];
10565 + else
10566 + return dev->ep_out[ep_num];
10567 +}
10568 +
10569 +/**
10570 + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
10571 + * qualified with its direction (possible 32 endpoints per device).
10572 + */
10573 +#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) \
10574 + ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
10575 + ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
10576 +
10577 +/** Gets the QH that contains the list_head */
10578 +#define dwc_list_to_qh(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qh_t,qh_list_entry))
10579 +
10580 +/** Gets the QTD that contains the list_head */
10581 +#define dwc_list_to_qtd(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qtd_t,qtd_list_entry))
10582 +
10583 +/** Check if QH is non-periodic */
10584 +#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
10585 + (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
10586 +
10587 +/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
10588 +#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
10589 +
10590 +/** Packet size for any kind of endpoint descriptor */
10591 +#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
10592 +
10593 +/**
10594 + * Returns true if _frame1 is less than or equal to _frame2. The comparison is
10595 + * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
10596 + * frame number when the max frame number is reached.
10597 + */
10598 +static inline int dwc_frame_num_le(uint16_t _frame1, uint16_t _frame2)
10599 +{
10600 + return ((_frame2 - _frame1) & DWC_HFNUM_MAX_FRNUM) <=
10601 + (DWC_HFNUM_MAX_FRNUM >> 1);
10602 +}
10603 +
10604 +/**
10605 + * Returns true if _frame1 is greater than _frame2. The comparison is done
10606 + * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
10607 + * number when the max frame number is reached.
10608 + */
10609 +static inline int dwc_frame_num_gt(uint16_t _frame1, uint16_t _frame2)
10610 +{
10611 + return (_frame1 != _frame2) &&
10612 + (((_frame1 - _frame2) & DWC_HFNUM_MAX_FRNUM) <
10613 + (DWC_HFNUM_MAX_FRNUM >> 1));
10614 +}
10615 +
10616 +/**
10617 + * Increments _frame by the amount specified by _inc. The addition is done
10618 + * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
10619 + */
10620 +static inline uint16_t dwc_frame_num_inc(uint16_t _frame, uint16_t _inc)
10621 +{
10622 + return (_frame + _inc) & DWC_HFNUM_MAX_FRNUM;
10623 +}
10624 +
10625 +static inline uint16_t dwc_full_frame_num (uint16_t _frame)
10626 +{
10627 + return ((_frame) & DWC_HFNUM_MAX_FRNUM) >> 3;
10628 +}
10629 +
10630 +static inline uint16_t dwc_micro_frame_num (uint16_t _frame)
10631 +{
10632 + return (_frame) & 0x7;
10633 +}
10634 +
10635 +#ifdef DEBUG
10636 +/**
10637 + * Macro to sample the remaining PHY clocks left in the current frame. This
10638 + * may be used during debugging to determine the average time it takes to
10639 + * execute sections of code. There are two possible sample points, "a" and
10640 + * "b", so the _letter argument must be one of these values.
10641 + *
10642 + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
10643 + * example, "cat /sys/devices/lm0/hcd_frrem".
10644 + */
10645 +#define dwc_sample_frrem(_hcd, _qh, _letter) \
10646 +{ \
10647 + hfnum_data_t hfnum; \
10648 + dwc_otg_qtd_t *qtd; \
10649 + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
10650 + if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
10651 + hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
10652 + switch (hfnum.b.frnum & 0x7) { \
10653 + case 7: \
10654 + _hcd->hfnum_7_samples_##_letter++; \
10655 + _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
10656 + break; \
10657 + case 0: \
10658 + _hcd->hfnum_0_samples_##_letter++; \
10659 + _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
10660 + break; \
10661 + default: \
10662 + _hcd->hfnum_other_samples_##_letter++; \
10663 + _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
10664 + break; \
10665 + } \
10666 + } \
10667 +}
10668 +#else // DEBUG
10669 +#define dwc_sample_frrem(_hcd, _qh, _letter)
10670 +#endif // DEBUG
10671 +#endif // __DWC_HCD_H__
10672 +#endif /* DWC_DEVICE_ONLY */
10673 --- /dev/null
10674 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
10675 @@ -0,0 +1,1841 @@
10676 +/* ==========================================================================
10677 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_intr.c $
10678 + * $Revision: 1.1.1.1 $
10679 + * $Date: 2009-04-17 06:15:34 $
10680 + * $Change: 553126 $
10681 + *
10682 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
10683 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
10684 + * otherwise expressly agreed to in writing between Synopsys and you.
10685 + *
10686 + * The Software IS NOT an item of Licensed Software or Licensed Product under
10687 + * any End User Software License Agreement or Agreement for Licensed Product
10688 + * with Synopsys or any supplement thereto. You are permitted to use and
10689 + * redistribute this Software in source and binary forms, with or without
10690 + * modification, provided that redistributions of source code must retain this
10691 + * notice. You may not view, use, disclose, copy or distribute this file or
10692 + * any information contained herein except pursuant to this license grant from
10693 + * Synopsys. If you do not agree with this notice, including the disclaimer
10694 + * below, then you are not authorized to use the Software.
10695 + *
10696 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
10697 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10698 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10699 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
10700 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10701 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
10702 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
10703 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
10704 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
10705 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10706 + * DAMAGE.
10707 + * ========================================================================== */
10708 +#ifndef DWC_DEVICE_ONLY
10709 +
10710 +#include "dwc_otg_driver.h"
10711 +#include "dwc_otg_hcd.h"
10712 +#include "dwc_otg_regs.h"
10713 +
10714 +const int erratum_usb09_patched = 0;
10715 +const int deferral_on = 1;
10716 +const int nak_deferral_delay = 8;
10717 +const int nyet_deferral_delay = 1;
10718 +/** @file
10719 + * This file contains the implementation of the HCD Interrupt handlers.
10720 + */
10721 +
10722 +/** This function handles interrupts for the HCD. */
10723 +int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
10724 +{
10725 + int retval = 0;
10726 +
10727 + dwc_otg_core_if_t *core_if = _dwc_otg_hcd->core_if;
10728 + gintsts_data_t gintsts;
10729 +#ifdef DEBUG
10730 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
10731 +#endif
10732 +
10733 + /* Check if HOST Mode */
10734 + if (dwc_otg_is_host_mode(core_if)) {
10735 + gintsts.d32 = dwc_otg_read_core_intr(core_if);
10736 + if (!gintsts.d32) {
10737 + return 0;
10738 + }
10739 +
10740 +#ifdef DEBUG
10741 + /* Don't print debug message in the interrupt handler on SOF */
10742 +# ifndef DEBUG_SOF
10743 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
10744 +# endif
10745 + DWC_DEBUGPL (DBG_HCD, "\n");
10746 +#endif
10747 +
10748 +#ifdef DEBUG
10749 +# ifndef DEBUG_SOF
10750 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
10751 +# endif
10752 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32);
10753 +#endif
10754 +
10755 + if (gintsts.b.sofintr) {
10756 + retval |= dwc_otg_hcd_handle_sof_intr (_dwc_otg_hcd);
10757 + }
10758 + if (gintsts.b.rxstsqlvl) {
10759 + retval |= dwc_otg_hcd_handle_rx_status_q_level_intr (_dwc_otg_hcd);
10760 + }
10761 + if (gintsts.b.nptxfempty) {
10762 + retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr (_dwc_otg_hcd);
10763 + }
10764 + if (gintsts.b.i2cintr) {
10765 + /** @todo Implement i2cintr handler. */
10766 + }
10767 + if (gintsts.b.portintr) {
10768 + retval |= dwc_otg_hcd_handle_port_intr (_dwc_otg_hcd);
10769 + }
10770 + if (gintsts.b.hcintr) {
10771 + retval |= dwc_otg_hcd_handle_hc_intr (_dwc_otg_hcd);
10772 + }
10773 + if (gintsts.b.ptxfempty) {
10774 + retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (_dwc_otg_hcd);
10775 + }
10776 +#ifdef DEBUG
10777 +# ifndef DEBUG_SOF
10778 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
10779 +# endif
10780 + {
10781 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n");
10782 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
10783 + dwc_read_reg32(&global_regs->gintsts));
10784 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
10785 + dwc_read_reg32(&global_regs->gintmsk));
10786 + }
10787 +#endif
10788 +
10789 +#ifdef DEBUG
10790 +# ifndef DEBUG_SOF
10791 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
10792 +# endif
10793 + DWC_DEBUGPL (DBG_HCD, "\n");
10794 +#endif
10795 +
10796 + }
10797 +
10798 + return retval;
10799 +}
10800 +
10801 +#ifdef DWC_TRACK_MISSED_SOFS
10802 +#warning Compiling code to track missed SOFs
10803 +#define FRAME_NUM_ARRAY_SIZE 1000
10804 +/**
10805 + * This function is for debug only.
10806 + */
10807 +static inline void track_missed_sofs(uint16_t _curr_frame_number) {
10808 + static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
10809 + static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
10810 + static int frame_num_idx = 0;
10811 + static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
10812 + static int dumped_frame_num_array = 0;
10813 +
10814 + if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
10815 + if ((((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != _curr_frame_number)) {
10816 + frame_num_array[frame_num_idx] = _curr_frame_number;
10817 + last_frame_num_array[frame_num_idx++] = last_frame_num;
10818 + }
10819 + } else if (!dumped_frame_num_array) {
10820 + int i;
10821 + printk(KERN_EMERG USB_DWC "Frame Last Frame\n");
10822 + printk(KERN_EMERG USB_DWC "----- ----------\n");
10823 + for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
10824 + printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n",
10825 + frame_num_array[i], last_frame_num_array[i]);
10826 + }
10827 + dumped_frame_num_array = 1;
10828 + }
10829 + last_frame_num = _curr_frame_number;
10830 +}
10831 +#endif
10832 +
10833 +/**
10834 + * Handles the start-of-frame interrupt in host mode. Non-periodic
10835 + * transactions may be queued to the DWC_otg controller for the current
10836 + * (micro)frame. Periodic transactions may be queued to the controller for the
10837 + * next (micro)frame.
10838 + */
10839 +int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_hcd)
10840 +{
10841 + hfnum_data_t hfnum;
10842 + struct list_head *qh_entry;
10843 + dwc_otg_qh_t *qh;
10844 + dwc_otg_transaction_type_e tr_type;
10845 + gintsts_data_t gintsts = {.d32 = 0};
10846 +
10847 + hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
10848 +
10849 +#ifdef DEBUG_SOF
10850 + DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
10851 +#endif
10852 +
10853 + _hcd->frame_number = hfnum.b.frnum;
10854 +
10855 +#ifdef DEBUG
10856 + _hcd->frrem_accum += hfnum.b.frrem;
10857 + _hcd->frrem_samples++;
10858 +#endif
10859 +
10860 +#ifdef DWC_TRACK_MISSED_SOFS
10861 + track_missed_sofs(_hcd->frame_number);
10862 +#endif
10863 +
10864 + /* Determine whether any periodic QHs should be executed. */
10865 + qh_entry = _hcd->periodic_sched_inactive.next;
10866 + while (qh_entry != &_hcd->periodic_sched_inactive) {
10867 + qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry);
10868 + qh_entry = qh_entry->next;
10869 + if (dwc_frame_num_le(qh->sched_frame, _hcd->frame_number)) {
10870 + /*
10871 + * Move QH to the ready list to be executed next
10872 + * (micro)frame.
10873 + */
10874 + list_move(&qh->qh_list_entry, &_hcd->periodic_sched_ready);
10875 + }
10876 + }
10877 +
10878 + tr_type = dwc_otg_hcd_select_transactions(_hcd);
10879 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
10880 + dwc_otg_hcd_queue_transactions(_hcd, tr_type);
10881 + }
10882 +
10883 + /* Clear interrupt */
10884 + gintsts.b.sofintr = 1;
10885 + dwc_write_reg32(&_hcd->core_if->core_global_regs->gintsts, gintsts.d32);
10886 +
10887 + return 1;
10888 +}
10889 +
10890 +/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
10891 + * least one packet in the Rx FIFO. The packets are moved from the FIFO to
10892 + * memory if the DWC_otg controller is operating in Slave mode. */
10893 +int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
10894 +{
10895 + host_grxsts_data_t grxsts;
10896 + dwc_hc_t *hc = NULL;
10897 +
10898 + DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
10899 +
10900 + grxsts.d32 = dwc_read_reg32(&_dwc_otg_hcd->core_if->core_global_regs->grxstsp);
10901 +
10902 + hc = _dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
10903 +
10904 + /* Packet Status */
10905 + DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
10906 + DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
10907 + DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start);
10908 + DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
10909 +
10910 + switch (grxsts.b.pktsts) {
10911 + case DWC_GRXSTS_PKTSTS_IN:
10912 + /* Read the data into the host buffer. */
10913 + if (grxsts.b.bcnt > 0) {
10914 + dwc_otg_read_packet(_dwc_otg_hcd->core_if,
10915 + hc->xfer_buff,
10916 + grxsts.b.bcnt);
10917 +
10918 + /* Update the HC fields for the next packet received. */
10919 + hc->xfer_count += grxsts.b.bcnt;
10920 + hc->xfer_buff += grxsts.b.bcnt;
10921 + }
10922 +
10923 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
10924 + case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
10925 + case DWC_GRXSTS_PKTSTS_CH_HALTED:
10926 + /* Handled in interrupt, just ignore data */
10927 + break;
10928 + default:
10929 + DWC_ERROR ("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts);
10930 + break;
10931 + }
10932 +
10933 + return 1;
10934 +}
10935 +
10936 +/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
10937 + * data packets may be written to the FIFO for OUT transfers. More requests
10938 + * may be written to the non-periodic request queue for IN transfers. This
10939 + * interrupt is enabled only in Slave mode. */
10940 +int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
10941 +{
10942 + DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
10943 + dwc_otg_hcd_queue_transactions(_dwc_otg_hcd,
10944 + DWC_OTG_TRANSACTION_NON_PERIODIC);
10945 + return 1;
10946 +}
10947 +
10948 +/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
10949 + * packets may be written to the FIFO for OUT transfers. More requests may be
10950 + * written to the periodic request queue for IN transfers. This interrupt is
10951 + * enabled only in Slave mode. */
10952 +int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
10953 +{
10954 + DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
10955 + dwc_otg_hcd_queue_transactions(_dwc_otg_hcd,
10956 + DWC_OTG_TRANSACTION_PERIODIC);
10957 + return 1;
10958 +}
10959 +
10960 +/** There are multiple conditions that can cause a port interrupt. This function
10961 + * determines which interrupt conditions have occurred and handles them
10962 + * appropriately. */
10963 +int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
10964 +{
10965 + int retval = 0;
10966 + hprt0_data_t hprt0;
10967 + hprt0_data_t hprt0_modify;
10968 +
10969 + hprt0.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0);
10970 + hprt0_modify.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0);
10971 +
10972 + /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
10973 + * GINTSTS */
10974 +
10975 + hprt0_modify.b.prtena = 0;
10976 + hprt0_modify.b.prtconndet = 0;
10977 + hprt0_modify.b.prtenchng = 0;
10978 + hprt0_modify.b.prtovrcurrchng = 0;
10979 +
10980 + /* Port Connect Detected
10981 + * Set flag and clear if detected */
10982 + if (hprt0.b.prtconndet) {
10983 + DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
10984 + "Port Connect Detected--\n", hprt0.d32);
10985 + _dwc_otg_hcd->flags.b.port_connect_status_change = 1;
10986 + _dwc_otg_hcd->flags.b.port_connect_status = 1;
10987 + hprt0_modify.b.prtconndet = 1;
10988 +
10989 + /* B-Device has connected, Delete the connection timer. */
10990 + del_timer( &_dwc_otg_hcd->conn_timer );
10991 +
10992 + /* The Hub driver asserts a reset when it sees port connect
10993 + * status change flag */
10994 + retval |= 1;
10995 + }
10996 +
10997 + /* Port Enable Changed
10998 + * Clear if detected - Set internal flag if disabled */
10999 + if (hprt0.b.prtenchng) {
11000 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
11001 + "Port Enable Changed--\n", hprt0.d32);
11002 + hprt0_modify.b.prtenchng = 1;
11003 + if (hprt0.b.prtena == 1) {
11004 + int do_reset = 0;
11005 + dwc_otg_core_params_t *params = _dwc_otg_hcd->core_if->core_params;
11006 + dwc_otg_core_global_regs_t *global_regs = _dwc_otg_hcd->core_if->core_global_regs;
11007 + dwc_otg_host_if_t *host_if = _dwc_otg_hcd->core_if->host_if;
11008 +
11009 + /* Check if we need to adjust the PHY clock speed for
11010 + * low power and adjust it */
11011 + if (params->host_support_fs_ls_low_power)
11012 + {
11013 + gusbcfg_data_t usbcfg;
11014 +
11015 + usbcfg.d32 = dwc_read_reg32 (&global_regs->gusbcfg);
11016 +
11017 + if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) ||
11018 + (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED))
11019 + {
11020 + /*
11021 + * Low power
11022 + */
11023 + hcfg_data_t hcfg;
11024 + if (usbcfg.b.phylpwrclksel == 0) {
11025 + /* Set PHY low power clock select for FS/LS devices */
11026 + usbcfg.b.phylpwrclksel = 1;
11027 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
11028 + do_reset = 1;
11029 + }
11030 +
11031 + hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
11032 +
11033 + if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) &&
11034 + (params->host_ls_low_power_phy_clk ==
11035 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ))
11036 + {
11037 + /* 6 MHZ */
11038 + DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
11039 + if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) {
11040 + hcfg.b.fslspclksel = DWC_HCFG_6_MHZ;
11041 + dwc_write_reg32(&host_if->host_global_regs->hcfg,
11042 + hcfg.d32);
11043 + do_reset = 1;
11044 + }
11045 + }
11046 + else {
11047 + /* 48 MHZ */
11048 + DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n");
11049 + if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) {
11050 + hcfg.b.fslspclksel = DWC_HCFG_48_MHZ;
11051 + dwc_write_reg32(&host_if->host_global_regs->hcfg,
11052 + hcfg.d32);
11053 + do_reset = 1;
11054 + }
11055 + }
11056 + }
11057 + else {
11058 + /*
11059 + * Not low power
11060 + */
11061 + if (usbcfg.b.phylpwrclksel == 1) {
11062 + usbcfg.b.phylpwrclksel = 0;
11063 + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
11064 + do_reset = 1;
11065 + }
11066 + }
11067 +
11068 + if (do_reset) {
11069 + tasklet_schedule(_dwc_otg_hcd->reset_tasklet);
11070 + }
11071 + }
11072 +
11073 + if (!do_reset) {
11074 + /* Port has been enabled set the reset change flag */
11075 + _dwc_otg_hcd->flags.b.port_reset_change = 1;
11076 + }
11077 +
11078 + } else {
11079 + _dwc_otg_hcd->flags.b.port_enable_change = 1;
11080 + }
11081 + retval |= 1;
11082 + }
11083 +
11084 + /** Overcurrent Change Interrupt */
11085 + if (hprt0.b.prtovrcurrchng) {
11086 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
11087 + "Port Overcurrent Changed--\n", hprt0.d32);
11088 + _dwc_otg_hcd->flags.b.port_over_current_change = 1;
11089 + hprt0_modify.b.prtovrcurrchng = 1;
11090 + retval |= 1;
11091 + }
11092 +
11093 + /* Clear Port Interrupts */
11094 + dwc_write_reg32(_dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
11095 +
11096 + return retval;
11097 +}
11098 +
11099 +
11100 +/** This interrupt indicates that one or more host channels has a pending
11101 + * interrupt. There are multiple conditions that can cause each host channel
11102 + * interrupt. This function determines which conditions have occurred for each
11103 + * host channel interrupt and handles them appropriately. */
11104 +int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
11105 +{
11106 + int i;
11107 + int retval = 0;
11108 + haint_data_t haint;
11109 +
11110 + /* Clear appropriate bits in HCINTn to clear the interrupt bit in
11111 + * GINTSTS */
11112 +
11113 + haint.d32 = dwc_otg_read_host_all_channels_intr(_dwc_otg_hcd->core_if);
11114 +
11115 + for (i=0; i<_dwc_otg_hcd->core_if->core_params->host_channels; i++) {
11116 + if (haint.b2.chint & (1 << i)) {
11117 + retval |= dwc_otg_hcd_handle_hc_n_intr (_dwc_otg_hcd, i);
11118 + }
11119 + }
11120 +
11121 + return retval;
11122 +}
11123 +
11124 +/* Macro used to clear one channel interrupt */
11125 +#define clear_hc_int(_hc_regs_,_intr_) \
11126 +do { \
11127 + hcint_data_t hcint_clear = {.d32 = 0}; \
11128 + hcint_clear.b._intr_ = 1; \
11129 + dwc_write_reg32(&((_hc_regs_)->hcint), hcint_clear.d32); \
11130 +} while (0)
11131 +
11132 +/*
11133 + * Macro used to disable one channel interrupt. Channel interrupts are
11134 + * disabled when the channel is halted or released by the interrupt handler.
11135 + * There is no need to handle further interrupts of that type until the
11136 + * channel is re-assigned. In fact, subsequent handling may cause crashes
11137 + * because the channel structures are cleaned up when the channel is released.
11138 + */
11139 +#define disable_hc_int(_hc_regs_,_intr_) \
11140 +do { \
11141 + hcintmsk_data_t hcintmsk = {.d32 = 0}; \
11142 + hcintmsk.b._intr_ = 1; \
11143 + dwc_modify_reg32(&((_hc_regs_)->hcintmsk), hcintmsk.d32, 0); \
11144 +} while (0)
11145 +
11146 +/**
11147 + * Gets the actual length of a transfer after the transfer halts. _halt_status
11148 + * holds the reason for the halt.
11149 + *
11150 + * For IN transfers where _halt_status is DWC_OTG_HC_XFER_COMPLETE,
11151 + * *_short_read is set to 1 upon return if less than the requested
11152 + * number of bytes were transferred. Otherwise, *_short_read is set to 0 upon
11153 + * return. _short_read may also be NULL on entry, in which case it remains
11154 + * unchanged.
11155 + */
11156 +static uint32_t get_actual_xfer_length(dwc_hc_t *_hc,
11157 + dwc_otg_hc_regs_t *_hc_regs,
11158 + dwc_otg_qtd_t *_qtd,
11159 + dwc_otg_halt_status_e _halt_status,
11160 + int *_short_read)
11161 +{
11162 + hctsiz_data_t hctsiz;
11163 + uint32_t length;
11164 +
11165 + if (_short_read != NULL) {
11166 + *_short_read = 0;
11167 + }
11168 + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
11169 +
11170 + if (_halt_status == DWC_OTG_HC_XFER_COMPLETE) {
11171 + if (_hc->ep_is_in) {
11172 + length = _hc->xfer_len - hctsiz.b.xfersize;
11173 + if (_short_read != NULL) {
11174 + *_short_read = (hctsiz.b.xfersize != 0);
11175 + }
11176 + } else if (_hc->qh->do_split) {
11177 + length = _qtd->ssplit_out_xfer_count;
11178 + } else {
11179 + length = _hc->xfer_len;
11180 + }
11181 + } else {
11182 + /*
11183 + * Must use the hctsiz.pktcnt field to determine how much data
11184 + * has been transferred. This field reflects the number of
11185 + * packets that have been transferred via the USB. This is
11186 + * always an integral number of packets if the transfer was
11187 + * halted before its normal completion. (Can't use the
11188 + * hctsiz.xfersize field because that reflects the number of
11189 + * bytes transferred via the AHB, not the USB).
11190 + */
11191 + length = (_hc->start_pkt_count - hctsiz.b.pktcnt) * _hc->max_packet;
11192 + }
11193 +
11194 + return length;
11195 +}
11196 +
11197 +/**
11198 + * Updates the state of the URB after a Transfer Complete interrupt on the
11199 + * host channel. Updates the actual_length field of the URB based on the
11200 + * number of bytes transferred via the host channel. Sets the URB status
11201 + * if the data transfer is finished.
11202 + *
11203 + * @return 1 if the data transfer specified by the URB is completely finished,
11204 + * 0 otherwise.
11205 + */
11206 +static int update_urb_state_xfer_comp(dwc_hc_t *_hc,
11207 + dwc_otg_hc_regs_t * _hc_regs, struct urb *_urb,
11208 + dwc_otg_qtd_t * _qtd, int *status)
11209 +{
11210 + int xfer_done = 0;
11211 + int short_read = 0;
11212 +
11213 + _urb->actual_length += get_actual_xfer_length(_hc, _hc_regs, _qtd,
11214 + DWC_OTG_HC_XFER_COMPLETE,
11215 + &short_read);
11216 +
11217 + if (short_read || (_urb->actual_length == _urb->transfer_buffer_length)) {
11218 + xfer_done = 1;
11219 + if (short_read && (_urb->transfer_flags & URB_SHORT_NOT_OK)) {
11220 + *status = -EREMOTEIO;
11221 + } else {
11222 + *status = 0;
11223 + }
11224 + }
11225 +
11226 +#ifdef DEBUG
11227 + {
11228 + hctsiz_data_t hctsiz;
11229 + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
11230 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
11231 + __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num);
11232 + DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", _hc->xfer_len);
11233 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize);
11234 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
11235 + _urb->transfer_buffer_length);
11236 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", _urb->actual_length);
11237 + DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
11238 + short_read, xfer_done);
11239 + }
11240 +#endif
11241 +
11242 + return xfer_done;
11243 +}
11244 +
11245 +/*
11246 + * Save the starting data toggle for the next transfer. The data toggle is
11247 + * saved in the QH for non-control transfers and it's saved in the QTD for
11248 + * control transfers.
11249 + */
11250 +static void save_data_toggle(dwc_hc_t *_hc,
11251 + dwc_otg_hc_regs_t *_hc_regs,
11252 + dwc_otg_qtd_t *_qtd)
11253 +{
11254 + hctsiz_data_t hctsiz;
11255 + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
11256 +
11257 + if (_hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
11258 + dwc_otg_qh_t *qh = _hc->qh;
11259 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
11260 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
11261 + } else {
11262 + qh->data_toggle = DWC_OTG_HC_PID_DATA1;
11263 + }
11264 + } else {
11265 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
11266 + _qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
11267 + } else {
11268 + _qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
11269 + }
11270 + }
11271 +}
11272 +
11273 +/**
11274 + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
11275 + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
11276 + * still linked to the QH, the QH is added to the end of the inactive
11277 + * non-periodic schedule. For periodic QHs, removes the QH from the periodic
11278 + * schedule if no more QTDs are linked to the QH.
11279 + */
11280 +static void deactivate_qh(dwc_otg_hcd_t *_hcd,
11281 + dwc_otg_qh_t *_qh,
11282 + int free_qtd)
11283 +{
11284 + int continue_split = 0;
11285 + dwc_otg_qtd_t *qtd;
11286 +
11287 + DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, _hcd, _qh, free_qtd);
11288 +
11289 + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
11290 +
11291 + if (qtd->complete_split) {
11292 + continue_split = 1;
11293 + }
11294 + else if ((qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID) ||
11295 + (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END))
11296 + {
11297 + continue_split = 1;
11298 + }
11299 +
11300 + if (free_qtd) {
11301 + /*
11302 + * Note that this was previously a call to
11303 + * dwc_otg_hcd_qtd_remove_and_free(qtd), which frees the qtd.
11304 + * However, that call frees the qtd memory, and we continue in the
11305 + * interrupt logic to access it many more times, including writing
11306 + * to it. With slub debugging on, it is clear that we were writing
11307 + * to memory we had freed.
11308 + * Call this instead, and now I have moved the freeing of the memory to
11309 + * the end of processing this interrupt.
11310 + */
11311 + //dwc_otg_hcd_qtd_remove_and_free(qtd);
11312 + dwc_otg_hcd_qtd_remove(qtd);
11313 +
11314 + continue_split = 0;
11315 + }
11316 +
11317 + _qh->channel = NULL;
11318 + _qh->qtd_in_process = NULL;
11319 + dwc_otg_hcd_qh_deactivate(_hcd, _qh, continue_split);
11320 +}
11321 +
11322 +/**
11323 + * Updates the state of an Isochronous URB when the transfer is stopped for
11324 + * any reason. The fields of the current entry in the frame descriptor array
11325 + * are set based on the transfer state and the input _halt_status. Completes
11326 + * the Isochronous URB if all the URB frames have been completed.
11327 + *
11328 + * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
11329 + * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
11330 + */
11331 +static dwc_otg_halt_status_e
11332 +update_isoc_urb_state(dwc_otg_hcd_t *_hcd,
11333 + dwc_hc_t *_hc,
11334 + dwc_otg_hc_regs_t *_hc_regs,
11335 + dwc_otg_qtd_t *_qtd,
11336 + dwc_otg_halt_status_e _halt_status)
11337 +{
11338 + struct urb *urb = _qtd->urb;
11339 + dwc_otg_halt_status_e ret_val = _halt_status;
11340 + struct usb_iso_packet_descriptor *frame_desc;
11341 +
11342 + frame_desc = &urb->iso_frame_desc[_qtd->isoc_frame_index];
11343 + switch (_halt_status) {
11344 + case DWC_OTG_HC_XFER_COMPLETE:
11345 + frame_desc->status = 0;
11346 + frame_desc->actual_length =
11347 + get_actual_xfer_length(_hc, _hc_regs, _qtd,
11348 + _halt_status, NULL);
11349 + break;
11350 + case DWC_OTG_HC_XFER_FRAME_OVERRUN:
11351 + urb->error_count++;
11352 + if (_hc->ep_is_in) {
11353 + frame_desc->status = -ENOSR;
11354 + } else {
11355 + frame_desc->status = -ECOMM;
11356 + }
11357 + frame_desc->actual_length = 0;
11358 + break;
11359 + case DWC_OTG_HC_XFER_BABBLE_ERR:
11360 + urb->error_count++;
11361 + frame_desc->status = -EOVERFLOW;
11362 + /* Don't need to update actual_length in this case. */
11363 + break;
11364 + case DWC_OTG_HC_XFER_XACT_ERR:
11365 + urb->error_count++;
11366 + frame_desc->status = -EPROTO;
11367 + frame_desc->actual_length =
11368 + get_actual_xfer_length(_hc, _hc_regs, _qtd,
11369 + _halt_status, NULL);
11370 + default:
11371 + DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__,
11372 + _halt_status);
11373 + BUG();
11374 + break;
11375 + }
11376 +
11377 + if (++_qtd->isoc_frame_index == urb->number_of_packets) {
11378 + /*
11379 + * urb->status is not used for isoc transfers.
11380 + * The individual frame_desc statuses are used instead.
11381 + */
11382 + dwc_otg_hcd_complete_urb(_hcd, urb, 0);
11383 + ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
11384 + } else {
11385 + ret_val = DWC_OTG_HC_XFER_COMPLETE;
11386 + }
11387 +
11388 + return ret_val;
11389 +}
11390 +
11391 +/**
11392 + * Releases a host channel for use by other transfers. Attempts to select and
11393 + * queue more transactions since at least one host channel is available.
11394 + *
11395 + * @param _hcd The HCD state structure.
11396 + * @param _hc The host channel to release.
11397 + * @param _qtd The QTD associated with the host channel. This QTD may be freed
11398 + * if the transfer is complete or an error has occurred.
11399 + * @param _halt_status Reason the channel is being released. This status
11400 + * determines the actions taken by this function.
11401 + */
11402 +static void release_channel(dwc_otg_hcd_t *_hcd,
11403 + dwc_hc_t *_hc,
11404 + dwc_otg_qtd_t *_qtd,
11405 + dwc_otg_halt_status_e _halt_status,
11406 + int *must_free)
11407 +{
11408 + dwc_otg_transaction_type_e tr_type;
11409 + int free_qtd;
11410 + dwc_otg_qh_t * _qh;
11411 + int deact = 1;
11412 + int retry_delay = 1;
11413 + unsigned long flags;
11414 +
11415 + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n", __func__,
11416 + _hc->hc_num, _halt_status);
11417 +
11418 + switch (_halt_status) {
11419 + case DWC_OTG_HC_XFER_NYET:
11420 + case DWC_OTG_HC_XFER_NAK:
11421 + if (_halt_status == DWC_OTG_HC_XFER_NYET) {
11422 + retry_delay = nyet_deferral_delay;
11423 + } else {
11424 + retry_delay = nak_deferral_delay;
11425 + }
11426 + free_qtd = 0;
11427 + if (deferral_on && _hc->do_split) {
11428 + _qh = _hc->qh;
11429 + if (_qh) {
11430 + deact = dwc_otg_hcd_qh_deferr(_hcd, _qh , retry_delay);
11431 + }
11432 + }
11433 + break;
11434 + case DWC_OTG_HC_XFER_URB_COMPLETE:
11435 + free_qtd = 1;
11436 + break;
11437 + case DWC_OTG_HC_XFER_AHB_ERR:
11438 + case DWC_OTG_HC_XFER_STALL:
11439 + case DWC_OTG_HC_XFER_BABBLE_ERR:
11440 + free_qtd = 1;
11441 + break;
11442 + case DWC_OTG_HC_XFER_XACT_ERR:
11443 + if (_qtd->error_count >= 3) {
11444 + DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n");
11445 + free_qtd = 1;
11446 + //_qtd->urb->status = -EPROTO;
11447 + dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPROTO);
11448 + } else {
11449 + free_qtd = 0;
11450 + }
11451 + break;
11452 + case DWC_OTG_HC_XFER_URB_DEQUEUE:
11453 + /*
11454 + * The QTD has already been removed and the QH has been
11455 + * deactivated. Don't want to do anything except release the
11456 + * host channel and try to queue more transfers.
11457 + */
11458 + goto cleanup;
11459 + case DWC_OTG_HC_XFER_NO_HALT_STATUS:
11460 + DWC_ERROR("%s: No halt_status, channel %d\n", __func__, _hc->hc_num);
11461 + free_qtd = 0;
11462 + break;
11463 + default:
11464 + free_qtd = 0;
11465 + break;
11466 + }
11467 + if (free_qtd) {
11468 + /* Only change must_free to true (do not set to zero here -- it is
11469 + * pre-initialized to zero).
11470 + */
11471 + *must_free = 1;
11472 + }
11473 + if (deact) {
11474 + deactivate_qh(_hcd, _hc->qh, free_qtd);
11475 + }
11476 + cleanup:
11477 + /*
11478 + * Release the host channel for use by other transfers. The cleanup
11479 + * function clears the channel interrupt enables and conditions, so
11480 + * there's no need to clear the Channel Halted interrupt separately.
11481 + */
11482 + dwc_otg_hc_cleanup(_hcd->core_if, _hc);
11483 + list_add_tail(&_hc->hc_list_entry, &_hcd->free_hc_list);
11484 +
11485 + local_irq_save(flags);
11486 + _hcd->available_host_channels++;
11487 + local_irq_restore(flags);
11488 + /* Try to queue more transfers now that there's a free channel, */
11489 + /* unless erratum_usb09_patched is set */
11490 + if (!erratum_usb09_patched) {
11491 + tr_type = dwc_otg_hcd_select_transactions(_hcd);
11492 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
11493 + dwc_otg_hcd_queue_transactions(_hcd, tr_type);
11494 + }
11495 + }
11496 +}
11497 +
11498 +/**
11499 + * Halts a host channel. If the channel cannot be halted immediately because
11500 + * the request queue is full, this function ensures that the FIFO empty
11501 + * interrupt for the appropriate queue is enabled so that the halt request can
11502 + * be queued when there is space in the request queue.
11503 + *
11504 + * This function may also be called in DMA mode. In that case, the channel is
11505 + * simply released since the core always halts the channel automatically in
11506 + * DMA mode.
11507 + */
11508 +static void halt_channel(dwc_otg_hcd_t *_hcd,
11509 + dwc_hc_t *_hc,
11510 + dwc_otg_qtd_t *_qtd,
11511 + dwc_otg_halt_status_e _halt_status, int *must_free)
11512 +{
11513 + if (_hcd->core_if->dma_enable) {
11514 + release_channel(_hcd, _hc, _qtd, _halt_status, must_free);
11515 + return;
11516 + }
11517 +
11518 + /* Slave mode processing... */
11519 + dwc_otg_hc_halt(_hcd->core_if, _hc, _halt_status);
11520 +
11521 + if (_hc->halt_on_queue) {
11522 + gintmsk_data_t gintmsk = {.d32 = 0};
11523 + dwc_otg_core_global_regs_t *global_regs;
11524 + global_regs = _hcd->core_if->core_global_regs;
11525 +
11526 + if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
11527 + _hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
11528 + /*
11529 + * Make sure the Non-periodic Tx FIFO empty interrupt
11530 + * is enabled so that the non-periodic schedule will
11531 + * be processed.
11532 + */
11533 + gintmsk.b.nptxfempty = 1;
11534 + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
11535 + } else {
11536 + /*
11537 + * Move the QH from the periodic queued schedule to
11538 + * the periodic assigned schedule. This allows the
11539 + * halt to be queued when the periodic schedule is
11540 + * processed.
11541 + */
11542 + list_move(&_hc->qh->qh_list_entry,
11543 + &_hcd->periodic_sched_assigned);
11544 +
11545 + /*
11546 + * Make sure the Periodic Tx FIFO Empty interrupt is
11547 + * enabled so that the periodic schedule will be
11548 + * processed.
11549 + */
11550 + gintmsk.b.ptxfempty = 1;
11551 + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
11552 + }
11553 + }
11554 +}
11555 +
11556 +/**
11557 + * Performs common cleanup for non-periodic transfers after a Transfer
11558 + * Complete interrupt. This function should be called after any endpoint type
11559 + * specific handling is finished to release the host channel.
11560 + */
11561 +static void complete_non_periodic_xfer(dwc_otg_hcd_t *_hcd,
11562 + dwc_hc_t *_hc,
11563 + dwc_otg_hc_regs_t *_hc_regs,
11564 + dwc_otg_qtd_t *_qtd,
11565 + dwc_otg_halt_status_e _halt_status, int *must_free)
11566 +{
11567 + hcint_data_t hcint;
11568 +
11569 + _qtd->error_count = 0;
11570 +
11571 + hcint.d32 = dwc_read_reg32(&_hc_regs->hcint);
11572 + if (hcint.b.nyet) {
11573 + /*
11574 + * Got a NYET on the last transaction of the transfer. This
11575 + * means that the endpoint should be in the PING state at the
11576 + * beginning of the next transfer.
11577 + */
11578 + _hc->qh->ping_state = 1;
11579 + clear_hc_int(_hc_regs,nyet);
11580 + }
11581 +
11582 + /*
11583 + * Always halt and release the host channel to make it available for
11584 + * more transfers. There may still be more phases for a control
11585 + * transfer or more data packets for a bulk transfer at this point,
11586 + * but the host channel is still halted. A channel will be reassigned
11587 + * to the transfer when the non-periodic schedule is processed after
11588 + * the channel is released. This allows transactions to be queued
11589 + * properly via dwc_otg_hcd_queue_transactions, which also enables the
11590 + * Tx FIFO Empty interrupt if necessary.
11591 + */
11592 + if (_hc->ep_is_in) {
11593 + /*
11594 + * IN transfers in Slave mode require an explicit disable to
11595 + * halt the channel. (In DMA mode, this call simply releases
11596 + * the channel.)
11597 + */
11598 + halt_channel(_hcd, _hc, _qtd, _halt_status, must_free);
11599 + } else {
11600 + /*
11601 + * The channel is automatically disabled by the core for OUT
11602 + * transfers in Slave mode.
11603 + */
11604 + release_channel(_hcd, _hc, _qtd, _halt_status, must_free);
11605 + }
11606 +}
11607 +
11608 +/**
11609 + * Performs common cleanup for periodic transfers after a Transfer Complete
11610 + * interrupt. This function should be called after any endpoint type specific
11611 + * handling is finished to release the host channel.
11612 + */
11613 +static void complete_periodic_xfer(dwc_otg_hcd_t *_hcd,
11614 + dwc_hc_t *_hc,
11615 + dwc_otg_hc_regs_t *_hc_regs,
11616 + dwc_otg_qtd_t *_qtd,
11617 + dwc_otg_halt_status_e _halt_status, int *must_free)
11618 +{
11619 + hctsiz_data_t hctsiz;
11620 + _qtd->error_count = 0;
11621 +
11622 + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
11623 + if (!_hc->ep_is_in || hctsiz.b.pktcnt == 0) {
11624 + /* Core halts channel in these cases. */
11625 + release_channel(_hcd, _hc, _qtd, _halt_status, must_free);
11626 + } else {
11627 + /* Flush any outstanding requests from the Tx queue. */
11628 + halt_channel(_hcd, _hc, _qtd, _halt_status, must_free);
11629 + }
11630 +}
11631 +
11632 +/**
11633 + * Handles a host channel Transfer Complete interrupt. This handler may be
11634 + * called in either DMA mode or Slave mode.
11635 + */
11636 +static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *_hcd,
11637 + dwc_hc_t *_hc,
11638 + dwc_otg_hc_regs_t *_hc_regs,
11639 + dwc_otg_qtd_t *_qtd, int *must_free)
11640 +{
11641 + int urb_xfer_done;
11642 + dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
11643 + struct urb *urb = _qtd->urb;
11644 + int pipe_type = usb_pipetype(urb->pipe);
11645 + int status = -EINPROGRESS;
11646 +
11647 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11648 + "Transfer Complete--\n", _hc->hc_num);
11649 +
11650 + /*
11651 + * Handle xfer complete on CSPLIT.
11652 + */
11653 + if (_hc->qh->do_split) {
11654 + _qtd->complete_split = 0;
11655 + }
11656 +
11657 + /* Update the QTD and URB states. */
11658 + switch (pipe_type) {
11659 + case PIPE_CONTROL:
11660 + switch (_qtd->control_phase) {
11661 + case DWC_OTG_CONTROL_SETUP:
11662 + if (urb->transfer_buffer_length > 0) {
11663 + _qtd->control_phase = DWC_OTG_CONTROL_DATA;
11664 + } else {
11665 + _qtd->control_phase = DWC_OTG_CONTROL_STATUS;
11666 + }
11667 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
11668 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
11669 + break;
11670 + case DWC_OTG_CONTROL_DATA: {
11671 + urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs,urb, _qtd, &status);
11672 + if (urb_xfer_done) {
11673 + _qtd->control_phase = DWC_OTG_CONTROL_STATUS;
11674 + DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
11675 + } else {
11676 + save_data_toggle(_hc, _hc_regs, _qtd);
11677 + }
11678 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
11679 + break;
11680 + }
11681 + case DWC_OTG_CONTROL_STATUS:
11682 + DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
11683 + if (status == -EINPROGRESS) {
11684 + status = 0;
11685 + }
11686 + dwc_otg_hcd_complete_urb(_hcd, urb, status);
11687 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
11688 + break;
11689 + }
11690 +
11691 + complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd,
11692 + halt_status, must_free);
11693 + break;
11694 + case PIPE_BULK:
11695 + DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
11696 + urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd, &status);
11697 + if (urb_xfer_done) {
11698 + dwc_otg_hcd_complete_urb(_hcd, urb, status);
11699 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
11700 + } else {
11701 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
11702 + }
11703 +
11704 + save_data_toggle(_hc, _hc_regs, _qtd);
11705 + complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd,halt_status, must_free);
11706 + break;
11707 + case PIPE_INTERRUPT:
11708 + DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
11709 + update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd, &status);
11710 +
11711 + /*
11712 + * Interrupt URB is done on the first transfer complete
11713 + * interrupt.
11714 + */
11715 + dwc_otg_hcd_complete_urb(_hcd, urb, status);
11716 + save_data_toggle(_hc, _hc_regs, _qtd);
11717 + complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd,
11718 + DWC_OTG_HC_XFER_URB_COMPLETE, must_free);
11719 + break;
11720 + case PIPE_ISOCHRONOUS:
11721 + DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
11722 + if (_qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL)
11723 + {
11724 + halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
11725 + DWC_OTG_HC_XFER_COMPLETE);
11726 + }
11727 + complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, halt_status, must_free);
11728 + break;
11729 + }
11730 +
11731 + disable_hc_int(_hc_regs,xfercompl);
11732 +
11733 + return 1;
11734 +}
11735 +
11736 +/**
11737 + * Handles a host channel STALL interrupt. This handler may be called in
11738 + * either DMA mode or Slave mode.
11739 + */
11740 +static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *_hcd,
11741 + dwc_hc_t *_hc,
11742 + dwc_otg_hc_regs_t *_hc_regs,
11743 + dwc_otg_qtd_t *_qtd, int *must_free)
11744 +{
11745 + struct urb *urb = _qtd->urb;
11746 + int pipe_type = usb_pipetype(urb->pipe);
11747 +
11748 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11749 + "STALL Received--\n", _hc->hc_num);
11750 +
11751 + if (pipe_type == PIPE_CONTROL) {
11752 + dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE);
11753 + }
11754 +
11755 + if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) {
11756 + dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE);
11757 + /*
11758 + * USB protocol requires resetting the data toggle for bulk
11759 + * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
11760 + * setup command is issued to the endpoint. Anticipate the
11761 + * CLEAR_FEATURE command since a STALL has occurred and reset
11762 + * the data toggle now.
11763 + */
11764 + _hc->qh->data_toggle = 0;
11765 + }
11766 +
11767 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_STALL, must_free);
11768 + disable_hc_int(_hc_regs,stall);
11769 +
11770 + return 1;
11771 +}
11772 +
11773 +/*
11774 + * Updates the state of the URB when a transfer has been stopped due to an
11775 + * abnormal condition before the transfer completes. Modifies the
11776 + * actual_length field of the URB to reflect the number of bytes that have
11777 + * actually been transferred via the host channel.
11778 + */
11779 +static void update_urb_state_xfer_intr(dwc_hc_t *_hc,
11780 + dwc_otg_hc_regs_t *_hc_regs,
11781 + struct urb *_urb,
11782 + dwc_otg_qtd_t *_qtd,
11783 + dwc_otg_halt_status_e _halt_status)
11784 +{
11785 + uint32_t bytes_transferred = get_actual_xfer_length(_hc, _hc_regs, _qtd,
11786 + _halt_status, NULL);
11787 + _urb->actual_length += bytes_transferred;
11788 +
11789 +#ifdef DEBUG
11790 + {
11791 + hctsiz_data_t hctsiz;
11792 + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
11793 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
11794 + __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num);
11795 + DWC_DEBUGPL(DBG_HCDV, " _hc->start_pkt_count %d\n", _hc->start_pkt_count);
11796 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
11797 + DWC_DEBUGPL(DBG_HCDV, " _hc->max_packet %d\n", _hc->max_packet);
11798 + DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred);
11799 + DWC_DEBUGPL(DBG_HCDV, " _urb->actual_length %d\n", _urb->actual_length);
11800 + DWC_DEBUGPL(DBG_HCDV, " _urb->transfer_buffer_length %d\n",
11801 + _urb->transfer_buffer_length);
11802 + }
11803 +#endif
11804 +}
11805 +
11806 +/**
11807 + * Handles a host channel NAK interrupt. This handler may be called in either
11808 + * DMA mode or Slave mode.
11809 + */
11810 +static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *_hcd,
11811 + dwc_hc_t *_hc,
11812 + dwc_otg_hc_regs_t *_hc_regs,
11813 + dwc_otg_qtd_t *_qtd, int *must_free)
11814 +{
11815 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11816 + "NAK Received--\n", _hc->hc_num);
11817 +
11818 + /*
11819 + * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
11820 + * interrupt. Re-start the SSPLIT transfer.
11821 + */
11822 + if (_hc->do_split) {
11823 + if (_hc->complete_split) {
11824 + _qtd->error_count = 0;
11825 + }
11826 + _qtd->complete_split = 0;
11827 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free);
11828 + goto handle_nak_done;
11829 + }
11830 +
11831 + switch (usb_pipetype(_qtd->urb->pipe)) {
11832 + case PIPE_CONTROL:
11833 + case PIPE_BULK:
11834 + if (_hcd->core_if->dma_enable && _hc->ep_is_in) {
11835 + /*
11836 + * NAK interrupts are enabled on bulk/control IN
11837 + * transfers in DMA mode for the sole purpose of
11838 + * resetting the error count after a transaction error
11839 + * occurs. The core will continue transferring data.
11840 + */
11841 + _qtd->error_count = 0;
11842 + goto handle_nak_done;
11843 + }
11844 +
11845 + /*
11846 + * NAK interrupts normally occur during OUT transfers in DMA
11847 + * or Slave mode. For IN transfers, more requests will be
11848 + * queued as request queue space is available.
11849 + */
11850 + _qtd->error_count = 0;
11851 +
11852 + if (!_hc->qh->ping_state) {
11853 + update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb,
11854 + _qtd, DWC_OTG_HC_XFER_NAK);
11855 + save_data_toggle(_hc, _hc_regs, _qtd);
11856 + if (_qtd->urb->dev->speed == USB_SPEED_HIGH) {
11857 + _hc->qh->ping_state = 1;
11858 + }
11859 + }
11860 +
11861 + /*
11862 + * Halt the channel so the transfer can be re-started from
11863 + * the appropriate point or the PING protocol will
11864 + * start/continue.
11865 + */
11866 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free);
11867 + break;
11868 + case PIPE_INTERRUPT:
11869 + _qtd->error_count = 0;
11870 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free);
11871 + break;
11872 + case PIPE_ISOCHRONOUS:
11873 + /* Should never get called for isochronous transfers. */
11874 + BUG();
11875 + break;
11876 + }
11877 +
11878 + handle_nak_done:
11879 + disable_hc_int(_hc_regs,nak);
11880 +
11881 + return 1;
11882 +}
11883 +
11884 +/**
11885 + * Handles a host channel ACK interrupt. This interrupt is enabled when
11886 + * performing the PING protocol in Slave mode, when errors occur during
11887 + * either Slave mode or DMA mode, and during Start Split transactions.
11888 + */
11889 +static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *_hcd,
11890 + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
11891 +{
11892 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11893 + "ACK Received--\n", _hc->hc_num);
11894 +
11895 + if (_hc->do_split) {
11896 + /*
11897 + * Handle ACK on SSPLIT.
11898 + * ACK should not occur in CSPLIT.
11899 + */
11900 + if ((!_hc->ep_is_in) && (_hc->data_pid_start != DWC_OTG_HC_PID_SETUP)) {
11901 + _qtd->ssplit_out_xfer_count = _hc->xfer_len;
11902 + }
11903 + if (!(_hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !_hc->ep_is_in)) {
11904 + /* Don't need complete for isochronous out transfers. */
11905 + _qtd->complete_split = 1;
11906 + }
11907 +
11908 + /* ISOC OUT */
11909 + if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && !_hc->ep_is_in) {
11910 + switch (_hc->xact_pos) {
11911 + case DWC_HCSPLIT_XACTPOS_ALL:
11912 + break;
11913 + case DWC_HCSPLIT_XACTPOS_END:
11914 + _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
11915 + _qtd->isoc_split_offset = 0;
11916 + break;
11917 + case DWC_HCSPLIT_XACTPOS_BEGIN:
11918 + case DWC_HCSPLIT_XACTPOS_MID:
11919 + /*
11920 + * For BEGIN or MID, calculate the length for
11921 + * the next microframe to determine the correct
11922 + * SSPLIT token, either MID or END.
11923 + */
11924 + do {
11925 + struct usb_iso_packet_descriptor *frame_desc;
11926 +
11927 + frame_desc = &_qtd->urb->iso_frame_desc[_qtd->isoc_frame_index];
11928 + _qtd->isoc_split_offset += 188;
11929 +
11930 + if ((frame_desc->length - _qtd->isoc_split_offset) <= 188) {
11931 + _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END;
11932 + }
11933 + else {
11934 + _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID;
11935 + }
11936 +
11937 + } while(0);
11938 + break;
11939 + }
11940 + } else {
11941 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free);
11942 + }
11943 + } else {
11944 + _qtd->error_count = 0;
11945 +
11946 + if (_hc->qh->ping_state) {
11947 + _hc->qh->ping_state = 0;
11948 + /*
11949 + * Halt the channel so the transfer can be re-started
11950 + * from the appropriate point. This only happens in
11951 + * Slave mode. In DMA mode, the ping_state is cleared
11952 + * when the transfer is started because the core
11953 + * automatically executes the PING, then the transfer.
11954 + */
11955 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free);
11956 + } else {
11957 + halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
11958 + }
11959 + }
11960 +
11961 + /*
11962 + * If the ACK occurred when _not_ in the PING state, let the channel
11963 + * continue transferring data after clearing the error count.
11964 + */
11965 +
11966 + disable_hc_int(_hc_regs,ack);
11967 +
11968 + return 1;
11969 +}
11970 +
11971 +/**
11972 + * Handles a host channel NYET interrupt. This interrupt should only occur on
11973 + * Bulk and Control OUT endpoints and for complete split transactions. If a
11974 + * NYET occurs at the same time as a Transfer Complete interrupt, it is
11975 + * handled in the xfercomp interrupt handler, not here. This handler may be
11976 + * called in either DMA mode or Slave mode.
11977 + */
11978 +static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *_hcd,
11979 + dwc_hc_t *_hc,
11980 + dwc_otg_hc_regs_t *_hc_regs,
11981 + dwc_otg_qtd_t *_qtd, int *must_free)
11982 +{
11983 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11984 + "NYET Received--\n", _hc->hc_num);
11985 +
11986 + /*
11987 + * NYET on CSPLIT
11988 + * re-do the CSPLIT immediately on non-periodic
11989 + */
11990 + if ((_hc->do_split) && (_hc->complete_split)) {
11991 + if ((_hc->ep_type == DWC_OTG_EP_TYPE_INTR) ||
11992 + (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
11993 + int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
11994 +
11995 + if (dwc_full_frame_num(frnum) !=
11996 + dwc_full_frame_num(_hc->qh->sched_frame)) {
11997 + /*
11998 + * No longer in the same full speed frame.
11999 + * Treat this as a transaction error.
12000 + */
12001 +#if 0
12002 + /** @todo Fix system performance so this can
12003 + * be treated as an error. Right now complete
12004 + * splits cannot be scheduled precisely enough
12005 + * due to other system activity, so this error
12006 + * occurs regularly in Slave mode.
12007 + */
12008 + _qtd->error_count++;
12009 +#endif
12010 + _qtd->complete_split = 0;
12011 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free);
12012 + /** @todo add support for isoc release */
12013 + goto handle_nyet_done;
12014 + }
12015 + }
12016 +
12017 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET, must_free);
12018 + goto handle_nyet_done;
12019 + }
12020 +
12021 + _hc->qh->ping_state = 1;
12022 + _qtd->error_count = 0;
12023 +
12024 + update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, _qtd,
12025 + DWC_OTG_HC_XFER_NYET);
12026 + save_data_toggle(_hc, _hc_regs, _qtd);
12027 +
12028 + /*
12029 + * Halt the channel and re-start the transfer so the PING
12030 + * protocol will start.
12031 + */
12032 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET, must_free);
12033 +
12034 +handle_nyet_done:
12035 + disable_hc_int(_hc_regs,nyet);
12036 + clear_hc_int(_hc_regs, nyet);
12037 + return 1;
12038 +}
12039 +
12040 +/**
12041 + * Handles a host channel babble interrupt. This handler may be called in
12042 + * either DMA mode or Slave mode.
12043 + */
12044 +static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *_hcd,
12045 + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12046 +{
12047 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12048 + "Babble Error--\n", _hc->hc_num);
12049 + if (_hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
12050 + dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EOVERFLOW);
12051 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_BABBLE_ERR, must_free);
12052 + } else {
12053 + dwc_otg_halt_status_e halt_status;
12054 + halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
12055 + DWC_OTG_HC_XFER_BABBLE_ERR);
12056 + halt_channel(_hcd, _hc, _qtd, halt_status, must_free);
12057 + }
12058 + disable_hc_int(_hc_regs,bblerr);
12059 + return 1;
12060 +}
12061 +
12062 +/**
12063 + * Handles a host channel AHB error interrupt. This handler is only called in
12064 + * DMA mode.
12065 + */
12066 +static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *_hcd,
12067 + dwc_hc_t *_hc,
12068 + dwc_otg_hc_regs_t *_hc_regs,
12069 + dwc_otg_qtd_t *_qtd)
12070 +{
12071 + hcchar_data_t hcchar;
12072 + hcsplt_data_t hcsplt;
12073 + hctsiz_data_t hctsiz;
12074 + uint32_t hcdma;
12075 + struct urb *urb = _qtd->urb;
12076 +
12077 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12078 + "AHB Error--\n", _hc->hc_num);
12079 +
12080 + hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar);
12081 + hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt);
12082 + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
12083 + hcdma = dwc_read_reg32(&_hc_regs->hcdma);
12084 +
12085 + DWC_ERROR("AHB ERROR, Channel %d\n", _hc->hc_num);
12086 + DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
12087 + DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
12088 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
12089 + DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe));
12090 + DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
12091 + (usb_pipein(urb->pipe) ? "IN" : "OUT"));
12092 + DWC_ERROR(" Endpoint type: %s\n",
12093 + ({char *pipetype;
12094 + switch (usb_pipetype(urb->pipe)) {
12095 + case PIPE_CONTROL: pipetype = "CONTROL"; break;
12096 + case PIPE_BULK: pipetype = "BULK"; break;
12097 + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
12098 + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
12099 + default: pipetype = "UNKNOWN"; break;
12100 + }; pipetype;}));
12101 + DWC_ERROR(" Speed: %s\n",
12102 + ({char *speed;
12103 + switch (urb->dev->speed) {
12104 + case USB_SPEED_HIGH: speed = "HIGH"; break;
12105 + case USB_SPEED_FULL: speed = "FULL"; break;
12106 + case USB_SPEED_LOW: speed = "LOW"; break;
12107 + default: speed = "UNKNOWN"; break;
12108 + }; speed;}));
12109 + DWC_ERROR(" Max packet size: %d\n",
12110 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
12111 + DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length);
12112 + DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
12113 + urb->transfer_buffer, (void *)(u32)urb->transfer_dma);
12114 + DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
12115 + urb->setup_packet, (void *)(u32)urb->setup_dma);
12116 + DWC_ERROR(" Interval: %d\n", urb->interval);
12117 +
12118 + dwc_otg_hcd_complete_urb(_hcd, urb, -EIO);
12119 +
12120 + /*
12121 + * Force a channel halt. Don't call halt_channel because that won't
12122 + * write to the HCCHARn register in DMA mode to force the halt.
12123 + */
12124 + dwc_otg_hc_halt(_hcd->core_if, _hc, DWC_OTG_HC_XFER_AHB_ERR);
12125 +
12126 + disable_hc_int(_hc_regs,ahberr);
12127 + return 1;
12128 +}
12129 +
12130 +/**
12131 + * Handles a host channel transaction error interrupt. This handler may be
12132 + * called in either DMA mode or Slave mode.
12133 + */
12134 +static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *_hcd,
12135 + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12136 +{
12137 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12138 + "Transaction Error--\n", _hc->hc_num);
12139 +
12140 + switch (usb_pipetype(_qtd->urb->pipe)) {
12141 + case PIPE_CONTROL:
12142 + case PIPE_BULK:
12143 + _qtd->error_count++;
12144 + if (!_hc->qh->ping_state) {
12145 + update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb,
12146 + _qtd, DWC_OTG_HC_XFER_XACT_ERR);
12147 + save_data_toggle(_hc, _hc_regs, _qtd);
12148 + if (!_hc->ep_is_in && _qtd->urb->dev->speed == USB_SPEED_HIGH) {
12149 + _hc->qh->ping_state = 1;
12150 + }
12151 + }
12152 +
12153 + /*
12154 + * Halt the channel so the transfer can be re-started from
12155 + * the appropriate point or the PING protocol will start.
12156 + */
12157 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free);
12158 + break;
12159 + case PIPE_INTERRUPT:
12160 + _qtd->error_count++;
12161 + if ((_hc->do_split) && (_hc->complete_split)) {
12162 + _qtd->complete_split = 0;
12163 + }
12164 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free);
12165 + break;
12166 + case PIPE_ISOCHRONOUS:
12167 + {
12168 + dwc_otg_halt_status_e halt_status;
12169 + halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
12170 + DWC_OTG_HC_XFER_XACT_ERR);
12171 +
12172 + halt_channel(_hcd, _hc, _qtd, halt_status, must_free);
12173 + }
12174 + break;
12175 + }
12176 +
12177 +
12178 + disable_hc_int(_hc_regs,xacterr);
12179 +
12180 + return 1;
12181 +}
12182 +
12183 +/**
12184 + * Handles a host channel frame overrun interrupt. This handler may be called
12185 + * in either DMA mode or Slave mode.
12186 + */
12187 +static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *_hcd,
12188 + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12189 +{
12190 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12191 + "Frame Overrun--\n", _hc->hc_num);
12192 +
12193 + switch (usb_pipetype(_qtd->urb->pipe)) {
12194 + case PIPE_CONTROL:
12195 + case PIPE_BULK:
12196 + break;
12197 + case PIPE_INTERRUPT:
12198 + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN, must_free);
12199 + break;
12200 + case PIPE_ISOCHRONOUS:
12201 + {
12202 + dwc_otg_halt_status_e halt_status;
12203 + halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
12204 + DWC_OTG_HC_XFER_FRAME_OVERRUN);
12205 +
12206 + halt_channel(_hcd, _hc, _qtd, halt_status, must_free);
12207 + }
12208 + break;
12209 + }
12210 +
12211 + disable_hc_int(_hc_regs,frmovrun);
12212 +
12213 + return 1;
12214 +}
12215 +
12216 +/**
12217 + * Handles a host channel data toggle error interrupt. This handler may be
12218 + * called in either DMA mode or Slave mode.
12219 + */
12220 +static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *_hcd,
12221 + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12222 +{
12223 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12224 + "Data Toggle Error--\n", _hc->hc_num);
12225 +
12226 + if (_hc->ep_is_in) {
12227 + _qtd->error_count = 0;
12228 + } else {
12229 + DWC_ERROR("Data Toggle Error on OUT transfer,"
12230 + "channel %d\n", _hc->hc_num);
12231 + }
12232 +
12233 + disable_hc_int(_hc_regs,datatglerr);
12234 +
12235 + return 1;
12236 +}
12237 +
12238 +#ifdef DEBUG
12239 +/**
12240 + * This function is for debug only. It checks that a valid halt status is set
12241 + * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
12242 + * taken and a warning is issued.
12243 + * @return 1 if halt status is ok, 0 otherwise.
12244 + */
12245 +static inline int halt_status_ok(dwc_otg_hcd_t *_hcd,
12246 + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12247 +{
12248 + hcchar_data_t hcchar;
12249 + hctsiz_data_t hctsiz;
12250 + hcint_data_t hcint;
12251 + hcintmsk_data_t hcintmsk;
12252 + hcsplt_data_t hcsplt;
12253 +
12254 + if (_hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
12255 + /*
12256 + * This code is here only as a check. This condition should
12257 + * never happen. Ignore the halt if it does occur.
12258 + */
12259 + hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar);
12260 + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
12261 + hcint.d32 = dwc_read_reg32(&_hc_regs->hcint);
12262 + hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk);
12263 + hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt);
12264 + DWC_WARN("%s: _hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
12265 + "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
12266 + "hcint 0x%08x, hcintmsk 0x%08x, "
12267 + "hcsplt 0x%08x, qtd->complete_split %d\n",
12268 + __func__, _hc->hc_num, hcchar.d32, hctsiz.d32,
12269 + hcint.d32, hcintmsk.d32,
12270 + hcsplt.d32, _qtd->complete_split);
12271 +
12272 + DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
12273 + __func__, _hc->hc_num);
12274 + DWC_WARN("\n");
12275 + clear_hc_int(_hc_regs,chhltd);
12276 + return 0;
12277 + }
12278 +
12279 + /*
12280 + * This code is here only as a check. hcchar.chdis should
12281 + * never be set when the halt interrupt occurs. Halt the
12282 + * channel again if it does occur.
12283 + */
12284 + hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar);
12285 + if (hcchar.b.chdis) {
12286 + DWC_WARN("%s: hcchar.chdis set unexpectedly, "
12287 + "hcchar 0x%08x, trying to halt again\n",
12288 + __func__, hcchar.d32);
12289 + clear_hc_int(_hc_regs,chhltd);
12290 + _hc->halt_pending = 0;
12291 + halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
12292 + return 0;
12293 + }
12294 +
12295 + return 1;
12296 +}
12297 +#endif
12298 +
12299 +/**
12300 + * Handles a host Channel Halted interrupt in DMA mode. This handler
12301 + * determines the reason the channel halted and proceeds accordingly.
12302 + */
12303 +static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *_hcd,
12304 + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12305 +{
12306 + hcint_data_t hcint;
12307 + hcintmsk_data_t hcintmsk;
12308 +
12309 + if (_hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
12310 + _hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
12311 + /*
12312 + * Just release the channel. A dequeue can happen on a
12313 + * transfer timeout. In the case of an AHB Error, the channel
12314 + * was forced to halt because there's no way to gracefully
12315 + * recover.
12316 + */
12317 + release_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
12318 + return;
12319 + }
12320 +
12321 + /* Read the HCINTn register to determine the cause for the halt. */
12322 + hcint.d32 = dwc_read_reg32(&_hc_regs->hcint);
12323 + hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk);
12324 +
12325 + if (hcint.b.xfercomp) {
12326 + /** @todo This is here because of a possible hardware bug. Spec
12327 + * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
12328 + * interrupt w/ACK bit set should occur, but I only see the
12329 + * XFERCOMP bit, even with it masked out. This is a workaround
12330 + * for that behavior. Should fix this when hardware is fixed.
12331 + */
12332 + if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!_hc->ep_is_in)) {
12333 + handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12334 + }
12335 + handle_hc_xfercomp_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12336 + } else if (hcint.b.stall) {
12337 + handle_hc_stall_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12338 + } else if (hcint.b.xacterr) {
12339 + /*
12340 + * Must handle xacterr before nak or ack. Could get a xacterr
12341 + * at the same time as either of these on a BULK/CONTROL OUT
12342 + * that started with a PING. The xacterr takes precedence.
12343 + */
12344 + handle_hc_xacterr_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12345 + } else if (hcint.b.nyet) {
12346 + /*
12347 + * Must handle nyet before nak or ack. Could get a nyet at the
12348 + * same time as either of those on a BULK/CONTROL OUT that
12349 + * started with a PING. The nyet takes precedence.
12350 + */
12351 + handle_hc_nyet_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12352 + } else if (hcint.b.bblerr) {
12353 + handle_hc_babble_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12354 + } else if (hcint.b.frmovrun) {
12355 + handle_hc_frmovrun_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12356 + } else if (hcint.b.datatglerr) {
12357 + handle_hc_datatglerr_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12358 + _hc->qh->data_toggle = 0;
12359 + halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
12360 + } else if (hcint.b.nak && !hcintmsk.b.nak) {
12361 + /*
12362 + * If nak is not masked, it's because a non-split IN transfer
12363 + * is in an error state. In that case, the nak is handled by
12364 + * the nak interrupt handler, not here. Handle nak here for
12365 + * BULK/CONTROL OUT transfers, which halt on a NAK to allow
12366 + * rewinding the buffer pointer.
12367 + */
12368 + handle_hc_nak_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12369 + } else if (hcint.b.ack && !hcintmsk.b.ack) {
12370 + /*
12371 + * If ack is not masked, it's because a non-split IN transfer
12372 + * is in an error state. In that case, the ack is handled by
12373 + * the ack interrupt handler, not here. Handle ack here for
12374 + * split transfers. Start splits halt on ACK.
12375 + */
12376 + handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12377 + } else {
12378 + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
12379 + _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
12380 + /*
12381 + * A periodic transfer halted with no other channel
12382 + * interrupts set. Assume it was halted by the core
12383 + * because it could not be completed in its scheduled
12384 + * (micro)frame.
12385 + */
12386 +#ifdef DEBUG
12387 + DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
12388 + __func__, _hc->hc_num);
12389 +#endif /* */
12390 + halt_channel(_hcd, _hc, _qtd,
12391 + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, must_free);
12392 + } else {
12393 +#ifdef DEBUG
12394 + DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
12395 + "for halting is unknown, nyet %d, hcint 0x%08x, intsts 0x%08x\n",
12396 + __func__, _hc->hc_num, hcint.b.nyet, hcint.d32,
12397 + dwc_read_reg32(&_hcd->core_if->core_global_regs->gintsts));
12398 +#endif
12399 + halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
12400 + }
12401 + }
12402 +}
12403 +
12404 +/**
12405 + * Handles a host channel Channel Halted interrupt.
12406 + *
12407 + * In slave mode, this handler is called only when the driver specifically
12408 + * requests a halt. This occurs during handling other host channel interrupts
12409 + * (e.g. nak, xacterr, stall, nyet, etc.).
12410 + *
12411 + * In DMA mode, this is the interrupt that occurs when the core has finished
12412 + * processing a transfer on a channel. Other host channel interrupts (except
12413 + * ahberr) are disabled in DMA mode.
12414 + */
12415 +static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *_hcd,
12416 + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12417 +{
12418 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12419 + "Channel Halted--\n", _hc->hc_num);
12420 +
12421 + if (_hcd->core_if->dma_enable) {
12422 + handle_hc_chhltd_intr_dma(_hcd, _hc, _hc_regs, _qtd, must_free);
12423 + } else {
12424 +#ifdef DEBUG
12425 + if (!halt_status_ok(_hcd, _hc, _hc_regs, _qtd, must_free)) {
12426 + return 1;
12427 + }
12428 +#endif /* */
12429 + release_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
12430 + }
12431 +
12432 + return 1;
12433 +}
12434 +
12435 +/** Handles interrupt for a specific Host Channel */
12436 +int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num)
12437 +{
12438 + int must_free = 0;
12439 + int retval = 0;
12440 + hcint_data_t hcint;
12441 + hcintmsk_data_t hcintmsk;
12442 + dwc_hc_t *hc;
12443 + dwc_otg_hc_regs_t *hc_regs;
12444 + dwc_otg_qtd_t *qtd;
12445 +
12446 + DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", _num);
12447 +
12448 + hc = _dwc_otg_hcd->hc_ptr_array[_num];
12449 + hc_regs = _dwc_otg_hcd->core_if->host_if->hc_regs[_num];
12450 + qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
12451 +
12452 + hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
12453 + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
12454 + DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
12455 + hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
12456 + hcint.d32 = hcint.d32 & hcintmsk.d32;
12457 +
12458 + if (!_dwc_otg_hcd->core_if->dma_enable) {
12459 + if ((hcint.b.chhltd) && (hcint.d32 != 0x2)) {
12460 + hcint.b.chhltd = 0;
12461 + }
12462 + }
12463 +
12464 + if (hcint.b.xfercomp) {
12465 + retval |= handle_hc_xfercomp_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12466 + /*
12467 + * If NYET occurred at same time as Xfer Complete, the NYET is
12468 + * handled by the Xfer Complete interrupt handler. Don't want
12469 + * to call the NYET interrupt handler in this case.
12470 + */
12471 + hcint.b.nyet = 0;
12472 + }
12473 + if (hcint.b.chhltd) {
12474 + retval |= handle_hc_chhltd_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12475 + }
12476 + if (hcint.b.ahberr) {
12477 + retval |= handle_hc_ahberr_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
12478 + }
12479 + if (hcint.b.stall) {
12480 + retval |= handle_hc_stall_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12481 + }
12482 + if (hcint.b.nak) {
12483 + retval |= handle_hc_nak_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12484 + }
12485 + if (hcint.b.ack) {
12486 + retval |= handle_hc_ack_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12487 + }
12488 + if (hcint.b.nyet) {
12489 + retval |= handle_hc_nyet_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12490 + }
12491 + if (hcint.b.xacterr) {
12492 + retval |= handle_hc_xacterr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12493 + }
12494 + if (hcint.b.bblerr) {
12495 + retval |= handle_hc_babble_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12496 + }
12497 + if (hcint.b.frmovrun) {
12498 + retval |= handle_hc_frmovrun_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12499 + }
12500 + if (hcint.b.datatglerr) {
12501 + retval |= handle_hc_datatglerr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12502 + }
12503 +
12504 + /*
12505 + * Logic to free the qtd here, at the end of the hc intr
12506 + * processing, if the handling of this interrupt determined
12507 + * that it needs to be freed.
12508 + */
12509 + if (must_free) {
12510 + /* Free the qtd here now that we are done using it. */
12511 + dwc_otg_hcd_qtd_free(qtd);
12512 + }
12513 + return retval;
12514 +}
12515 +
12516 +#endif /* DWC_DEVICE_ONLY */
12517 --- /dev/null
12518 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
12519 @@ -0,0 +1,794 @@
12520 +/* ==========================================================================
12521 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
12522 + * $Revision: 1.1.1.1 $
12523 + * $Date: 2009-04-17 06:15:34 $
12524 + * $Change: 537387 $
12525 + *
12526 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
12527 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
12528 + * otherwise expressly agreed to in writing between Synopsys and you.
12529 + *
12530 + * The Software IS NOT an item of Licensed Software or Licensed Product under
12531 + * any End User Software License Agreement or Agreement for Licensed Product
12532 + * with Synopsys or any supplement thereto. You are permitted to use and
12533 + * redistribute this Software in source and binary forms, with or without
12534 + * modification, provided that redistributions of source code must retain this
12535 + * notice. You may not view, use, disclose, copy or distribute this file or
12536 + * any information contained herein except pursuant to this license grant from
12537 + * Synopsys. If you do not agree with this notice, including the disclaimer
12538 + * below, then you are not authorized to use the Software.
12539 + *
12540 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
12541 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
12542 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
12543 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
12544 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
12545 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12546 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
12547 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
12548 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
12549 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
12550 + * DAMAGE.
12551 + * ========================================================================== */
12552 +#ifndef DWC_DEVICE_ONLY
12553 +
12554 +/**
12555 + * @file
12556 + *
12557 + * This file contains the functions to manage Queue Heads and Queue
12558 + * Transfer Descriptors.
12559 + */
12560 +#include <linux/kernel.h>
12561 +#include <linux/module.h>
12562 +#include <linux/moduleparam.h>
12563 +#include <linux/init.h>
12564 +#include <linux/device.h>
12565 +#include <linux/errno.h>
12566 +#include <linux/list.h>
12567 +#include <linux/interrupt.h>
12568 +#include <linux/string.h>
12569 +
12570 +#include "dwc_otg_driver.h"
12571 +#include "dwc_otg_hcd.h"
12572 +#include "dwc_otg_regs.h"
12573 +
12574 +/**
12575 + * This function allocates and initializes a QH.
12576 + *
12577 + * @param _hcd The HCD state structure for the DWC OTG controller.
12578 + * @param[in] _urb Holds the information about the device/endpoint that we need
12579 + * to initialize the QH.
12580 + *
12581 + * @return Returns pointer to the newly allocated QH, or NULL on error. */
12582 +dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb)
12583 +{
12584 + dwc_otg_qh_t *qh;
12585 +
12586 + /* Allocate memory */
12587 + /** @todo add memflags argument */
12588 + qh = dwc_otg_hcd_qh_alloc ();
12589 + if (qh == NULL) {
12590 + return NULL;
12591 + }
12592 +
12593 + dwc_otg_hcd_qh_init (_hcd, qh, _urb);
12594 + return qh;
12595 +}
12596 +
12597 +/** Free each QTD in the QH's QTD-list then free the QH. QH should already be
12598 + * removed from a list. QTD list should already be empty if called from URB
12599 + * Dequeue.
12600 + *
12601 + * @param[in] _qh The QH to free.
12602 + */
12603 +void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh)
12604 +{
12605 + dwc_otg_qtd_t *qtd;
12606 + struct list_head *pos;
12607 + unsigned long flags;
12608 +
12609 + /* Free each QTD in the QTD list */
12610 + local_irq_save (flags);
12611 + for (pos = _qh->qtd_list.next;
12612 + pos != &_qh->qtd_list;
12613 + pos = _qh->qtd_list.next)
12614 + {
12615 + list_del (pos);
12616 + qtd = dwc_list_to_qtd (pos);
12617 + dwc_otg_hcd_qtd_free (qtd);
12618 + }
12619 + local_irq_restore (flags);
12620 +
12621 + kfree (_qh);
12622 + return;
12623 +}
12624 +
12625 +/** Initializes a QH structure.
12626 + *
12627 + * @param[in] _hcd The HCD state structure for the DWC OTG controller.
12628 + * @param[in] _qh The QH to init.
12629 + * @param[in] _urb Holds the information about the device/endpoint that we need
12630 + * to initialize the QH. */
12631 +#define SCHEDULE_SLOP 10
12632 +void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb)
12633 +{
12634 + memset (_qh, 0, sizeof (dwc_otg_qh_t));
12635 +
12636 + /* Initialize QH */
12637 + switch (usb_pipetype(_urb->pipe)) {
12638 + case PIPE_CONTROL:
12639 + _qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
12640 + break;
12641 + case PIPE_BULK:
12642 + _qh->ep_type = USB_ENDPOINT_XFER_BULK;
12643 + break;
12644 + case PIPE_ISOCHRONOUS:
12645 + _qh->ep_type = USB_ENDPOINT_XFER_ISOC;
12646 + break;
12647 + case PIPE_INTERRUPT:
12648 + _qh->ep_type = USB_ENDPOINT_XFER_INT;
12649 + break;
12650 + }
12651 +
12652 + _qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0;
12653 +
12654 + _qh->data_toggle = DWC_OTG_HC_PID_DATA0;
12655 + _qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
12656 + INIT_LIST_HEAD(&_qh->qtd_list);
12657 + INIT_LIST_HEAD(&_qh->qh_list_entry);
12658 + _qh->channel = NULL;
12659 +
12660 + /* FS/LS Enpoint on HS Hub
12661 + * NOT virtual root hub */
12662 + _qh->do_split = 0;
12663 + _qh->speed = _urb->dev->speed;
12664 + if (((_urb->dev->speed == USB_SPEED_LOW) ||
12665 + (_urb->dev->speed == USB_SPEED_FULL)) &&
12666 + (_urb->dev->tt) && (_urb->dev->tt->hub) && (_urb->dev->tt->hub->devnum != 1)) {
12667 + DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
12668 + usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
12669 + _urb->dev->ttport);
12670 + _qh->do_split = 1;
12671 + }
12672 +
12673 + if (_qh->ep_type == USB_ENDPOINT_XFER_INT ||
12674 + _qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
12675 + /* Compute scheduling parameters once and save them. */
12676 + hprt0_data_t hprt;
12677 +
12678 + /** @todo Account for split transfers in the bus time. */
12679 + int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp);
12680 + _qh->usecs = NS_TO_US(usb_calc_bus_time(_urb->dev->speed,
12681 + usb_pipein(_urb->pipe),
12682 + (_qh->ep_type == USB_ENDPOINT_XFER_ISOC),bytecount));
12683 +
12684 + /* Start in a slightly future (micro)frame. */
12685 + _qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number, SCHEDULE_SLOP);
12686 + _qh->interval = _urb->interval;
12687 +#if 0
12688 + /* Increase interrupt polling rate for debugging. */
12689 + if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
12690 + _qh->interval = 8;
12691 + }
12692 +#endif
12693 + hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0);
12694 + if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
12695 + ((_urb->dev->speed == USB_SPEED_LOW) ||
12696 + (_urb->dev->speed == USB_SPEED_FULL)))
12697 + {
12698 + _qh->interval *= 8;
12699 + _qh->sched_frame |= 0x7;
12700 + _qh->start_split_frame = _qh->sched_frame;
12701 + }
12702 + }
12703 +
12704 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
12705 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh);
12706 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
12707 + _urb->dev->devnum);
12708 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
12709 + usb_pipeendpoint(_urb->pipe),
12710 + usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
12711 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n",
12712 + ({ char *speed; switch (_urb->dev->speed) {
12713 + case USB_SPEED_LOW: speed = "low"; break;
12714 + case USB_SPEED_FULL: speed = "full"; break;
12715 + case USB_SPEED_HIGH: speed = "high"; break;
12716 + default: speed = "?"; break;
12717 + }; speed;}));
12718 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",
12719 + ({ char *type; switch (_qh->ep_type) {
12720 + case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break;
12721 + case USB_ENDPOINT_XFER_INT: type = "interrupt"; break;
12722 + case USB_ENDPOINT_XFER_CONTROL: type = "control"; break;
12723 + case USB_ENDPOINT_XFER_BULK: type = "bulk"; break;
12724 + default: type = "?"; break;
12725 + }; type;}));
12726 +#ifdef DEBUG
12727 + if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
12728 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
12729 + _qh->usecs);
12730 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
12731 + _qh->interval);
12732 + }
12733 +#endif
12734 +
12735 + return;
12736 +}
12737 +
12738 +/**
12739 + * Microframe scheduler
12740 + * track the total use in hcd->frame_usecs
12741 + * keep each qh use in qh->frame_usecs
12742 + * when surrendering the qh then donate the time back
12743 + */
12744 +const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
12745 +
12746 +/*
12747 + * called from dwc_otg_hcd.c:dwc_otg_hcd_init
12748 + */
12749 +int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
12750 +{
12751 + int i;
12752 + for (i=0; i<8; i++) {
12753 + _hcd->frame_usecs[i] = max_uframe_usecs[i];
12754 + }
12755 + return 0;
12756 +}
12757 +
12758 +static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
12759 +{
12760 + int i;
12761 + unsigned short utime;
12762 + int t_left;
12763 + int ret;
12764 + int done;
12765 +
12766 + ret = -1;
12767 + utime = _qh->usecs;
12768 + t_left = utime;
12769 + i = 0;
12770 + done = 0;
12771 + while (done == 0) {
12772 + /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
12773 + if (utime <= _hcd->frame_usecs[i]) {
12774 + _hcd->frame_usecs[i] -= utime;
12775 + _qh->frame_usecs[i] += utime;
12776 + t_left -= utime;
12777 + ret = i;
12778 + done = 1;
12779 + return ret;
12780 + } else {
12781 + i++;
12782 + if (i == 8) {
12783 + done = 1;
12784 + ret = -1;
12785 + }
12786 + }
12787 + }
12788 + return ret;
12789 +}
12790 +
12791 +/*
12792 + * use this for FS apps that can span multiple uframes
12793 + */
12794 +static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
12795 +{
12796 + int i;
12797 + int j;
12798 + unsigned short utime;
12799 + int t_left;
12800 + int ret;
12801 + int done;
12802 + unsigned short xtime;
12803 +
12804 + ret = -1;
12805 + utime = _qh->usecs;
12806 + t_left = utime;
12807 + i = 0;
12808 + done = 0;
12809 +loop:
12810 + while (done == 0) {
12811 + if(_hcd->frame_usecs[i] <= 0) {
12812 + i++;
12813 + if (i == 8) {
12814 + done = 1;
12815 + ret = -1;
12816 + }
12817 + goto loop;
12818 + }
12819 +
12820 + /*
12821 + * we need n consequtive slots
12822 + * so use j as a start slot j plus j+1 must be enough time (for now)
12823 + */
12824 + xtime= _hcd->frame_usecs[i];
12825 + for (j = i+1 ; j < 8 ; j++ ) {
12826 + /*
12827 + * if we add this frame remaining time to xtime we may
12828 + * be OK, if not we need to test j for a complete frame
12829 + */
12830 + if ((xtime+_hcd->frame_usecs[j]) < utime) {
12831 + if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
12832 + j = 8;
12833 + ret = -1;
12834 + continue;
12835 + }
12836 + }
12837 + if (xtime >= utime) {
12838 + ret = i;
12839 + j = 8; /* stop loop with a good value ret */
12840 + continue;
12841 + }
12842 + /* add the frame time to x time */
12843 + xtime += _hcd->frame_usecs[j];
12844 + /* we must have a fully available next frame or break */
12845 + if ((xtime < utime)
12846 + && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
12847 + ret = -1;
12848 + j = 8; /* stop loop with a bad value ret */
12849 + continue;
12850 + }
12851 + }
12852 + if (ret >= 0) {
12853 + t_left = utime;
12854 + for (j = i; (t_left>0) && (j < 8); j++ ) {
12855 + t_left -= _hcd->frame_usecs[j];
12856 + if ( t_left <= 0 ) {
12857 + _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
12858 + _hcd->frame_usecs[j]= -t_left;
12859 + ret = i;
12860 + done = 1;
12861 + } else {
12862 + _qh->frame_usecs[j] += _hcd->frame_usecs[j];
12863 + _hcd->frame_usecs[j] = 0;
12864 + }
12865 + }
12866 + } else {
12867 + i++;
12868 + if (i == 8) {
12869 + done = 1;
12870 + ret = -1;
12871 + }
12872 + }
12873 + }
12874 + return ret;
12875 +}
12876 +
12877 +static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
12878 +{
12879 + int ret;
12880 + ret = -1;
12881 +
12882 + if (_qh->speed == USB_SPEED_HIGH) {
12883 + /* if this is a hs transaction we need a full frame */
12884 + ret = find_single_uframe(_hcd, _qh);
12885 + } else {
12886 + /* if this is a fs transaction we may need a sequence of frames */
12887 + ret = find_multi_uframe(_hcd, _qh);
12888 + }
12889 + return ret;
12890 +}
12891 +
12892 +/**
12893 + * Checks that the max transfer size allowed in a host channel is large enough
12894 + * to handle the maximum data transfer in a single (micro)frame for a periodic
12895 + * transfer.
12896 + *
12897 + * @param _hcd The HCD state structure for the DWC OTG controller.
12898 + * @param _qh QH for a periodic endpoint.
12899 + *
12900 + * @return 0 if successful, negative error code otherwise.
12901 + */
12902 +static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
12903 +{
12904 + int status;
12905 + uint32_t max_xfer_size;
12906 + uint32_t max_channel_xfer_size;
12907 +
12908 + status = 0;
12909 +
12910 + max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp);
12911 + max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size;
12912 +
12913 + if (max_xfer_size > max_channel_xfer_size) {
12914 + DWC_NOTICE("%s: Periodic xfer length %d > "
12915 + "max xfer length for channel %d\n",
12916 + __func__, max_xfer_size, max_channel_xfer_size);
12917 + status = -ENOSPC;
12918 + }
12919 +
12920 + return status;
12921 +}
12922 +
12923 +/**
12924 + * Schedules an interrupt or isochronous transfer in the periodic schedule.
12925 + *
12926 + * @param _hcd The HCD state structure for the DWC OTG controller.
12927 + * @param _qh QH for the periodic transfer. The QH should already contain the
12928 + * scheduling information.
12929 + *
12930 + * @return 0 if successful, negative error code otherwise.
12931 + */
12932 +static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
12933 +{
12934 + int status = 0;
12935 +
12936 + int frame;
12937 + status = find_uframe(_hcd, _qh);
12938 + frame = -1;
12939 + if (status == 0) {
12940 + frame = 7;
12941 + } else {
12942 + if (status > 0 )
12943 + frame = status-1;
12944 + }
12945 +
12946 + /* Set the new frame up */
12947 + if (frame > -1) {
12948 + _qh->sched_frame &= ~0x7;
12949 + _qh->sched_frame |= (frame & 7);
12950 + }
12951 +
12952 + if (status != -1 )
12953 + status = 0;
12954 + if (status) {
12955 + DWC_NOTICE("%s: Insufficient periodic bandwidth for "
12956 + "periodic transfer.\n", __func__);
12957 + return status;
12958 + }
12959 +
12960 + status = check_max_xfer_size(_hcd, _qh);
12961 + if (status) {
12962 + DWC_NOTICE("%s: Channel max transfer size too small "
12963 + "for periodic transfer.\n", __func__);
12964 + return status;
12965 + }
12966 +
12967 + /* Always start in the inactive schedule. */
12968 + list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive);
12969 +
12970 +
12971 + /* Update claimed usecs per (micro)frame. */
12972 + _hcd->periodic_usecs += _qh->usecs;
12973 +
12974 + /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
12975 + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval;
12976 + if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
12977 + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++;
12978 + DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
12979 + _qh, _qh->usecs, _qh->interval);
12980 + } else {
12981 + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++;
12982 + DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
12983 + _qh, _qh->usecs, _qh->interval);
12984 + }
12985 +
12986 + return status;
12987 +}
12988 +
12989 +/**
12990 + * This function adds a QH to either the non periodic or periodic schedule if
12991 + * it is not already in the schedule. If the QH is already in the schedule, no
12992 + * action is taken.
12993 + *
12994 + * @return 0 if successful, negative error code otherwise.
12995 + */
12996 +int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
12997 +{
12998 + unsigned long flags;
12999 + int status = 0;
13000 +
13001 + local_irq_save(flags);
13002 +
13003 + if (!list_empty(&_qh->qh_list_entry)) {
13004 + /* QH already in a schedule. */
13005 + goto done;
13006 + }
13007 +
13008 + /* Add the new QH to the appropriate schedule */
13009 + if (dwc_qh_is_non_per(_qh)) {
13010 + /* Always start in the inactive schedule. */
13011 + list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive);
13012 + } else {
13013 + status = schedule_periodic(_hcd, _qh);
13014 + }
13015 +
13016 + done:
13017 + local_irq_restore(flags);
13018 +
13019 + return status;
13020 +}
13021 +
13022 +/**
13023 + * This function adds a QH to the non periodic deferred schedule.
13024 + *
13025 + * @return 0 if successful, negative error code otherwise.
13026 + */
13027 +int dwc_otg_hcd_qh_add_deferred(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
13028 +{
13029 + unsigned long flags;
13030 + local_irq_save(flags);
13031 + if (!list_empty(&_qh->qh_list_entry)) {
13032 + /* QH already in a schedule. */
13033 + goto done;
13034 + }
13035 +
13036 + /* Add the new QH to the non periodic deferred schedule */
13037 + if (dwc_qh_is_non_per(_qh)) {
13038 + list_add_tail(&_qh->qh_list_entry,
13039 + &_hcd->non_periodic_sched_deferred);
13040 + }
13041 +done:
13042 + local_irq_restore(flags);
13043 + return 0;
13044 +}
13045 +
13046 +/**
13047 + * Removes an interrupt or isochronous transfer from the periodic schedule.
13048 + *
13049 + * @param _hcd The HCD state structure for the DWC OTG controller.
13050 + * @param _qh QH for the periodic transfer.
13051 + */
13052 +static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
13053 +{
13054 + int i;
13055 + list_del_init(&_qh->qh_list_entry);
13056 +
13057 +
13058 + /* Update claimed usecs per (micro)frame. */
13059 + _hcd->periodic_usecs -= _qh->usecs;
13060 +
13061 + for (i = 0; i < 8; i++) {
13062 + _hcd->frame_usecs[i] += _qh->frame_usecs[i];
13063 + _qh->frame_usecs[i] = 0;
13064 + }
13065 + /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
13066 + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval;
13067 +
13068 + if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
13069 + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--;
13070 + DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
13071 + _qh, _qh->usecs, _qh->interval);
13072 + } else {
13073 + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--;
13074 + DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
13075 + _qh, _qh->usecs, _qh->interval);
13076 + }
13077 +}
13078 +
13079 +/**
13080 + * Removes a QH from either the non-periodic or periodic schedule. Memory is
13081 + * not freed.
13082 + *
13083 + * @param[in] _hcd The HCD state structure.
13084 + * @param[in] _qh QH to remove from schedule. */
13085 +void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
13086 +{
13087 + unsigned long flags;
13088 +
13089 + local_irq_save(flags);
13090 +
13091 + if (list_empty(&_qh->qh_list_entry)) {
13092 + /* QH is not in a schedule. */
13093 + goto done;
13094 + }
13095 +
13096 + if (dwc_qh_is_non_per(_qh)) {
13097 + if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) {
13098 + _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
13099 + }
13100 + list_del_init(&_qh->qh_list_entry);
13101 + } else {
13102 + deschedule_periodic(_hcd, _qh);
13103 + }
13104 +
13105 + done:
13106 + local_irq_restore(flags);
13107 +}
13108 +
13109 +/**
13110 + * Defers a QH. For non-periodic QHs, removes the QH from the active
13111 + * non-periodic schedule. The QH is added to the deferred non-periodic
13112 + * schedule if any QTDs are still attached to the QH.
13113 + */
13114 +int dwc_otg_hcd_qh_deferr(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh, int delay)
13115 +{
13116 + int deact = 1;
13117 + unsigned long flags;
13118 + local_irq_save(flags);
13119 + if (dwc_qh_is_non_per(_qh)) {
13120 + _qh->sched_frame =
13121 + dwc_frame_num_inc(_hcd->frame_number,
13122 + delay);
13123 + _qh->channel = NULL;
13124 + _qh->qtd_in_process = NULL;
13125 + deact = 0;
13126 + dwc_otg_hcd_qh_remove(_hcd, _qh);
13127 + if (!list_empty(&_qh->qtd_list)) {
13128 + /* Add back to deferred non-periodic schedule. */
13129 + dwc_otg_hcd_qh_add_deferred(_hcd, _qh);
13130 + }
13131 + }
13132 + local_irq_restore(flags);
13133 + return deact;
13134 +}
13135 +
13136 +/**
13137 + * Deactivates a QH. For non-periodic QHs, removes the QH from the active
13138 + * non-periodic schedule. The QH is added to the inactive non-periodic
13139 + * schedule if any QTDs are still attached to the QH.
13140 + *
13141 + * For periodic QHs, the QH is removed from the periodic queued schedule. If
13142 + * there are any QTDs still attached to the QH, the QH is added to either the
13143 + * periodic inactive schedule or the periodic ready schedule and its next
13144 + * scheduled frame is calculated. The QH is placed in the ready schedule if
13145 + * the scheduled frame has been reached already. Otherwise it's placed in the
13146 + * inactive schedule. If there are no QTDs attached to the QH, the QH is
13147 + * completely removed from the periodic schedule.
13148 + */
13149 +void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split)
13150 +{
13151 + unsigned long flags;
13152 + local_irq_save(flags);
13153 +
13154 + if (dwc_qh_is_non_per(_qh)) {
13155 + dwc_otg_hcd_qh_remove(_hcd, _qh);
13156 + if (!list_empty(&_qh->qtd_list)) {
13157 + /* Add back to inactive non-periodic schedule. */
13158 + dwc_otg_hcd_qh_add(_hcd, _qh);
13159 + }
13160 + } else {
13161 + uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
13162 +
13163 + if (_qh->do_split) {
13164 + /* Schedule the next continuing periodic split transfer */
13165 + if (sched_next_periodic_split) {
13166 +
13167 + _qh->sched_frame = frame_number;
13168 + if (dwc_frame_num_le(frame_number,
13169 + dwc_frame_num_inc(_qh->start_split_frame, 1))) {
13170 + /*
13171 + * Allow one frame to elapse after start
13172 + * split microframe before scheduling
13173 + * complete split, but DONT if we are
13174 + * doing the next start split in the
13175 + * same frame for an ISOC out.
13176 + */
13177 + if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) {
13178 + _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1);
13179 + }
13180 + }
13181 + } else {
13182 + _qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame,
13183 + _qh->interval);
13184 + if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
13185 + _qh->sched_frame = frame_number;
13186 + }
13187 + _qh->sched_frame |= 0x7;
13188 + _qh->start_split_frame = _qh->sched_frame;
13189 + }
13190 + } else {
13191 + _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval);
13192 + if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
13193 + _qh->sched_frame = frame_number;
13194 + }
13195 + }
13196 +
13197 + if (list_empty(&_qh->qtd_list)) {
13198 + dwc_otg_hcd_qh_remove(_hcd, _qh);
13199 + } else {
13200 + /*
13201 + * Remove from periodic_sched_queued and move to
13202 + * appropriate queue.
13203 + */
13204 + if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
13205 + list_move(&_qh->qh_list_entry,
13206 + &_hcd->periodic_sched_ready);
13207 + } else {
13208 + list_move(&_qh->qh_list_entry,
13209 + &_hcd->periodic_sched_inactive);
13210 + }
13211 + }
13212 + }
13213 +
13214 + local_irq_restore(flags);
13215 +}
13216 +
13217 +/**
13218 + * This function allocates and initializes a QTD.
13219 + *
13220 + * @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up
13221 + * pointing to each other so each pair should have a unique correlation.
13222 + *
13223 + * @return Returns pointer to the newly allocated QTD, or NULL on error. */
13224 +dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb)
13225 +{
13226 + dwc_otg_qtd_t *qtd;
13227 +
13228 + qtd = dwc_otg_hcd_qtd_alloc ();
13229 + if (qtd == NULL) {
13230 + return NULL;
13231 + }
13232 +
13233 + dwc_otg_hcd_qtd_init (qtd, _urb);
13234 + return qtd;
13235 +}
13236 +
13237 +/**
13238 + * Initializes a QTD structure.
13239 + *
13240 + * @param[in] _qtd The QTD to initialize.
13241 + * @param[in] _urb The URB to use for initialization. */
13242 +void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb)
13243 +{
13244 + memset (_qtd, 0, sizeof (dwc_otg_qtd_t));
13245 + _qtd->urb = _urb;
13246 + if (usb_pipecontrol(_urb->pipe)) {
13247 + /*
13248 + * The only time the QTD data toggle is used is on the data
13249 + * phase of control transfers. This phase always starts with
13250 + * DATA1.
13251 + */
13252 + _qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
13253 + _qtd->control_phase = DWC_OTG_CONTROL_SETUP;
13254 + }
13255 +
13256 + /* start split */
13257 + _qtd->complete_split = 0;
13258 + _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
13259 + _qtd->isoc_split_offset = 0;
13260 +
13261 + /* Store the qtd ptr in the urb to reference what QTD. */
13262 + _urb->hcpriv = _qtd;
13263 + return;
13264 +}
13265 +
13266 +/**
13267 + * This function adds a QTD to the QTD-list of a QH. It will find the correct
13268 + * QH to place the QTD into. If it does not find a QH, then it will create a
13269 + * new QH. If the QH to which the QTD is added is not currently scheduled, it
13270 + * is placed into the proper schedule based on its EP type.
13271 + *
13272 + * @param[in] _qtd The QTD to add
13273 + * @param[in] _dwc_otg_hcd The DWC HCD structure
13274 + *
13275 + * @return 0 if successful, negative error code otherwise.
13276 + */
13277 +int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * _qtd, dwc_otg_hcd_t * _dwc_otg_hcd)
13278 +{
13279 + struct usb_host_endpoint *ep;
13280 + dwc_otg_qh_t *qh;
13281 + unsigned long flags;
13282 + int retval = 0;
13283 + struct urb *urb = _qtd->urb;
13284 +
13285 + local_irq_save(flags);
13286 +
13287 + /*
13288 + * Get the QH which holds the QTD-list to insert to. Create QH if it
13289 + * doesn't exist.
13290 + */
13291 + ep = dwc_urb_to_endpoint(urb);
13292 + qh = (dwc_otg_qh_t *)ep->hcpriv;
13293 + if (qh == NULL) {
13294 + qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb);
13295 + if (qh == NULL) {
13296 + retval = -1;
13297 + goto done;
13298 + }
13299 + ep->hcpriv = qh;
13300 + }
13301 +
13302 + _qtd->qtd_qh_ptr = qh;
13303 + retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh);
13304 + if (retval == 0) {
13305 + list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list);
13306 + }
13307 +
13308 + done:
13309 + local_irq_restore(flags);
13310 + return retval;
13311 +}
13312 +
13313 +#endif /* DWC_DEVICE_ONLY */
13314 --- /dev/null
13315 +++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c
13316 @@ -0,0 +1,100 @@
13317 +/******************************************************************************
13318 +**
13319 +** FILE NAME : dwc_otg_ifx.c
13320 +** PROJECT : Twinpass/Danube
13321 +** MODULES : DWC OTG USB
13322 +**
13323 +** DATE : 12 Auguest 2007
13324 +** AUTHOR : Sung Winder
13325 +** DESCRIPTION : Platform specific initialization.
13326 +** COPYRIGHT : Copyright (c) 2007
13327 +** Infineon Technologies AG
13328 +** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
13329 +** Hsin-chu City, 300 Taiwan.
13330 +**
13331 +** This program is free software; you can redistribute it and/or modify
13332 +** it under the terms of the GNU General Public License as published by
13333 +** the Free Software Foundation; either version 2 of the License, or
13334 +** (at your option) any later version.
13335 +**
13336 +** HISTORY
13337 +** $Date $Author $Comment
13338 +** 12 Auguest 2007 Sung Winder Initiate Version
13339 +*******************************************************************************/
13340 +#include "dwc_otg_ifx.h"
13341 +
13342 +#include <linux/platform_device.h>
13343 +#include <linux/kernel.h>
13344 +#include <linux/ioport.h>
13345 +#include <linux/gpio.h>
13346 +
13347 +#include <asm/io.h>
13348 +//#include <asm/mach-ifxmips/ifxmips.h>
13349 +#include <lantiq_soc.h>
13350 +
13351 +#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
13352 +
13353 +#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
13354 +#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
13355 +#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
13356 +#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
13357 +#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
13358 +#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
13359 +#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
13360 +#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
13361 +#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
13362 +#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
13363 +#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
13364 +#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
13365 +#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
13366 +#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
13367 +#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
13368 +#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
13369 +#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
13370 +#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
13371 +
13372 +
13373 +#define writel ltq_w32
13374 +#define readl ltq_r32
13375 +void dwc_otg_power_on (void)
13376 +{
13377 + // clear power
13378 + writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR);
13379 + // set clock gating
13380 + writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
13381 + // set power
13382 + writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR);
13383 + writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR);
13384 + writel(readl(DANUBE_PMU_PWDCR) & ~0x8000, DANUBE_PMU_PWDCR);
13385 +
13386 +#if 1//defined (DWC_HOST_ONLY)
13387 + // make the hardware be a host controller (default)
13388 + //clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
13389 + writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_HDSEL_BIT), DANUBE_RCU_UBSCFG);
13390 +
13391 + //#elif defined (DWC_DEVICE_ONLY)
13392 + /* set the controller to the device mode */
13393 + // set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
13394 +#else
13395 +#error "For Danube/Twinpass, it should be HOST or Device Only."
13396 +#endif
13397 +
13398 + // set the HC's byte-order to big-endian
13399 + //set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
13400 + writel(readl(DANUBE_RCU_UBSCFG) | (1<<DANUBE_USBCFG_HOST_END_BIT), DANUBE_RCU_UBSCFG);
13401 + //clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
13402 + writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_SLV_END_BIT), DANUBE_RCU_UBSCFG);
13403 + //writel(0x400, DANUBE_RCU_UBSCFG);
13404 +
13405 + // PHY configurations.
13406 + writel (0x14014, (volatile unsigned long *)0xbe10103c);
13407 +}
13408 +
13409 +int ifx_usb_hc_init(unsigned long base_addr, int irq)
13410 +{
13411 + return 0;
13412 +}
13413 +
13414 +void ifx_usb_hc_remove(void)
13415 +{
13416 +}
13417 --- /dev/null
13418 +++ b/drivers/usb/dwc_otg/dwc_otg_ifx.h
13419 @@ -0,0 +1,85 @@
13420 +/******************************************************************************
13421 +**
13422 +** FILE NAME : dwc_otg_ifx.h
13423 +** PROJECT : Twinpass/Danube
13424 +** MODULES : DWC OTG USB
13425 +**
13426 +** DATE : 12 April 2007
13427 +** AUTHOR : Sung Winder
13428 +** DESCRIPTION : Platform specific initialization.
13429 +** COPYRIGHT : Copyright (c) 2007
13430 +** Infineon Technologies AG
13431 +** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
13432 +** Hsin-chu City, 300 Taiwan.
13433 +**
13434 +** This program is free software; you can redistribute it and/or modify
13435 +** it under the terms of the GNU General Public License as published by
13436 +** the Free Software Foundation; either version 2 of the License, or
13437 +** (at your option) any later version.
13438 +**
13439 +** HISTORY
13440 +** $Date $Author $Comment
13441 +** 12 April 2007 Sung Winder Initiate Version
13442 +*******************************************************************************/
13443 +#if !defined(__DWC_OTG_IFX_H__)
13444 +#define __DWC_OTG_IFX_H__
13445 +
13446 +#include <linux/irq.h>
13447 +#include <irq.h>
13448 +
13449 +// 20070316, winder added.
13450 +#ifndef SZ_256K
13451 +#define SZ_256K 0x00040000
13452 +#endif
13453 +
13454 +extern void dwc_otg_power_on (void);
13455 +
13456 +/* FIXME: The current Linux-2.6 do not have these header files, but anyway, we need these. */
13457 +// #include <asm/danube/danube.h>
13458 +// #include <asm/ifx/irq.h>
13459 +
13460 +/* winder, I used the Danube parameter as default. *
13461 + * We could change this through module param. */
13462 +#define IFX_USB_IOMEM_BASE 0x1e101000
13463 +#define IFX_USB_IOMEM_SIZE SZ_256K
13464 +#define IFX_USB_IRQ LTQ_USB_INT
13465 +
13466 +/**
13467 + * This function is called to set correct clock gating and power.
13468 + * For Twinpass/Danube board.
13469 + */
13470 +#ifndef DANUBE_RCU_BASE_ADDR
13471 +#define DANUBE_RCU_BASE_ADDR (0xBF203000)
13472 +#endif
13473 +
13474 +#ifndef DANUBE_CGU
13475 +#define DANUBE_CGU (0xBF103000)
13476 +#endif
13477 +#ifndef DANUBE_CGU_IFCCR
13478 +/***CGU Interface Clock Control Register***/
13479 +#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018))
13480 +#endif
13481 +
13482 +#ifndef DANUBE_PMU
13483 +#define DANUBE_PMU (KSEG1+0x1F102000)
13484 +#endif
13485 +#ifndef DANUBE_PMU_PWDCR
13486 +/* PMU Power down Control Register */
13487 +#define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C))
13488 +#endif
13489 +
13490 +
13491 +#define DANUBE_RCU_UBSCFG ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x18))
13492 +#define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device
13493 +#define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end
13494 +#define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end
13495 +
13496 +extern void ltq_mask_and_ack_irq(struct irq_data *d);
13497 +
13498 +static void inline mask_and_ack_ifx_irq(int x)
13499 +{
13500 + struct irq_data d;
13501 + d.irq = x;
13502 + ltq_mask_and_ack_irq(&d);
13503 +}
13504 +#endif //__DWC_OTG_IFX_H__
13505 --- /dev/null
13506 +++ b/drivers/usb/dwc_otg/dwc_otg_plat.h
13507 @@ -0,0 +1,269 @@
13508 +/* ==========================================================================
13509 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/platform/dwc_otg_plat.h $
13510 + * $Revision: 1.1.1.1 $
13511 + * $Date: 2009-04-17 06:15:34 $
13512 + * $Change: 510301 $
13513 + *
13514 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
13515 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
13516 + * otherwise expressly agreed to in writing between Synopsys and you.
13517 + *
13518 + * The Software IS NOT an item of Licensed Software or Licensed Product under
13519 + * any End User Software License Agreement or Agreement for Licensed Product
13520 + * with Synopsys or any supplement thereto. You are permitted to use and
13521 + * redistribute this Software in source and binary forms, with or without
13522 + * modification, provided that redistributions of source code must retain this
13523 + * notice. You may not view, use, disclose, copy or distribute this file or
13524 + * any information contained herein except pursuant to this license grant from
13525 + * Synopsys. If you do not agree with this notice, including the disclaimer
13526 + * below, then you are not authorized to use the Software.
13527 + *
13528 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
13529 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13530 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13531 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
13532 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13533 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
13534 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
13535 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
13536 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
13537 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13538 + * DAMAGE.
13539 + * ========================================================================== */
13540 +
13541 +#if !defined(__DWC_OTG_PLAT_H__)
13542 +#define __DWC_OTG_PLAT_H__
13543 +
13544 +#include <linux/types.h>
13545 +#include <linux/slab.h>
13546 +#include <linux/list.h>
13547 +#include <linux/delay.h>
13548 +#include <asm/io.h>
13549 +
13550 +/**
13551 + * @file
13552 + *
13553 + * This file contains the Platform Specific constants, interfaces
13554 + * (functions and macros) for Linux.
13555 + *
13556 + */
13557 +/*#if !defined(__LINUX__)
13558 +#error "The contents of this file is Linux specific!!!"
13559 +#endif
13560 +*/
13561 +#include <lantiq_soc.h>
13562 +#define writel ltq_w32
13563 +#define readl ltq_r32
13564 +
13565 +/**
13566 + * Reads the content of a register.
13567 + *
13568 + * @param _reg address of register to read.
13569 + * @return contents of the register.
13570 + *
13571 +
13572 + * Usage:<br>
13573 + * <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code>
13574 + */
13575 +static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *_reg)
13576 +{
13577 + return readl(_reg);
13578 +};
13579 +
13580 +/**
13581 + * Writes a register with a 32 bit value.
13582 + *
13583 + * @param _reg address of register to read.
13584 + * @param _value to write to _reg.
13585 + *
13586 + * Usage:<br>
13587 + * <code>dwc_write_reg32(&dev_regs->dctl, 0); </code>
13588 + */
13589 +static __inline__ void dwc_write_reg32( volatile uint32_t *_reg, const uint32_t _value)
13590 +{
13591 + writel( _value, _reg );
13592 +};
13593 +
13594 +/**
13595 + * This function modifies bit values in a register. Using the
13596 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
13597 + *
13598 + * @param _reg address of register to read.
13599 + * @param _clear_mask bit mask to be cleared.
13600 + * @param _set_mask bit mask to be set.
13601 + *
13602 + * Usage:<br>
13603 + * <code> // Clear the SOF Interrupt Mask bit and <br>
13604 + * // set the OTG Interrupt mask bit, leaving all others as they were.
13605 + * dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code>
13606 + */
13607 +static __inline__
13608 + void dwc_modify_reg32( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
13609 +{
13610 + writel( (readl(_reg) & ~_clear_mask) | _set_mask, _reg );
13611 +};
13612 +
13613 +
13614 +/**
13615 + * Wrapper for the OS micro-second delay function.
13616 + * @param[in] _usecs Microseconds of delay
13617 + */
13618 +static __inline__ void UDELAY( const uint32_t _usecs )
13619 +{
13620 + udelay( _usecs );
13621 +}
13622 +
13623 +/**
13624 + * Wrapper for the OS milli-second delay function.
13625 + * @param[in] _msecs milliseconds of delay
13626 + */
13627 +static __inline__ void MDELAY( const uint32_t _msecs )
13628 +{
13629 + mdelay( _msecs );
13630 +}
13631 +
13632 +/**
13633 + * Wrapper for the Linux spin_lock. On the ARM (Integrator)
13634 + * spin_lock() is a nop.
13635 + *
13636 + * @param _lock Pointer to the spinlock.
13637 + */
13638 +static __inline__ void SPIN_LOCK( spinlock_t *_lock )
13639 +{
13640 + spin_lock(_lock);
13641 +}
13642 +
13643 +/**
13644 + * Wrapper for the Linux spin_unlock. On the ARM (Integrator)
13645 + * spin_lock() is a nop.
13646 + *
13647 + * @param _lock Pointer to the spinlock.
13648 + */
13649 +static __inline__ void SPIN_UNLOCK( spinlock_t *_lock )
13650 +{
13651 + spin_unlock(_lock);
13652 +}
13653 +
13654 +/**
13655 + * Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM
13656 + * (Integrator) spin_lock() is a nop.
13657 + *
13658 + * @param _l Pointer to the spinlock.
13659 + * @param _f unsigned long for irq flags storage.
13660 + */
13661 +#define SPIN_LOCK_IRQSAVE( _l, _f ) { \
13662 + spin_lock_irqsave(_l,_f); \
13663 + }
13664 +
13665 +/**
13666 + * Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM
13667 + * (Integrator) spin_lock() is a nop.
13668 + *
13669 + * @param _l Pointer to the spinlock.
13670 + * @param _f unsigned long for irq flags storage.
13671 + */
13672 +#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) {\
13673 + spin_unlock_irqrestore(_l,_f); \
13674 + }
13675 +
13676 +
13677 +/*
13678 + * Debugging support vanishes in non-debug builds.
13679 + */
13680 +
13681 +
13682 +/**
13683 + * The Debug Level bit-mask variable.
13684 + */
13685 +extern uint32_t g_dbg_lvl;
13686 +/**
13687 + * Set the Debug Level variable.
13688 + */
13689 +static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new )
13690 +{
13691 + uint32_t old = g_dbg_lvl;
13692 + g_dbg_lvl = _new;
13693 + return old;
13694 +}
13695 +
13696 +/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
13697 +#define DBG_CIL (0x2)
13698 +/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
13699 + * messages */
13700 +#define DBG_CILV (0x20)
13701 +/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
13702 + * messages */
13703 +#define DBG_PCD (0x4)
13704 +/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
13705 + * messages */
13706 +#define DBG_PCDV (0x40)
13707 +/** When debug level has the DBG_HCD bit set, display Host debug messages */
13708 +#define DBG_HCD (0x8)
13709 +/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
13710 + * messages */
13711 +#define DBG_HCDV (0x80)
13712 +/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
13713 + * mode. */
13714 +#define DBG_HCD_URB (0x800)
13715 +
13716 +/** When debug level has any bit set, display debug messages */
13717 +#define DBG_ANY (0xFF)
13718 +
13719 +/** All debug messages off */
13720 +#define DBG_OFF 0
13721 +
13722 +/** Prefix string for DWC_DEBUG print macros. */
13723 +#define USB_DWC "DWC_otg: "
13724 +
13725 +/**
13726 + * Print a debug message when the Global debug level variable contains
13727 + * the bit defined in <code>lvl</code>.
13728 + *
13729 + * @param[in] lvl - Debug level, use one of the DBG_ constants above.
13730 + * @param[in] x - like printf
13731 + *
13732 + * Example:<p>
13733 + * <code>
13734 + * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
13735 + * </code>
13736 + * <br>
13737 + * results in:<br>
13738 + * <code>
13739 + * usb-DWC_otg: dwc_otg_cil_init(ca867000)
13740 + * </code>
13741 + */
13742 +#ifdef DEBUG
13743 +
13744 +# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0)
13745 +# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
13746 +
13747 +# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
13748 +
13749 +#else
13750 +
13751 +# define DWC_DEBUGPL(lvl, x...) do{}while(0)
13752 +# define DWC_DEBUGP(x...)
13753 +
13754 +# define CHK_DEBUG_LEVEL(level) (0)
13755 +
13756 +#endif /*DEBUG*/
13757 +
13758 +/**
13759 + * Print an Error message.
13760 + */
13761 +#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x )
13762 +/**
13763 + * Print a Warning message.
13764 + */
13765 +#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x )
13766 +/**
13767 + * Print a notice (normal but significant message).
13768 + */
13769 +#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x )
13770 +/**
13771 + * Basic message printing.
13772 + */
13773 +#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x )
13774 +
13775 +#endif
13776 +
13777 --- /dev/null
13778 +++ b/drivers/usb/dwc_otg/dwc_otg_regs.h
13779 @@ -0,0 +1,1797 @@
13780 +/* ==========================================================================
13781 + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_regs.h $
13782 + * $Revision: 1.1.1.1 $
13783 + * $Date: 2009-04-17 06:15:34 $
13784 + * $Change: 631780 $
13785 + *
13786 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
13787 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
13788 + * otherwise expressly agreed to in writing between Synopsys and you.
13789 + *
13790 + * The Software IS NOT an item of Licensed Software or Licensed Product under
13791 + * any End User Software License Agreement or Agreement for Licensed Product
13792 + * with Synopsys or any supplement thereto. You are permitted to use and
13793 + * redistribute this Software in source and binary forms, with or without
13794 + * modification, provided that redistributions of source code must retain this
13795 + * notice. You may not view, use, disclose, copy or distribute this file or
13796 + * any information contained herein except pursuant to this license grant from
13797 + * Synopsys. If you do not agree with this notice, including the disclaimer
13798 + * below, then you are not authorized to use the Software.
13799 + *
13800 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
13801 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13802 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13803 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
13804 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13805 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
13806 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
13807 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
13808 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
13809 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13810 + * DAMAGE.
13811 + * ========================================================================== */
13812 +
13813 +#ifndef __DWC_OTG_REGS_H__
13814 +#define __DWC_OTG_REGS_H__
13815 +
13816 +/**
13817 + * @file
13818 + *
13819 + * This file contains the data structures for accessing the DWC_otg core registers.
13820 + *
13821 + * The application interfaces with the HS OTG core by reading from and
13822 + * writing to the Control and Status Register (CSR) space through the
13823 + * AHB Slave interface. These registers are 32 bits wide, and the
13824 + * addresses are 32-bit-block aligned.
13825 + * CSRs are classified as follows:
13826 + * - Core Global Registers
13827 + * - Device Mode Registers
13828 + * - Device Global Registers
13829 + * - Device Endpoint Specific Registers
13830 + * - Host Mode Registers
13831 + * - Host Global Registers
13832 + * - Host Port CSRs
13833 + * - Host Channel Specific Registers
13834 + *
13835 + * Only the Core Global registers can be accessed in both Device and
13836 + * Host modes. When the HS OTG core is operating in one mode, either
13837 + * Device or Host, the application must not access registers from the
13838 + * other mode. When the core switches from one mode to another, the
13839 + * registers in the new mode of operation must be reprogrammed as they
13840 + * would be after a power-on reset.
13841 + */
13842 +
13843 +/****************************************************************************/
13844 +/** DWC_otg Core registers .
13845 + * The dwc_otg_core_global_regs structure defines the size
13846 + * and relative field offsets for the Core Global registers.
13847 + */
13848 +typedef struct dwc_otg_core_global_regs
13849 +{
13850 + /** OTG Control and Status Register. <i>Offset: 000h</i> */
13851 + volatile uint32_t gotgctl;
13852 + /** OTG Interrupt Register. <i>Offset: 004h</i> */
13853 + volatile uint32_t gotgint;
13854 + /**Core AHB Configuration Register. <i>Offset: 008h</i> */
13855 + volatile uint32_t gahbcfg;
13856 +#define DWC_GLBINTRMASK 0x0001
13857 +#define DWC_DMAENABLE 0x0020
13858 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
13859 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
13860 +#define DWC_PTXEMPTYLVL_EMPTY 0x0100
13861 +#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
13862 +
13863 +
13864 + /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
13865 + volatile uint32_t gusbcfg;
13866 + /**Core Reset Register. <i>Offset: 010h</i> */
13867 + volatile uint32_t grstctl;
13868 + /**Core Interrupt Register. <i>Offset: 014h</i> */
13869 + volatile uint32_t gintsts;
13870 + /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
13871 + volatile uint32_t gintmsk;
13872 + /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
13873 + volatile uint32_t grxstsr;
13874 + /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
13875 + volatile uint32_t grxstsp;
13876 + /**Receive FIFO Size Register. <i>Offset: 024h</i> */
13877 + volatile uint32_t grxfsiz;
13878 + /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
13879 + volatile uint32_t gnptxfsiz;
13880 + /**Non Periodic Transmit FIFO/Queue Status Register (Read
13881 + * Only). <i>Offset: 02Ch</i> */
13882 + volatile uint32_t gnptxsts;
13883 + /**I2C Access Register. <i>Offset: 030h</i> */
13884 + volatile uint32_t gi2cctl;
13885 + /**PHY Vendor Control Register. <i>Offset: 034h</i> */
13886 + volatile uint32_t gpvndctl;
13887 + /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
13888 + volatile uint32_t ggpio;
13889 + /**User ID Register. <i>Offset: 03Ch</i> */
13890 + volatile uint32_t guid;
13891 + /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
13892 + volatile uint32_t gsnpsid;
13893 + /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
13894 + volatile uint32_t ghwcfg1;
13895 + /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
13896 + volatile uint32_t ghwcfg2;
13897 +#define DWC_SLAVE_ONLY_ARCH 0
13898 +#define DWC_EXT_DMA_ARCH 1
13899 +#define DWC_INT_DMA_ARCH 2
13900 +
13901 +#define DWC_MODE_HNP_SRP_CAPABLE 0
13902 +#define DWC_MODE_SRP_ONLY_CAPABLE 1
13903 +#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
13904 +#define DWC_MODE_SRP_CAPABLE_DEVICE 3
13905 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
13906 +#define DWC_MODE_SRP_CAPABLE_HOST 5
13907 +#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
13908 +
13909 + /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
13910 + volatile uint32_t ghwcfg3;
13911 + /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
13912 + volatile uint32_t ghwcfg4;
13913 + /** Reserved <i>Offset: 054h-0FFh</i> */
13914 + uint32_t reserved[43];
13915 + /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
13916 + volatile uint32_t hptxfsiz;
13917 + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
13918 + otherwise Device Transmit FIFO#n Register.
13919 + * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
13920 + //volatile uint32_t dptxfsiz[15];
13921 + volatile uint32_t dptxfsiz_dieptxf[15];
13922 +} dwc_otg_core_global_regs_t;
13923 +
13924 +/**
13925 + * This union represents the bit fields of the Core OTG Control
13926 + * and Status Register (GOTGCTL). Set the bits using the bit
13927 + * fields then write the <i>d32</i> value to the register.
13928 + */
13929 +typedef union gotgctl_data
13930 +{
13931 + /** raw register data */
13932 + uint32_t d32;
13933 + /** register bits */
13934 + struct
13935 + {
13936 + unsigned reserved31_21 : 11;
13937 + unsigned currmod : 1;
13938 + unsigned bsesvld : 1;
13939 + unsigned asesvld : 1;
13940 + unsigned reserved17 : 1;
13941 + unsigned conidsts : 1;
13942 + unsigned reserved15_12 : 4;
13943 + unsigned devhnpen : 1;
13944 + unsigned hstsethnpen : 1;
13945 + unsigned hnpreq : 1;
13946 + unsigned hstnegscs : 1;
13947 + unsigned reserved7_2 : 6;
13948 + unsigned sesreq : 1;
13949 + unsigned sesreqscs : 1;
13950 + } b;
13951 +} gotgctl_data_t;
13952 +
13953 +/**
13954 + * This union represents the bit fields of the Core OTG Interrupt Register
13955 + * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
13956 + * value to the register.
13957 + */
13958 +typedef union gotgint_data
13959 +{
13960 + /** raw register data */
13961 + uint32_t d32;
13962 + /** register bits */
13963 + struct
13964 + {
13965 + /** Current Mode */
13966 + unsigned reserved31_20 : 12;
13967 + /** Debounce Done */
13968 + unsigned debdone : 1;
13969 + /** A-Device Timeout Change */
13970 + unsigned adevtoutchng : 1;
13971 + /** Host Negotiation Detected */
13972 + unsigned hstnegdet : 1;
13973 + unsigned reserver16_10 : 7;
13974 + /** Host Negotiation Success Status Change */
13975 + unsigned hstnegsucstschng : 1;
13976 + /** Session Request Success Status Change */
13977 + unsigned sesreqsucstschng : 1;
13978 + unsigned reserved3_7 : 5;
13979 + /** Session End Detected */
13980 + unsigned sesenddet : 1;
13981 + /** Current Mode */
13982 + unsigned reserved1_0 : 2;
13983 + } b;
13984 +} gotgint_data_t;
13985 +
13986 +
13987 +/**
13988 + * This union represents the bit fields of the Core AHB Configuration
13989 + * Register (GAHBCFG). Set/clear the bits using the bit fields then
13990 + * write the <i>d32</i> value to the register.
13991 + */
13992 +typedef union gahbcfg_data
13993 +{
13994 + /** raw register data */
13995 + uint32_t d32;
13996 + /** register bits */
13997 + struct
13998 + {
13999 +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
14000 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
14001 + unsigned reserved9_31 : 23;
14002 + unsigned ptxfemplvl : 1;
14003 + unsigned nptxfemplvl_txfemplvl : 1;
14004 +#define DWC_GAHBCFG_DMAENABLE 1
14005 + unsigned reserved : 1;
14006 + unsigned dmaenable : 1;
14007 +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
14008 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
14009 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
14010 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
14011 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
14012 + unsigned hburstlen : 4;
14013 + unsigned glblintrmsk : 1;
14014 +#define DWC_GAHBCFG_GLBINT_ENABLE 1
14015 +
14016 + } b;
14017 +} gahbcfg_data_t;
14018 +
14019 +/**
14020 + * This union represents the bit fields of the Core USB Configuration
14021 + * Register (GUSBCFG). Set the bits using the bit fields then write
14022 + * the <i>d32</i> value to the register.
14023 + */
14024 +typedef union gusbcfg_data
14025 +{
14026 + /** raw register data */
14027 + uint32_t d32;
14028 + /** register bits */
14029 + struct
14030 + {
14031 + unsigned corrupt_tx_packet: 1; /*fscz*/
14032 + unsigned force_device_mode: 1;
14033 + unsigned force_host_mode: 1;
14034 + unsigned reserved23_28 : 6;
14035 + unsigned term_sel_dl_pulse : 1;
14036 + unsigned ulpi_int_vbus_indicator : 1;
14037 + unsigned ulpi_ext_vbus_drv : 1;
14038 + unsigned ulpi_clk_sus_m : 1;
14039 + unsigned ulpi_auto_res : 1;
14040 + unsigned ulpi_fsls : 1;
14041 + unsigned otgutmifssel : 1;
14042 + unsigned phylpwrclksel : 1;
14043 + unsigned nptxfrwnden : 1;
14044 + unsigned usbtrdtim : 4;
14045 + unsigned hnpcap : 1;
14046 + unsigned srpcap : 1;
14047 + unsigned ddrsel : 1;
14048 + unsigned physel : 1;
14049 + unsigned fsintf : 1;
14050 + unsigned ulpi_utmi_sel : 1;
14051 + unsigned phyif : 1;
14052 + unsigned toutcal : 3;
14053 + } b;
14054 +} gusbcfg_data_t;
14055 +
14056 +/**
14057 + * This union represents the bit fields of the Core Reset Register
14058 + * (GRSTCTL). Set/clear the bits using the bit fields then write the
14059 + * <i>d32</i> value to the register.
14060 + */
14061 +typedef union grstctl_data
14062 +{
14063 + /** raw register data */
14064 + uint32_t d32;
14065 + /** register bits */
14066 + struct
14067 + {
14068 + /** AHB Master Idle. Indicates the AHB Master State
14069 + * Machine is in IDLE condition. */
14070 + unsigned ahbidle : 1;
14071 + /** DMA Request Signal. Indicated DMA request is in
14072 + * probress. Used for debug purpose. */
14073 + unsigned dmareq : 1;
14074 + /** Reserved */
14075 + unsigned reserved29_11 : 19;
14076 + /** TxFIFO Number (TxFNum) (Device and Host).
14077 + *
14078 + * This is the FIFO number which needs to be flushed,
14079 + * using the TxFIFO Flush bit. This field should not
14080 + * be changed until the TxFIFO Flush bit is cleared by
14081 + * the core.
14082 + * - 0x0 : Non Periodic TxFIFO Flush
14083 + * - 0x1 : Periodic TxFIFO #1 Flush in device mode
14084 + * or Periodic TxFIFO in host mode
14085 + * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
14086 + * - ...
14087 + * - 0xF : Periodic TxFIFO #15 Flush in device mode
14088 + * - 0x10: Flush all the Transmit NonPeriodic and
14089 + * Transmit Periodic FIFOs in the core
14090 + */
14091 + unsigned txfnum : 5;
14092 + /** TxFIFO Flush (TxFFlsh) (Device and Host).
14093 + *
14094 + * This bit is used to selectively flush a single or
14095 + * all transmit FIFOs. The application must first
14096 + * ensure that the core is not in the middle of a
14097 + * transaction. <p>The application should write into
14098 + * this bit, only after making sure that neither the
14099 + * DMA engine is writing into the TxFIFO nor the MAC
14100 + * is reading the data out of the FIFO. <p>The
14101 + * application should wait until the core clears this
14102 + * bit, before performing any operations. This bit
14103 + * will takes 8 clocks (slowest of PHY or AHB clock)
14104 + * to clear.
14105 + */
14106 + unsigned txfflsh : 1;
14107 + /** RxFIFO Flush (RxFFlsh) (Device and Host)
14108 + *
14109 + * The application can flush the entire Receive FIFO
14110 + * using this bit. <p>The application must first
14111 + * ensure that the core is not in the middle of a
14112 + * transaction. <p>The application should write into
14113 + * this bit, only after making sure that neither the
14114 + * DMA engine is reading from the RxFIFO nor the MAC
14115 + * is writing the data in to the FIFO. <p>The
14116 + * application should wait until the bit is cleared
14117 + * before performing any other operations. This bit
14118 + * will takes 8 clocks (slowest of PHY or AHB clock)
14119 + * to clear.
14120 + */
14121 + unsigned rxfflsh : 1;
14122 + /** In Token Sequence Learning Queue Flush
14123 + * (INTknQFlsh) (Device Only)
14124 + */
14125 + unsigned intknqflsh : 1;
14126 + /** Host Frame Counter Reset (Host Only)<br>
14127 + *
14128 + * The application can reset the (micro)frame number
14129 + * counter inside the core, using this bit. When the
14130 + * (micro)frame counter is reset, the subsequent SOF
14131 + * sent out by the core, will have a (micro)frame
14132 + * number of 0.
14133 + */
14134 + unsigned hstfrm : 1;
14135 + /** Hclk Soft Reset
14136 + *
14137 + * The application uses this bit to reset the control logic in
14138 + * the AHB clock domain. Only AHB clock domain pipelines are
14139 + * reset.
14140 + */
14141 + unsigned hsftrst : 1;
14142 + /** Core Soft Reset (CSftRst) (Device and Host)
14143 + *
14144 + * The application can flush the control logic in the
14145 + * entire core using this bit. This bit resets the
14146 + * pipelines in the AHB Clock domain as well as the
14147 + * PHY Clock domain.
14148 + *
14149 + * The state machines are reset to an IDLE state, the
14150 + * control bits in the CSRs are cleared, all the
14151 + * transmit FIFOs and the receive FIFO are flushed.
14152 + *
14153 + * The status mask bits that control the generation of
14154 + * the interrupt, are cleared, to clear the
14155 + * interrupt. The interrupt status bits are not
14156 + * cleared, so the application can get the status of
14157 + * any events that occurred in the core after it has
14158 + * set this bit.
14159 + *
14160 + * Any transactions on the AHB are terminated as soon
14161 + * as possible following the protocol. Any
14162 + * transactions on the USB are terminated immediately.
14163 + *
14164 + * The configuration settings in the CSRs are
14165 + * unchanged, so the software doesn't have to
14166 + * reprogram these registers (Device
14167 + * Configuration/Host Configuration/Core System
14168 + * Configuration/Core PHY Configuration).
14169 + *
14170 + * The application can write to this bit, any time it
14171 + * wants to reset the core. This is a self clearing
14172 + * bit and the core clears this bit after all the
14173 + * necessary logic is reset in the core, which may
14174 + * take several clocks, depending on the current state
14175 + * of the core.
14176 + */
14177 + unsigned csftrst : 1;
14178 + } b;
14179 +} grstctl_t;
14180 +
14181 +
14182 +/**
14183 + * This union represents the bit fields of the Core Interrupt Mask
14184 + * Register (GINTMSK). Set/clear the bits using the bit fields then
14185 + * write the <i>d32</i> value to the register.
14186 + */
14187 +typedef union gintmsk_data
14188 +{
14189 + /** raw register data */
14190 + uint32_t d32;
14191 + /** register bits */
14192 + struct
14193 + {
14194 + unsigned wkupintr : 1;
14195 + unsigned sessreqintr : 1;
14196 + unsigned disconnect : 1;
14197 + unsigned conidstschng : 1;
14198 + unsigned reserved27 : 1;
14199 + unsigned ptxfempty : 1;
14200 + unsigned hcintr : 1;
14201 + unsigned portintr : 1;
14202 + unsigned reserved22_23 : 2;
14203 + unsigned incomplisoout : 1;
14204 + unsigned incomplisoin : 1;
14205 + unsigned outepintr : 1;
14206 + unsigned inepintr : 1;
14207 + unsigned epmismatch : 1;
14208 + unsigned reserved16 : 1;
14209 + unsigned eopframe : 1;
14210 + unsigned isooutdrop : 1;
14211 + unsigned enumdone : 1;
14212 + unsigned usbreset : 1;
14213 + unsigned usbsuspend : 1;
14214 + unsigned erlysuspend : 1;
14215 + unsigned i2cintr : 1;
14216 + unsigned reserved8 : 1;
14217 + unsigned goutnakeff : 1;
14218 + unsigned ginnakeff : 1;
14219 + unsigned nptxfempty : 1;
14220 + unsigned rxstsqlvl : 1;
14221 + unsigned sofintr : 1;
14222 + unsigned otgintr : 1;
14223 + unsigned modemismatch : 1;
14224 + unsigned reserved0 : 1;
14225 + } b;
14226 +} gintmsk_data_t;
14227 +/**
14228 + * This union represents the bit fields of the Core Interrupt Register
14229 + * (GINTSTS). Set/clear the bits using the bit fields then write the
14230 + * <i>d32</i> value to the register.
14231 + */
14232 +typedef union gintsts_data
14233 +{
14234 + /** raw register data */
14235 + uint32_t d32;
14236 +#define DWC_SOF_INTR_MASK 0x0008
14237 + /** register bits */
14238 + struct
14239 + {
14240 +#define DWC_HOST_MODE 1
14241 + unsigned wkupintr : 1;
14242 + unsigned sessreqintr : 1;
14243 + unsigned disconnect : 1;
14244 + unsigned conidstschng : 1;
14245 + unsigned reserved27 : 1;
14246 + unsigned ptxfempty : 1;
14247 + unsigned hcintr : 1;
14248 + unsigned portintr : 1;
14249 + unsigned reserved22_23 : 2;
14250 + unsigned incomplisoout : 1;
14251 + unsigned incomplisoin : 1;
14252 + unsigned outepintr : 1;
14253 + unsigned inepint: 1;
14254 + unsigned epmismatch : 1;
14255 + unsigned intokenrx : 1;
14256 + unsigned eopframe : 1;
14257 + unsigned isooutdrop : 1;
14258 + unsigned enumdone : 1;
14259 + unsigned usbreset : 1;
14260 + unsigned usbsuspend : 1;
14261 + unsigned erlysuspend : 1;
14262 + unsigned i2cintr : 1;
14263 + unsigned reserved8 : 1;
14264 + unsigned goutnakeff : 1;
14265 + unsigned ginnakeff : 1;
14266 + unsigned nptxfempty : 1;
14267 + unsigned rxstsqlvl : 1;
14268 + unsigned sofintr : 1;
14269 + unsigned otgintr : 1;
14270 + unsigned modemismatch : 1;
14271 + unsigned curmode : 1;
14272 + } b;
14273 +} gintsts_data_t;
14274 +
14275 +
14276 +/**
14277 + * This union represents the bit fields in the Device Receive Status Read and
14278 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
14279 + * element then read out the bits using the <i>b</i>it elements.
14280 + */
14281 +typedef union device_grxsts_data {
14282 + /** raw register data */
14283 + uint32_t d32;
14284 + /** register bits */
14285 + struct {
14286 + unsigned reserved : 7;
14287 + unsigned fn : 4;
14288 +#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
14289 +#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
14290 +
14291 +#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
14292 +#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
14293 +#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
14294 + unsigned pktsts : 4;
14295 + unsigned dpid : 2;
14296 + unsigned bcnt : 11;
14297 + unsigned epnum : 4;
14298 + } b;
14299 +} device_grxsts_data_t;
14300 +
14301 +/**
14302 + * This union represents the bit fields in the Host Receive Status Read and
14303 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
14304 + * element then read out the bits using the <i>b</i>it elements.
14305 + */
14306 +typedef union host_grxsts_data {
14307 + /** raw register data */
14308 + uint32_t d32;
14309 + /** register bits */
14310 + struct {
14311 + unsigned reserved31_21 : 11;
14312 +#define DWC_GRXSTS_PKTSTS_IN 0x2
14313 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
14314 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
14315 +#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
14316 + unsigned pktsts : 4;
14317 + unsigned dpid : 2;
14318 + unsigned bcnt : 11;
14319 + unsigned chnum : 4;
14320 + } b;
14321 +} host_grxsts_data_t;
14322 +
14323 +/**
14324 + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
14325 + * GNPTXFSIZ, DPTXFSIZn). Read the register into the <i>d32</i> element then
14326 + * read out the bits using the <i>b</i>it elements.
14327 + */
14328 +typedef union fifosize_data {
14329 + /** raw register data */
14330 + uint32_t d32;
14331 + /** register bits */
14332 + struct {
14333 + unsigned depth : 16;
14334 + unsigned startaddr : 16;
14335 + } b;
14336 +} fifosize_data_t;
14337 +
14338 +/**
14339 + * This union represents the bit fields in the Non-Periodic Transmit
14340 + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
14341 + * <i>d32</i> element then read out the bits using the <i>b</i>it
14342 + * elements.
14343 + */
14344 +typedef union gnptxsts_data {
14345 + /** raw register data */
14346 + uint32_t d32;
14347 + /** register bits */
14348 + struct {
14349 + unsigned reserved : 1;
14350 + /** Top of the Non-Periodic Transmit Request Queue
14351 + * - bits 30:27 - Channel/EP Number
14352 + * - bits 26:25 - Token Type
14353 + * - bit 24 - Terminate (Last entry for the selected
14354 + * channel/EP)
14355 + * - 2'b00 - IN/OUT
14356 + * - 2'b01 - Zero Length OUT
14357 + * - 2'b10 - PING/Complete Split
14358 + * - 2'b11 - Channel Halt
14359 +
14360 + */
14361 + unsigned nptxqtop_chnep : 4;
14362 + unsigned nptxqtop_token : 2;
14363 + unsigned nptxqtop_terminate : 1;
14364 + unsigned nptxqspcavail : 8;
14365 + unsigned nptxfspcavail : 16;
14366 + } b;
14367 +} gnptxsts_data_t;
14368 +
14369 +/**
14370 + * This union represents the bit fields in the Transmit
14371 + * FIFO Status Register (DTXFSTS). Read the register into the
14372 + * <i>d32</i> element then read out the bits using the <i>b</i>it
14373 + * elements.
14374 + */
14375 +typedef union dtxfsts_data /* fscz */ //*
14376 +{
14377 + /** raw register data */
14378 + uint32_t d32;
14379 + /** register bits */
14380 + struct {
14381 + unsigned reserved : 16;
14382 + unsigned txfspcavail : 16;
14383 + } b;
14384 +} dtxfsts_data_t;
14385 +
14386 +/**
14387 + * This union represents the bit fields in the I2C Control Register
14388 + * (I2CCTL). Read the register into the <i>d32</i> element then read out the
14389 + * bits using the <i>b</i>it elements.
14390 + */
14391 +typedef union gi2cctl_data {
14392 + /** raw register data */
14393 + uint32_t d32;
14394 + /** register bits */
14395 + struct {
14396 + unsigned bsydne : 1;
14397 + unsigned rw : 1;
14398 + unsigned reserved : 2;
14399 + unsigned i2cdevaddr : 2;
14400 + unsigned i2csuspctl : 1;
14401 + unsigned ack : 1;
14402 + unsigned i2cen : 1;
14403 + unsigned addr : 7;
14404 + unsigned regaddr : 8;
14405 + unsigned rwdata : 8;
14406 + } b;
14407 +} gi2cctl_data_t;
14408 +
14409 +/**
14410 + * This union represents the bit fields in the User HW Config1
14411 + * Register. Read the register into the <i>d32</i> element then read
14412 + * out the bits using the <i>b</i>it elements.
14413 + */
14414 +typedef union hwcfg1_data {
14415 + /** raw register data */
14416 + uint32_t d32;
14417 + /** register bits */
14418 + struct {
14419 + unsigned ep_dir15 : 2;
14420 + unsigned ep_dir14 : 2;
14421 + unsigned ep_dir13 : 2;
14422 + unsigned ep_dir12 : 2;
14423 + unsigned ep_dir11 : 2;
14424 + unsigned ep_dir10 : 2;
14425 + unsigned ep_dir9 : 2;
14426 + unsigned ep_dir8 : 2;
14427 + unsigned ep_dir7 : 2;
14428 + unsigned ep_dir6 : 2;
14429 + unsigned ep_dir5 : 2;
14430 + unsigned ep_dir4 : 2;
14431 + unsigned ep_dir3 : 2;
14432 + unsigned ep_dir2 : 2;
14433 + unsigned ep_dir1 : 2;
14434 + unsigned ep_dir0 : 2;
14435 + } b;
14436 +} hwcfg1_data_t;
14437 +
14438 +/**
14439 + * This union represents the bit fields in the User HW Config2
14440 + * Register. Read the register into the <i>d32</i> element then read
14441 + * out the bits using the <i>b</i>it elements.
14442 + */
14443 +typedef union hwcfg2_data
14444 +{
14445 + /** raw register data */
14446 + uint32_t d32;
14447 + /** register bits */
14448 + struct {
14449 + /* GHWCFG2 */
14450 + unsigned reserved31 : 1;
14451 + unsigned dev_token_q_depth : 5;
14452 + unsigned host_perio_tx_q_depth : 2;
14453 + unsigned nonperio_tx_q_depth : 2;
14454 + unsigned rx_status_q_depth : 2;
14455 + unsigned dynamic_fifo : 1;
14456 + unsigned perio_ep_supported : 1;
14457 + unsigned num_host_chan : 4;
14458 + unsigned num_dev_ep : 4;
14459 + unsigned fs_phy_type : 2;
14460 +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
14461 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
14462 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
14463 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
14464 + unsigned hs_phy_type : 2;
14465 + unsigned point2point : 1;
14466 + unsigned architecture : 2;
14467 +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
14468 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
14469 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
14470 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
14471 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
14472 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
14473 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
14474 + unsigned op_mode : 3;
14475 + } b;
14476 +} hwcfg2_data_t;
14477 +
14478 +/**
14479 + * This union represents the bit fields in the User HW Config3
14480 + * Register. Read the register into the <i>d32</i> element then read
14481 + * out the bits using the <i>b</i>it elements.
14482 + */
14483 +typedef union hwcfg3_data
14484 +{
14485 + /** raw register data */
14486 + uint32_t d32;
14487 + /** register bits */
14488 + struct {
14489 + /* GHWCFG3 */
14490 + unsigned dfifo_depth : 16;
14491 + unsigned reserved15_13 : 3;
14492 + unsigned ahb_phy_clock_synch : 1;
14493 + unsigned synch_reset_type : 1;
14494 + unsigned optional_features : 1;
14495 + unsigned vendor_ctrl_if : 1;
14496 + unsigned i2c : 1;
14497 + unsigned otg_func : 1;
14498 + unsigned packet_size_cntr_width : 3;
14499 + unsigned xfer_size_cntr_width : 4;
14500 + } b;
14501 +} hwcfg3_data_t;
14502 +
14503 +/**
14504 + * This union represents the bit fields in the User HW Config4
14505 + * Register. Read the register into the <i>d32</i> element then read
14506 + * out the bits using the <i>b</i>it elements.
14507 + */
14508 +typedef union hwcfg4_data
14509 +{
14510 + /** raw register data */
14511 + uint32_t d32;
14512 + /** register bits */
14513 + struct {
14514 +unsigned reserved31_30 : 2; /* fscz */
14515 + unsigned num_in_eps : 4;
14516 + unsigned ded_fifo_en : 1;
14517 +
14518 + unsigned session_end_filt_en : 1;
14519 + unsigned b_valid_filt_en : 1;
14520 + unsigned a_valid_filt_en : 1;
14521 + unsigned vbus_valid_filt_en : 1;
14522 + unsigned iddig_filt_en : 1;
14523 + unsigned num_dev_mode_ctrl_ep : 4;
14524 + unsigned utmi_phy_data_width : 2;
14525 + unsigned min_ahb_freq : 9;
14526 + unsigned power_optimiz : 1;
14527 + unsigned num_dev_perio_in_ep : 4;
14528 + } b;
14529 +} hwcfg4_data_t;
14530 +
14531 +////////////////////////////////////////////
14532 +// Device Registers
14533 +/**
14534 + * Device Global Registers. <i>Offsets 800h-BFFh</i>
14535 + *
14536 + * The following structures define the size and relative field offsets
14537 + * for the Device Mode Registers.
14538 + *
14539 + * <i>These registers are visible only in Device mode and must not be
14540 + * accessed in Host mode, as the results are unknown.</i>
14541 + */
14542 +typedef struct dwc_otg_dev_global_regs
14543 +{
14544 + /** Device Configuration Register. <i>Offset 800h</i> */
14545 + volatile uint32_t dcfg;
14546 + /** Device Control Register. <i>Offset: 804h</i> */
14547 + volatile uint32_t dctl;
14548 + /** Device Status Register (Read Only). <i>Offset: 808h</i> */
14549 + volatile uint32_t dsts;
14550 + /** Reserved. <i>Offset: 80Ch</i> */
14551 + uint32_t unused;
14552 + /** Device IN Endpoint Common Interrupt Mask
14553 + * Register. <i>Offset: 810h</i> */
14554 + volatile uint32_t diepmsk;
14555 + /** Device OUT Endpoint Common Interrupt Mask
14556 + * Register. <i>Offset: 814h</i> */
14557 + volatile uint32_t doepmsk;
14558 + /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
14559 + volatile uint32_t daint;
14560 + /** Device All Endpoints Interrupt Mask Register. <i>Offset:
14561 + * 81Ch</i> */
14562 + volatile uint32_t daintmsk;
14563 + /** Device IN Token Queue Read Register-1 (Read Only).
14564 + * <i>Offset: 820h</i> */
14565 + volatile uint32_t dtknqr1;
14566 + /** Device IN Token Queue Read Register-2 (Read Only).
14567 + * <i>Offset: 824h</i> */
14568 + volatile uint32_t dtknqr2;
14569 + /** Device VBUS discharge Register. <i>Offset: 828h</i> */
14570 + volatile uint32_t dvbusdis;
14571 + /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
14572 + volatile uint32_t dvbuspulse;
14573 + /** Device IN Token Queue Read Register-3 (Read Only).
14574 + * Device Thresholding control register (Read/Write)
14575 + * <i>Offset: 830h</i> */
14576 + volatile uint32_t dtknqr3_dthrctl;
14577 + /** Device IN Token Queue Read Register-4 (Read Only). /
14578 + * Device IN EPs empty Inr. Mask Register (Read/Write)
14579 + * <i>Offset: 834h</i> */
14580 + volatile uint32_t dtknqr4_fifoemptymsk;
14581 +} dwc_otg_device_global_regs_t;
14582 +
14583 +/**
14584 + * This union represents the bit fields in the Device Configuration
14585 + * Register. Read the register into the <i>d32</i> member then
14586 + * set/clear the bits using the <i>b</i>it elements. Write the
14587 + * <i>d32</i> member to the dcfg register.
14588 + */
14589 +typedef union dcfg_data
14590 +{
14591 + /** raw register data */
14592 + uint32_t d32;
14593 + /** register bits */
14594 + struct {
14595 + unsigned reserved31_23 : 9;
14596 + /** In Endpoint Mis-match count */
14597 + unsigned epmscnt : 5;
14598 + unsigned reserved13_17 : 5;
14599 + /** Periodic Frame Interval */
14600 +#define DWC_DCFG_FRAME_INTERVAL_80 0
14601 +#define DWC_DCFG_FRAME_INTERVAL_85 1
14602 +#define DWC_DCFG_FRAME_INTERVAL_90 2
14603 +#define DWC_DCFG_FRAME_INTERVAL_95 3
14604 + unsigned perfrint : 2;
14605 + /** Device Addresses */
14606 + unsigned devaddr : 7;
14607 + unsigned reserved3 : 1;
14608 + /** Non Zero Length Status OUT Handshake */
14609 +#define DWC_DCFG_SEND_STALL 1
14610 + unsigned nzstsouthshk : 1;
14611 + /** Device Speed */
14612 + unsigned devspd : 2;
14613 + } b;
14614 +} dcfg_data_t;
14615 +
14616 +/**
14617 + * This union represents the bit fields in the Device Control
14618 + * Register. Read the register into the <i>d32</i> member then
14619 + * set/clear the bits using the <i>b</i>it elements.
14620 + */
14621 +typedef union dctl_data
14622 +{
14623 + /** raw register data */
14624 + uint32_t d32;
14625 + /** register bits */
14626 + struct {
14627 + unsigned reserved : 20;
14628 + /** Power-On Programming Done */
14629 + unsigned pwronprgdone : 1;
14630 + /** Clear Global OUT NAK */
14631 + unsigned cgoutnak : 1;
14632 + /** Set Global OUT NAK */
14633 + unsigned sgoutnak : 1;
14634 + /** Clear Global Non-Periodic IN NAK */
14635 + unsigned cgnpinnak : 1;
14636 + /** Set Global Non-Periodic IN NAK */
14637 + unsigned sgnpinnak : 1;
14638 + /** Test Control */
14639 + unsigned tstctl : 3;
14640 + /** Global OUT NAK Status */
14641 + unsigned goutnaksts : 1;
14642 + /** Global Non-Periodic IN NAK Status */
14643 + unsigned gnpinnaksts : 1;
14644 + /** Soft Disconnect */
14645 + unsigned sftdiscon : 1;
14646 + /** Remote Wakeup */
14647 + unsigned rmtwkupsig : 1;
14648 + } b;
14649 +} dctl_data_t;
14650 +
14651 +/**
14652 + * This union represents the bit fields in the Device Status
14653 + * Register. Read the register into the <i>d32</i> member then
14654 + * set/clear the bits using the <i>b</i>it elements.
14655 + */
14656 +typedef union dsts_data
14657 +{
14658 + /** raw register data */
14659 + uint32_t d32;
14660 + /** register bits */
14661 + struct {
14662 + unsigned reserved22_31 : 10;
14663 + /** Frame or Microframe Number of the received SOF */
14664 + unsigned soffn : 14;
14665 + unsigned reserved4_7: 4;
14666 + /** Erratic Error */
14667 + unsigned errticerr : 1;
14668 + /** Enumerated Speed */
14669 +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
14670 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
14671 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
14672 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
14673 + unsigned enumspd : 2;
14674 + /** Suspend Status */
14675 + unsigned suspsts : 1;
14676 + } b;
14677 +} dsts_data_t;
14678 +
14679 +
14680 +/**
14681 + * This union represents the bit fields in the Device IN EP Interrupt
14682 + * Register and the Device IN EP Common Mask Register.
14683 + *
14684 + * - Read the register into the <i>d32</i> member then set/clear the
14685 + * bits using the <i>b</i>it elements.
14686 + */
14687 +typedef union diepint_data
14688 +{
14689 + /** raw register data */
14690 + uint32_t d32;
14691 + /** register bits */
14692 + struct {
14693 + unsigned reserved07_31 : 23;
14694 + unsigned txfifoundrn : 1;
14695 + /** IN Endpoint HAK Effective mask */
14696 + unsigned emptyintr : 1;
14697 + /** IN Endpoint NAK Effective mask */
14698 + unsigned inepnakeff : 1;
14699 + /** IN Token Received with EP mismatch mask */
14700 + unsigned intknepmis : 1;
14701 + /** IN Token received with TxF Empty mask */
14702 + unsigned intktxfemp : 1;
14703 + /** TimeOUT Handshake mask (non-ISOC EPs) */
14704 + unsigned timeout : 1;
14705 + /** AHB Error mask */
14706 + unsigned ahberr : 1;
14707 + /** Endpoint disable mask */
14708 + unsigned epdisabled : 1;
14709 + /** Transfer complete mask */
14710 + unsigned xfercompl : 1;
14711 + } b;
14712 +} diepint_data_t;
14713 +/**
14714 + * This union represents the bit fields in the Device IN EP Common
14715 + * Interrupt Mask Register.
14716 + */
14717 +typedef union diepint_data diepmsk_data_t;
14718 +
14719 +/**
14720 + * This union represents the bit fields in the Device OUT EP Interrupt
14721 + * Registerand Device OUT EP Common Interrupt Mask Register.
14722 + *
14723 + * - Read the register into the <i>d32</i> member then set/clear the
14724 + * bits using the <i>b</i>it elements.
14725 + */
14726 +typedef union doepint_data
14727 +{
14728 + /** raw register data */
14729 + uint32_t d32;
14730 + /** register bits */
14731 + struct {
14732 + unsigned reserved04_31 : 27;
14733 + /** OUT Token Received when Endpoint Disabled */
14734 + unsigned outtknepdis : 1;
14735 + /** Setup Phase Done (contorl EPs) */
14736 + unsigned setup : 1;
14737 + /** AHB Error */
14738 + unsigned ahberr : 1;
14739 + /** Endpoint disable */
14740 + unsigned epdisabled : 1;
14741 + /** Transfer complete */
14742 + unsigned xfercompl : 1;
14743 + } b;
14744 +} doepint_data_t;
14745 +/**
14746 + * This union represents the bit fields in the Device OUT EP Common
14747 + * Interrupt Mask Register.
14748 + */
14749 +typedef union doepint_data doepmsk_data_t;
14750 +
14751 +
14752 +/**
14753 + * This union represents the bit fields in the Device All EP Interrupt
14754 + * and Mask Registers.
14755 + * - Read the register into the <i>d32</i> member then set/clear the
14756 + * bits using the <i>b</i>it elements.
14757 + */
14758 +typedef union daint_data
14759 +{
14760 + /** raw register data */
14761 + uint32_t d32;
14762 + /** register bits */
14763 + struct {
14764 + /** OUT Endpoint bits */
14765 + unsigned out : 16;
14766 + /** IN Endpoint bits */
14767 + unsigned in : 16;
14768 + } ep;
14769 + struct {
14770 + /** OUT Endpoint bits */
14771 + unsigned outep15 : 1;
14772 + unsigned outep14 : 1;
14773 + unsigned outep13 : 1;
14774 + unsigned outep12 : 1;
14775 + unsigned outep11 : 1;
14776 + unsigned outep10 : 1;
14777 + unsigned outep9 : 1;
14778 + unsigned outep8 : 1;
14779 + unsigned outep7 : 1;
14780 + unsigned outep6 : 1;
14781 + unsigned outep5 : 1;
14782 + unsigned outep4 : 1;
14783 + unsigned outep3 : 1;
14784 + unsigned outep2 : 1;
14785 + unsigned outep1 : 1;
14786 + unsigned outep0 : 1;
14787 + /** IN Endpoint bits */
14788 + unsigned inep15 : 1;
14789 + unsigned inep14 : 1;
14790 + unsigned inep13 : 1;
14791 + unsigned inep12 : 1;
14792 + unsigned inep11 : 1;
14793 + unsigned inep10 : 1;
14794 + unsigned inep9 : 1;
14795 + unsigned inep8 : 1;
14796 + unsigned inep7 : 1;
14797 + unsigned inep6 : 1;
14798 + unsigned inep5 : 1;
14799 + unsigned inep4 : 1;
14800 + unsigned inep3 : 1;
14801 + unsigned inep2 : 1;
14802 + unsigned inep1 : 1;
14803 + unsigned inep0 : 1;
14804 + } b;
14805 +} daint_data_t;
14806 +
14807 +/**
14808 + * This union represents the bit fields in the Device IN Token Queue
14809 + * Read Registers.
14810 + * - Read the register into the <i>d32</i> member.
14811 + * - READ-ONLY Register
14812 + */
14813 +typedef union dtknq1_data
14814 +{
14815 + /** raw register data */
14816 + uint32_t d32;
14817 + /** register bits */
14818 + struct {
14819 + /** EP Numbers of IN Tokens 0 ... 4 */
14820 + unsigned epnums0_5 : 24;
14821 + /** write pointer has wrapped. */
14822 + unsigned wrap_bit : 1;
14823 + /** Reserved */
14824 + unsigned reserved05_06 : 2;
14825 + /** In Token Queue Write Pointer */
14826 + unsigned intknwptr : 5;
14827 + }b;
14828 +} dtknq1_data_t;
14829 +
14830 +/**
14831 + * This union represents Threshold control Register
14832 + * - Read and write the register into the <i>d32</i> member.
14833 + * - READ-WRITABLE Register
14834 + */
14835 +typedef union dthrctl_data //* /*fscz */
14836 +{
14837 + /** raw register data */
14838 + uint32_t d32;
14839 + /** register bits */
14840 + struct {
14841 + /** Reserved */
14842 + unsigned reserved26_31 : 6;
14843 + /** Rx Thr. Length */
14844 + unsigned rx_thr_len : 9;
14845 + /** Rx Thr. Enable */
14846 + unsigned rx_thr_en : 1;
14847 + /** Reserved */
14848 + unsigned reserved11_15 : 5;
14849 + /** Tx Thr. Length */
14850 + unsigned tx_thr_len : 9;
14851 + /** ISO Tx Thr. Enable */
14852 + unsigned iso_thr_en : 1;
14853 + /** non ISO Tx Thr. Enable */
14854 + unsigned non_iso_thr_en : 1;
14855 +
14856 + }b;
14857 +} dthrctl_data_t;
14858 +
14859 +/**
14860 + * Device Logical IN Endpoint-Specific Registers. <i>Offsets
14861 + * 900h-AFCh</i>
14862 + *
14863 + * There will be one set of endpoint registers per logical endpoint
14864 + * implemented.
14865 + *
14866 + * <i>These registers are visible only in Device mode and must not be
14867 + * accessed in Host mode, as the results are unknown.</i>
14868 + */
14869 +typedef struct dwc_otg_dev_in_ep_regs
14870 +{
14871 + /** Device IN Endpoint Control Register. <i>Offset:900h +
14872 + * (ep_num * 20h) + 00h</i> */
14873 + volatile uint32_t diepctl;
14874 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
14875 + uint32_t reserved04;
14876 + /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
14877 + * (ep_num * 20h) + 08h</i> */
14878 + volatile uint32_t diepint;
14879 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
14880 + uint32_t reserved0C;
14881 + /** Device IN Endpoint Transfer Size
14882 + * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
14883 + volatile uint32_t dieptsiz;
14884 + /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
14885 + * (ep_num * 20h) + 14h</i> */
14886 + volatile uint32_t diepdma;
14887 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 18h - 900h +
14888 + * (ep_num * 20h) + 1Ch</i>*/
14889 + volatile uint32_t dtxfsts;
14890 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 1Ch - 900h +
14891 + * (ep_num * 20h) + 1Ch</i>*/
14892 + uint32_t reserved18;
14893 +} dwc_otg_dev_in_ep_regs_t;
14894 +
14895 +/**
14896 + * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
14897 + * B00h-CFCh</i>
14898 + *
14899 + * There will be one set of endpoint registers per logical endpoint
14900 + * implemented.
14901 + *
14902 + * <i>These registers are visible only in Device mode and must not be
14903 + * accessed in Host mode, as the results are unknown.</i>
14904 + */
14905 +typedef struct dwc_otg_dev_out_ep_regs
14906 +{
14907 + /** Device OUT Endpoint Control Register. <i>Offset:B00h +
14908 + * (ep_num * 20h) + 00h</i> */
14909 + volatile uint32_t doepctl;
14910 + /** Device OUT Endpoint Frame number Register. <i>Offset:
14911 + * B00h + (ep_num * 20h) + 04h</i> */
14912 + volatile uint32_t doepfn;
14913 + /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
14914 + * (ep_num * 20h) + 08h</i> */
14915 + volatile uint32_t doepint;
14916 + /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
14917 + uint32_t reserved0C;
14918 + /** Device OUT Endpoint Transfer Size Register. <i>Offset:
14919 + * B00h + (ep_num * 20h) + 10h</i> */
14920 + volatile uint32_t doeptsiz;
14921 + /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
14922 + * + (ep_num * 20h) + 14h</i> */
14923 + volatile uint32_t doepdma;
14924 + /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 18h - B00h +
14925 + * (ep_num * 20h) + 1Ch</i> */
14926 + uint32_t unused[2];
14927 +} dwc_otg_dev_out_ep_regs_t;
14928 +
14929 +/**
14930 + * This union represents the bit fields in the Device EP Control
14931 + * Register. Read the register into the <i>d32</i> member then
14932 + * set/clear the bits using the <i>b</i>it elements.
14933 + */
14934 +typedef union depctl_data
14935 +{
14936 + /** raw register data */
14937 + uint32_t d32;
14938 + /** register bits */
14939 + struct {
14940 + /** Endpoint Enable */
14941 + unsigned epena : 1;
14942 + /** Endpoint Disable */
14943 + unsigned epdis : 1;
14944 + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
14945 + * Writing to this field sets the Endpoint DPID (DPID)
14946 + * field in this register to DATA1 Set Odd
14947 + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
14948 + * Writing to this field sets the Even/Odd
14949 + * (micro)frame (EO_FrNum) field to odd (micro) frame.
14950 + */
14951 + unsigned setd1pid : 1;
14952 + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
14953 + * Writing to this field sets the Endpoint DPID (DPID)
14954 + * field in this register to DATA0. Set Even
14955 + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
14956 + * Writing to this field sets the Even/Odd
14957 + * (micro)frame (EO_FrNum) field to even (micro)
14958 + * frame.
14959 + */
14960 + unsigned setd0pid : 1;
14961 + /** Set NAK */
14962 + unsigned snak : 1;
14963 + /** Clear NAK */
14964 + unsigned cnak : 1;
14965 + /** Tx Fifo Number
14966 + * IN EPn/IN EP0
14967 + * OUT EPn/OUT EP0 - reserved */
14968 + unsigned txfnum : 4;
14969 + /** Stall Handshake */
14970 + unsigned stall : 1;
14971 + /** Snoop Mode
14972 + * OUT EPn/OUT EP0
14973 + * IN EPn/IN EP0 - reserved */
14974 + unsigned snp : 1;
14975 + /** Endpoint Type
14976 + * 2'b00: Control
14977 + * 2'b01: Isochronous
14978 + * 2'b10: Bulk
14979 + * 2'b11: Interrupt */
14980 + unsigned eptype : 2;
14981 + /** NAK Status */
14982 + unsigned naksts : 1;
14983 + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
14984 + * This field contains the PID of the packet going to
14985 + * be received or transmitted on this endpoint. The
14986 + * application should program the PID of the first
14987 + * packet going to be received or transmitted on this
14988 + * endpoint , after the endpoint is
14989 + * activated. Application use the SetD1PID and
14990 + * SetD0PID fields of this register to program either
14991 + * D0 or D1 PID.
14992 + *
14993 + * The encoding for this field is
14994 + * - 0: D0
14995 + * - 1: D1
14996 + */
14997 + unsigned dpid : 1;
14998 + /** USB Active Endpoint */
14999 + unsigned usbactep : 1;
15000 + /** Next Endpoint
15001 + * IN EPn/IN EP0
15002 + * OUT EPn/OUT EP0 - reserved */
15003 + unsigned nextep : 4;
15004 + /** Maximum Packet Size
15005 + * IN/OUT EPn
15006 + * IN/OUT EP0 - 2 bits
15007 + * 2'b00: 64 Bytes
15008 + * 2'b01: 32
15009 + * 2'b10: 16
15010 + * 2'b11: 8 */
15011 +#define DWC_DEP0CTL_MPS_64 0
15012 +#define DWC_DEP0CTL_MPS_32 1
15013 +#define DWC_DEP0CTL_MPS_16 2
15014 +#define DWC_DEP0CTL_MPS_8 3
15015 + unsigned mps : 11;
15016 + } b;
15017 +} depctl_data_t;
15018 +
15019 +/**
15020 + * This union represents the bit fields in the Device EP Transfer
15021 + * Size Register. Read the register into the <i>d32</i> member then
15022 + * set/clear the bits using the <i>b</i>it elements.
15023 + */
15024 +typedef union deptsiz_data
15025 +{
15026 + /** raw register data */
15027 + uint32_t d32;
15028 + /** register bits */
15029 + struct {
15030 + unsigned reserved : 1;
15031 + /** Multi Count - Periodic IN endpoints */
15032 + unsigned mc : 2;
15033 + /** Packet Count */
15034 + unsigned pktcnt : 10;
15035 + /** Transfer size */
15036 + unsigned xfersize : 19;
15037 + } b;
15038 +} deptsiz_data_t;
15039 +
15040 +/**
15041 + * This union represents the bit fields in the Device EP 0 Transfer
15042 + * Size Register. Read the register into the <i>d32</i> member then
15043 + * set/clear the bits using the <i>b</i>it elements.
15044 + */
15045 +typedef union deptsiz0_data
15046 +{
15047 + /** raw register data */
15048 + uint32_t d32;
15049 + /** register bits */
15050 + struct {
15051 + unsigned reserved31 : 1;
15052 + /**Setup Packet Count (DOEPTSIZ0 Only) */
15053 + unsigned supcnt : 2;
15054 + /** Reserved */
15055 + unsigned reserved28_20 : 9;
15056 + /** Packet Count */
15057 + unsigned pktcnt : 1;
15058 + /** Reserved */
15059 + unsigned reserved18_7 : 12;
15060 + /** Transfer size */
15061 + unsigned xfersize : 7;
15062 + } b;
15063 +} deptsiz0_data_t;
15064 +
15065 +
15066 +/** Maximum number of Periodic FIFOs */
15067 +#define MAX_PERIO_FIFOS 15
15068 +/** Maximum number of TX FIFOs */
15069 +#define MAX_TX_FIFOS 15
15070 +/** Maximum number of Endpoints/HostChannels */
15071 +#define MAX_EPS_CHANNELS 16
15072 +//#define MAX_EPS_CHANNELS 4
15073 +
15074 +/**
15075 + * The dwc_otg_dev_if structure contains information needed to manage
15076 + * the DWC_otg controller acting in device mode. It represents the
15077 + * programming view of the device-specific aspects of the controller.
15078 + */
15079 +typedef struct dwc_otg_dev_if {
15080 + /** Pointer to device Global registers.
15081 + * Device Global Registers starting at offset 800h
15082 + */
15083 + dwc_otg_device_global_regs_t *dev_global_regs;
15084 +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
15085 +
15086 + /**
15087 + * Device Logical IN Endpoint-Specific Registers 900h-AFCh
15088 + */
15089 + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
15090 +#define DWC_DEV_IN_EP_REG_OFFSET 0x900
15091 +#define DWC_EP_REG_OFFSET 0x20
15092 +
15093 + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
15094 + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
15095 +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
15096 +
15097 + /* Device configuration information*/
15098 + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
15099 + //uint8_t num_eps; /**< Number of EPs range: 0-16 (includes EP0) */
15100 + //uint8_t num_perio_eps; /**< # of Periodic EP range: 0-15 */
15101 + /*fscz */
15102 + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
15103 + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
15104 +
15105 + /** Size of periodic FIFOs (Bytes) */
15106 + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
15107 +
15108 + /** Size of Tx FIFOs (Bytes) */
15109 + uint16_t tx_fifo_size[MAX_TX_FIFOS];
15110 +
15111 + /** Thresholding enable flags and length varaiables **/
15112 + uint16_t rx_thr_en;
15113 + uint16_t iso_tx_thr_en;
15114 + uint16_t non_iso_tx_thr_en;
15115 +
15116 + uint16_t rx_thr_length;
15117 + uint16_t tx_thr_length;
15118 +} dwc_otg_dev_if_t;
15119 +
15120 +/**
15121 + * This union represents the bit fields in the Power and Clock Gating Control
15122 + * Register. Read the register into the <i>d32</i> member then set/clear the
15123 + * bits using the <i>b</i>it elements.
15124 + */
15125 +typedef union pcgcctl_data
15126 +{
15127 + /** raw register data */
15128 + uint32_t d32;
15129 +
15130 + /** register bits */
15131 + struct {
15132 + unsigned reserved31_05 : 27;
15133 + /** PHY Suspended */
15134 + unsigned physuspended : 1;
15135 + /** Reset Power Down Modules */
15136 + unsigned rstpdwnmodule : 1;
15137 + /** Power Clamp */
15138 + unsigned pwrclmp : 1;
15139 + /** Gate Hclk */
15140 + unsigned gatehclk : 1;
15141 + /** Stop Pclk */
15142 + unsigned stoppclk : 1;
15143 + } b;
15144 +} pcgcctl_data_t;
15145 +
15146 +/////////////////////////////////////////////////
15147 +// Host Mode Register Structures
15148 +//
15149 +/**
15150 + * The Host Global Registers structure defines the size and relative
15151 + * field offsets for the Host Mode Global Registers. Host Global
15152 + * Registers offsets 400h-7FFh.
15153 +*/
15154 +typedef struct dwc_otg_host_global_regs
15155 +{
15156 + /** Host Configuration Register. <i>Offset: 400h</i> */
15157 + volatile uint32_t hcfg;
15158 + /** Host Frame Interval Register. <i>Offset: 404h</i> */
15159 + volatile uint32_t hfir;
15160 + /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
15161 + volatile uint32_t hfnum;
15162 + /** Reserved. <i>Offset: 40Ch</i> */
15163 + uint32_t reserved40C;
15164 + /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
15165 + volatile uint32_t hptxsts;
15166 + /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
15167 + volatile uint32_t haint;
15168 + /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
15169 + volatile uint32_t haintmsk;
15170 +} dwc_otg_host_global_regs_t;
15171 +
15172 +/**
15173 + * This union represents the bit fields in the Host Configuration Register.
15174 + * Read the register into the <i>d32</i> member then set/clear the bits using
15175 + * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
15176 + */
15177 +typedef union hcfg_data
15178 +{
15179 + /** raw register data */
15180 + uint32_t d32;
15181 +
15182 + /** register bits */
15183 + struct {
15184 + /** Reserved */
15185 + //unsigned reserved31_03 : 29;
15186 + /** FS/LS Only Support */
15187 + unsigned fslssupp : 1;
15188 + /** FS/LS Phy Clock Select */
15189 +#define DWC_HCFG_30_60_MHZ 0
15190 +#define DWC_HCFG_48_MHZ 1
15191 +#define DWC_HCFG_6_MHZ 2
15192 + unsigned fslspclksel : 2;
15193 + } b;
15194 +} hcfg_data_t;
15195 +
15196 +/**
15197 + * This union represents the bit fields in the Host Frame Remaing/Number
15198 + * Register.
15199 + */
15200 +typedef union hfir_data
15201 +{
15202 + /** raw register data */
15203 + uint32_t d32;
15204 +
15205 + /** register bits */
15206 + struct {
15207 + unsigned reserved : 16;
15208 + unsigned frint : 16;
15209 + } b;
15210 +} hfir_data_t;
15211 +
15212 +/**
15213 + * This union represents the bit fields in the Host Frame Remaing/Number
15214 + * Register.
15215 + */
15216 +typedef union hfnum_data
15217 +{
15218 + /** raw register data */
15219 + uint32_t d32;
15220 +
15221 + /** register bits */
15222 + struct {
15223 + unsigned frrem : 16;
15224 +#define DWC_HFNUM_MAX_FRNUM 0x3FFF
15225 + unsigned frnum : 16;
15226 + } b;
15227 +} hfnum_data_t;
15228 +
15229 +typedef union hptxsts_data
15230 +{
15231 + /** raw register data */
15232 + uint32_t d32;
15233 +
15234 + /** register bits */
15235 + struct {
15236 + /** Top of the Periodic Transmit Request Queue
15237 + * - bit 24 - Terminate (last entry for the selected channel)
15238 + * - bits 26:25 - Token Type
15239 + * - 2'b00 - Zero length
15240 + * - 2'b01 - Ping
15241 + * - 2'b10 - Disable
15242 + * - bits 30:27 - Channel Number
15243 + * - bit 31 - Odd/even microframe
15244 + */
15245 + unsigned ptxqtop_odd : 1;
15246 + unsigned ptxqtop_chnum : 4;
15247 + unsigned ptxqtop_token : 2;
15248 + unsigned ptxqtop_terminate : 1;
15249 + unsigned ptxqspcavail : 8;
15250 + unsigned ptxfspcavail : 16;
15251 + } b;
15252 +} hptxsts_data_t;
15253 +
15254 +/**
15255 + * This union represents the bit fields in the Host Port Control and Status
15256 + * Register. Read the register into the <i>d32</i> member then set/clear the
15257 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
15258 + * hprt0 register.
15259 + */
15260 +typedef union hprt0_data
15261 +{
15262 + /** raw register data */
15263 + uint32_t d32;
15264 + /** register bits */
15265 + struct {
15266 + unsigned reserved19_31 : 13;
15267 +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
15268 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
15269 +#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
15270 + unsigned prtspd : 2;
15271 + unsigned prttstctl : 4;
15272 + unsigned prtpwr : 1;
15273 + unsigned prtlnsts : 2;
15274 + unsigned reserved9 : 1;
15275 + unsigned prtrst : 1;
15276 + unsigned prtsusp : 1;
15277 + unsigned prtres : 1;
15278 + unsigned prtovrcurrchng : 1;
15279 + unsigned prtovrcurract : 1;
15280 + unsigned prtenchng : 1;
15281 + unsigned prtena : 1;
15282 + unsigned prtconndet : 1;
15283 + unsigned prtconnsts : 1;
15284 + } b;
15285 +} hprt0_data_t;
15286 +
15287 +/**
15288 + * This union represents the bit fields in the Host All Interrupt
15289 + * Register.
15290 + */
15291 +typedef union haint_data
15292 +{
15293 + /** raw register data */
15294 + uint32_t d32;
15295 + /** register bits */
15296 + struct {
15297 + unsigned reserved : 16;
15298 + unsigned ch15 : 1;
15299 + unsigned ch14 : 1;
15300 + unsigned ch13 : 1;
15301 + unsigned ch12 : 1;
15302 + unsigned ch11 : 1;
15303 + unsigned ch10 : 1;
15304 + unsigned ch9 : 1;
15305 + unsigned ch8 : 1;
15306 + unsigned ch7 : 1;
15307 + unsigned ch6 : 1;
15308 + unsigned ch5 : 1;
15309 + unsigned ch4 : 1;
15310 + unsigned ch3 : 1;
15311 + unsigned ch2 : 1;
15312 + unsigned ch1 : 1;
15313 + unsigned ch0 : 1;
15314 + } b;
15315 + struct {
15316 + unsigned reserved : 16;
15317 + unsigned chint : 16;
15318 + } b2;
15319 +} haint_data_t;
15320 +
15321 +/**
15322 + * This union represents the bit fields in the Host All Interrupt
15323 + * Register.
15324 + */
15325 +typedef union haintmsk_data
15326 +{
15327 + /** raw register data */
15328 + uint32_t d32;
15329 + /** register bits */
15330 + struct {
15331 + unsigned reserved : 16;
15332 + unsigned ch15 : 1;
15333 + unsigned ch14 : 1;
15334 + unsigned ch13 : 1;
15335 + unsigned ch12 : 1;
15336 + unsigned ch11 : 1;
15337 + unsigned ch10 : 1;
15338 + unsigned ch9 : 1;
15339 + unsigned ch8 : 1;
15340 + unsigned ch7 : 1;
15341 + unsigned ch6 : 1;
15342 + unsigned ch5 : 1;
15343 + unsigned ch4 : 1;
15344 + unsigned ch3 : 1;
15345 + unsigned ch2 : 1;
15346 + unsigned ch1 : 1;
15347 + unsigned ch0 : 1;
15348 + } b;
15349 + struct {
15350 + unsigned reserved : 16;
15351 + unsigned chint : 16;
15352 + } b2;
15353 +} haintmsk_data_t;
15354 +
15355 +/**
15356 + * Host Channel Specific Registers. <i>500h-5FCh</i>
15357 + */
15358 +typedef struct dwc_otg_hc_regs
15359 +{
15360 + /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
15361 + volatile uint32_t hcchar;
15362 + /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
15363 + volatile uint32_t hcsplt;
15364 + /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
15365 + volatile uint32_t hcint;
15366 + /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
15367 + volatile uint32_t hcintmsk;
15368 + /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
15369 + volatile uint32_t hctsiz;
15370 + /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
15371 + volatile uint32_t hcdma;
15372 + /** Reserved. <i>Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch</i> */
15373 + uint32_t reserved[2];
15374 +} dwc_otg_hc_regs_t;
15375 +
15376 +/**
15377 + * This union represents the bit fields in the Host Channel Characteristics
15378 + * Register. Read the register into the <i>d32</i> member then set/clear the
15379 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
15380 + * hcchar register.
15381 + */
15382 +typedef union hcchar_data
15383 +{
15384 + /** raw register data */
15385 + uint32_t d32;
15386 +
15387 + /** register bits */
15388 + struct {
15389 + /** Channel enable */
15390 + unsigned chen : 1;
15391 + /** Channel disable */
15392 + unsigned chdis : 1;
15393 + /**
15394 + * Frame to transmit periodic transaction.
15395 + * 0: even, 1: odd
15396 + */
15397 + unsigned oddfrm : 1;
15398 + /** Device address */
15399 + unsigned devaddr : 7;
15400 + /** Packets per frame for periodic transfers. 0 is reserved. */
15401 + unsigned multicnt : 2;
15402 + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
15403 + unsigned eptype : 2;
15404 + /** 0: Full/high speed device, 1: Low speed device */
15405 + unsigned lspddev : 1;
15406 + unsigned reserved : 1;
15407 + /** 0: OUT, 1: IN */
15408 + unsigned epdir : 1;
15409 + /** Endpoint number */
15410 + unsigned epnum : 4;
15411 + /** Maximum packet size in bytes */
15412 + unsigned mps : 11;
15413 + } b;
15414 +} hcchar_data_t;
15415 +
15416 +typedef union hcsplt_data
15417 +{
15418 + /** raw register data */
15419 + uint32_t d32;
15420 +
15421 + /** register bits */
15422 + struct {
15423 + /** Split Enble */
15424 + unsigned spltena : 1;
15425 + /** Reserved */
15426 + unsigned reserved : 14;
15427 + /** Do Complete Split */
15428 + unsigned compsplt : 1;
15429 + /** Transaction Position */
15430 +#define DWC_HCSPLIT_XACTPOS_MID 0
15431 +#define DWC_HCSPLIT_XACTPOS_END 1
15432 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2
15433 +#define DWC_HCSPLIT_XACTPOS_ALL 3
15434 + unsigned xactpos : 2;
15435 + /** Hub Address */
15436 + unsigned hubaddr : 7;
15437 + /** Port Address */
15438 + unsigned prtaddr : 7;
15439 + } b;
15440 +} hcsplt_data_t;
15441 +
15442 +
15443 +/**
15444 + * This union represents the bit fields in the Host All Interrupt
15445 + * Register.
15446 + */
15447 +typedef union hcint_data
15448 +{
15449 + /** raw register data */
15450 + uint32_t d32;
15451 + /** register bits */
15452 + struct {
15453 + /** Reserved */
15454 + unsigned reserved : 21;
15455 + /** Data Toggle Error */
15456 + unsigned datatglerr : 1;
15457 + /** Frame Overrun */
15458 + unsigned frmovrun : 1;
15459 + /** Babble Error */
15460 + unsigned bblerr : 1;
15461 + /** Transaction Err */
15462 + unsigned xacterr : 1;
15463 + /** NYET Response Received */
15464 + unsigned nyet : 1;
15465 + /** ACK Response Received */
15466 + unsigned ack : 1;
15467 + /** NAK Response Received */
15468 + unsigned nak : 1;
15469 + /** STALL Response Received */
15470 + unsigned stall : 1;
15471 + /** AHB Error */
15472 + unsigned ahberr : 1;
15473 + /** Channel Halted */
15474 + unsigned chhltd : 1;
15475 + /** Transfer Complete */
15476 + unsigned xfercomp : 1;
15477 + } b;
15478 +} hcint_data_t;
15479 +
15480 +/**
15481 + * This union represents the bit fields in the Host Channel Transfer Size
15482 + * Register. Read the register into the <i>d32</i> member then set/clear the
15483 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
15484 + * hcchar register.
15485 + */
15486 +typedef union hctsiz_data
15487 +{
15488 + /** raw register data */
15489 + uint32_t d32;
15490 +
15491 + /** register bits */
15492 + struct {
15493 + /** Do PING protocol when 1 */
15494 + unsigned dopng : 1;
15495 + /**
15496 + * Packet ID for next data packet
15497 + * 0: DATA0
15498 + * 1: DATA2
15499 + * 2: DATA1
15500 + * 3: MDATA (non-Control), SETUP (Control)
15501 + */
15502 +#define DWC_HCTSIZ_DATA0 0
15503 +#define DWC_HCTSIZ_DATA1 2
15504 +#define DWC_HCTSIZ_DATA2 1
15505 +#define DWC_HCTSIZ_MDATA 3
15506 +#define DWC_HCTSIZ_SETUP 3
15507 + unsigned pid : 2;
15508 + /** Data packets to transfer */
15509 + unsigned pktcnt : 10;
15510 + /** Total transfer size in bytes */
15511 + unsigned xfersize : 19;
15512 + } b;
15513 +} hctsiz_data_t;
15514 +
15515 +/**
15516 + * This union represents the bit fields in the Host Channel Interrupt Mask
15517 + * Register. Read the register into the <i>d32</i> member then set/clear the
15518 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
15519 + * hcintmsk register.
15520 + */
15521 +typedef union hcintmsk_data
15522 +{
15523 + /** raw register data */
15524 + uint32_t d32;
15525 +
15526 + /** register bits */
15527 + struct {
15528 + unsigned reserved : 21;
15529 + unsigned datatglerr : 1;
15530 + unsigned frmovrun : 1;
15531 + unsigned bblerr : 1;
15532 + unsigned xacterr : 1;
15533 + unsigned nyet : 1;
15534 + unsigned ack : 1;
15535 + unsigned nak : 1;
15536 + unsigned stall : 1;
15537 + unsigned ahberr : 1;
15538 + unsigned chhltd : 1;
15539 + unsigned xfercompl : 1;
15540 + } b;
15541 +} hcintmsk_data_t;
15542 +
15543 +/** OTG Host Interface Structure.
15544 + *
15545 + * The OTG Host Interface Structure structure contains information
15546 + * needed to manage the DWC_otg controller acting in host mode. It
15547 + * represents the programming view of the host-specific aspects of the
15548 + * controller.
15549 + */
15550 +typedef struct dwc_otg_host_if {
15551 + /** Host Global Registers starting at offset 400h.*/
15552 + dwc_otg_host_global_regs_t *host_global_regs;
15553 +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
15554 +
15555 + /** Host Port 0 Control and Status Register */
15556 + volatile uint32_t *hprt0;
15557 +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
15558 +
15559 +
15560 + /** Host Channel Specific Registers at offsets 500h-5FCh. */
15561 + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
15562 +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
15563 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20
15564 +
15565 +
15566 + /* Host configuration information */
15567 + /** Number of Host Channels (range: 1-16) */
15568 + uint8_t num_host_channels;
15569 + /** Periodic EPs supported (0: no, 1: yes) */
15570 + uint8_t perio_eps_supported;
15571 + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
15572 + uint16_t perio_tx_fifo_size;
15573 +
15574 +} dwc_otg_host_if_t;
15575 +
15576 +#endif
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