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[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches / 105-header_xway.patch
1 --- /dev/null
2 +++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h
3 @@ -0,0 +1,18 @@
4 +/*
5 + * This program is free software; you can redistribute it and/or modify it
6 + * under the terms of the GNU General Public License version 2 as published
7 + * by the Free Software Foundation.
8 + *
9 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
10 + */
11 +
12 +#ifndef __LANTIQ_IRQ_H
13 +#define __LANTIQ_IRQ_H
14 +
15 +#include <xway_irq.h>
16 +
17 +#define NR_IRQS 256
18 +
19 +#include_next <irq.h>
20 +
21 +#endif
22 --- /dev/null
23 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
24 @@ -0,0 +1,155 @@
25 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
26 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
27 +
28 +
29 +/******************************************************************************
30 + Copyright (c) 2002, Infineon Technologies. All rights reserved.
31 +
32 + No Warranty
33 + Because the program is licensed free of charge, there is no warranty for
34 + the program, to the extent permitted by applicable law. Except when
35 + otherwise stated in writing the copyright holders and/or other parties
36 + provide the program "as is" without warranty of any kind, either
37 + expressed or implied, including, but not limited to, the implied
38 + warranties of merchantability and fitness for a particular purpose. The
39 + entire risk as to the quality and performance of the program is with
40 + you. should the program prove defective, you assume the cost of all
41 + necessary servicing, repair or correction.
42 +
43 + In no event unless required by applicable law or agreed to in writing
44 + will any copyright holder, or any other party who may modify and/or
45 + redistribute the program as permitted above, be liable to you for
46 + damages, including any general, special, incidental or consequential
47 + damages arising out of the use or inability to use the program
48 + (including but not limited to loss of data or data being rendered
49 + inaccurate or losses sustained by you or third parties or a failure of
50 + the program to operate with any other programs), even if such holder or
51 + other party has been advised of the possibility of such damages.
52 +******************************************************************************/
53 +
54 +
55 +/*
56 + * ####################################
57 + * Definition
58 + * ####################################
59 + */
60 +
61 +/*
62 + * Available Timer/Counter Index
63 + */
64 +#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
65 +#define TIMER_ANY 0x00
66 +#define TIMER1A TIMER(1, 0)
67 +#define TIMER1B TIMER(1, 1)
68 +#define TIMER2A TIMER(2, 0)
69 +#define TIMER2B TIMER(2, 1)
70 +#define TIMER3A TIMER(3, 0)
71 +#define TIMER3B TIMER(3, 1)
72 +
73 +/*
74 + * Flag of Timer/Counter
75 + * These flags specify the way in which timer is configured.
76 + */
77 +/* Bit size of timer/counter. */
78 +#define TIMER_FLAG_16BIT 0x0000
79 +#define TIMER_FLAG_32BIT 0x0001
80 +/* Switch between timer and counter. */
81 +#define TIMER_FLAG_TIMER 0x0000
82 +#define TIMER_FLAG_COUNTER 0x0002
83 +/* Stop or continue when overflowing/underflowing. */
84 +#define TIMER_FLAG_ONCE 0x0000
85 +#define TIMER_FLAG_CYCLIC 0x0004
86 +/* Count up or counter down. */
87 +#define TIMER_FLAG_UP 0x0000
88 +#define TIMER_FLAG_DOWN 0x0008
89 +/* Count on specific level or edge. */
90 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
91 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
92 +#define TIMER_FLAG_RISE_EDGE 0x0010
93 +#define TIMER_FLAG_FALL_EDGE 0x0020
94 +#define TIMER_FLAG_ANY_EDGE 0x0030
95 +/* Signal is syncronous to module clock or not. */
96 +#define TIMER_FLAG_UNSYNC 0x0000
97 +#define TIMER_FLAG_SYNC 0x0080
98 +/* Different interrupt handle type. */
99 +#define TIMER_FLAG_NO_HANDLE 0x0000
100 +#if defined(__KERNEL__)
101 + #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
102 +#endif // defined(__KERNEL__)
103 +#define TIMER_FLAG_SIGNAL 0x0300
104 +/* Internal clock source or external clock source */
105 +#define TIMER_FLAG_INT_SRC 0x0000
106 +#define TIMER_FLAG_EXT_SRC 0x1000
107 +
108 +
109 +/*
110 + * ioctl Command
111 + */
112 +#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
113 +#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
114 +#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
115 +#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
116 +#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
117 +#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
118 +#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
119 +#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
120 +
121 +/*
122 + * Data Type Used to Call ioctl
123 + */
124 +struct gptu_ioctl_param {
125 + unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
126 + * GPTU_SET_COUNTER, this field is ID of expected *
127 + * timer/counter. If it's zero, a timer/counter would *
128 + * be dynamically allocated and ID would be stored in *
129 + * this field. *
130 + * In command GPTU_GET_COUNT_VALUE, this field is *
131 + * ignored. *
132 + * In other command, this field is ID of timer/counter *
133 + * allocated. */
134 + unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
135 + * GPTU_SET_COUNTER, this field contains flags to *
136 + * specify how to configure timer/counter. *
137 + * In command GPTU_START_TIMER, zero indicate start *
138 + * and non-zero indicate resume timer/counter. *
139 + * In other command, this field is ignored. */
140 + unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
141 + * init/reload value. *
142 + * In command GPTU_SET_TIMER, this field contains *
143 + * frequency (0.001Hz) of timer. *
144 + * In command GPTU_GET_COUNT_VALUE, current count *
145 + * value would be stored in this field. *
146 + * In command GPTU_CALCULATE_DIVIDER, this field *
147 + * contains frequency wanted, and after calculation, *
148 + * divider would be stored in this field to overwrite *
149 + * the frequency. *
150 + * In other command, this field is ignored. */
151 + int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
152 + * if signal is required, this field contains process *
153 + * ID to which signal would be sent. *
154 + * In other command, this field is ignored. */
155 + int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
156 + * if signal is required, this field contains signal *
157 + * number which would be sent. *
158 + * In other command, this field is ignored. */
159 +};
160 +
161 +/*
162 + * ####################################
163 + * Data Type
164 + * ####################################
165 + */
166 +typedef void (*timer_callback)(unsigned long arg);
167 +
168 +extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
169 +extern int ifxmips_free_timer(unsigned int);
170 +extern int ifxmips_start_timer(unsigned int, int);
171 +extern int ifxmips_stop_timer(unsigned int);
172 +extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
173 +extern int ifxmips_get_count_value(unsigned int, unsigned long *);
174 +extern u32 ifxmips_cal_divider(unsigned long);
175 +extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
176 +extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
177 + u32 reload, unsigned long arg1, unsigned long arg2);
178 +
179 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
180 --- /dev/null
181 +++ b/arch/mips/include/asm/mach-lantiq/xway/xway.h
182 @@ -0,0 +1,121 @@
183 +/*
184 + * This program is free software; you can redistribute it and/or modify it
185 + * under the terms of the GNU General Public License version 2 as published
186 + * by the Free Software Foundation.
187 + *
188 + * Copyright (C) 2005 infineon
189 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
190 + */
191 +
192 +#ifdef CONFIG_SOC_LANTIQ_XWAY
193 +
194 +#ifndef _LQ_XWAY_H__
195 +#define _LQ_XWAY_H__
196 +
197 +#include <lantiq.h>
198 +
199 +/* request a non-gpio and set the PIO config */
200 +extern int lq_gpio_request(unsigned int pin, unsigned int alt0,
201 + unsigned int alt1, unsigned int dir, const char *name);
202 +extern int lq_gpio_setconfig(unsigned int pin, unsigned int reg, unsigned int val);
203 +
204 +extern void lq_pmu_enable(unsigned int module);
205 +extern void lq_pmu_disable(unsigned int module);
206 +
207 +extern unsigned int lq_get_fpi_bus_clock(int bus);
208 +
209 +#define BOARD_SYSTEM_TYPE "LANTIQ"
210 +
211 +/*------------ Chip IDs */
212 +#define SOC_ID_DANUBE1 0x129
213 +#define SOC_ID_DANUBE2 0x12B
214 +#define SOC_ID_TWINPASS 0x12D
215 +#define SOC_ID_ARX188 0x16C
216 +#define SOC_ID_ARX168 0x16D
217 +#define SOC_ID_ARX182 0x16F
218 +
219 +/*------------ SoC Types */
220 +#define SOC_TYPE_DANUBE 0x01
221 +#define SOC_TYPE_TWINPASS 0x02
222 +#define SOC_TYPE_AR9 0x03
223 +
224 +/*------------ ASC0/1 */
225 +#define LQ_ASC0_BASE 0x1E100400
226 +#define LQ_ASC1_BASE 0x1E100C00
227 +#define LQ_ASC_SIZE 0x400
228 +
229 +/*------------ RCU */
230 +#define LQ_RCU_BASE_ADDR 0xBF203000
231 +
232 +/*------------ GPTU */
233 +#define LQ_GPTU_BASE_ADDR 0xB8000300
234 +
235 +/*------------ EBU */
236 +#define LQ_EBU_GPIO_START 0x14000000
237 +#define LQ_EBU_GPIO_SIZE 0x1000
238 +
239 +#define LQ_EBU_BASE_ADDR 0xBE105300
240 +
241 +#define LQ_EBU_BUSCON0 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0060))
242 +#define LQ_EBU_PCC_CON ((u32 *)(LQ_EBU_BASE_ADDR + 0x0090))
243 +#define LQ_EBU_PCC_IEN ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A4))
244 +#define LQ_EBU_PCC_ISTAT ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A0))
245 +#define LQ_EBU_BUSCON1 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0064))
246 +#define LQ_EBU_ADDRSEL1 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0024))
247 +
248 +#define EBU_WRDIS 0x80000000
249 +
250 +/*------------ CGU */
251 +#define LQ_CGU_BASE_ADDR (KSEG1 + 0x1F103000)
252 +
253 +/*------------ PMU */
254 +#define LQ_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
255 +
256 +#define PMU_DMA 0x0020
257 +#define PMU_USB 0x8041
258 +#define PMU_LED 0x0800
259 +#define PMU_GPT 0x1000
260 +#define PMU_PPE 0x2000
261 +#define PMU_FPI 0x4000
262 +#define PMU_SWITCH 0x10000000
263 +
264 +/*------------ ETOP */
265 +#define LQ_PPE32_BASE_ADDR 0xBE180000
266 +#define LQ_PPE32_SIZE 0x40000
267 +
268 +/*------------ DMA */
269 +#define LQ_DMA_BASE_ADDR 0xBE104100
270 +
271 +/*------------ PCI */
272 +#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
273 +#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
274 +
275 +/*------------ WDT */
276 +#define LQ_WDT_BASE 0x1F880000
277 +#define LQ_WDT_SIZE 0x400
278 +
279 +/*------------ Serial To Parallel conversion */
280 +#define LQ_STP_BASE 0x1E100BB0
281 +#define LQ_STP_SIZE 0x40
282 +
283 +/*------------ GPIO */
284 +#define LQ_GPIO0_BASE_ADDR 0x1E100B10
285 +#define LQ_GPIO1_BASE_ADDR 0x1E100B40
286 +#define LQ_GPIO_SIZE 0x30
287 +
288 +/*------------ SSC */
289 +#define LQ_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
290 +
291 +/*------------ MEI */
292 +#define LQ_MEI_BASE_ADDR (KSEG1 + 0x1E116000)
293 +
294 +/*------------ DEU */
295 +#define LQ_DEU_BASE (KSEG1 + 0x1E103100)
296 +
297 +/*------------ MPS */
298 +#define LQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
299 +#define LQ_MPS_CHIPID ((u32 *)(LQ_MPS_BASE_ADDR + 0x0344))
300 +
301 +#endif
302 +
303 +#endif
304 --- /dev/null
305 +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
306 @@ -0,0 +1,194 @@
307 +/*
308 + * This program is free software; you can redistribute it and/or modify it
309 + * under the terms of the GNU General Public License version 2 as published
310 + * by the Free Software Foundation.
311 + *
312 + * This program is distributed in the hope that it will be useful,
313 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
314 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
315 + * GNU General Public License for more details.
316 + *
317 + * You should have received a copy of the GNU General Public License
318 + * along with this program; if not, write to the Free Software
319 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
320 + *
321 + * Copyright (C) 2005 infineon
322 + * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
323 + *
324 + */
325 +#ifndef _LQ_DMA_H__
326 +#define _LQ_DMA_H__
327 +
328 +#define RCV_INT 1
329 +#define TX_BUF_FULL_INT 2
330 +#define TRANSMIT_CPT_INT 4
331 +#define LQ_DMA_CH_ON 1
332 +#define LQ_DMA_CH_OFF 0
333 +#define LQ_DMA_CH_DEFAULT_WEIGHT 100
334 +
335 +enum attr_t{
336 + TX = 0,
337 + RX = 1,
338 + RESERVED = 2,
339 + DEFAULT = 3,
340 +};
341 +
342 +#define DMA_OWN 1
343 +#define CPU_OWN 0
344 +#define DMA_MAJOR 250
345 +
346 +#define DMA_DESC_OWN_CPU 0x0
347 +#define DMA_DESC_OWN_DMA 0x80000000
348 +#define DMA_DESC_CPT_SET 0x40000000
349 +#define DMA_DESC_SOP_SET 0x20000000
350 +#define DMA_DESC_EOP_SET 0x10000000
351 +
352 +#define MISCFG_MASK 0x40
353 +#define RDERR_MASK 0x20
354 +#define CHOFF_MASK 0x10
355 +#define DESCPT_MASK 0x8
356 +#define DUR_MASK 0x4
357 +#define EOP_MASK 0x2
358 +
359 +#define DMA_DROP_MASK (1<<31)
360 +
361 +#define LQ_DMA_RX -1
362 +#define LQ_DMA_TX 1
363 +
364 +struct dma_chan_map {
365 + const char *dev_name;
366 + enum attr_t dir;
367 + int pri;
368 + int irq;
369 + int rel_chan_no;
370 +};
371 +
372 +#ifdef CONFIG_CPU_LITTLE_ENDIAN
373 +struct rx_desc {
374 + u32 data_length:16;
375 + volatile u32 reserved:7;
376 + volatile u32 byte_offset:2;
377 + volatile u32 Burst_length_offset:3;
378 + volatile u32 EoP:1;
379 + volatile u32 Res:1;
380 + volatile u32 C:1;
381 + volatile u32 OWN:1;
382 + volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
383 +};
384 +
385 +struct tx_desc {
386 + volatile u32 data_length:16;
387 + volatile u32 reserved1:7;
388 + volatile u32 byte_offset:5;
389 + volatile u32 EoP:1;
390 + volatile u32 SoP:1;
391 + volatile u32 C:1;
392 + volatile u32 OWN:1;
393 + volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
394 +};
395 +#else /* BIG */
396 +struct rx_desc {
397 + union {
398 + struct {
399 + volatile u32 OWN:1;
400 + volatile u32 C:1;
401 + volatile u32 SoP:1;
402 + volatile u32 EoP:1;
403 + volatile u32 Burst_length_offset:3;
404 + volatile u32 byte_offset:2;
405 + volatile u32 reserve:7;
406 + volatile u32 data_length:16;
407 + } field;
408 + volatile u32 word;
409 + } status;
410 + volatile u32 Data_Pointer;
411 +};
412 +
413 +struct tx_desc {
414 + union {
415 + struct {
416 + volatile u32 OWN:1;
417 + volatile u32 C:1;
418 + volatile u32 SoP:1;
419 + volatile u32 EoP:1;
420 + volatile u32 byte_offset:5;
421 + volatile u32 reserved:7;
422 + volatile u32 data_length:16;
423 + } field;
424 + volatile u32 word;
425 + } status;
426 + volatile u32 Data_Pointer;
427 +};
428 +#endif /* ENDIAN */
429 +
430 +struct dma_channel_info {
431 + /* relative channel number */
432 + int rel_chan_no;
433 + /* class for this channel for QoS */
434 + int pri;
435 + /* specify byte_offset */
436 + int byte_offset;
437 + /* direction */
438 + int dir;
439 + /* irq number */
440 + int irq;
441 + /* descriptor parameter */
442 + int desc_base;
443 + int desc_len;
444 + int curr_desc;
445 + int prev_desc; /* only used if it is a tx channel*/
446 + /* weight setting for WFQ algorithm*/
447 + int weight;
448 + int default_weight;
449 + int packet_size;
450 + int burst_len;
451 + /* on or off of this channel */
452 + int control;
453 + /* optional information for the upper layer devices */
454 +#if defined(CONFIG_LQ_ETHERNET_D2) || defined(CONFIG_LQ_PPA)
455 + void *opt[64];
456 +#else
457 + void *opt[25];
458 +#endif
459 + /* Pointer to the peripheral device who is using this channel */
460 + void *dma_dev;
461 + /* channel operations */
462 + void (*open)(struct dma_channel_info *pCh);
463 + void (*close)(struct dma_channel_info *pCh);
464 + void (*reset)(struct dma_channel_info *pCh);
465 + void (*enable_irq)(struct dma_channel_info *pCh);
466 + void (*disable_irq)(struct dma_channel_info *pCh);
467 +};
468 +
469 +struct dma_device_info {
470 + /* device name of this peripheral */
471 + char device_name[15];
472 + int reserved;
473 + int tx_burst_len;
474 + int rx_burst_len;
475 + int default_weight;
476 + int current_tx_chan;
477 + int current_rx_chan;
478 + int num_tx_chan;
479 + int num_rx_chan;
480 + int max_rx_chan_num;
481 + int max_tx_chan_num;
482 + struct dma_channel_info *tx_chan[20];
483 + struct dma_channel_info *rx_chan[20];
484 + /*functions, optional*/
485 + u8 *(*buffer_alloc)(int len, int *offset, void **opt);
486 + void (*buffer_free)(u8 *dataptr, void *opt);
487 + int (*intr_handler)(struct dma_device_info *info, int status);
488 + void *priv; /* used by peripheral driver only */
489 +};
490 +
491 +struct dma_device_info *dma_device_reserve(char *dev_name);
492 +void dma_device_release(struct dma_device_info *dev);
493 +void dma_device_register(struct dma_device_info *info);
494 +void dma_device_unregister(struct dma_device_info *info);
495 +int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt);
496 +int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len,
497 + void *opt);
498 +
499 +#endif
500 +
501 --- /dev/null
502 +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_irq.h
503 @@ -0,0 +1,62 @@
504 +/*
505 + * This program is free software; you can redistribute it and/or modify it
506 + * under the terms of the GNU General Public License version 2 as published
507 + * by the Free Software Foundation.
508 + *
509 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
510 + */
511 +
512 +#ifndef _LANTIQ_XWAY_IRQ_H__
513 +#define _LANTIQ_XWAY_IRQ_H__
514 +
515 +#define INT_NUM_IRQ0 8
516 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
517 +#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
518 +#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
519 +#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
520 +#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
521 +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
522 +
523 +#define LQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 7))
524 +#define LQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 2)
525 +#define LQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 3)
526 +
527 +#define LQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
528 +#define LQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
529 +#define LQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
530 +
531 +#define LQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
532 +#define LQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
533 +
534 +#define LQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
535 +#define LQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
536 +#define LQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
537 +
538 +#define MIPS_CPU_TIMER_IRQ 7
539 +
540 +#define LQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
541 +#define LQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
542 +#define LQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
543 +#define LQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
544 +#define LQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
545 +#define LQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
546 +#define LQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
547 +#define LQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
548 +#define LQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
549 +#define LQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
550 +#define LQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
551 +#define LQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
552 +#define LQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
553 +#define LQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
554 +#define LQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
555 +#define LQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
556 +#define LQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
557 +#define LQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
558 +#define LQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
559 +#define LQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
560 +
561 +#define LQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
562 +
563 +#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
564 +
565 +#endif
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