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a13022786b04ee2d2892aab0fab65b5e145dc57c
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches / 200-serial.patch
1 --- a/drivers/serial/Kconfig
2 +++ b/drivers/serial/Kconfig
3 @@ -1397,6 +1397,14 @@
4 help
5 Support for Console on the NWP serial ports.
6
7 +config SERIAL_LANTIQ
8 + bool "Lantiq serial driver"
9 + depends on LANTIQ
10 + select SERIAL_CORE
11 + select SERIAL_CORE_CONSOLE
12 + help
13 + Driver for the Lantiq SoC ASC hardware
14 +
15 config SERIAL_QE
16 tristate "Freescale QUICC Engine serial port support"
17 depends on QUICC_ENGINE
18 --- a/drivers/serial/Makefile
19 +++ b/drivers/serial/Makefile
20 @@ -84,3 +84,4 @@
21 obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o
22 obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o
23 obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
24 +obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
25 --- /dev/null
26 +++ b/drivers/serial/lantiq.c
27 @@ -0,0 +1,772 @@
28 +/*
29 + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
30 + *
31 + * This program is free software; you can redistribute it and/or modify it
32 + * under the terms of the GNU General Public License version 2 as published
33 + * by the Free Software Foundation.
34 + *
35 + * This program is distributed in the hope that it will be useful,
36 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 + * GNU General Public License for more details.
39 + *
40 + * You should have received a copy of the GNU General Public License
41 + * along with this program; if not, write to the Free Software
42 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43 + *
44 + * Copyright (C) 2004 Infineon IFAP DC COM CPE
45 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
46 + * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
47 + * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
48 + */
49 +
50 +#include <linux/slab.h>
51 +#include <linux/module.h>
52 +#include <linux/ioport.h>
53 +#include <linux/init.h>
54 +#include <linux/console.h>
55 +#include <linux/sysrq.h>
56 +#include <linux/device.h>
57 +#include <linux/tty.h>
58 +#include <linux/tty_flip.h>
59 +#include <linux/serial_core.h>
60 +#include <linux/serial.h>
61 +#include <linux/platform_device.h>
62 +#include <linux/io.h>
63 +#include <linux/clk.h>
64 +
65 +#define lq_r32(reg) __raw_readl(reg)
66 +#define lq_r8(reg) __raw_readb(reg)
67 +#define lq_w32(val, reg) __raw_writel(val, reg)
68 +#define lq_w8(val, reg) __raw_writeb(val, reg)
69 +#define lq_w32_mask(clear, set, reg) lq_w32((lq_r32(reg) & ~(clear)) | (set), reg)
70 +
71 +#define PORT_IFXMIPSASC 111
72 +#define MAXPORTS 2
73 +
74 +#define UART_DUMMY_UER_RX 1
75 +
76 +#define DRVNAME "lq_asc"
77 +
78 +#ifdef __BIG_ENDIAN
79 +#define IFXMIPS_ASC_TBUF (0x0020 + 3)
80 +#define IFXMIPS_ASC_RBUF (0x0024 + 3)
81 +#else
82 +#define IFXMIPS_ASC_TBUF 0x0020
83 +#define IFXMIPS_ASC_RBUF 0x0024
84 +#endif
85 +
86 +#define IFXMIPS_ASC_FSTAT 0x0048
87 +#define IFXMIPS_ASC_WHBSTATE 0x0018
88 +#define IFXMIPS_ASC_STATE 0x0014
89 +#define IFXMIPS_ASC_IRNCR 0x00F8
90 +#define IFXMIPS_ASC_CLC 0x0000
91 +#define IFXMIPS_ASC_ID 0x0008
92 +#define IFXMIPS_ASC_PISEL 0x0004
93 +#define IFXMIPS_ASC_TXFCON 0x0044
94 +#define IFXMIPS_ASC_RXFCON 0x0040
95 +#define IFXMIPS_ASC_CON 0x0010
96 +#define IFXMIPS_ASC_BG 0x0050
97 +#define IFXMIPS_ASC_IRNREN 0x00F4
98 +
99 +#define ASC_IRNREN_TX 0x1
100 +#define ASC_IRNREN_RX 0x2
101 +#define ASC_IRNREN_ERR 0x4
102 +#define ASC_IRNREN_TX_BUF 0x8
103 +#define ASC_IRNCR_TIR 0x1
104 +#define ASC_IRNCR_RIR 0x2
105 +#define ASC_IRNCR_EIR 0x4
106 +
107 +#define ASCOPT_CSIZE 0x3
108 +#define ASCOPT_CS7 0x1
109 +#define ASCOPT_CS8 0x2
110 +#define ASCOPT_PARENB 0x4
111 +#define ASCOPT_STOPB 0x8
112 +#define ASCOPT_PARODD 0x0
113 +#define ASCOPT_CREAD 0x20
114 +#define TXFIFO_FL 1
115 +#define RXFIFO_FL 1
116 +#define ASCCLC_DISS 0x2
117 +#define ASCCLC_RMCMASK 0x0000FF00
118 +#define ASCCLC_RMCOFFSET 8
119 +#define ASCCON_M_8ASYNC 0x0
120 +#define ASCCON_M_7ASYNC 0x2
121 +#define ASCCON_ODD 0x00000020
122 +#define ASCCON_STP 0x00000080
123 +#define ASCCON_BRS 0x00000100
124 +#define ASCCON_FDE 0x00000200
125 +#define ASCCON_R 0x00008000
126 +#define ASCCON_FEN 0x00020000
127 +#define ASCCON_ROEN 0x00080000
128 +#define ASCCON_TOEN 0x00100000
129 +#define ASCSTATE_PE 0x00010000
130 +#define ASCSTATE_FE 0x00020000
131 +#define ASCSTATE_ROE 0x00080000
132 +#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
133 +#define ASCWHBSTATE_CLRREN 0x00000001
134 +#define ASCWHBSTATE_SETREN 0x00000002
135 +#define ASCWHBSTATE_CLRPE 0x00000004
136 +#define ASCWHBSTATE_CLRFE 0x00000008
137 +#define ASCWHBSTATE_CLRROE 0x00000020
138 +#define ASCTXFCON_TXFEN 0x0001
139 +#define ASCTXFCON_TXFFLU 0x0002
140 +#define ASCTXFCON_TXFITLMASK 0x3F00
141 +#define ASCTXFCON_TXFITLOFF 8
142 +#define ASCRXFCON_RXFEN 0x0001
143 +#define ASCRXFCON_RXFFLU 0x0002
144 +#define ASCRXFCON_RXFITLMASK 0x3F00
145 +#define ASCRXFCON_RXFITLOFF 8
146 +#define ASCFSTAT_RXFFLMASK 0x003F
147 +#define ASCFSTAT_TXFFLMASK 0x3F00
148 +#define ASCFSTAT_TXFFLOFF 8
149 +#define ASCFSTAT_RXFREEMASK 0x003F0000
150 +#define ASCFSTAT_RXFREEOFF 16
151 +#define ASCFSTAT_TXFREEMASK 0x3F000000
152 +#define ASCFSTAT_TXFREEOFF 24
153 +
154 +static void lqasc_tx_chars(struct uart_port *port);
155 +extern void prom_printf(const char *fmt, ...);
156 +static struct lq_uart_port *lqasc_port[2];
157 +static struct uart_driver lqasc_reg;
158 +
159 +struct lq_uart_port {
160 + struct uart_port port;
161 + struct clk *clk;
162 + unsigned int tx_irq;
163 + unsigned int rx_irq;
164 + unsigned int err_irq;
165 +};
166 +
167 +static inline struct
168 +lq_uart_port *to_lq_uart_port(struct uart_port *port)
169 +{
170 + return container_of(port, struct lq_uart_port, port);
171 +}
172 +
173 +static void
174 +lqasc_stop_tx(struct uart_port *port)
175 +{
176 + return;
177 +}
178 +
179 +static void
180 +lqasc_start_tx(struct uart_port *port)
181 +{
182 + unsigned long flags;
183 + local_irq_save(flags);
184 + lqasc_tx_chars(port);
185 + local_irq_restore(flags);
186 + return;
187 +}
188 +
189 +static void
190 +lqasc_stop_rx(struct uart_port *port)
191 +{
192 + lq_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE);
193 +}
194 +
195 +static void
196 +lqasc_enable_ms(struct uart_port *port)
197 +{
198 +}
199 +
200 +static void
201 +lqasc_rx_chars(struct uart_port *port)
202 +{
203 + struct tty_struct *tty = port->state->port.tty;
204 + unsigned int ch = 0, rsr = 0, fifocnt;
205 +
206 + fifocnt = lq_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
207 + while (fifocnt--) {
208 + u8 flag = TTY_NORMAL;
209 + ch = lq_r8(port->membase + IFXMIPS_ASC_RBUF);
210 + rsr = (lq_r32(port->membase + IFXMIPS_ASC_STATE)
211 + & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
212 + tty_flip_buffer_push(tty);
213 + port->icount.rx++;
214 +
215 + /*
216 + * Note that the error handling code is
217 + * out of the main execution path
218 + */
219 + if (rsr & ASCSTATE_ANY) {
220 + if (rsr & ASCSTATE_PE) {
221 + port->icount.parity++;
222 + lq_w32_mask(0, ASCWHBSTATE_CLRPE,
223 + port->membase + IFXMIPS_ASC_WHBSTATE);
224 + } else if (rsr & ASCSTATE_FE) {
225 + port->icount.frame++;
226 + lq_w32_mask(0, ASCWHBSTATE_CLRFE,
227 + port->membase + IFXMIPS_ASC_WHBSTATE);
228 + }
229 + if (rsr & ASCSTATE_ROE) {
230 + port->icount.overrun++;
231 + lq_w32_mask(0, ASCWHBSTATE_CLRROE,
232 + port->membase + IFXMIPS_ASC_WHBSTATE);
233 + }
234 +
235 + rsr &= port->read_status_mask;
236 +
237 + if (rsr & ASCSTATE_PE)
238 + flag = TTY_PARITY;
239 + else if (rsr & ASCSTATE_FE)
240 + flag = TTY_FRAME;
241 + }
242 +
243 + if ((rsr & port->ignore_status_mask) == 0)
244 + tty_insert_flip_char(tty, ch, flag);
245 +
246 + if (rsr & ASCSTATE_ROE)
247 + /*
248 + * Overrun is special, since it's reported
249 + * immediately, and doesn't affect the current
250 + * character
251 + */
252 + tty_insert_flip_char(tty, 0, TTY_OVERRUN);
253 + }
254 + if (ch != 0)
255 + tty_flip_buffer_push(tty);
256 + return;
257 +}
258 +
259 +static void
260 +lqasc_tx_chars(struct uart_port *port)
261 +{
262 + struct circ_buf *xmit = &port->state->xmit;
263 + if (uart_tx_stopped(port)) {
264 + lqasc_stop_tx(port);
265 + return;
266 + }
267 +
268 + while (((lq_r32(port->membase + IFXMIPS_ASC_FSTAT) &
269 + ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
270 + if (port->x_char) {
271 + lq_w8(port->x_char, port->membase + IFXMIPS_ASC_TBUF);
272 + port->icount.tx++;
273 + port->x_char = 0;
274 + continue;
275 + }
276 +
277 + if (uart_circ_empty(xmit))
278 + break;
279 +
280 + lq_w8(port->state->xmit.buf[port->state->xmit.tail],
281 + port->membase + IFXMIPS_ASC_TBUF);
282 + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
283 + port->icount.tx++;
284 + }
285 +
286 + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
287 + uart_write_wakeup(port);
288 +}
289 +
290 +static irqreturn_t
291 +lqasc_tx_int(int irq, void *_port)
292 +{
293 + struct uart_port *port = (struct uart_port *)_port;
294 + lq_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR);
295 + lqasc_start_tx(port);
296 + return IRQ_HANDLED;
297 +}
298 +
299 +static irqreturn_t
300 +lqasc_err_int(int irq, void *_port)
301 +{
302 + struct uart_port *port = (struct uart_port *)_port;
303 + /* clear any pending interrupts */
304 + lq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE,
305 + port->membase + IFXMIPS_ASC_WHBSTATE);
306 + return IRQ_HANDLED;
307 +}
308 +
309 +static irqreturn_t
310 +lqasc_rx_int(int irq, void *_port)
311 +{
312 + struct uart_port *port = (struct uart_port *)_port;
313 + lq_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR);
314 + lqasc_rx_chars(port);
315 + return IRQ_HANDLED;
316 +}
317 +
318 +static unsigned int
319 +lqasc_tx_empty(struct uart_port *port)
320 +{
321 + int status;
322 + status = lq_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
323 + return status ? 0 : TIOCSER_TEMT;
324 +}
325 +
326 +static unsigned int
327 +lqasc_get_mctrl(struct uart_port *port)
328 +{
329 + return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
330 +}
331 +
332 +static void
333 +lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
334 +{
335 +}
336 +
337 +static void
338 +lqasc_break_ctl(struct uart_port *port, int break_state)
339 +{
340 +}
341 +
342 +static int
343 +lqasc_startup(struct uart_port *port)
344 +{
345 + struct lq_uart_port *ifx_port = to_lq_uart_port(port);
346 + int retval;
347 +
348 + port->uartclk = clk_get_rate(ifx_port->clk);
349 +
350 + lq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
351 + port->membase + IFXMIPS_ASC_CLC);
352 +
353 + lq_w32(0, port->membase + IFXMIPS_ASC_PISEL);
354 + lq_w32(
355 + ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
356 + ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
357 + port->membase + IFXMIPS_ASC_TXFCON);
358 + lq_w32(
359 + ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
360 + | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
361 + port->membase + IFXMIPS_ASC_RXFCON);
362 + /* make sure other settings are written to hardware before setting enable bits */
363 + wmb();
364 + lq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
365 + ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
366 +
367 + retval = request_irq(ifx_port->tx_irq, lqasc_tx_int,
368 + IRQF_DISABLED, "asc_tx", port);
369 + if (retval) {
370 + pr_err("failed to request lqasc_tx_int\n");
371 + return retval;
372 + }
373 +
374 + retval = request_irq(ifx_port->rx_irq, lqasc_rx_int,
375 + IRQF_DISABLED, "asc_rx", port);
376 + if (retval) {
377 + pr_err("failed to request lqasc_rx_int\n");
378 + goto err1;
379 + }
380 +
381 + retval = request_irq(ifx_port->err_irq, lqasc_err_int,
382 + IRQF_DISABLED, "asc_err", port);
383 + if (retval) {
384 + pr_err("failed to request lqasc_err_int\n");
385 + goto err2;
386 + }
387 +
388 + lq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
389 + port->membase + IFXMIPS_ASC_IRNREN);
390 + return 0;
391 +
392 +err2:
393 + free_irq(ifx_port->rx_irq, port);
394 +err1:
395 + free_irq(ifx_port->tx_irq, port);
396 + return retval;
397 +}
398 +
399 +static void
400 +lqasc_shutdown(struct uart_port *port)
401 +{
402 + struct lq_uart_port *ifx_port = to_lq_uart_port(port);
403 + free_irq(ifx_port->tx_irq, port);
404 + free_irq(ifx_port->rx_irq, port);
405 + free_irq(ifx_port->err_irq, port);
406 +
407 + lq_w32(0, port->membase + IFXMIPS_ASC_CON);
408 + lq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
409 + port->membase + IFXMIPS_ASC_RXFCON);
410 + lq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
411 + port->membase + IFXMIPS_ASC_TXFCON);
412 +}
413 +
414 +static void
415 +lqasc_set_termios(struct uart_port *port,
416 + struct ktermios *new, struct ktermios *old)
417 +{
418 + unsigned int cflag;
419 + unsigned int iflag;
420 + unsigned int quot;
421 + unsigned int baud;
422 + unsigned int con = 0;
423 + unsigned long flags;
424 +
425 + cflag = new->c_cflag;
426 + iflag = new->c_iflag;
427 +
428 + switch (cflag & CSIZE) {
429 + case CS7:
430 + con = ASCCON_M_7ASYNC;
431 + break;
432 +
433 + case CS5:
434 + case CS6:
435 + default:
436 + con = ASCCON_M_8ASYNC;
437 + break;
438 + }
439 +
440 + if (cflag & CSTOPB)
441 + con |= ASCCON_STP;
442 +
443 + if (cflag & PARENB) {
444 + if (!(cflag & PARODD))
445 + con &= ~ASCCON_ODD;
446 + else
447 + con |= ASCCON_ODD;
448 + }
449 +
450 + port->read_status_mask = ASCSTATE_ROE;
451 + if (iflag & INPCK)
452 + port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
453 +
454 + port->ignore_status_mask = 0;
455 + if (iflag & IGNPAR)
456 + port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
457 +
458 + if (iflag & IGNBRK) {
459 + /*
460 + * If we're ignoring parity and break indicators,
461 + * ignore overruns too (for real raw support).
462 + */
463 + if (iflag & IGNPAR)
464 + port->ignore_status_mask |= ASCSTATE_ROE;
465 + }
466 +
467 + if ((cflag & CREAD) == 0)
468 + port->ignore_status_mask |= UART_DUMMY_UER_RX;
469 +
470 + /* set error signals - framing, parity and overrun, enable receiver */
471 + con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
472 +
473 + local_irq_save(flags);
474 +
475 + /* set up CON */
476 + lq_w32_mask(0, con, port->membase + IFXMIPS_ASC_CON);
477 +
478 + /* Set baud rate - take a divider of 2 into account */
479 + baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
480 + quot = uart_get_divisor(port, baud);
481 + quot = quot / 2 - 1;
482 +
483 + /* disable the baudrate generator */
484 + lq_w32_mask(ASCCON_R, 0, port->membase + IFXMIPS_ASC_CON);
485 +
486 + /* make sure the fractional divider is off */
487 + lq_w32_mask(ASCCON_FDE, 0, port->membase + IFXMIPS_ASC_CON);
488 +
489 + /* set up to use divisor of 2 */
490 + lq_w32_mask(ASCCON_BRS, 0, port->membase + IFXMIPS_ASC_CON);
491 +
492 + /* now we can write the new baudrate into the register */
493 + lq_w32(quot, port->membase + IFXMIPS_ASC_BG);
494 +
495 + /* turn the baudrate generator back on */
496 + lq_w32_mask(0, ASCCON_R, port->membase + IFXMIPS_ASC_CON);
497 +
498 + /* enable rx */
499 + lq_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE);
500 +
501 + local_irq_restore(flags);
502 +}
503 +
504 +static const char*
505 +lqasc_type(struct uart_port *port)
506 +{
507 + if (port->type == PORT_IFXMIPSASC)
508 + return DRVNAME;
509 + else
510 + return NULL;
511 +}
512 +
513 +static void
514 +lqasc_release_port(struct uart_port *port)
515 +{
516 + if (port->flags & UPF_IOREMAP) {
517 + iounmap(port->membase);
518 + port->membase = NULL;
519 + }
520 +}
521 +
522 +static int
523 +lqasc_request_port(struct uart_port *port)
524 +{
525 + struct platform_device *pdev = to_platform_device(port->dev);
526 + struct resource *mmres;
527 + int size;
528 +
529 + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
530 + if (!mmres)
531 + return -ENODEV;
532 + size = resource_size(mmres);
533 +
534 + if (port->flags & UPF_IOREMAP) {
535 + port->membase = ioremap_nocache(port->mapbase, size);
536 + if (port->membase == NULL)
537 + return -ENOMEM;
538 + }
539 + return 0;
540 +}
541 +
542 +static void
543 +lqasc_config_port(struct uart_port *port, int flags)
544 +{
545 + if (flags & UART_CONFIG_TYPE) {
546 + port->type = PORT_IFXMIPSASC;
547 + lqasc_request_port(port);
548 + }
549 +}
550 +
551 +static int
552 +lqasc_verify_port(struct uart_port *port,
553 + struct serial_struct *ser)
554 +{
555 + int ret = 0;
556 + if (ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
557 + ret = -EINVAL;
558 + if (ser->irq < 0 || ser->irq >= NR_IRQS)
559 + ret = -EINVAL;
560 + if (ser->baud_base < 9600)
561 + ret = -EINVAL;
562 + return ret;
563 +}
564 +
565 +static struct uart_ops lqasc_pops = {
566 + .tx_empty = lqasc_tx_empty,
567 + .set_mctrl = lqasc_set_mctrl,
568 + .get_mctrl = lqasc_get_mctrl,
569 + .stop_tx = lqasc_stop_tx,
570 + .start_tx = lqasc_start_tx,
571 + .stop_rx = lqasc_stop_rx,
572 + .enable_ms = lqasc_enable_ms,
573 + .break_ctl = lqasc_break_ctl,
574 + .startup = lqasc_startup,
575 + .shutdown = lqasc_shutdown,
576 + .set_termios = lqasc_set_termios,
577 + .type = lqasc_type,
578 + .release_port = lqasc_release_port,
579 + .request_port = lqasc_request_port,
580 + .config_port = lqasc_config_port,
581 + .verify_port = lqasc_verify_port,
582 +};
583 +
584 +static void
585 +lqasc_console_putchar(struct uart_port *port, int ch)
586 +{
587 + int fifofree;
588 +
589 + if (!port->membase)
590 + return;
591 +
592 + do {
593 + fifofree = (lq_r32(port->membase + IFXMIPS_ASC_FSTAT)
594 + & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
595 + } while (fifofree == 0);
596 + lq_w8(ch, port->membase + IFXMIPS_ASC_TBUF);
597 +}
598 +
599 +
600 +static void
601 +lqasc_console_write(struct console *co, const char *s, u_int count)
602 +{
603 + struct lq_uart_port *ifx_port;
604 + struct uart_port *port;
605 + unsigned long flags;
606 +
607 + if (co->index >= MAXPORTS)
608 + return;
609 +
610 + ifx_port = lqasc_port[co->index];
611 + if (!ifx_port)
612 + return;
613 +
614 + port = &ifx_port->port;
615 +
616 + local_irq_save(flags);
617 + uart_console_write(port, s, count, lqasc_console_putchar);
618 + local_irq_restore(flags);
619 +}
620 +
621 +static int __init
622 +lqasc_console_setup(struct console *co, char *options)
623 +{
624 + struct lq_uart_port *ifx_port;
625 + struct uart_port *port;
626 + int baud = 115200;
627 + int bits = 8;
628 + int parity = 'n';
629 + int flow = 'n';
630 +
631 + if (co->index >= MAXPORTS)
632 + return -ENODEV;
633 +
634 + ifx_port = lqasc_port[co->index];
635 + if (!ifx_port)
636 + return -ENODEV;
637 +
638 + port = &ifx_port->port;
639 +
640 + port->uartclk = clk_get_rate(ifx_port->clk);
641 +
642 + if (options)
643 + uart_parse_options(options, &baud, &parity, &bits, &flow);
644 + return uart_set_options(port, co, baud, parity, bits, flow);
645 +}
646 +
647 +static struct console lqasc_console = {
648 + .name = "ttyS",
649 + .write = lqasc_console_write,
650 + .device = uart_console_device,
651 + .setup = lqasc_console_setup,
652 + .flags = CON_PRINTBUFFER,
653 + .index = -1,
654 + .data = &lqasc_reg,
655 +};
656 +
657 +static int __init
658 +lqasc_console_init(void)
659 +{
660 + register_console(&lqasc_console);
661 + return 0;
662 +}
663 +console_initcall(lqasc_console_init);
664 +
665 +static struct uart_driver lqasc_reg = {
666 + .owner = THIS_MODULE,
667 + .driver_name = DRVNAME,
668 + .dev_name = "ttyS",
669 + .major = TTY_MAJOR,
670 + .minor = 64,
671 + .nr = MAXPORTS,
672 + .cons = &lqasc_console,
673 +};
674 +
675 +static int __devinit
676 +lqasc_probe(struct platform_device *pdev)
677 +{
678 + struct lq_uart_port *ifx_port;
679 + struct uart_port *port;
680 + struct resource *mmres, *irqres;
681 + int tx_irq, rx_irq, err_irq;
682 + struct clk *clk;
683 + int ret;
684 +
685 + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
686 + irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
687 + if (!mmres || !irqres)
688 + return -ENODEV;
689 +
690 + if (pdev->id >= MAXPORTS)
691 + return -EBUSY;
692 +
693 + if (lqasc_port[pdev->id] != NULL)
694 + return -EBUSY;
695 +
696 + clk = clk_get(&pdev->dev, "fpi");
697 + if (IS_ERR(clk)) {
698 + pr_err("failed to get fpi clk\n");
699 + return -ENOENT;
700 + }
701 +
702 + tx_irq = platform_get_irq_byname(pdev, "tx");
703 + if (tx_irq < 0) {
704 + /* without named resources: assume standard irq scheme */
705 + tx_irq = irqres->start;
706 + rx_irq = irqres->start+2;
707 + err_irq = irqres->start+3;
708 + } else {
709 + /* other irqs must be named also! */
710 + rx_irq = platform_get_irq_byname(pdev, "rx");
711 + err_irq = platform_get_irq_byname(pdev, "err");
712 + if ((rx_irq < 0) | (err_irq < 0))
713 + return -ENODEV;
714 + }
715 +
716 + ifx_port = kzalloc(sizeof(struct lq_uart_port), GFP_KERNEL);
717 + if (!ifx_port)
718 + return -ENOMEM;
719 +
720 + port = &ifx_port->port;
721 +
722 + port->iotype = SERIAL_IO_MEM;
723 + port->flags = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP;
724 + port->ops = &lqasc_pops;
725 + port->fifosize = 16;
726 + port->type = PORT_IFXMIPSASC,
727 + port->line = pdev->id;
728 + port->dev = &pdev->dev;
729 +
730 + port->irq = tx_irq; /* unused, just to be backward-compatibe */
731 + port->mapbase = mmres->start;
732 +
733 + ifx_port->clk = clk;
734 +
735 + ifx_port->tx_irq = tx_irq;
736 + ifx_port->rx_irq = rx_irq;
737 + ifx_port->err_irq = err_irq;
738 +
739 + lqasc_port[pdev->id] = ifx_port;
740 + platform_set_drvdata(pdev, ifx_port);
741 +
742 + ret = uart_add_one_port(&lqasc_reg, port);
743 +
744 + return ret;
745 +}
746 +
747 +static int __devexit
748 +lqasc_remove(struct platform_device *pdev)
749 +{
750 + struct lq_uart_port *ifx_port = platform_get_drvdata(pdev);
751 + int ret;
752 +
753 + clk_put(ifx_port->clk);
754 + platform_set_drvdata(pdev, NULL);
755 + lqasc_port[pdev->id] = NULL;
756 + ret = uart_remove_one_port(&lqasc_reg, &ifx_port->port);
757 + kfree(ifx_port);
758 +
759 + return 0;
760 +}
761 +
762 +static struct platform_driver lqasc_driver = {
763 + .probe = lqasc_probe,
764 + .remove = __devexit_p(lqasc_remove),
765 +
766 + .driver = {
767 + .name = DRVNAME,
768 + .owner = THIS_MODULE,
769 + },
770 +};
771 +
772 +int __init
773 +init_lqasc(void)
774 +{
775 + int ret;
776 +
777 + ret = uart_register_driver(&lqasc_reg);
778 + if (ret != 0)
779 + return ret;
780 +
781 + ret = platform_driver_register(&lqasc_driver);
782 + if (ret != 0)
783 + uart_unregister_driver(&lqasc_reg);
784 +
785 + return ret;
786 +}
787 +
788 +void __exit
789 +exit_lqasc(void)
790 +{
791 + platform_driver_unregister(&lqasc_driver);
792 + uart_unregister_driver(&lqasc_reg);
793 +}
794 +
795 +module_init(init_lqasc);
796 +module_exit(exit_lqasc);
797 +
798 +MODULE_DESCRIPTION("Lantiq serial port driver");
799 +MODULE_LICENSE("GPL");
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