target/linux/lantiq/patches/910-falcon-i2c.patch

   1 --- a/drivers/i2c/busses/Makefile
   2 +++ b/drivers/i2c/busses/Makefile
   3 @@ -76,5 +76,6 @@
   4  obj-$(CONFIG_I2C_STUB)         += i2c-stub.o
   5  obj-$(CONFIG_SCx200_ACB)       += scx200_acb.o
   6  obj-$(CONFIG_SCx200_I2C)       += scx200_i2c.o
   7 +obj-$(CONFIG_I2C_FALCON)       += i2c-falcon.o
   8
   9  ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
  10 --- a/drivers/i2c/busses/Kconfig
  11 +++ b/drivers/i2c/busses/Kconfig
  12 @@ -281,6 +281,10 @@
  13
  14  comment "I2C system bus drivers (mostly embedded / system-on-chip)"
  15
  16 +config I2C_FALCON
  17 +       tristate "Falcon I2C interface"
  18 +#      depends on SOC_FALCON
  19 +
  20  config I2C_AT91
  21         tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
  22         depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
  23 --- /dev/null
  24 +++ b/drivers/i2c/busses/i2c-falcon.c
  25 @@ -0,0 +1,802 @@
  26 +/*
  27 + *   This program is free software; you can redistribute it and/or modify
  28 + *   it under the terms of the GNU General Public License as published by
  29 + *   the Free Software Foundation; either version 2 of the License, or
  30 + *   (at your option) any later version.
  31 + *
  32 + *   This program is distributed in the hope that it will be useful,
  33 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  34 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  35 + *   GNU General Public License for more details.
  36 + *
  37 + *   You should have received a copy of the GNU General Public License
  38 + *   along with this program; if not, write to the Free Software
  39 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  40 + */
  41 +
  42 +/* #define DEBUG */
  43 +
  44 +#include <linux/module.h>
  45 +#include <linux/ioport.h>
  46 +#include <linux/init.h>
  47 +#include <linux/platform_device.h>
  48 +#include <linux/i2c.h>
  49 +#include <linux/interrupt.h>
  50 +#include <linux/spinlock.h>
  51 +#include <linux/io.h>
  52 +#include <linux/clk.h>
  53 +#include <linux/err.h>
  54 +
  55 +/* CURRENT ISSUES:
  56 + * - no high speed support
  57 + * - rx issue with "address mode" & "tx end" interrupts
  58 + * - ten bit mode is not tested
  59 + */
  60 +
  61 +/* mapping for access macros */
  62 +#define reg_r32(reg)           __raw_readl(reg)
  63 +#define reg_w32(val, reg)      __raw_writel(val, reg)
  64 +#define reg_w32_mask(clear, set, reg)  \
  65 +                               reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
  66 +#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)&reg)[idx])
  67 +#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)&reg)[idx])
  68 +#define i2c    (priv->membase)
  69 +#include <falcon/i2c_reg.h>
  70 +
  71 +/* enable hacks to overcome current issue */
  72 +#define FALCON_FIX_ME
  73 +
  74 +#define FALCON_I2C_ADDR                        0x00
  75 +#define FALCON_I2C_READY_TIMEOUT       1000
  76 +#define FALCON_I2C_WAIT_TIMEOUT                10
  77 +
  78 +#define DRV_NAME "i2c-falcon"
  79 +
  80 +#if defined(DEBUG)
  81 +#define static /* no static functions for better debugging */
  82 +#endif
  83 +
  84 +#define FALCON_I2C_ARB_LOST    (1 << 0)
  85 +#define FALCON_I2C_NACK                (1 << 1)
  86 +#define FALCON_I2C_RX_UFL      (1 << 2)
  87 +#define FALCON_I2C_RX_OFL      (1 << 3)
  88 +#define FALCON_I2C_TX_UFL      (1 << 4)
  89 +#define FALCON_I2C_TX_OFL      (1 << 5)
  90 +#define FALCON_I2C_BURST_REQ   (1 << 6)
  91 +#define FALCON_I2C_RX          (1 << 7)
  92 +#define FALCON_I2C_TX_END      (1 << 8)
  93 +#define FALCON_I2C_ADDR_MATCH  (1 << 9) /* doesn't trigger */
  94 +
  95 +struct falcon_i2c {
  96 +       spinlock_t lock;
  97 +
  98 +       enum {
  99 +               FALCON_I2C_MODE_100     = 1,
 100 +               FALCON_I2C_MODE_400     = 2,
 101 +               FALCON_I2C_MODE_3400    = 3
 102 +       } mode;                         /* current speed mode */
 103 +
 104 +       int ten_bit;                    /* current address mode */
 105 +       unsigned long status;           /* bus events holder */
 106 +       struct clk *clk;                /* clock input for i2c hardware block */
 107 +       struct gpon_reg_i2c __iomem *membase;   /* base of mapped registers */
 108 +       int irq_lb, irq_b, irq_err, irq_p;      /* last burst, burst, error,
 109 +                                                  protocol IRQs */
 110 +       struct completion done;
 111 +       struct i2c_adapter adap;
 112 +       struct device *dev;
 113 +};
 114 +
 115 +#define FALCON_I2C_ERROR_MASK          (FALCON_I2C_NACK \
 116 +                                       | FALCON_I2C_ARB_LOST \
 117 +                                       | FALCON_I2C_RX_OFL \
 118 +                                       | FALCON_I2C_RX_UFL \
 119 +                                       | FALCON_I2C_TX_OFL \
 120 +                                       | FALCON_I2C_TX_UFL)
 121 +
 122 +#define FALCON_I2C_ERROR(priv)         (priv->status & FALCON_I2C_ERROR_MASK)
 123 +#define FALCON_I2C_ERROR_CLEAR(priv)   do { \
 124 +                                               priv->status &= \
 125 +                                               ~FALCON_I2C_ERROR_MASK; \
 126 +                                       } while (0)
 127 +
 128 +static void falcon_addr_configure(struct falcon_i2c *priv, int ten_bit)
 129 +{
 130 +       u32 ten_bit_mask = ten_bit ? I2C_ADDR_CFG_TBAM_10bit : 0;
 131 +
 132 +       /* configure address */
 133 +       i2c_w32(I2C_ADDR_CFG_SOPE_EN /* generate stop when no more data in the
 134 +                                       fifo */
 135 +               | I2C_ADDR_CFG_SONA_EN /* generate stop when NA received */
 136 +               | I2C_ADDR_CFG_MnS_EN /* we are master device */
 137 +               | ten_bit_mask
 138 +               | FALCON_I2C_ADDR, /* our address */
 139 +               addr_cfg);
 140 +}
 141 +
 142 +static irqreturn_t falcon_i2c_isr(int irq, void *dev_id)
 143 +{
 144 +       u32 i_raw, i_pro, i_err;
 145 +       struct falcon_i2c *priv = dev_id;
 146 +       unsigned long flags;
 147 +       unsigned int old_status;
 148 +
 149 +       spin_lock_irqsave(&priv->lock, flags);
 150 +
 151 +       old_status = (unsigned int)priv->status;
 152 +
 153 +       i_raw = i2c_r32(mis);
 154 +
 155 +       /* protocol interrupt */
 156 +       if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) {
 157 +               i_pro = i2c_r32(p_irqss);
 158 +
 159 +               /* tx -> rx switch */
 160 +               if (i_pro & I2C_P_IRQSS_RX)
 161 +                       priv->status |= FALCON_I2C_RX;
 162 +
 163 +               /* tx end */
 164 +               if (i_pro & I2C_P_IRQSS_TX_END)
 165 +                       priv->status |= FALCON_I2C_TX_END;
 166 +
 167 +               /* not acknowledge */
 168 +               if (i_pro & I2C_P_IRQSS_NACK)
 169 +                       priv->status |= FALCON_I2C_NACK;
 170 +
 171 +               /* arbitration lost */
 172 +               if (i_pro & I2C_P_IRQSS_AL)
 173 +                       priv->status |= FALCON_I2C_ARB_LOST;
 174 +
 175 +               /* address match */
 176 +               if (i_pro & I2C_P_IRQSS_AM)
 177 +                       priv->status |= FALCON_I2C_ADDR_MATCH;
 178 +
 179 +               i2c_w32(i_pro, p_irqsc);
 180 +       }
 181 +
 182 +       /* error interrupt */
 183 +       if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
 184 +               i_err = i2c_r32(err_irqss);
 185 +
 186 +               /* tx fifo overflow */
 187 +               if (i_err & I2C_ERR_IRQSS_TXF_OFL)
 188 +                       priv->status |= FALCON_I2C_TX_OFL;
 189 +
 190 +               /* tx fifo underflow */
 191 +               if (i_err & I2C_ERR_IRQSS_TXF_UFL)
 192 +                       priv->status |= FALCON_I2C_TX_UFL;
 193 +
 194 +               /* rx fifo overflow */
 195 +               if (i_err & I2C_ERR_IRQSS_RXF_OFL)
 196 +                       priv->status |= FALCON_I2C_RX_OFL;
 197 +
 198 +               /* rx fifo underflow */
 199 +               if (i_err & I2C_ERR_IRQSS_RXF_UFL)
 200 +                       priv->status |= FALCON_I2C_RX_UFL;
 201 +
 202 +               i2c_w32(i_err, err_irqsc);
 203 +       }
 204 +
 205 +       /* burst request */
 206 +       if (i_raw & I2C_RIS_BREQ_INT_INTOCC) {
 207 +               i2c_w32_mask(I2C_IMSC_BREQ_INT_EN, 0, imsc);
 208 +               i2c_w32_mask(0, I2C_ICR_BREQ_INT_CLR, icr);
 209 +
 210 +               priv->status |= FALCON_I2C_BURST_REQ;
 211 +       }
 212 +
 213 +       /* last burst request */
 214 +       if (i_raw & I2C_RIS_LBREQ_INT_INTOCC) {
 215 +               i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN, 0, imsc);
 216 +               i2c_w32_mask(0, I2C_ICR_LBREQ_INT_CLR, icr);
 217 +
 218 +               priv->status |= FALCON_I2C_BURST_REQ;
 219 +       }
 220 +
 221 +       if (old_status != (unsigned int)priv->status)
 222 +               complete(&priv->done);
 223 +
 224 +       spin_unlock_irqrestore(&priv->lock, flags);
 225 +
 226 +       return IRQ_HANDLED;
 227 +}
 228 +
 229 +static int falcon_i2c_ready(struct falcon_i2c *priv)
 230 +{
 231 +       int timeout;
 232 +       u32 bus_stat;
 233 +       unsigned long flags;
 234 +       int ret;
 235 +
 236 +       for (timeout = 0; timeout < FALCON_I2C_READY_TIMEOUT; timeout++) {
 237 +               bus_stat = i2c_r32(bus_stat);
 238 +
 239 +               if (bus_stat & I2C_BUS_STAT_BS_SC) {
 240 +                       cpu_relax();
 241 +               } else {
 242 +                       spin_lock_irqsave(&priv->lock, flags);
 243 +
 244 +                       if (FALCON_I2C_ERROR(priv)) {
 245 +                               ret = priv->status;
 246 +
 247 +                               dev_dbg(priv->dev, "bus ready wait error 0x%08lx\n", priv->status);
 248 +
 249 +                               FALCON_I2C_ERROR_CLEAR(priv);
 250 +                       } else {
 251 +                               ret = 0;
 252 +                       }
 253 +
 254 +                       spin_unlock_irqrestore(&priv->lock, flags);
 255 +
 256 +                       return ret;
 257 +               }
 258 +       }
 259 +
 260 +       dev_dbg(priv->dev, "bus ready wait timeout\n");
 261 +
 262 +       return -ETIME;
 263 +}
 264 +
 265 +static int falcon_i2c_wait(struct falcon_i2c *priv, unsigned long status)
 266 +{
 267 +       int ret = 0;
 268 +       unsigned long flags;
 269 +       unsigned int timeout;
 270 +
 271 +       spin_lock_irqsave(&priv->lock, flags);
 272 +
 273 +       priv->status &= FALCON_I2C_BURST_REQ;
 274 +
 275 +       /* check if the event already occurred */
 276 +       if ((priv->status & status) == status) {
 277 +               priv->status &= ~status;
 278 +               spin_unlock_irqrestore(&priv->lock, flags);
 279 +
 280 +               return 0;
 281 +       }
 282 +
 283 +       spin_unlock_irqrestore(&priv->lock, flags);
 284 +
 285 +       /* unmask burst interrupts */
 286 +       i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
 287 +
 288 +       for (timeout = 0; timeout < FALCON_I2C_WAIT_TIMEOUT; timeout++) {
 289 +               /* wait for the data request */
 290 +               wait_for_completion_timeout(&priv->done, HZ / 10);
 291 +
 292 +               /* handle errors */
 293 +               spin_lock_irqsave(&priv->lock, flags);
 294 +
 295 +               if (FALCON_I2C_ERROR(priv)) {
 296 +                       dev_dbg(priv->dev, "wait error 0x%08lx (waiting for 0x%08lx)\n",
 297 +                           priv->status,
 298 +                           status);
 299 +
 300 +                       if (priv->status & FALCON_I2C_NACK)
 301 +                               ret = -ENXIO;
 302 +                       else
 303 +                               ret = -EREMOTEIO;
 304 +
 305 +                       FALCON_I2C_ERROR_CLEAR(priv);
 306 +               } else {
 307 +                       if ((priv->status & status) == status) {
 308 +                               priv->status &= ~status;
 309 +                               spin_unlock_irqrestore(&priv->lock, flags);
 310 +
 311 +                               return 0;
 312 +                       }
 313 +               }
 314 +
 315 +               spin_unlock_irqrestore(&priv->lock, flags);
 316 +
 317 +               if (ret)
 318 +                       return ret;
 319 +       }
 320 +
 321 +       dev_dbg(priv->dev, "wait timeout error 0x%08lx (waiting for 0x%08lx)\n",
 322 +           priv->status,
 323 +           status);
 324 +
 325 +       return -ETIME;
 326 +}
 327 +
 328 +static int falcon_i2c_tx(struct falcon_i2c *priv, int ten_bit, u16 addr,
 329 +                        u8 *buf, int len)
 330 +{
 331 +       int i;
 332 +       int ret;
 333 +
 334 +       dev_dbg(priv->dev, "%s\n", __func__);
 335 +
 336 +       /* tell fifo the number of bytes we are going to send */
 337 +       i2c_w32(len + (ten_bit ? 2 : 1), tps_ctrl);
 338 +
 339 +       /* wait for the data request */
 340 +       ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
 341 +       if (ret)
 342 +               return ret;
 343 +
 344 +       /* send slave address */
 345 +       if (ten_bit) {
 346 +               i2c_w32(0x78 | ((addr >> 7) & 0x7), txd);
 347 +               i2c_w32(0x78 | ((addr & 0x7f) << 1) | 0, txd);
 348 +       } else {
 349 +               i2c_w32((addr << 1) | 0, txd);
 350 +       }
 351 +
 352 +       /* fill fifo */
 353 +       for (i = 0; i < len; i++) {
 354 +               ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
 355 +               if (ret)
 356 +                       return ret;
 357 +
 358 +               i2c_w32(buf[i], txd);
 359 +       }
 360 +
 361 +       return falcon_i2c_wait(priv, FALCON_I2C_TX_END);
 362 +}
 363 +
 364 +static int falcon_i2c_rx(struct falcon_i2c *priv, int ten_bit, u16 addr,
 365 +                        u8 *buf, int len)
 366 +{
 367 +       int i;
 368 +       int ret;
 369 +
 370 +       dev_dbg(priv->dev, "%s\n", __func__);
 371 +
 372 +       /* we need to transmit address only */
 373 +       i2c_w32(ten_bit ? 2 : 1, tps_ctrl);
 374 +
 375 +       /* set maximum received packet size */
 376 +       i2c_w32(len, mrps_ctrl);
 377 +
 378 +       /* wait for the data request */
 379 +       ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
 380 +       if (ret)
 381 +               return ret;
 382 +
 383 +       /* write down the address */
 384 +       if (ten_bit) {
 385 +               i2c_w32(0x78 | ((addr >> 7) & 0x7), txd);
 386 +               i2c_w32(0x78 | ((addr & 0x7f) << 1) | 1, txd);
 387 +       } else {
 388 +               i2c_w32((addr << 1) | 1, txd);
 389 +       }
 390 +
 391 +       /* wait for the read request */
 392 +       ret = falcon_i2c_wait(priv, FALCON_I2C_TX_END
 393 +#ifndef FALCON_FIX_ME
 394 +                             | FALCON_I2C_ADDR_MATCH
 395 +#endif
 396 +                             | FALCON_I2C_RX);
 397 +
 398 +       if (ret)
 399 +               return ret;
 400 +
 401 +       /* read bytes */
 402 +       for (i = 0; i < len; i++) {
 403 +#ifdef FALCON_FIX_ME
 404 +               while (i2c_r32(rps_stat) == 0)
 405 +                       cpu_relax();
 406 +#else
 407 +               ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
 408 +
 409 +               if (ret)
 410 +                       return ret;
 411 +#endif
 412 +
 413 +               buf[i] = i2c_r32(rxd);
 414 +       }
 415 +
 416 +#ifndef FALCON_FIX_ME
 417 +       /* wait for transmission end */
 418 +       return falcon_i2c_wait(priv, FALCON_I2C_TX_END);
 419 +#else
 420 +       return 0;
 421 +#endif
 422 +}
 423 +
 424 +static int falcon_i2c_xfer_msg(struct falcon_i2c *priv, struct i2c_msg *msg)
 425 +{
 426 +       int ret;
 427 +       int ten_bit;
 428 +       unsigned long flags;
 429 +
 430 +       dev_dbg(priv->dev, "%s %u byte(s) %s 0x%02x\n",
 431 +               (msg->flags & I2C_M_RD) ? "read" : "write", msg->len,
 432 +               (msg->flags & I2C_M_RD) ? "from" : "to", msg->addr);
 433 +
 434 +       if (msg->flags & I2C_M_TEN)
 435 +               ten_bit = 1;
 436 +       else
 437 +               ten_bit = 0;
 438 +
 439 +       /* reconfigure bus if need to send message in different address mode */
 440 +       spin_lock_irqsave(&priv->lock, flags);
 441 +       if (ten_bit != priv->ten_bit) {
 442 +
 443 +               /* disable bus */
 444 +               i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 445 +
 446 +               /* reconfigure address */
 447 +               falcon_addr_configure(priv, ten_bit);
 448 +
 449 +               /* enable bus */
 450 +               i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
 451 +
 452 +               priv->ten_bit = ten_bit;
 453 +       }
 454 +       spin_unlock_irqrestore(&priv->lock, flags);
 455 +
 456 +       /* read/write actual message */
 457 +       if (msg->flags & I2C_M_RD)
 458 +               ret = falcon_i2c_rx(priv, ten_bit, msg->addr, msg->buf,
 459 +                                   msg->len);
 460 +       else
 461 +               ret = falcon_i2c_tx(priv, ten_bit, msg->addr, msg->buf,
 462 +                                   msg->len);
 463 +
 464 +       if (ret)
 465 +               return ret;
 466 +
 467 +       return 0;
 468 +}
 469 +
 470 +static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
 471 +                          int num)
 472 +{
 473 +       int i;
 474 +       int ret;
 475 +       unsigned long flags;
 476 +       struct falcon_i2c *priv = i2c_get_adapdata(adap);
 477 +
 478 +       dev_dbg(priv->dev, "xfer %u messages\n", num);
 479 +
 480 +       /* transfer each message */
 481 +       for (i = 0; i < num; i++) {
 482 +#ifdef FALCON_FIX_ME
 483 +               /* disable bus */
 484 +               i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 485 +               /* enable bus */
 486 +               i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
 487 +#endif
 488 +
 489 +               /* clear bus status */
 490 +               spin_lock_irqsave(&priv->lock, flags);
 491 +               priv->status = 0;
 492 +               spin_unlock_irqrestore(&priv->lock, flags);
 493 +
 494 +               /* wait for the bus to become ready */
 495 +               ret = falcon_i2c_ready(priv);
 496 +               if (ret)
 497 +                       return ret;
 498 +
 499 +               /* transfer message */
 500 +               ret = falcon_i2c_xfer_msg(priv, &msg[i]);
 501 +
 502 +               if (ret)
 503 +                       return ret;
 504 +
 505 +               /* check for unhandled errors */
 506 +               spin_lock_irqsave(&priv->lock, flags);
 507 +               if (FALCON_I2C_ERROR(priv))
 508 +                       ret = priv->status;
 509 +               spin_unlock_irqrestore(&priv->lock, flags);
 510 +
 511 +               if (ret) {
 512 +                       dev_warn(priv->dev, "message %u unhandled error 0x%x\n",
 513 +                               i, ret);
 514 +
 515 +                       return ret;
 516 +               }
 517 +       }
 518 +
 519 +       return 0;
 520 +}
 521 +
 522 +static u32 falcon_i2c_func(struct i2c_adapter *adap)
 523 +{
 524 +       return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
 525 +}
 526 +
 527 +static struct i2c_algorithm falcon_i2c_algorithm = {
 528 +       .master_xfer    = falcon_i2c_xfer,
 529 +       .functionality  = falcon_i2c_func,
 530 +};
 531 +
 532 +static int falcon_i2c_hw_init(struct i2c_adapter *adap)
 533 +{
 534 +       struct falcon_i2c *priv = i2c_get_adapdata(adap);
 535 +
 536 +       /* disable bus */
 537 +       i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 538 +
 539 +       /* set normal operation clock divider */
 540 +       i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
 541 +
 542 +       /* set frequency */
 543 +       if (priv->mode == FALCON_I2C_MODE_100) {
 544 +               dev_dbg(priv->dev, "set standard mode (100 kHz)\n");
 545 +
 546 +               i2c_w32(0, fdiv_high_cfg);
 547 +
 548 +               i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET)
 549 +                       | (499 << I2C_FDIV_CFG_DEC_OFFSET),
 550 +                       fdiv_cfg);
 551 +       } else if (priv->mode == FALCON_I2C_MODE_400) {
 552 +               dev_dbg(priv->dev, "set fast mode (400 kHz)\n");
 553 +
 554 +               i2c_w32(0, fdiv_high_cfg);
 555 +
 556 +               i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET)
 557 +                       | (124 << I2C_FDIV_CFG_DEC_OFFSET),
 558 +                       fdiv_cfg);
 559 +       } else if (priv->mode == FALCON_I2C_MODE_3400) {
 560 +               dev_dbg(priv->dev, "set high mode (3.4 MHz)\n");
 561 +
 562 +               i2c_w32(0, fdiv_cfg);
 563 +
 564 +               /* TODO recalculate value for 100MHz input */
 565 +               i2c_w32((41 << I2C_FDIV_CFG_INC_OFFSET)
 566 +                       | (152 << I2C_FDIV_CFG_DEC_OFFSET),
 567 +                       fdiv_high_cfg);
 568 +       } else {
 569 +               dev_warn(priv->dev, "unknown mode\n");
 570 +
 571 +               return -ENODEV;
 572 +       }
 573 +
 574 +       /* configure fifo */
 575 +       i2c_w32(I2C_FIFO_CFG_TXFC /* tx fifo as flow controller */
 576 +               | I2C_FIFO_CFG_RXFC /* rx fifo as flow controller */
 577 +               | I2C_FIFO_CFG_TXFA_TXFA2 /* tx fifo 4-byte aligned */
 578 +               | I2C_FIFO_CFG_RXFA_RXFA2 /* rx fifo 4-byte aligned */
 579 +               | I2C_FIFO_CFG_TXBS_TXBS0 /* tx fifo burst size is 1 word */
 580 +               | I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */
 581 +               fifo_cfg);
 582 +
 583 +       /* configure address */
 584 +       falcon_addr_configure(priv, priv->ten_bit);
 585 +
 586 +       /* enable bus */
 587 +       i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
 588 +
 589 +       /* mask burst interrupts */
 590 +       i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
 591 +
 592 +       /* enable interrupts */
 593 +       i2c_w32(I2C_IMSC_LBREQ_INT_EN
 594 +               | I2C_IMSC_BREQ_INT_EN
 595 +               | I2C_IMSC_I2C_P_INT_EN
 596 +               | I2C_IMSC_I2C_ERR_INT_EN,
 597 +               imsc);
 598 +
 599 +       return 0;
 600 +}
 601 +
 602 +static int __devinit falcon_i2c_probe(struct platform_device *pdev)
 603 +{
 604 +       int ret = 0;
 605 +       struct falcon_i2c *priv;
 606 +       struct i2c_adapter *adap;
 607 +       struct resource *mmres, *ioarea,
 608 +                       *irqres_lb, *irqres_b, *irqres_err, *irqres_p;
 609 +       struct clk *clk;
 610 +
 611 +       dev_dbg(&pdev->dev, "probing\n");
 612 +
 613 +       mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 614 +       irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 615 +                                                "i2c_lb");
 616 +       irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b");
 617 +       irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 618 +                                                 "i2c_err");
 619 +       irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p");
 620 +
 621 +       if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) {
 622 +               dev_err(&pdev->dev, "no resources\n");
 623 +               return -ENODEV;
 624 +       }
 625 +
 626 +       clk = clk_get(&pdev->dev, "fpi");
 627 +       if (IS_ERR(clk)) {
 628 +               dev_err(&pdev->dev, "failed to get fpi clk\n");
 629 +               return -ENOENT;
 630 +       }
 631 +
 632 +       if (clk_get_rate(clk) != 100000000) {
 633 +               dev_err(&pdev->dev, "input clock is not 100MHz\n");
 634 +               return -ENOENT;
 635 +       }
 636 +
 637 +       /* allocate private data */
 638 +       priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 639 +       if (!priv) {
 640 +               dev_err(&pdev->dev, "can't allocate private data\n");
 641 +               return -ENOMEM;
 642 +       }
 643 +
 644 +       adap = &priv->adap;
 645 +       i2c_set_adapdata(adap, priv);
 646 +       adap->owner = THIS_MODULE;
 647 +       adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 648 +       strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
 649 +       adap->algo = &falcon_i2c_algorithm;
 650 +
 651 +       priv->ten_bit = 0;
 652 +       priv->mode = FALCON_I2C_MODE_100;
 653 +       priv->clk = clk;
 654 +       priv->dev = &pdev->dev;
 655 +
 656 +       spin_lock_init(&priv->lock);
 657 +
 658 +       ioarea = request_mem_region(mmres->start, resource_size(mmres),
 659 +                                        pdev->name);
 660 +
 661 +       if (ioarea == NULL) {
 662 +               dev_err(&pdev->dev, "I2C region already claimed\n");
 663 +               ret = -ENXIO;
 664 +               goto err_free_priv;
 665 +       }
 666 +
 667 +       /* map memory */
 668 +       priv->membase = ioremap_nocache(mmres->start & ~KSEG1,
 669 +               resource_size(mmres));
 670 +       if (priv->membase == NULL) {
 671 +               ret = -ENOMEM;
 672 +               goto err_release_region;
 673 +       }
 674 +
 675 +       priv->irq_lb = irqres_lb->start;
 676 +       ret = request_irq(priv->irq_lb, falcon_i2c_isr, IRQF_DISABLED,
 677 +                         irqres_lb->name, priv);
 678 +       if (ret) {
 679 +               dev_err(&pdev->dev, "can't get last burst IRQ %d\n", irqres_lb->start);
 680 +               ret = -ENODEV;
 681 +               goto err_unmap_mem;
 682 +       }
 683 +
 684 +       priv->irq_b = irqres_b->start;
 685 +       ret = request_irq(priv->irq_b, falcon_i2c_isr, IRQF_DISABLED,
 686 +                         irqres_b->name, priv);
 687 +       if (ret) {
 688 +               dev_err(&pdev->dev, "can't get burst IRQ %d\n", irqres_b->start);
 689 +               ret = -ENODEV;
 690 +               goto err_free_lb_irq;
 691 +       }
 692 +
 693 +       priv->irq_err = irqres_err->start;
 694 +       ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED,
 695 +                         irqres_err->name, priv);
 696 +       if (ret) {
 697 +               dev_err(&pdev->dev, "can't get error IRQ %d\n", irqres_err->start);
 698 +               ret = -ENODEV;
 699 +               goto err_free_b_irq;
 700 +       }
 701 +
 702 +       priv->irq_p = irqres_p->start;
 703 +       ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED,
 704 +                         irqres_p->name, priv);
 705 +       if (ret) {
 706 +               dev_err(&pdev->dev, "can't get protocol IRQ %d\n", irqres_p->start);
 707 +               ret = -ENODEV;
 708 +               goto err_free_err_irq;
 709 +       }
 710 +
 711 +       dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
 712 +       dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start,
 713 +           irqres_b->start, irqres_err->start, irqres_p->start);
 714 +
 715 +       /* add our adapter to the i2c stack */
 716 +       ret = i2c_add_numbered_adapter(adap);
 717 +       if (ret) {
 718 +               dev_err(&pdev->dev, "can't register I2C adapter\n");
 719 +               goto err_free_p_irq;
 720 +       }
 721 +
 722 +       platform_set_drvdata(pdev, priv);
 723 +       i2c_set_adapdata(adap, priv);
 724 +
 725 +       /* print module version information */
 726 +       dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
 727 +               (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
 728 +               (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
 729 +
 730 +       init_completion(&priv->done);
 731 +
 732 +       /* initialize HW */
 733 +       ret = falcon_i2c_hw_init(adap);
 734 +       if (ret) {
 735 +               dev_err(&pdev->dev, "can't configure adapter\n");
 736 +               goto err_remove_adapter;
 737 +       }
 738 +
 739 +       return 0;
 740 +
 741 +err_remove_adapter:
 742 +       i2c_del_adapter(adap);
 743 +       platform_set_drvdata(pdev, NULL);
 744 +
 745 +err_free_p_irq:
 746 +       free_irq(priv->irq_p, priv);
 747 +
 748 +err_free_err_irq:
 749 +       free_irq(priv->irq_err, priv);
 750 +
 751 +err_free_b_irq:
 752 +       free_irq(priv->irq_b, priv);
 753 +
 754 +err_free_lb_irq:
 755 +       free_irq(priv->irq_lb, priv);
 756 +
 757 +err_unmap_mem:
 758 +       iounmap(priv->membase);
 759 +
 760 +err_release_region:
 761 +       release_mem_region(mmres->start, resource_size(mmres));
 762 +
 763 +err_free_priv:
 764 +       kfree(priv);
 765 +
 766 +       return ret;
 767 +}
 768 +
 769 +static int __devexit falcon_i2c_remove(struct platform_device *pdev)
 770 +{
 771 +       struct falcon_i2c *priv = platform_get_drvdata(pdev);
 772 +       struct resource *mmres;
 773 +
 774 +       /* disable bus */
 775 +       i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
 776 +
 777 +       /* remove driver */
 778 +       platform_set_drvdata(pdev, NULL);
 779 +       i2c_del_adapter(&priv->adap);
 780 +
 781 +       free_irq(priv->irq_lb, priv);
 782 +       free_irq(priv->irq_b, priv);
 783 +       free_irq(priv->irq_err, priv);
 784 +       free_irq(priv->irq_p, priv);
 785 +
 786 +       kfree(priv);
 787 +
 788 +       mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 789 +       release_mem_region(mmres->start, resource_size(mmres));
 790 +
 791 +       dev_dbg(&pdev->dev, "removed\n");
 792 +
 793 +       return 0;
 794 +}
 795 +
 796 +static struct platform_driver falcon_i2c_driver = {
 797 +       .probe  = falcon_i2c_probe,
 798 +       .remove = __devexit_p(falcon_i2c_remove),
 799 +       .driver = {
 800 +               .name   = DRV_NAME,
 801 +               .owner  = THIS_MODULE,
 802 +       },
 803 +};
 804 +
 805 +static int __init falcon_i2c_init(void)
 806 +{
 807 +       int ret;
 808 +
 809 +       ret = platform_driver_register(&falcon_i2c_driver);
 810 +
 811 +       if (ret)
 812 +               printk(KERN_DEBUG DRV_NAME ": can't register platform driver");
 813 +
 814 +       return ret;
 815 +}
 816 +
 817 +static void __exit falcon_i2c_exit(void)
 818 +{
 819 +       platform_driver_unregister(&falcon_i2c_driver);
 820 +}
 821 +
 822 +module_init(falcon_i2c_init);
 823 +module_exit(falcon_i2c_exit);
 824 +
 825 +MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter");
 826 +MODULE_ALIAS("platform:i2c_falcon");
 827 +MODULE_LICENSE("GPL");