fix Magicbox for .21 and convert to the new structure
[openwrt/svn-archive/archive.git] / target / linux / magicbox-2.6 / files / arch / ppc / platforms / 4xx / magicbox.c
1 /*
2 * Support for IBM PPC 405EP-based MagicBox board
3 * Copyright (C) 2006 Karol Lewandowski
4 *
5 * Heavily based on bubinga.c
6 *
7 * Author: SAW (IBM), derived from walnut.c.
8 * Maintained by MontaVista Software <source@mvista.com>
9 *
10 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
11 * terms of the GNU General Public License version 2. This program is
12 * licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/smp.h>
19 #include <linux/threads.h>
20 #include <linux/param.h>
21 #include <linux/string.h>
22 #include <linux/blkdev.h>
23 #include <linux/pci.h>
24 #include <linux/tty.h>
25 #include <linux/serial.h>
26 #include <linux/serial_core.h>
27
28 #include <asm/system.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/processor.h>
31 #include <asm/machdep.h>
32 #include <asm/page.h>
33 #include <asm/time.h>
34 #include <asm/io.h>
35 #include <asm/kgdb.h>
36 #include <asm/ocp.h>
37 #include <asm/ibm_ocp_pci.h>
38
39 #include <platforms/4xx/ibm405ep.h>
40
41 #undef DEBUG
42
43 #ifdef DEBUG
44 #define DBG(x...) printk(x)
45 #else
46 #define DBG(x...)
47 #endif
48
49 extern bd_t __res;
50
51 /* Some IRQs unique to board
52 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
53 */
54 int __init
55 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
56 {
57 static char pci_irq_table[][4] =
58 /*
59 * PCI IDSEL/INTPIN->INTLINE
60 * A B C D
61 */
62 {
63 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
64 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
65 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
66 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
67 };
68
69 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
70 return PCI_IRQ_TABLE_LOOKUP;
71 };
72
73
74 /* The serial clock for the chip is an internal clock determined by
75 * different clock speeds/dividers.
76 * Calculate the proper input baud rate and setup the serial driver.
77 */
78 static void __init
79 magicbox_early_serial_map(void)
80 {
81 u32 uart_div;
82 int uart_clock;
83 struct uart_port port;
84
85 /* Calculate the serial clock input frequency
86 *
87 * The base baud is the PLL OUTA (provided in the board info
88 * structure) divided by the external UART Divisor, divided
89 * by 16.
90 */
91 uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
92 uart_clock = __res.bi_procfreq / uart_div;
93
94 /* Setup serial port access */
95 memset(&port, 0, sizeof(port));
96 port.membase = (void*)ACTING_UART0_IO_BASE;
97 port.irq = ACTING_UART0_INT;
98 port.uartclk = uart_clock;
99 port.regshift = 0;
100 port.iotype = SERIAL_IO_MEM;
101 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
102 port.line = 0;
103
104 if (early_serial_setup(&port) != 0) {
105 printk("Early serial init of port 0 failed\n");
106 }
107
108 port.membase = (void*)ACTING_UART1_IO_BASE;
109 port.irq = ACTING_UART1_INT;
110 port.line = 1;
111
112 if (early_serial_setup(&port) != 0) {
113 printk("Early serial init of port 1 failed\n");
114 }
115 }
116
117 void __init
118 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
119 {
120 unsigned int bar_response, bar;
121 /*
122 * Expected PCI mapping:
123 *
124 * PLB addr PCI memory addr
125 * --------------------- ---------------------
126 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
127 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
128 *
129 * PLB addr PCI io addr
130 * --------------------- ---------------------
131 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
132 *
133 * The following code is simplified by assuming that the bootrom
134 * has been well behaved in following this mapping.
135 */
136
137 #ifdef DEBUG
138 int i;
139
140 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
141 printk("PCI bridge regs before fixup \n");
142 for (i = 0; i <= 3; i++) {
143 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
144 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
145 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
146 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
147 }
148 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
149 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
150 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
151 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
152
153 #endif
154
155 /* added for IBM boot rom version 1.15 bios bar changes -AK */
156
157 /* Disable region first */
158 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
159 /* PLB starting addr, PCI: 0x80000000 */
160 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
161 /* PCI start addr, 0x80000000 */
162 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
163 /* 512MB range of PLB to PCI */
164 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
165 /* Enable no pre-fetch, enable region */
166 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
167 (PPC405_PCI_UPPER_MEM -
168 PPC405_PCI_MEM_BASE)) | 0x01));
169
170 /* Disable region one */
171 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
172 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
173 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
174 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
175 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
176 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
177
178 /* Disable region two */
179 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
180 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
181 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
182 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
183 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
184 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
185 out_le32((void *) &(pcip->ptm2la), 0x00000000);
186
187 /* Zero config bars */
188 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
189 early_write_config_dword(hose, hose->first_busno,
190 PCI_FUNC(hose->first_busno), bar,
191 0x00000000);
192 early_read_config_dword(hose, hose->first_busno,
193 PCI_FUNC(hose->first_busno), bar,
194 &bar_response);
195 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
196 hose->first_busno, PCI_SLOT(hose->first_busno),
197 PCI_FUNC(hose->first_busno), bar, bar_response);
198 }
199 /* end work arround */
200
201 #ifdef DEBUG
202 printk("PCI bridge regs after fixup \n");
203 for (i = 0; i <= 3; i++) {
204 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
205 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
206 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
207 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
208 }
209 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
210 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
211 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
212 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
213
214 #endif /* DEBUG */
215 }
216
217 void __init
218 magicbox_setup_arch(void)
219 {
220 ppc4xx_setup_arch();
221
222 ibm_ocp_set_emac(0, 1);
223
224 magicbox_early_serial_map();
225
226 /* Identify the system */
227 printk("MagicBox port (C) 2005 Karol Lewandowski <kl@jasmine.eu.org>\n");
228 }
229
230 void __init
231 magicbox_map_io(void)
232 {
233 ppc4xx_map_io();
234 }
235
236 void __init
237 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
238 unsigned long r6, unsigned long r7)
239 {
240 ppc4xx_init(r3, r4, r5, r6, r7);
241
242 ppc_md.setup_arch = magicbox_setup_arch;
243 ppc_md.setup_io_mappings = magicbox_map_io;
244
245 #ifdef CONFIG_KGDB
246 ppc_md.early_serial_map = bubinga_early_serial_map;
247 #endif
248
249 }