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kernel: update kernel 4.4 to version 4.4.7
[openwrt/svn-archive/archive.git] / target / linux / mediatek / patches-4.4 / 0002-soc-mediatek-Separate-scpsys-driver-common-code.patch
1 From 2c93328ed05061a50e3bd4111379dbcf6946d3ac Mon Sep 17 00:00:00 2001
2 From: James Liao <jamesjj.liao@mediatek.com>
3 Date: Wed, 30 Dec 2015 14:41:43 +0800
4 Subject: [PATCH 02/81] soc: mediatek: Separate scpsys driver common code
5
6 Separate scpsys driver common code to mtk-scpsys.c, and move MT8173
7 platform code to mtk-scpsys-mt8173.c.
8
9 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
10 ---
11 drivers/soc/mediatek/Kconfig | 13 +-
12 drivers/soc/mediatek/Makefile | 1 +
13 drivers/soc/mediatek/mtk-scpsys-mt8173.c | 179 ++++++++++++++++++
14 drivers/soc/mediatek/mtk-scpsys.c | 301 ++++++++----------------------
15 drivers/soc/mediatek/mtk-scpsys.h | 54 ++++++
16 5 files changed, 320 insertions(+), 228 deletions(-)
17 create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt8173.c
18 create mode 100644 drivers/soc/mediatek/mtk-scpsys.h
19
20 --- a/drivers/soc/mediatek/Kconfig
21 +++ b/drivers/soc/mediatek/Kconfig
22 @@ -22,11 +22,20 @@ config MTK_PMIC_WRAP
23
24 config MTK_SCPSYS
25 bool "MediaTek SCPSYS Support"
26 - depends on ARCH_MEDIATEK || COMPILE_TEST
27 - default ARM64 && ARCH_MEDIATEK
28 select REGMAP
29 select MTK_INFRACFG
30 select PM_GENERIC_DOMAINS if PM
31 help
32 Say yes here to add support for the MediaTek SCPSYS power domain
33 driver.
34 +
35 +config MTK_SCPSYS_MT8173
36 + bool "MediaTek MT8173 SCPSYS Support"
37 + depends on ARCH_MEDIATEK || COMPILE_TEST
38 + select MTK_SCPSYS
39 + default ARCH_MEDIATEK
40 + help
41 + Say yes here to add support for the MT8173 SCPSYS power domain
42 + driver.
43 + The System Control Processor System (SCPSYS) has several power
44 + management related tasks in the system.
45 --- a/drivers/soc/mediatek/Makefile
46 +++ b/drivers/soc/mediatek/Makefile
47 @@ -1,3 +1,4 @@
48 obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
49 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
50 obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
51 +obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
52 --- /dev/null
53 +++ b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
54 @@ -0,0 +1,179 @@
55 +/*
56 + * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
57 + *
58 + * This program is free software; you can redistribute it and/or modify
59 + * it under the terms of the GNU General Public License version 2 as
60 + * published by the Free Software Foundation.
61 + *
62 + * This program is distributed in the hope that it will be useful,
63 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
64 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
65 + * GNU General Public License for more details.
66 + */
67 +#include <linux/mfd/syscon.h>
68 +#include <linux/module.h>
69 +#include <linux/of_device.h>
70 +#include <linux/pm_domain.h>
71 +#include <linux/soc/mediatek/infracfg.h>
72 +#include <dt-bindings/power/mt8173-power.h>
73 +
74 +#include "mtk-scpsys.h"
75 +
76 +#define SPM_VDE_PWR_CON 0x0210
77 +#define SPM_MFG_PWR_CON 0x0214
78 +#define SPM_VEN_PWR_CON 0x0230
79 +#define SPM_ISP_PWR_CON 0x0238
80 +#define SPM_DIS_PWR_CON 0x023c
81 +#define SPM_VEN2_PWR_CON 0x0298
82 +#define SPM_AUDIO_PWR_CON 0x029c
83 +#define SPM_MFG_2D_PWR_CON 0x02c0
84 +#define SPM_MFG_ASYNC_PWR_CON 0x02c4
85 +#define SPM_USB_PWR_CON 0x02cc
86 +
87 +#define PWR_STATUS_DISP BIT(3)
88 +#define PWR_STATUS_MFG BIT(4)
89 +#define PWR_STATUS_ISP BIT(5)
90 +#define PWR_STATUS_VDEC BIT(7)
91 +#define PWR_STATUS_VENC_LT BIT(20)
92 +#define PWR_STATUS_VENC BIT(21)
93 +#define PWR_STATUS_MFG_2D BIT(22)
94 +#define PWR_STATUS_MFG_ASYNC BIT(23)
95 +#define PWR_STATUS_AUDIO BIT(24)
96 +#define PWR_STATUS_USB BIT(25)
97 +
98 +static const struct scp_domain_data scp_domain_data[] __initconst = {
99 + [MT8173_POWER_DOMAIN_VDEC] = {
100 + .name = "vdec",
101 + .sta_mask = PWR_STATUS_VDEC,
102 + .ctl_offs = SPM_VDE_PWR_CON,
103 + .sram_pdn_bits = GENMASK(11, 8),
104 + .sram_pdn_ack_bits = GENMASK(12, 12),
105 + .clk_id = {CLK_MM},
106 + },
107 + [MT8173_POWER_DOMAIN_VENC] = {
108 + .name = "venc",
109 + .sta_mask = PWR_STATUS_VENC,
110 + .ctl_offs = SPM_VEN_PWR_CON,
111 + .sram_pdn_bits = GENMASK(11, 8),
112 + .sram_pdn_ack_bits = GENMASK(15, 12),
113 + .clk_id = {CLK_MM, CLK_VENC},
114 + },
115 + [MT8173_POWER_DOMAIN_ISP] = {
116 + .name = "isp",
117 + .sta_mask = PWR_STATUS_ISP,
118 + .ctl_offs = SPM_ISP_PWR_CON,
119 + .sram_pdn_bits = GENMASK(11, 8),
120 + .sram_pdn_ack_bits = GENMASK(13, 12),
121 + .clk_id = {CLK_MM},
122 + },
123 + [MT8173_POWER_DOMAIN_MM] = {
124 + .name = "mm",
125 + .sta_mask = PWR_STATUS_DISP,
126 + .ctl_offs = SPM_DIS_PWR_CON,
127 + .sram_pdn_bits = GENMASK(11, 8),
128 + .sram_pdn_ack_bits = GENMASK(12, 12),
129 + .clk_id = {CLK_MM},
130 + .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
131 + MT8173_TOP_AXI_PROT_EN_MM_M1,
132 + },
133 + [MT8173_POWER_DOMAIN_VENC_LT] = {
134 + .name = "venc_lt",
135 + .sta_mask = PWR_STATUS_VENC_LT,
136 + .ctl_offs = SPM_VEN2_PWR_CON,
137 + .sram_pdn_bits = GENMASK(11, 8),
138 + .sram_pdn_ack_bits = GENMASK(15, 12),
139 + .clk_id = {CLK_MM, CLK_VENC_LT},
140 + },
141 + [MT8173_POWER_DOMAIN_AUDIO] = {
142 + .name = "audio",
143 + .sta_mask = PWR_STATUS_AUDIO,
144 + .ctl_offs = SPM_AUDIO_PWR_CON,
145 + .sram_pdn_bits = GENMASK(11, 8),
146 + .sram_pdn_ack_bits = GENMASK(15, 12),
147 + .clk_id = {CLK_NONE},
148 + },
149 + [MT8173_POWER_DOMAIN_USB] = {
150 + .name = "usb",
151 + .sta_mask = PWR_STATUS_USB,
152 + .ctl_offs = SPM_USB_PWR_CON,
153 + .sram_pdn_bits = GENMASK(11, 8),
154 + .sram_pdn_ack_bits = GENMASK(15, 12),
155 + .clk_id = {CLK_NONE},
156 + .active_wakeup = true,
157 + },
158 + [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
159 + .name = "mfg_async",
160 + .sta_mask = PWR_STATUS_MFG_ASYNC,
161 + .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
162 + .sram_pdn_bits = GENMASK(11, 8),
163 + .sram_pdn_ack_bits = 0,
164 + .clk_id = {CLK_MFG},
165 + },
166 + [MT8173_POWER_DOMAIN_MFG_2D] = {
167 + .name = "mfg_2d",
168 + .sta_mask = PWR_STATUS_MFG_2D,
169 + .ctl_offs = SPM_MFG_2D_PWR_CON,
170 + .sram_pdn_bits = GENMASK(11, 8),
171 + .sram_pdn_ack_bits = GENMASK(13, 12),
172 + .clk_id = {CLK_NONE},
173 + },
174 + [MT8173_POWER_DOMAIN_MFG] = {
175 + .name = "mfg",
176 + .sta_mask = PWR_STATUS_MFG,
177 + .ctl_offs = SPM_MFG_PWR_CON,
178 + .sram_pdn_bits = GENMASK(13, 8),
179 + .sram_pdn_ack_bits = GENMASK(21, 16),
180 + .clk_id = {CLK_NONE},
181 + .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
182 + MT8173_TOP_AXI_PROT_EN_MFG_M0 |
183 + MT8173_TOP_AXI_PROT_EN_MFG_M1 |
184 + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
185 + },
186 +};
187 +
188 +#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
189 +
190 +static int __init scpsys_probe(struct platform_device *pdev)
191 +{
192 + struct scp *scp;
193 + struct genpd_onecell_data *pd_data;
194 + int ret;
195 +
196 + scp = init_scp(pdev, scp_domain_data, NUM_DOMAINS);
197 + if (IS_ERR(scp))
198 + return PTR_ERR(scp);
199 +
200 + mtk_register_power_domains(pdev, scp, NUM_DOMAINS);
201 +
202 + pd_data = &scp->pd_data;
203 +
204 + ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
205 + pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
206 + if (ret && IS_ENABLED(CONFIG_PM))
207 + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
208 +
209 + ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
210 + pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
211 + if (ret && IS_ENABLED(CONFIG_PM))
212 + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
213 +
214 + return 0;
215 +}
216 +
217 +static const struct of_device_id of_scpsys_match_tbl[] = {
218 + {
219 + .compatible = "mediatek,mt8173-scpsys",
220 + }, {
221 + /* sentinel */
222 + }
223 +};
224 +
225 +static struct platform_driver scpsys_drv = {
226 + .driver = {
227 + .name = "mtk-scpsys-mt8173",
228 + .owner = THIS_MODULE,
229 + .of_match_table = of_match_ptr(of_scpsys_match_tbl),
230 + },
231 +};
232 +
233 +module_platform_driver_probe(scpsys_drv, scpsys_probe);
234 --- a/drivers/soc/mediatek/mtk-scpsys.c
235 +++ b/drivers/soc/mediatek/mtk-scpsys.c
236 @@ -11,28 +11,14 @@
237 * GNU General Public License for more details.
238 */
239 #include <linux/clk.h>
240 -#include <linux/delay.h>
241 #include <linux/io.h>
242 -#include <linux/kernel.h>
243 #include <linux/mfd/syscon.h>
244 -#include <linux/module.h>
245 -#include <linux/of_device.h>
246 #include <linux/platform_device.h>
247 #include <linux/pm_domain.h>
248 -#include <linux/regmap.h>
249 #include <linux/soc/mediatek/infracfg.h>
250 -#include <dt-bindings/power/mt8173-power.h>
251
252 -#define SPM_VDE_PWR_CON 0x0210
253 -#define SPM_MFG_PWR_CON 0x0214
254 -#define SPM_VEN_PWR_CON 0x0230
255 -#define SPM_ISP_PWR_CON 0x0238
256 -#define SPM_DIS_PWR_CON 0x023c
257 -#define SPM_VEN2_PWR_CON 0x0298
258 -#define SPM_AUDIO_PWR_CON 0x029c
259 -#define SPM_MFG_2D_PWR_CON 0x02c0
260 -#define SPM_MFG_ASYNC_PWR_CON 0x02c4
261 -#define SPM_USB_PWR_CON 0x02cc
262 +#include "mtk-scpsys.h"
263 +
264 #define SPM_PWR_STATUS 0x060c
265 #define SPM_PWR_STATUS_2ND 0x0610
266
267 @@ -42,153 +28,6 @@
268 #define PWR_ON_2ND_BIT BIT(3)
269 #define PWR_CLK_DIS_BIT BIT(4)
270
271 -#define PWR_STATUS_DISP BIT(3)
272 -#define PWR_STATUS_MFG BIT(4)
273 -#define PWR_STATUS_ISP BIT(5)
274 -#define PWR_STATUS_VDEC BIT(7)
275 -#define PWR_STATUS_VENC_LT BIT(20)
276 -#define PWR_STATUS_VENC BIT(21)
277 -#define PWR_STATUS_MFG_2D BIT(22)
278 -#define PWR_STATUS_MFG_ASYNC BIT(23)
279 -#define PWR_STATUS_AUDIO BIT(24)
280 -#define PWR_STATUS_USB BIT(25)
281 -
282 -enum clk_id {
283 - MT8173_CLK_NONE,
284 - MT8173_CLK_MM,
285 - MT8173_CLK_MFG,
286 - MT8173_CLK_VENC,
287 - MT8173_CLK_VENC_LT,
288 - MT8173_CLK_MAX,
289 -};
290 -
291 -#define MAX_CLKS 2
292 -
293 -struct scp_domain_data {
294 - const char *name;
295 - u32 sta_mask;
296 - int ctl_offs;
297 - u32 sram_pdn_bits;
298 - u32 sram_pdn_ack_bits;
299 - u32 bus_prot_mask;
300 - enum clk_id clk_id[MAX_CLKS];
301 - bool active_wakeup;
302 -};
303 -
304 -static const struct scp_domain_data scp_domain_data[] __initconst = {
305 - [MT8173_POWER_DOMAIN_VDEC] = {
306 - .name = "vdec",
307 - .sta_mask = PWR_STATUS_VDEC,
308 - .ctl_offs = SPM_VDE_PWR_CON,
309 - .sram_pdn_bits = GENMASK(11, 8),
310 - .sram_pdn_ack_bits = GENMASK(12, 12),
311 - .clk_id = {MT8173_CLK_MM},
312 - },
313 - [MT8173_POWER_DOMAIN_VENC] = {
314 - .name = "venc",
315 - .sta_mask = PWR_STATUS_VENC,
316 - .ctl_offs = SPM_VEN_PWR_CON,
317 - .sram_pdn_bits = GENMASK(11, 8),
318 - .sram_pdn_ack_bits = GENMASK(15, 12),
319 - .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
320 - },
321 - [MT8173_POWER_DOMAIN_ISP] = {
322 - .name = "isp",
323 - .sta_mask = PWR_STATUS_ISP,
324 - .ctl_offs = SPM_ISP_PWR_CON,
325 - .sram_pdn_bits = GENMASK(11, 8),
326 - .sram_pdn_ack_bits = GENMASK(13, 12),
327 - .clk_id = {MT8173_CLK_MM},
328 - },
329 - [MT8173_POWER_DOMAIN_MM] = {
330 - .name = "mm",
331 - .sta_mask = PWR_STATUS_DISP,
332 - .ctl_offs = SPM_DIS_PWR_CON,
333 - .sram_pdn_bits = GENMASK(11, 8),
334 - .sram_pdn_ack_bits = GENMASK(12, 12),
335 - .clk_id = {MT8173_CLK_MM},
336 - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
337 - MT8173_TOP_AXI_PROT_EN_MM_M1,
338 - },
339 - [MT8173_POWER_DOMAIN_VENC_LT] = {
340 - .name = "venc_lt",
341 - .sta_mask = PWR_STATUS_VENC_LT,
342 - .ctl_offs = SPM_VEN2_PWR_CON,
343 - .sram_pdn_bits = GENMASK(11, 8),
344 - .sram_pdn_ack_bits = GENMASK(15, 12),
345 - .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
346 - },
347 - [MT8173_POWER_DOMAIN_AUDIO] = {
348 - .name = "audio",
349 - .sta_mask = PWR_STATUS_AUDIO,
350 - .ctl_offs = SPM_AUDIO_PWR_CON,
351 - .sram_pdn_bits = GENMASK(11, 8),
352 - .sram_pdn_ack_bits = GENMASK(15, 12),
353 - .clk_id = {MT8173_CLK_NONE},
354 - },
355 - [MT8173_POWER_DOMAIN_USB] = {
356 - .name = "usb",
357 - .sta_mask = PWR_STATUS_USB,
358 - .ctl_offs = SPM_USB_PWR_CON,
359 - .sram_pdn_bits = GENMASK(11, 8),
360 - .sram_pdn_ack_bits = GENMASK(15, 12),
361 - .clk_id = {MT8173_CLK_NONE},
362 - .active_wakeup = true,
363 - },
364 - [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
365 - .name = "mfg_async",
366 - .sta_mask = PWR_STATUS_MFG_ASYNC,
367 - .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
368 - .sram_pdn_bits = GENMASK(11, 8),
369 - .sram_pdn_ack_bits = 0,
370 - .clk_id = {MT8173_CLK_MFG},
371 - },
372 - [MT8173_POWER_DOMAIN_MFG_2D] = {
373 - .name = "mfg_2d",
374 - .sta_mask = PWR_STATUS_MFG_2D,
375 - .ctl_offs = SPM_MFG_2D_PWR_CON,
376 - .sram_pdn_bits = GENMASK(11, 8),
377 - .sram_pdn_ack_bits = GENMASK(13, 12),
378 - .clk_id = {MT8173_CLK_NONE},
379 - },
380 - [MT8173_POWER_DOMAIN_MFG] = {
381 - .name = "mfg",
382 - .sta_mask = PWR_STATUS_MFG,
383 - .ctl_offs = SPM_MFG_PWR_CON,
384 - .sram_pdn_bits = GENMASK(13, 8),
385 - .sram_pdn_ack_bits = GENMASK(21, 16),
386 - .clk_id = {MT8173_CLK_NONE},
387 - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
388 - MT8173_TOP_AXI_PROT_EN_MFG_M0 |
389 - MT8173_TOP_AXI_PROT_EN_MFG_M1 |
390 - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
391 - },
392 -};
393 -
394 -#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
395 -
396 -struct scp;
397 -
398 -struct scp_domain {
399 - struct generic_pm_domain genpd;
400 - struct scp *scp;
401 - struct clk *clk[MAX_CLKS];
402 - u32 sta_mask;
403 - void __iomem *ctl_addr;
404 - u32 sram_pdn_bits;
405 - u32 sram_pdn_ack_bits;
406 - u32 bus_prot_mask;
407 - bool active_wakeup;
408 -};
409 -
410 -struct scp {
411 - struct scp_domain domains[NUM_DOMAINS];
412 - struct genpd_onecell_data pd_data;
413 - struct device *dev;
414 - void __iomem *base;
415 - struct regmap *infracfg;
416 -};
417 -
418 static int scpsys_domain_is_on(struct scp_domain *scpd)
419 {
420 struct scp *scp = scpd->scp;
421 @@ -398,63 +237,89 @@ static bool scpsys_active_wakeup(struct
422 return scpd->active_wakeup;
423 }
424
425 -static int __init scpsys_probe(struct platform_device *pdev)
426 +static void init_clks(struct platform_device *pdev, struct clk *clk[CLK_MAX])
427 +{
428 + enum clk_id clk_ids[] = {
429 + CLK_MM,
430 + CLK_MFG,
431 + CLK_VENC,
432 + CLK_VENC_LT
433 + };
434 +
435 + static const char * const clk_names[] = {
436 + "mm",
437 + "mfg",
438 + "venc",
439 + "venc_lt",
440 + };
441 +
442 + int i;
443 +
444 + for (i = 0; i < ARRAY_SIZE(clk_ids); i++)
445 + clk[clk_ids[i]] = devm_clk_get(&pdev->dev, clk_names[i]);
446 +}
447 +
448 +struct scp *init_scp(struct platform_device *pdev,
449 + const struct scp_domain_data *scp_domain_data, int num)
450 {
451 struct genpd_onecell_data *pd_data;
452 struct resource *res;
453 - int i, j, ret;
454 + int i, j;
455 struct scp *scp;
456 - struct clk *clk[MT8173_CLK_MAX];
457 + struct clk *clk[CLK_MAX];
458
459 scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
460 if (!scp)
461 - return -ENOMEM;
462 + return ERR_PTR(-ENOMEM);
463
464 scp->dev = &pdev->dev;
465
466 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
467 scp->base = devm_ioremap_resource(&pdev->dev, res);
468 if (IS_ERR(scp->base))
469 - return PTR_ERR(scp->base);
470 -
471 - pd_data = &scp->pd_data;
472 -
473 - pd_data->domains = devm_kzalloc(&pdev->dev,
474 - sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
475 - if (!pd_data->domains)
476 - return -ENOMEM;
477 -
478 - clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
479 - if (IS_ERR(clk[MT8173_CLK_MM]))
480 - return PTR_ERR(clk[MT8173_CLK_MM]);
481 -
482 - clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
483 - if (IS_ERR(clk[MT8173_CLK_MFG]))
484 - return PTR_ERR(clk[MT8173_CLK_MFG]);
485 -
486 - clk[MT8173_CLK_VENC] = devm_clk_get(&pdev->dev, "venc");
487 - if (IS_ERR(clk[MT8173_CLK_VENC]))
488 - return PTR_ERR(clk[MT8173_CLK_VENC]);
489 -
490 - clk[MT8173_CLK_VENC_LT] = devm_clk_get(&pdev->dev, "venc_lt");
491 - if (IS_ERR(clk[MT8173_CLK_VENC_LT]))
492 - return PTR_ERR(clk[MT8173_CLK_VENC_LT]);
493 + return ERR_CAST(scp->base);
494
495 scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
496 "infracfg");
497 if (IS_ERR(scp->infracfg)) {
498 dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
499 PTR_ERR(scp->infracfg));
500 - return PTR_ERR(scp->infracfg);
501 + return ERR_CAST(scp->infracfg);
502 }
503
504 - pd_data->num_domains = NUM_DOMAINS;
505 + scp->domains = devm_kzalloc(&pdev->dev,
506 + sizeof(*scp->domains) * num, GFP_KERNEL);
507 + if (!scp->domains)
508 + return ERR_PTR(-ENOMEM);
509 +
510 + pd_data = &scp->pd_data;
511
512 - for (i = 0; i < NUM_DOMAINS; i++) {
513 + pd_data->domains = devm_kzalloc(&pdev->dev,
514 + sizeof(*pd_data->domains) * num, GFP_KERNEL);
515 + if (!pd_data->domains)
516 + return ERR_PTR(-ENOMEM);
517 +
518 + pd_data->num_domains = num;
519 +
520 + init_clks(pdev, clk);
521 +
522 + for (i = 0; i < num; i++) {
523 struct scp_domain *scpd = &scp->domains[i];
524 struct generic_pm_domain *genpd = &scpd->genpd;
525 const struct scp_domain_data *data = &scp_domain_data[i];
526
527 + for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
528 + struct clk *c = clk[data->clk_id[j]];
529 +
530 + if (IS_ERR(c)) {
531 + dev_err(&pdev->dev, "%s: clk unavailable\n",
532 + data->name);
533 + return ERR_CAST(c);
534 + }
535 +
536 + scpd->clk[j] = c;
537 + }
538 +
539 pd_data->domains[i] = genpd;
540 scpd->scp = scp;
541
542 @@ -464,13 +329,25 @@ static int __init scpsys_probe(struct pl
543 scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
544 scpd->bus_prot_mask = data->bus_prot_mask;
545 scpd->active_wakeup = data->active_wakeup;
546 - for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++)
547 - scpd->clk[j] = clk[data->clk_id[j]];
548
549 genpd->name = data->name;
550 genpd->power_off = scpsys_power_off;
551 genpd->power_on = scpsys_power_on;
552 genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
553 + }
554 +
555 + return scp;
556 +}
557 +
558 +void mtk_register_power_domains(struct platform_device *pdev,
559 + struct scp *scp, int num)
560 +{
561 + struct genpd_onecell_data *pd_data;
562 + int i, ret;
563 +
564 + for (i = 0; i < num; i++) {
565 + struct scp_domain *scpd = &scp->domains[i];
566 + struct generic_pm_domain *genpd = &scpd->genpd;
567
568 /*
569 * Initially turn on all domains to make the domains usable
570 @@ -489,37 +366,9 @@ static int __init scpsys_probe(struct pl
571 * valid.
572 */
573
574 - ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
575 - pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
576 - if (ret && IS_ENABLED(CONFIG_PM))
577 - dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
578 -
579 - ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
580 - pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
581 - if (ret && IS_ENABLED(CONFIG_PM))
582 - dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
583 + pd_data = &scp->pd_data;
584
585 ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
586 if (ret)
587 dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
588 -
589 - return 0;
590 }
591 -
592 -static const struct of_device_id of_scpsys_match_tbl[] = {
593 - {
594 - .compatible = "mediatek,mt8173-scpsys",
595 - }, {
596 - /* sentinel */
597 - }
598 -};
599 -
600 -static struct platform_driver scpsys_drv = {
601 - .driver = {
602 - .name = "mtk-scpsys",
603 - .owner = THIS_MODULE,
604 - .of_match_table = of_match_ptr(of_scpsys_match_tbl),
605 - },
606 -};
607 -
608 -module_platform_driver_probe(scpsys_drv, scpsys_probe);
609 --- /dev/null
610 +++ b/drivers/soc/mediatek/mtk-scpsys.h
611 @@ -0,0 +1,54 @@
612 +#ifndef __DRV_SOC_MTK_H
613 +#define __DRV_SOC_MTK_H
614 +
615 +enum clk_id {
616 + CLK_NONE,
617 + CLK_MM,
618 + CLK_MFG,
619 + CLK_VENC,
620 + CLK_VENC_LT,
621 + CLK_MAX,
622 +};
623 +
624 +#define MAX_CLKS 2
625 +
626 +struct scp_domain_data {
627 + const char *name;
628 + u32 sta_mask;
629 + int ctl_offs;
630 + u32 sram_pdn_bits;
631 + u32 sram_pdn_ack_bits;
632 + u32 bus_prot_mask;
633 + enum clk_id clk_id[MAX_CLKS];
634 + bool active_wakeup;
635 +};
636 +
637 +struct scp;
638 +
639 +struct scp_domain {
640 + struct generic_pm_domain genpd;
641 + struct scp *scp;
642 + struct clk *clk[MAX_CLKS];
643 + u32 sta_mask;
644 + void __iomem *ctl_addr;
645 + u32 sram_pdn_bits;
646 + u32 sram_pdn_ack_bits;
647 + u32 bus_prot_mask;
648 + bool active_wakeup;
649 +};
650 +
651 +struct scp {
652 + struct scp_domain *domains;
653 + struct genpd_onecell_data pd_data;
654 + struct device *dev;
655 + void __iomem *base;
656 + struct regmap *infracfg;
657 +};
658 +
659 +struct scp *init_scp(struct platform_device *pdev,
660 + const struct scp_domain_data *scp_domain_data, int num);
661 +
662 +void mtk_register_power_domains(struct platform_device *pdev,
663 + struct scp *scp, int num);
664 +
665 +#endif /* __DRV_SOC_MTK_H */
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