target/linux/mediatek/patches/0031-I2C-mediatek-Add-driver-for-MediaTek-MT8173-I2C-cont.patch

   1 From 5f33206ebe4fb4a2cc8634f29c3e3c9bc01e3416 Mon Sep 17 00:00:00 2001
   2 From: Eddie Huang <eddie.huang@mediatek.com>
   3 Date: Wed, 6 May 2015 16:37:07 +0800
   4 Subject: [PATCH 31/76] I2C: mediatek: Add driver for MediaTek MT8173 I2C
   5  controller
   6
   7 Add mediatek MT8173 I2C controller driver. Compare to I2C controller
   8 of earlier mediatek SoC, MT8173 fix write-then-read limitation, and
   9 also increase message size to 64kb.
  10
  11 Signed-off-by: Xudong Chen <xudong.chen@mediatek.com>
  12 Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
  13 Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
  14 ---
  15  drivers/i2c/busses/i2c-mt65xx.c |  104 ++++++++++++++++++++++++++++-----------
  16  1 file changed, 76 insertions(+), 28 deletions(-)
  17
  18 --- a/drivers/i2c/busses/i2c-mt65xx.c
  19 +++ b/drivers/i2c/busses/i2c-mt65xx.c
  20 @@ -33,10 +33,13 @@
  21  #include <linux/clk.h>
  22  #include <linux/completion.h>
  23
  24 +#define I2C_RS_TRANSFER                        (1 << 4)
  25  #define I2C_HS_NACKERR                 (1 << 2)
  26  #define I2C_ACKERR                     (1 << 1)
  27  #define I2C_TRANSAC_COMP               (1 << 0)
  28  #define I2C_TRANSAC_START              (1 << 0)
  29 +#define I2C_RS_MUL_CNFG                        (1 << 15)
  30 +#define I2C_RS_MUL_TRIG                        (1 << 14)
  31  #define I2C_TIMING_STEP_DIV_MASK       (0x3f << 0)
  32  #define I2C_TIMING_SAMPLE_COUNT_MASK   (0x7 << 0)
  33  #define I2C_TIMING_SAMPLE_DIV_MASK     (0x7 << 8)
  34 @@ -67,6 +70,9 @@
  35  #define MAX_MSG_NUM_MT6577             1
  36  #define MAX_DMA_TRANS_SIZE_MT6577      255
  37  #define MAX_WRRD_TRANS_SIZE_MT6577     31
  38 +#define MAX_MSG_NUM_MT8173             65535
  39 +#define MAX_DMA_TRANS_SIZE_MT8173      65535
  40 +#define MAX_WRRD_TRANS_SIZE_MT8173     65535
  41  #define MAX_SAMPLE_CNT_DIV             8
  42  #define MAX_STEP_CNT_DIV               64
  43  #define MAX_HS_STEP_CNT_DIV            8
  44 @@ -139,6 +145,7 @@ struct mtk_i2c_compatible {
  45         const struct i2c_adapter_quirks *quirks;
  46         unsigned char pmic_i2c;
  47         unsigned char dcm;
  48 +       unsigned char auto_restart;
  49  };
  50
  51  struct mtk_i2c {
  52 @@ -172,21 +179,39 @@ static const struct i2c_adapter_quirks m
  53         .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT6577,
  54  };
  55
  56 +static const struct i2c_adapter_quirks mt8173_i2c_quirks = {
  57 +       .max_num_msgs = MAX_MSG_NUM_MT8173,
  58 +       .max_write_len = MAX_DMA_TRANS_SIZE_MT8173,
  59 +       .max_read_len = MAX_DMA_TRANS_SIZE_MT8173,
  60 +       .max_comb_1st_msg_len = MAX_DMA_TRANS_SIZE_MT8173,
  61 +       .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT8173,
  62 +};
  63 +
  64  static const struct mtk_i2c_compatible mt6577_compat = {
  65         .quirks = &mt6577_i2c_quirks,
  66         .pmic_i2c = 0,
  67         .dcm = 1,
  68 +       .auto_restart = 0,
  69  };
  70
  71  static const struct mtk_i2c_compatible mt6589_compat = {
  72         .quirks = &mt6577_i2c_quirks,
  73         .pmic_i2c = 1,
  74         .dcm = 0,
  75 +       .auto_restart = 0,
  76 +};
  77 +
  78 +static const struct mtk_i2c_compatible mt8173_compat = {
  79 +       .quirks = &mt8173_i2c_quirks,
  80 +       .pmic_i2c = 0,
  81 +       .dcm = 1,
  82 +       .auto_restart = 1,
  83  };
  84
  85  static const struct of_device_id mtk_i2c_of_match[] = {
  86         { .compatible = "mediatek,mt6577-i2c", .data = (void *)&mt6577_compat },
  87         { .compatible = "mediatek,mt6589-i2c", .data = (void *)&mt6589_compat },
  88 +       { .compatible = "mediatek,mt8173-i2c", .data = (void *)&mt8173_compat },
  89         {}
  90  };
  91  MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
  92 @@ -343,9 +368,11 @@ static int mtk_i2c_set_speed(struct mtk_
  93         return 0;
  94  }
  95
  96 -static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
  97 +static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
  98 +                                       int num, int left_num)
  99  {
 100         u16 addr_reg;
 101 +       u16 start_reg;
 102         u16 control_reg;
 103         dma_addr_t rpaddr = 0;
 104         dma_addr_t wpaddr = 0;
 105 @@ -361,6 +388,8 @@ static int mtk_i2c_do_transfer(struct mt
 106                 control_reg |= I2C_CONTROL_RS;
 107         if (i2c->op == I2C_MASTER_WRRD)
 108                 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
 109 +       if (left_num >= 1)
 110 +               control_reg |= I2C_CONTROL_RS;
 111         mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL);
 112
 113         /* set start condition */
 114 @@ -375,13 +404,13 @@ static int mtk_i2c_do_transfer(struct mt
 115         mtk_i2c_writew(addr_reg, i2c, OFFSET_SLAVE_ADDR);
 116
 117         /* Clear interrupt status */
 118 -       mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
 119 -               i2c, OFFSET_INTR_STAT);
 120 +       mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
 121 +                       | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
 122         mtk_i2c_writew(I2C_FIFO_ADDR_CLR, i2c, OFFSET_FIFO_ADDR_CLR);
 123
 124         /* Enable interrupt */
 125 -       mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
 126 -               i2c, OFFSET_INTR_MASK);
 127 +       mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
 128 +                       | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_MASK);
 129
 130         /* Set transfer and transaction len */
 131         if (i2c->op == I2C_MASTER_WRRD) {
 132 @@ -390,7 +419,7 @@ static int mtk_i2c_do_transfer(struct mt
 133                 mtk_i2c_writew(I2C_WRRD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
 134         } else {
 135                 mtk_i2c_writew(msgs->len, i2c, OFFSET_TRANSFER_LEN);
 136 -               mtk_i2c_writew(I2C_RD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
 137 +               mtk_i2c_writew(num, i2c, OFFSET_TRANSAC_LEN);
 138         }
 139
 140         /* Prepare buffer data to start transfer */
 141 @@ -436,13 +465,23 @@ static int mtk_i2c_do_transfer(struct mt
 142         /* flush before sending start */
 143         mb();
 144         mtk_i2c_writel_dma(I2C_DMA_START_EN, i2c, OFFSET_EN);
 145 -       mtk_i2c_writew(I2C_TRANSAC_START, i2c, OFFSET_START);
 146 +
 147 +       if (!i2c->dev_comp->auto_restart) {
 148 +               start_reg = I2C_TRANSAC_START;
 149 +       } else {
 150 +               if (left_num >= 1)
 151 +                       start_reg = I2C_TRANSAC_START | I2C_RS_MUL_CNFG
 152 +                                       | I2C_RS_MUL_TRIG;
 153 +               else
 154 +                       start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
 155 +       }
 156 +       mtk_i2c_writew(start_reg, i2c, OFFSET_START);
 157
 158         ret = wait_for_completion_timeout(&i2c->msg_complete,
 159                                 i2c->adap.timeout);
 160
 161         /* Clear interrupt mask */
 162 -       mtk_i2c_writew(~(I2C_HS_NACKERR | I2C_ACKERR
 163 +       mtk_i2c_writew(~(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
 164                         | I2C_TRANSAC_COMP), i2c, OFFSET_INTR_MASK);
 165
 166         if (i2c->op == I2C_MASTER_WR) {
 167 @@ -472,6 +511,10 @@ static int mtk_i2c_do_transfer(struct mt
 168                 return -EREMOTEIO;
 169         }
 170
 171 +       if (i2c->irq_stat & I2C_RS_TRANSFER)
 172 +               dev_dbg(i2c->dev, "addr: %x, restart transfer interrupt.\n",
 173 +                               msgs->addr);
 174 +
 175         return 0;
 176  }
 177
 178 @@ -486,28 +529,33 @@ static int mtk_i2c_transfer(struct i2c_a
 179         if (ret)
 180                 return ret;
 181
 182 -       if (msgs->buf == NULL) {
 183 -               dev_dbg(i2c->dev, "data buffer is NULL.\n");
 184 -               ret = -EINVAL;
 185 -               goto err_exit;
 186 -       }
 187 -
 188 -       if (msgs->flags & I2C_M_RD)
 189 -               i2c->op = I2C_MASTER_RD;
 190 -       else
 191 -               i2c->op = I2C_MASTER_WR;
 192 +       while (left_num--) {
 193 +               if (msgs->buf == NULL) {
 194 +                       dev_dbg(i2c->dev, "data buffer is NULL.\n");
 195 +                       ret = -EINVAL;
 196 +                       goto err_exit;
 197 +               }
 198
 199 -       if (num > 1) {
 200 -               /* combined two messages into one transaction */
 201 -               i2c->op = I2C_MASTER_WRRD;
 202 -               left_num--;
 203 -       }
 204 +               if (msgs->flags & I2C_M_RD)
 205 +                       i2c->op = I2C_MASTER_RD;
 206 +               else
 207 +                       i2c->op = I2C_MASTER_WR;
 208 +
 209 +               if (!i2c->dev_comp->auto_restart) {
 210 +                       if (num > 1) {
 211 +                               /* combined two messages into one transaction */
 212 +                               i2c->op = I2C_MASTER_WRRD;
 213 +                               left_num--;
 214 +                       }
 215 +               }
 216
 217 -       /* always use DMA mode. */
 218 -       ret = mtk_i2c_do_transfer(i2c, msgs);
 219 -       if (ret < 0)
 220 -               goto err_exit;
 221 +               /* always use DMA mode. */
 222 +               ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
 223 +               if (ret < 0)
 224 +                       goto err_exit;
 225
 226 +               msgs++;
 227 +       }
 228         /* the return value is number of executed messages */
 229         ret = num;
 230
 231 @@ -521,7 +569,7 @@ static irqreturn_t mtk_i2c_irq(int irqno
 232         struct mtk_i2c *i2c = dev_id;
 233
 234         i2c->irq_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
 235 -       mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR
 236 +       mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
 237                         | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
 238
 239         complete(&i2c->msg_complete);