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mediatek: add support for the new MT7623 Arm SoC
[openwrt/svn-archive/archive.git] / target / linux / mediatek / patches / 0059-arm-mediatek-basic-mt6323-pmic-support.patch
1 From 7f157285f2a01921917e0eed79b5d8cf734f5d27 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 24 Jun 2015 15:24:45 +0200
4 Subject: [PATCH 59/76] arm: mediatek: basic mt6323 pmic support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mfd/Kconfig | 10 +
9 drivers/mfd/Makefile | 1 +
10 drivers/mfd/mt6323-core.c | 230 +++++++++++++++++++++
11 drivers/regulator/Kconfig | 9 +
12 drivers/regulator/Makefile | 1 +
13 drivers/regulator/mt6323-regulator.c | 332 +++++++++++++++++++++++++++++++
14 include/linux/mfd/mt6323/core.h | 64 ++++++
15 include/linux/mfd/mt6323/registers.h | 362 ++++++++++++++++++++++++++++++++++
16 8 files changed, 1009 insertions(+)
17 create mode 100644 drivers/mfd/mt6323-core.c
18 create mode 100644 drivers/regulator/mt6323-regulator.c
19 create mode 100644 include/linux/mfd/mt6323/core.h
20 create mode 100644 include/linux/mfd/mt6323/registers.h
21
22 diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
23 index d5ad04d..ff2c14e 100644
24 --- a/drivers/mfd/Kconfig
25 +++ b/drivers/mfd/Kconfig
26 @@ -529,6 +529,16 @@ config MFD_MAX8998
27 additional drivers must be enabled in order to use the functionality
28 of the device.
29
30 +config MFD_MT6323
31 + tristate "MediaTek MT6323 PMIC Support"
32 + select MFD_CORE
33 + select IRQ_DOMAIN
34 + help
35 + Say yes here to add support for MediaTek MT6323 PMIC. This is
36 + a Power Management IC. This driver provides common support for
37 + accessing the device; additional drivers must be enabled in order
38 + to use the functionality of the device.
39 +
40 config MFD_MT6397
41 tristate "MediaTek MT6397 PMIC Support"
42 select MFD_CORE
43 diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
44 index 0e5cfeb..6e91123 100644
45 --- a/drivers/mfd/Makefile
46 +++ b/drivers/mfd/Makefile
47 @@ -184,4 +184,5 @@ obj-$(CONFIG_MFD_SKY81452) += sky81452.o
48
49 intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
50 obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
51 +obj-$(CONFIG_MFD_MT6323) += mt6323-core.o
52 obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
53 diff --git a/drivers/mfd/mt6323-core.c b/drivers/mfd/mt6323-core.c
54 new file mode 100644
55 index 0000000..012c620
56 --- /dev/null
57 +++ b/drivers/mfd/mt6323-core.c
58 @@ -0,0 +1,230 @@
59 +/*
60 + * Copyright (c) 2014 MediaTek Inc.
61 + * Author: Flora Fu, MediaTek
62 + *
63 + * This program is free software; you can redistribute it and/or modify
64 + * it under the terms of the GNU General Public License version 2 as
65 + * published by the Free Software Foundation.
66 + *
67 + * This program is distributed in the hope that it will be useful,
68 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
69 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
70 + * GNU General Public License for more details.
71 + */
72 +
73 +#include <linux/interrupt.h>
74 +#include <linux/module.h>
75 +#include <linux/of_device.h>
76 +#include <linux/of_irq.h>
77 +#include <linux/regmap.h>
78 +#include <linux/mfd/core.h>
79 +#include <linux/mfd/mt6397/core.h>
80 +#include <linux/mfd/mt6397/registers.h>
81 +
82 +static const struct mfd_cell mt6397_devs[] = {
83 + {
84 + .name = "mt6397-rtc",
85 + .of_compatible = "mediatek,mt6397-rtc",
86 + }, {
87 + .name = "mt6397-regulator",
88 + .of_compatible = "mediatek,mt6397-regulator",
89 + }, {
90 + .name = "mt6397-codec",
91 + .of_compatible = "mediatek,mt6397-codec",
92 + }, {
93 + .name = "mt6397-clk",
94 + .of_compatible = "mediatek,mt6397-clk",
95 + }, {
96 + .name = "mediatek-mt6397-pinctrl",
97 + .of_compatible = "mediatek,mt6397-pinctrl",
98 + },
99 +};
100 +
101 +static void mt6397_irq_lock(struct irq_data *data)
102 +{
103 + struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
104 +
105 + mutex_lock(&mt6397->irqlock);
106 +}
107 +
108 +static void mt6397_irq_sync_unlock(struct irq_data *data)
109 +{
110 + struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
111 +
112 + regmap_write(mt6397->regmap, MT6397_INT_CON0, mt6397->irq_masks_cur[0]);
113 + regmap_write(mt6397->regmap, MT6397_INT_CON1, mt6397->irq_masks_cur[1]);
114 +
115 + mutex_unlock(&mt6397->irqlock);
116 +}
117 +
118 +static void mt6397_irq_disable(struct irq_data *data)
119 +{
120 + struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
121 + int shift = data->hwirq & 0xf;
122 + int reg = data->hwirq >> 4;
123 +
124 + mt6397->irq_masks_cur[reg] &= ~BIT(shift);
125 +}
126 +
127 +static void mt6397_irq_enable(struct irq_data *data)
128 +{
129 + struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
130 + int shift = data->hwirq & 0xf;
131 + int reg = data->hwirq >> 4;
132 +
133 + mt6397->irq_masks_cur[reg] |= BIT(shift);
134 +}
135 +
136 +static struct irq_chip mt6397_irq_chip = {
137 + .name = "mt6397-irq",
138 + .irq_bus_lock = mt6397_irq_lock,
139 + .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
140 + .irq_enable = mt6397_irq_enable,
141 + .irq_disable = mt6397_irq_disable,
142 +};
143 +
144 +static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
145 + int irqbase)
146 +{
147 + unsigned int status;
148 + int i, irq, ret;
149 +
150 + ret = regmap_read(mt6397->regmap, reg, &status);
151 + if (ret) {
152 + dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
153 + return;
154 + }
155 +
156 + for (i = 0; i < 16; i++) {
157 + if (status & BIT(i)) {
158 + irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
159 + if (irq)
160 + handle_nested_irq(irq);
161 + }
162 + }
163 +
164 + regmap_write(mt6397->regmap, reg, status);
165 +}
166 +
167 +static irqreturn_t mt6397_irq_thread(int irq, void *data)
168 +{
169 + struct mt6397_chip *mt6397 = data;
170 +
171 + mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS0, 0);
172 + mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS1, 16);
173 +
174 + return IRQ_HANDLED;
175 +}
176 +
177 +static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
178 + irq_hw_number_t hw)
179 +{
180 + struct mt6397_chip *mt6397 = d->host_data;
181 +
182 + irq_set_chip_data(irq, mt6397);
183 + irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
184 + irq_set_nested_thread(irq, 1);
185 +#ifdef CONFIG_ARM
186 + set_irq_flags(irq, IRQF_VALID);
187 +#else
188 + irq_set_noprobe(irq);
189 +#endif
190 +
191 + return 0;
192 +}
193 +
194 +static struct irq_domain_ops mt6397_irq_domain_ops = {
195 + .map = mt6397_irq_domain_map,
196 +};
197 +
198 +static int mt6397_irq_init(struct mt6397_chip *mt6397)
199 +{
200 + int ret;
201 +
202 + mutex_init(&mt6397->irqlock);
203 +
204 + /* Mask all interrupt sources */
205 + regmap_write(mt6397->regmap, MT6397_INT_CON0, 0x0);
206 + regmap_write(mt6397->regmap, MT6397_INT_CON1, 0x0);
207 +
208 + mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
209 + MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
210 + if (!mt6397->irq_domain) {
211 + dev_err(mt6397->dev, "could not create irq domain\n");
212 + return -ENOMEM;
213 + }
214 +
215 + ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
216 + mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
217 + if (ret) {
218 + dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
219 + mt6397->irq, ret);
220 + return ret;
221 + }
222 +
223 + return 0;
224 +}
225 +
226 +static int mt6397_probe(struct platform_device *pdev)
227 +{
228 + int ret;
229 + struct mt6397_chip *mt6397;
230 +
231 + mt6397 = devm_kzalloc(&pdev->dev, sizeof(*mt6397), GFP_KERNEL);
232 + if (!mt6397)
233 + return -ENOMEM;
234 +
235 + mt6397->dev = &pdev->dev;
236 + /*
237 + * mt6397 MFD is child device of soc pmic wrapper.
238 + * Regmap is set from its parent.
239 + */
240 + mt6397->regmap = dev_get_regmap(pdev->dev.parent, NULL);
241 + if (!mt6397->regmap)
242 + return -ENODEV;
243 +
244 + platform_set_drvdata(pdev, mt6397);
245 +
246 + mt6397->irq = platform_get_irq(pdev, 0);
247 + if (mt6397->irq > 0) {
248 + ret = mt6397_irq_init(mt6397);
249 + if (ret)
250 + return ret;
251 + }
252 +
253 + ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
254 + ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
255 + if (ret)
256 + dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
257 +
258 + return ret;
259 +}
260 +
261 +static int mt6397_remove(struct platform_device *pdev)
262 +{
263 + mfd_remove_devices(&pdev->dev);
264 +
265 + return 0;
266 +}
267 +
268 +static const struct of_device_id mt6397_of_match[] = {
269 + { .compatible = "mediatek,mt6397" },
270 + { }
271 +};
272 +MODULE_DEVICE_TABLE(of, mt6397_of_match);
273 +
274 +static struct platform_driver mt6397_driver = {
275 + .probe = mt6397_probe,
276 + .remove = mt6397_remove,
277 + .driver = {
278 + .name = "mt6397",
279 + .of_match_table = of_match_ptr(mt6397_of_match),
280 + },
281 +};
282 +
283 +module_platform_driver(mt6397_driver);
284 +
285 +MODULE_AUTHOR("Flora Fu, MediaTek");
286 +MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
287 +MODULE_LICENSE("GPL");
288 +MODULE_ALIAS("platform:mt6397");
289 diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
290 index a6f116a..336d4c6 100644
291 --- a/drivers/regulator/Kconfig
292 +++ b/drivers/regulator/Kconfig
293 @@ -441,6 +441,15 @@ config REGULATOR_MC13892
294 Say y here to support the regulators found on the Freescale MC13892
295 PMIC.
296
297 +config REGULATOR_MT6323
298 + tristate "MediaTek MT6323 PMIC"
299 + depends on MFD_MT6323
300 + help
301 + Say y here to select this option to enable the power regulator of
302 + MediaTek MT6323 PMIC.
303 + This driver supports the control of different power rails of device
304 + through regulator interface.
305 +
306 config REGULATOR_MT6397
307 tristate "MediaTek MT6397 PMIC"
308 depends on MFD_MT6397
309 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
310 index 2c4da15..ac6a9da 100644
311 --- a/drivers/regulator/Makefile
312 +++ b/drivers/regulator/Makefile
313 @@ -59,6 +59,7 @@ obj-$(CONFIG_REGULATOR_MAX77843) += max77843.o
314 obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
315 obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
316 obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
317 +obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o
318 obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o
319 obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
320 obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o
321 diff --git a/drivers/regulator/mt6323-regulator.c b/drivers/regulator/mt6323-regulator.c
322 new file mode 100644
323 index 0000000..a5b2f47
324 --- /dev/null
325 +++ b/drivers/regulator/mt6323-regulator.c
326 @@ -0,0 +1,332 @@
327 +/*
328 + * Copyright (c) 2014 MediaTek Inc.
329 + * Author: Flora Fu <flora.fu@mediatek.com>
330 + *
331 + * This program is free software; you can redistribute it and/or modify
332 + * it under the terms of the GNU General Public License version 2 as
333 + * published by the Free Software Foundation.
334 + *
335 + * This program is distributed in the hope that it will be useful,
336 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
337 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
338 + * GNU General Public License for more details.
339 + */
340 +
341 +#include <linux/module.h>
342 +#include <linux/of.h>
343 +#include <linux/platform_device.h>
344 +#include <linux/regmap.h>
345 +#include <linux/mfd/mt6397/core.h>
346 +#include <linux/mfd/mt6397/registers.h>
347 +#include <linux/regulator/driver.h>
348 +#include <linux/regulator/machine.h>
349 +#include <linux/regulator/mt6397-regulator.h>
350 +#include <linux/regulator/of_regulator.h>
351 +
352 +/*
353 + * MT6397 regulators' information
354 + *
355 + * @desc: standard fields of regulator description.
356 + * @qi: Mask for query enable signal status of regulators
357 + * @vselon_reg: Register sections for hardware control mode of bucks
358 + * @vselctrl_reg: Register for controlling the buck control mode.
359 + * @vselctrl_mask: Mask for query buck's voltage control mode.
360 + */
361 +struct mt6397_regulator_info {
362 + struct regulator_desc desc;
363 + u32 qi;
364 + u32 vselon_reg;
365 + u32 vselctrl_reg;
366 + u32 vselctrl_mask;
367 +};
368 +
369 +#define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
370 + vosel, vosel_mask, voselon, vosel_ctrl) \
371 +[MT6397_ID_##vreg] = { \
372 + .desc = { \
373 + .name = #vreg, \
374 + .of_match = of_match_ptr(match), \
375 + .ops = &mt6397_volt_range_ops, \
376 + .type = REGULATOR_VOLTAGE, \
377 + .id = MT6397_ID_##vreg, \
378 + .owner = THIS_MODULE, \
379 + .n_voltages = (max - min)/step + 1, \
380 + .linear_ranges = volt_ranges, \
381 + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
382 + .vsel_reg = vosel, \
383 + .vsel_mask = vosel_mask, \
384 + .enable_reg = enreg, \
385 + .enable_mask = BIT(0), \
386 + }, \
387 + .qi = BIT(13), \
388 + .vselon_reg = voselon, \
389 + .vselctrl_reg = vosel_ctrl, \
390 + .vselctrl_mask = BIT(1), \
391 +}
392 +
393 +#define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
394 + vosel_mask) \
395 +[MT6397_ID_##vreg] = { \
396 + .desc = { \
397 + .name = #vreg, \
398 + .of_match = of_match_ptr(match), \
399 + .ops = &mt6397_volt_table_ops, \
400 + .type = REGULATOR_VOLTAGE, \
401 + .id = MT6397_ID_##vreg, \
402 + .owner = THIS_MODULE, \
403 + .n_voltages = ARRAY_SIZE(ldo_volt_table), \
404 + .volt_table = ldo_volt_table, \
405 + .vsel_reg = vosel, \
406 + .vsel_mask = vosel_mask, \
407 + .enable_reg = enreg, \
408 + .enable_mask = BIT(enbit), \
409 + }, \
410 + .qi = BIT(15), \
411 +}
412 +
413 +#define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \
414 +[MT6397_ID_##vreg] = { \
415 + .desc = { \
416 + .name = #vreg, \
417 + .of_match = of_match_ptr(match), \
418 + .ops = &mt6397_volt_fixed_ops, \
419 + .type = REGULATOR_VOLTAGE, \
420 + .id = MT6397_ID_##vreg, \
421 + .owner = THIS_MODULE, \
422 + .n_voltages = 1, \
423 + .enable_reg = enreg, \
424 + .enable_mask = BIT(enbit), \
425 + .min_uV = volt, \
426 + }, \
427 + .qi = BIT(15), \
428 +}
429 +
430 +static const struct regulator_linear_range buck_volt_range1[] = {
431 + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),
432 +};
433 +
434 +static const struct regulator_linear_range buck_volt_range2[] = {
435 + REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250),
436 +};
437 +
438 +static const struct regulator_linear_range buck_volt_range3[] = {
439 + REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000),
440 +};
441 +
442 +static const u32 ldo_volt_table1[] = {
443 + 1500000, 1800000, 2500000, 2800000,
444 +};
445 +
446 +static const u32 ldo_volt_table2[] = {
447 + 1800000, 3300000,
448 +};
449 +
450 +static const u32 ldo_volt_table3[] = {
451 + 3000000, 3300000,
452 +};
453 +
454 +static const u32 ldo_volt_table4[] = {
455 + 1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
456 +};
457 +
458 +static const u32 ldo_volt_table5[] = {
459 + 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
460 +};
461 +
462 +static const u32 ldo_volt_table5_v2[] = {
463 + 1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
464 +};
465 +
466 +static const u32 ldo_volt_table6[] = {
467 + 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000,
468 +};
469 +
470 +static const u32 ldo_volt_table7[] = {
471 + 1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000,
472 +};
473 +
474 +static int mt6397_get_status(struct regulator_dev *rdev)
475 +{
476 + int ret;
477 + u32 regval;
478 + struct mt6397_regulator_info *info = rdev_get_drvdata(rdev);
479 +
480 + ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval);
481 + if (ret != 0) {
482 + dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
483 + return ret;
484 + }
485 +
486 + return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
487 +}
488 +
489 +static struct regulator_ops mt6397_volt_range_ops = {
490 + .list_voltage = regulator_list_voltage_linear_range,
491 + .map_voltage = regulator_map_voltage_linear_range,
492 + .set_voltage_sel = regulator_set_voltage_sel_regmap,
493 + .get_voltage_sel = regulator_get_voltage_sel_regmap,
494 + .set_voltage_time_sel = regulator_set_voltage_time_sel,
495 + .enable = regulator_enable_regmap,
496 + .disable = regulator_disable_regmap,
497 + .is_enabled = regulator_is_enabled_regmap,
498 + .get_status = mt6397_get_status,
499 +};
500 +
501 +static struct regulator_ops mt6397_volt_table_ops = {
502 + .list_voltage = regulator_list_voltage_table,
503 + .map_voltage = regulator_map_voltage_iterate,
504 + .set_voltage_sel = regulator_set_voltage_sel_regmap,
505 + .get_voltage_sel = regulator_get_voltage_sel_regmap,
506 + .set_voltage_time_sel = regulator_set_voltage_time_sel,
507 + .enable = regulator_enable_regmap,
508 + .disable = regulator_disable_regmap,
509 + .is_enabled = regulator_is_enabled_regmap,
510 + .get_status = mt6397_get_status,
511 +};
512 +
513 +static struct regulator_ops mt6397_volt_fixed_ops = {
514 + .list_voltage = regulator_list_voltage_linear,
515 + .enable = regulator_enable_regmap,
516 + .disable = regulator_disable_regmap,
517 + .is_enabled = regulator_is_enabled_regmap,
518 + .get_status = mt6397_get_status,
519 +};
520 +
521 +/* The array is indexed by id(MT6397_ID_XXX) */
522 +static struct mt6397_regulator_info mt6397_regulators[] = {
523 + MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250,
524 + buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f,
525 + MT6397_VCA15_CON10, MT6397_VCA15_CON5),
526 + MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250,
527 + buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f,
528 + MT6397_VPCA7_CON10, MT6397_VPCA7_CON5),
529 + MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250,
530 + buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9,
531 + 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5),
532 + MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250,
533 + buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9,
534 + 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5),
535 + MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250,
536 + buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f,
537 + MT6397_VCORE_CON10, MT6397_VCORE_CON5),
538 + MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1,
539 + MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f,
540 + MT6397_VGPU_CON10, MT6397_VGPU_CON5),
541 + MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2,
542 + MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f,
543 + MT6397_VDRM_CON10, MT6397_VDRM_CON5),
544 + MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000,
545 + buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f,
546 + MT6397_VIO18_CON10, MT6397_VIO18_CON5),
547 + MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000),
548 + MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000),
549 + MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1,
550 + MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0),
551 + MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000),
552 + MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000),
553 + MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2,
554 + MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10),
555 + MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3,
556 + MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80),
557 + MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3,
558 + MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10),
559 + MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4,
560 + MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0),
561 + MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5,
562 + MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0),
563 + MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5,
564 + MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0),
565 + MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5,
566 + MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0),
567 + MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6,
568 + MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0),
569 + MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5,
570 + MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0),
571 + MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7,
572 + MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00),
573 +};
574 +
575 +static int mt6397_set_buck_vosel_reg(struct platform_device *pdev)
576 +{
577 + struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
578 + int i;
579 + u32 regval;
580 +
581 + for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
582 + if (mt6397_regulators[i].vselctrl_reg) {
583 + if (regmap_read(mt6397->regmap,
584 + mt6397_regulators[i].vselctrl_reg,
585 + &regval) < 0) {
586 + dev_err(&pdev->dev,
587 + "Failed to read buck ctrl\n");
588 + return -EIO;
589 + }
590 +
591 + if (regval & mt6397_regulators[i].vselctrl_mask) {
592 + mt6397_regulators[i].desc.vsel_reg =
593 + mt6397_regulators[i].vselon_reg;
594 + }
595 + }
596 + }
597 +
598 + return 0;
599 +}
600 +
601 +static int mt6397_regulator_probe(struct platform_device *pdev)
602 +{
603 + struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
604 + struct regulator_config config = {};
605 + struct regulator_dev *rdev;
606 + int i;
607 + u32 reg_value, version;
608 +
609 + /* Query buck controller to select activated voltage register part */
610 + if (mt6397_set_buck_vosel_reg(pdev))
611 + return -EIO;
612 +
613 + /* Read PMIC chip revision to update constraints and voltage table */
614 + if (regmap_read(mt6397->regmap, MT6397_CID, &reg_value) < 0) {
615 + dev_err(&pdev->dev, "Failed to read Chip ID\n");
616 + return -EIO;
617 + }
618 + dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
619 +
620 + version = (reg_value & 0xFF);
621 + switch (version) {
622 + case MT6397_REGULATOR_ID91:
623 + mt6397_regulators[MT6397_ID_VGP2].desc.volt_table =
624 + ldo_volt_table5_v2;
625 + break;
626 + default:
627 + break;
628 + }
629 +
630 + for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
631 + config.dev = &pdev->dev;
632 + config.driver_data = &mt6397_regulators[i];
633 + config.regmap = mt6397->regmap;
634 + rdev = devm_regulator_register(&pdev->dev,
635 + &mt6397_regulators[i].desc, &config);
636 + if (IS_ERR(rdev)) {
637 + dev_err(&pdev->dev, "failed to register %s\n",
638 + mt6397_regulators[i].desc.name);
639 + return PTR_ERR(rdev);
640 + }
641 + }
642 +
643 + return 0;
644 +}
645 +
646 +static struct platform_driver mt6397_regulator_driver = {
647 + .driver = {
648 + .name = "mt6397-regulator",
649 + },
650 + .probe = mt6397_regulator_probe,
651 +};
652 +
653 +module_platform_driver(mt6397_regulator_driver);
654 +
655 +MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>");
656 +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC");
657 +MODULE_LICENSE("GPL");
658 +MODULE_ALIAS("platform:mt6397-regulator");
659 diff --git a/include/linux/mfd/mt6323/core.h b/include/linux/mfd/mt6323/core.h
660 new file mode 100644
661 index 0000000..cf5265b
662 --- /dev/null
663 +++ b/include/linux/mfd/mt6323/core.h
664 @@ -0,0 +1,64 @@
665 +/*
666 + * Copyright (c) 2014 MediaTek Inc.
667 + * Author: Flora Fu, MediaTek
668 + *
669 + * This program is free software; you can redistribute it and/or modify
670 + * it under the terms of the GNU General Public License version 2 as
671 + * published by the Free Software Foundation.
672 + *
673 + * This program is distributed in the hope that it will be useful,
674 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
675 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
676 + * GNU General Public License for more details.
677 + */
678 +
679 +#ifndef __MFD_MT6397_CORE_H__
680 +#define __MFD_MT6397_CORE_H__
681 +
682 +enum mt6397_irq_numbers {
683 + MT6397_IRQ_SPKL_AB = 0,
684 + MT6397_IRQ_SPKR_AB,
685 + MT6397_IRQ_SPKL,
686 + MT6397_IRQ_SPKR,
687 + MT6397_IRQ_BAT_L,
688 + MT6397_IRQ_BAT_H,
689 + MT6397_IRQ_FG_BAT_L,
690 + MT6397_IRQ_FG_BAT_H,
691 + MT6397_IRQ_WATCHDOG,
692 + MT6397_IRQ_PWRKEY,
693 + MT6397_IRQ_THR_L,
694 + MT6397_IRQ_THR_H,
695 + MT6397_IRQ_VBATON_UNDET,
696 + MT6397_IRQ_BVALID_DET,
697 + MT6397_IRQ_CHRDET,
698 + MT6397_IRQ_OV,
699 + MT6397_IRQ_LDO,
700 + MT6397_IRQ_HOMEKEY,
701 + MT6397_IRQ_ACCDET,
702 + MT6397_IRQ_AUDIO,
703 + MT6397_IRQ_RTC,
704 + MT6397_IRQ_PWRKEY_RSTB,
705 + MT6397_IRQ_HDMI_SIFM,
706 + MT6397_IRQ_HDMI_CEC,
707 + MT6397_IRQ_VCA15,
708 + MT6397_IRQ_VSRMCA15,
709 + MT6397_IRQ_VCORE,
710 + MT6397_IRQ_VGPU,
711 + MT6397_IRQ_VIO18,
712 + MT6397_IRQ_VPCA7,
713 + MT6397_IRQ_VSRMCA7,
714 + MT6397_IRQ_VDRM,
715 + MT6397_IRQ_NR,
716 +};
717 +
718 +struct mt6397_chip {
719 + struct device *dev;
720 + struct regmap *regmap;
721 + int irq;
722 + struct irq_domain *irq_domain;
723 + struct mutex irqlock;
724 + u16 irq_masks_cur[2];
725 + u16 irq_masks_cache[2];
726 +};
727 +
728 +#endif /* __MFD_MT6397_CORE_H__ */
729 diff --git a/include/linux/mfd/mt6323/registers.h b/include/linux/mfd/mt6323/registers.h
730 new file mode 100644
731 index 0000000..f23a0a6
732 --- /dev/null
733 +++ b/include/linux/mfd/mt6323/registers.h
734 @@ -0,0 +1,362 @@
735 +/*
736 + * Copyright (c) 2014 MediaTek Inc.
737 + * Author: Flora Fu, MediaTek
738 + *
739 + * This program is free software; you can redistribute it and/or modify
740 + * it under the terms of the GNU General Public License version 2 as
741 + * published by the Free Software Foundation.
742 + *
743 + * This program is distributed in the hope that it will be useful,
744 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
745 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
746 + * GNU General Public License for more details.
747 + */
748 +
749 +#ifndef __MFD_MT6397_REGISTERS_H__
750 +#define __MFD_MT6397_REGISTERS_H__
751 +
752 +/* PMIC Registers */
753 +#define MT6397_CID 0x0100
754 +#define MT6397_TOP_CKPDN 0x0102
755 +#define MT6397_TOP_CKPDN_SET 0x0104
756 +#define MT6397_TOP_CKPDN_CLR 0x0106
757 +#define MT6397_TOP_CKPDN2 0x0108
758 +#define MT6397_TOP_CKPDN2_SET 0x010A
759 +#define MT6397_TOP_CKPDN2_CLR 0x010C
760 +#define MT6397_TOP_GPIO_CKPDN 0x010E
761 +#define MT6397_TOP_RST_CON 0x0114
762 +#define MT6397_WRP_CKPDN 0x011A
763 +#define MT6397_WRP_RST_CON 0x0120
764 +#define MT6397_TOP_RST_MISC 0x0126
765 +#define MT6397_TOP_CKCON1 0x0128
766 +#define MT6397_TOP_CKCON2 0x012A
767 +#define MT6397_TOP_CKTST1 0x012C
768 +#define MT6397_TOP_CKTST2 0x012E
769 +#define MT6397_OC_DEG_EN 0x0130
770 +#define MT6397_OC_CTL0 0x0132
771 +#define MT6397_OC_CTL1 0x0134
772 +#define MT6397_OC_CTL2 0x0136
773 +#define MT6397_INT_RSV 0x0138
774 +#define MT6397_TEST_CON0 0x013A
775 +#define MT6397_TEST_CON1 0x013C
776 +#define MT6397_STATUS0 0x013E
777 +#define MT6397_STATUS1 0x0140
778 +#define MT6397_PGSTATUS 0x0142
779 +#define MT6397_CHRSTATUS 0x0144
780 +#define MT6397_OCSTATUS0 0x0146
781 +#define MT6397_OCSTATUS1 0x0148
782 +#define MT6397_OCSTATUS2 0x014A
783 +#define MT6397_HDMI_PAD_IE 0x014C
784 +#define MT6397_TEST_OUT_L 0x014E
785 +#define MT6397_TEST_OUT_H 0x0150
786 +#define MT6397_TDSEL_CON 0x0152
787 +#define MT6397_RDSEL_CON 0x0154
788 +#define MT6397_GPIO_SMT_CON0 0x0156
789 +#define MT6397_GPIO_SMT_CON1 0x0158
790 +#define MT6397_GPIO_SMT_CON2 0x015A
791 +#define MT6397_GPIO_SMT_CON3 0x015C
792 +#define MT6397_DRV_CON0 0x015E
793 +#define MT6397_DRV_CON1 0x0160
794 +#define MT6397_DRV_CON2 0x0162
795 +#define MT6397_DRV_CON3 0x0164
796 +#define MT6397_DRV_CON4 0x0166
797 +#define MT6397_DRV_CON5 0x0168
798 +#define MT6397_DRV_CON6 0x016A
799 +#define MT6397_DRV_CON7 0x016C
800 +#define MT6397_DRV_CON8 0x016E
801 +#define MT6397_DRV_CON9 0x0170
802 +#define MT6397_DRV_CON10 0x0172
803 +#define MT6397_DRV_CON11 0x0174
804 +#define MT6397_DRV_CON12 0x0176
805 +#define MT6397_INT_CON0 0x0178
806 +#define MT6397_INT_CON1 0x017E
807 +#define MT6397_INT_STATUS0 0x0184
808 +#define MT6397_INT_STATUS1 0x0186
809 +#define MT6397_FQMTR_CON0 0x0188
810 +#define MT6397_FQMTR_CON1 0x018A
811 +#define MT6397_FQMTR_CON2 0x018C
812 +#define MT6397_EFUSE_DOUT_0_15 0x01C4
813 +#define MT6397_EFUSE_DOUT_16_31 0x01C6
814 +#define MT6397_EFUSE_DOUT_32_47 0x01C8
815 +#define MT6397_EFUSE_DOUT_48_63 0x01CA
816 +#define MT6397_SPI_CON 0x01CC
817 +#define MT6397_TOP_CKPDN3 0x01CE
818 +#define MT6397_TOP_CKCON3 0x01D4
819 +#define MT6397_EFUSE_DOUT_64_79 0x01D6
820 +#define MT6397_EFUSE_DOUT_80_95 0x01D8
821 +#define MT6397_EFUSE_DOUT_96_111 0x01DA
822 +#define MT6397_EFUSE_DOUT_112_127 0x01DC
823 +#define MT6397_EFUSE_DOUT_128_143 0x01DE
824 +#define MT6397_EFUSE_DOUT_144_159 0x01E0
825 +#define MT6397_EFUSE_DOUT_160_175 0x01E2
826 +#define MT6397_EFUSE_DOUT_176_191 0x01E4
827 +#define MT6397_EFUSE_DOUT_192_207 0x01E6
828 +#define MT6397_EFUSE_DOUT_208_223 0x01E8
829 +#define MT6397_EFUSE_DOUT_224_239 0x01EA
830 +#define MT6397_EFUSE_DOUT_240_255 0x01EC
831 +#define MT6397_EFUSE_DOUT_256_271 0x01EE
832 +#define MT6397_EFUSE_DOUT_272_287 0x01F0
833 +#define MT6397_EFUSE_DOUT_288_300 0x01F2
834 +#define MT6397_EFUSE_DOUT_304_319 0x01F4
835 +#define MT6397_BUCK_CON0 0x0200
836 +#define MT6397_BUCK_CON1 0x0202
837 +#define MT6397_BUCK_CON2 0x0204
838 +#define MT6397_BUCK_CON3 0x0206
839 +#define MT6397_BUCK_CON4 0x0208
840 +#define MT6397_BUCK_CON5 0x020A
841 +#define MT6397_BUCK_CON6 0x020C
842 +#define MT6397_BUCK_CON7 0x020E
843 +#define MT6397_BUCK_CON8 0x0210
844 +#define MT6397_BUCK_CON9 0x0212
845 +#define MT6397_VCA15_CON0 0x0214
846 +#define MT6397_VCA15_CON1 0x0216
847 +#define MT6397_VCA15_CON2 0x0218
848 +#define MT6397_VCA15_CON3 0x021A
849 +#define MT6397_VCA15_CON4 0x021C
850 +#define MT6397_VCA15_CON5 0x021E
851 +#define MT6397_VCA15_CON6 0x0220
852 +#define MT6397_VCA15_CON7 0x0222
853 +#define MT6397_VCA15_CON8 0x0224
854 +#define MT6397_VCA15_CON9 0x0226
855 +#define MT6397_VCA15_CON10 0x0228
856 +#define MT6397_VCA15_CON11 0x022A
857 +#define MT6397_VCA15_CON12 0x022C
858 +#define MT6397_VCA15_CON13 0x022E
859 +#define MT6397_VCA15_CON14 0x0230
860 +#define MT6397_VCA15_CON15 0x0232
861 +#define MT6397_VCA15_CON16 0x0234
862 +#define MT6397_VCA15_CON17 0x0236
863 +#define MT6397_VCA15_CON18 0x0238
864 +#define MT6397_VSRMCA15_CON0 0x023A
865 +#define MT6397_VSRMCA15_CON1 0x023C
866 +#define MT6397_VSRMCA15_CON2 0x023E
867 +#define MT6397_VSRMCA15_CON3 0x0240
868 +#define MT6397_VSRMCA15_CON4 0x0242
869 +#define MT6397_VSRMCA15_CON5 0x0244
870 +#define MT6397_VSRMCA15_CON6 0x0246
871 +#define MT6397_VSRMCA15_CON7 0x0248
872 +#define MT6397_VSRMCA15_CON8 0x024A
873 +#define MT6397_VSRMCA15_CON9 0x024C
874 +#define MT6397_VSRMCA15_CON10 0x024E
875 +#define MT6397_VSRMCA15_CON11 0x0250
876 +#define MT6397_VSRMCA15_CON12 0x0252
877 +#define MT6397_VSRMCA15_CON13 0x0254
878 +#define MT6397_VSRMCA15_CON14 0x0256
879 +#define MT6397_VSRMCA15_CON15 0x0258
880 +#define MT6397_VSRMCA15_CON16 0x025A
881 +#define MT6397_VSRMCA15_CON17 0x025C
882 +#define MT6397_VSRMCA15_CON18 0x025E
883 +#define MT6397_VSRMCA15_CON19 0x0260
884 +#define MT6397_VSRMCA15_CON20 0x0262
885 +#define MT6397_VSRMCA15_CON21 0x0264
886 +#define MT6397_VCORE_CON0 0x0266
887 +#define MT6397_VCORE_CON1 0x0268
888 +#define MT6397_VCORE_CON2 0x026A
889 +#define MT6397_VCORE_CON3 0x026C
890 +#define MT6397_VCORE_CON4 0x026E
891 +#define MT6397_VCORE_CON5 0x0270
892 +#define MT6397_VCORE_CON6 0x0272
893 +#define MT6397_VCORE_CON7 0x0274
894 +#define MT6397_VCORE_CON8 0x0276
895 +#define MT6397_VCORE_CON9 0x0278
896 +#define MT6397_VCORE_CON10 0x027A
897 +#define MT6397_VCORE_CON11 0x027C
898 +#define MT6397_VCORE_CON12 0x027E
899 +#define MT6397_VCORE_CON13 0x0280
900 +#define MT6397_VCORE_CON14 0x0282
901 +#define MT6397_VCORE_CON15 0x0284
902 +#define MT6397_VCORE_CON16 0x0286
903 +#define MT6397_VCORE_CON17 0x0288
904 +#define MT6397_VCORE_CON18 0x028A
905 +#define MT6397_VGPU_CON0 0x028C
906 +#define MT6397_VGPU_CON1 0x028E
907 +#define MT6397_VGPU_CON2 0x0290
908 +#define MT6397_VGPU_CON3 0x0292
909 +#define MT6397_VGPU_CON4 0x0294
910 +#define MT6397_VGPU_CON5 0x0296
911 +#define MT6397_VGPU_CON6 0x0298
912 +#define MT6397_VGPU_CON7 0x029A
913 +#define MT6397_VGPU_CON8 0x029C
914 +#define MT6397_VGPU_CON9 0x029E
915 +#define MT6397_VGPU_CON10 0x02A0
916 +#define MT6397_VGPU_CON11 0x02A2
917 +#define MT6397_VGPU_CON12 0x02A4
918 +#define MT6397_VGPU_CON13 0x02A6
919 +#define MT6397_VGPU_CON14 0x02A8
920 +#define MT6397_VGPU_CON15 0x02AA
921 +#define MT6397_VGPU_CON16 0x02AC
922 +#define MT6397_VGPU_CON17 0x02AE
923 +#define MT6397_VGPU_CON18 0x02B0
924 +#define MT6397_VIO18_CON0 0x0300
925 +#define MT6397_VIO18_CON1 0x0302
926 +#define MT6397_VIO18_CON2 0x0304
927 +#define MT6397_VIO18_CON3 0x0306
928 +#define MT6397_VIO18_CON4 0x0308
929 +#define MT6397_VIO18_CON5 0x030A
930 +#define MT6397_VIO18_CON6 0x030C
931 +#define MT6397_VIO18_CON7 0x030E
932 +#define MT6397_VIO18_CON8 0x0310
933 +#define MT6397_VIO18_CON9 0x0312
934 +#define MT6397_VIO18_CON10 0x0314
935 +#define MT6397_VIO18_CON11 0x0316
936 +#define MT6397_VIO18_CON12 0x0318
937 +#define MT6397_VIO18_CON13 0x031A
938 +#define MT6397_VIO18_CON14 0x031C
939 +#define MT6397_VIO18_CON15 0x031E
940 +#define MT6397_VIO18_CON16 0x0320
941 +#define MT6397_VIO18_CON17 0x0322
942 +#define MT6397_VIO18_CON18 0x0324
943 +#define MT6397_VPCA7_CON0 0x0326
944 +#define MT6397_VPCA7_CON1 0x0328
945 +#define MT6397_VPCA7_CON2 0x032A
946 +#define MT6397_VPCA7_CON3 0x032C
947 +#define MT6397_VPCA7_CON4 0x032E
948 +#define MT6397_VPCA7_CON5 0x0330
949 +#define MT6397_VPCA7_CON6 0x0332
950 +#define MT6397_VPCA7_CON7 0x0334
951 +#define MT6397_VPCA7_CON8 0x0336
952 +#define MT6397_VPCA7_CON9 0x0338
953 +#define MT6397_VPCA7_CON10 0x033A
954 +#define MT6397_VPCA7_CON11 0x033C
955 +#define MT6397_VPCA7_CON12 0x033E
956 +#define MT6397_VPCA7_CON13 0x0340
957 +#define MT6397_VPCA7_CON14 0x0342
958 +#define MT6397_VPCA7_CON15 0x0344
959 +#define MT6397_VPCA7_CON16 0x0346
960 +#define MT6397_VPCA7_CON17 0x0348
961 +#define MT6397_VPCA7_CON18 0x034A
962 +#define MT6397_VSRMCA7_CON0 0x034C
963 +#define MT6397_VSRMCA7_CON1 0x034E
964 +#define MT6397_VSRMCA7_CON2 0x0350
965 +#define MT6397_VSRMCA7_CON3 0x0352
966 +#define MT6397_VSRMCA7_CON4 0x0354
967 +#define MT6397_VSRMCA7_CON5 0x0356
968 +#define MT6397_VSRMCA7_CON6 0x0358
969 +#define MT6397_VSRMCA7_CON7 0x035A
970 +#define MT6397_VSRMCA7_CON8 0x035C
971 +#define MT6397_VSRMCA7_CON9 0x035E
972 +#define MT6397_VSRMCA7_CON10 0x0360
973 +#define MT6397_VSRMCA7_CON11 0x0362
974 +#define MT6397_VSRMCA7_CON12 0x0364
975 +#define MT6397_VSRMCA7_CON13 0x0366
976 +#define MT6397_VSRMCA7_CON14 0x0368
977 +#define MT6397_VSRMCA7_CON15 0x036A
978 +#define MT6397_VSRMCA7_CON16 0x036C
979 +#define MT6397_VSRMCA7_CON17 0x036E
980 +#define MT6397_VSRMCA7_CON18 0x0370
981 +#define MT6397_VSRMCA7_CON19 0x0372
982 +#define MT6397_VSRMCA7_CON20 0x0374
983 +#define MT6397_VSRMCA7_CON21 0x0376
984 +#define MT6397_VDRM_CON0 0x0378
985 +#define MT6397_VDRM_CON1 0x037A
986 +#define MT6397_VDRM_CON2 0x037C
987 +#define MT6397_VDRM_CON3 0x037E
988 +#define MT6397_VDRM_CON4 0x0380
989 +#define MT6397_VDRM_CON5 0x0382
990 +#define MT6397_VDRM_CON6 0x0384
991 +#define MT6397_VDRM_CON7 0x0386
992 +#define MT6397_VDRM_CON8 0x0388
993 +#define MT6397_VDRM_CON9 0x038A
994 +#define MT6397_VDRM_CON10 0x038C
995 +#define MT6397_VDRM_CON11 0x038E
996 +#define MT6397_VDRM_CON12 0x0390
997 +#define MT6397_VDRM_CON13 0x0392
998 +#define MT6397_VDRM_CON14 0x0394
999 +#define MT6397_VDRM_CON15 0x0396
1000 +#define MT6397_VDRM_CON16 0x0398
1001 +#define MT6397_VDRM_CON17 0x039A
1002 +#define MT6397_VDRM_CON18 0x039C
1003 +#define MT6397_BUCK_K_CON0 0x039E
1004 +#define MT6397_BUCK_K_CON1 0x03A0
1005 +#define MT6397_ANALDO_CON0 0x0400
1006 +#define MT6397_ANALDO_CON1 0x0402
1007 +#define MT6397_ANALDO_CON2 0x0404
1008 +#define MT6397_ANALDO_CON3 0x0406
1009 +#define MT6397_ANALDO_CON4 0x0408
1010 +#define MT6397_ANALDO_CON5 0x040A
1011 +#define MT6397_ANALDO_CON6 0x040C
1012 +#define MT6397_ANALDO_CON7 0x040E
1013 +#define MT6397_DIGLDO_CON0 0x0410
1014 +#define MT6397_DIGLDO_CON1 0x0412
1015 +#define MT6397_DIGLDO_CON2 0x0414
1016 +#define MT6397_DIGLDO_CON3 0x0416
1017 +#define MT6397_DIGLDO_CON4 0x0418
1018 +#define MT6397_DIGLDO_CON5 0x041A
1019 +#define MT6397_DIGLDO_CON6 0x041C
1020 +#define MT6397_DIGLDO_CON7 0x041E
1021 +#define MT6397_DIGLDO_CON8 0x0420
1022 +#define MT6397_DIGLDO_CON9 0x0422
1023 +#define MT6397_DIGLDO_CON10 0x0424
1024 +#define MT6397_DIGLDO_CON11 0x0426
1025 +#define MT6397_DIGLDO_CON12 0x0428
1026 +#define MT6397_DIGLDO_CON13 0x042A
1027 +#define MT6397_DIGLDO_CON14 0x042C
1028 +#define MT6397_DIGLDO_CON15 0x042E
1029 +#define MT6397_DIGLDO_CON16 0x0430
1030 +#define MT6397_DIGLDO_CON17 0x0432
1031 +#define MT6397_DIGLDO_CON18 0x0434
1032 +#define MT6397_DIGLDO_CON19 0x0436
1033 +#define MT6397_DIGLDO_CON20 0x0438
1034 +#define MT6397_DIGLDO_CON21 0x043A
1035 +#define MT6397_DIGLDO_CON22 0x043C
1036 +#define MT6397_DIGLDO_CON23 0x043E
1037 +#define MT6397_DIGLDO_CON24 0x0440
1038 +#define MT6397_DIGLDO_CON25 0x0442
1039 +#define MT6397_DIGLDO_CON26 0x0444
1040 +#define MT6397_DIGLDO_CON27 0x0446
1041 +#define MT6397_DIGLDO_CON28 0x0448
1042 +#define MT6397_DIGLDO_CON29 0x044A
1043 +#define MT6397_DIGLDO_CON30 0x044C
1044 +#define MT6397_DIGLDO_CON31 0x044E
1045 +#define MT6397_DIGLDO_CON32 0x0450
1046 +#define MT6397_DIGLDO_CON33 0x045A
1047 +#define MT6397_SPK_CON0 0x0600
1048 +#define MT6397_SPK_CON1 0x0602
1049 +#define MT6397_SPK_CON2 0x0604
1050 +#define MT6397_SPK_CON3 0x0606
1051 +#define MT6397_SPK_CON4 0x0608
1052 +#define MT6397_SPK_CON5 0x060A
1053 +#define MT6397_SPK_CON6 0x060C
1054 +#define MT6397_SPK_CON7 0x060E
1055 +#define MT6397_SPK_CON8 0x0610
1056 +#define MT6397_SPK_CON9 0x0612
1057 +#define MT6397_SPK_CON10 0x0614
1058 +#define MT6397_SPK_CON11 0x0616
1059 +#define MT6397_AUDDAC_CON0 0x0700
1060 +#define MT6397_AUDBUF_CFG0 0x0702
1061 +#define MT6397_AUDBUF_CFG1 0x0704
1062 +#define MT6397_AUDBUF_CFG2 0x0706
1063 +#define MT6397_AUDBUF_CFG3 0x0708
1064 +#define MT6397_AUDBUF_CFG4 0x070A
1065 +#define MT6397_IBIASDIST_CFG0 0x070C
1066 +#define MT6397_AUDACCDEPOP_CFG0 0x070E
1067 +#define MT6397_AUD_IV_CFG0 0x0710
1068 +#define MT6397_AUDCLKGEN_CFG0 0x0712
1069 +#define MT6397_AUDLDO_CFG0 0x0714
1070 +#define MT6397_AUDLDO_CFG1 0x0716
1071 +#define MT6397_AUDNVREGGLB_CFG0 0x0718
1072 +#define MT6397_AUD_NCP0 0x071A
1073 +#define MT6397_AUDPREAMP_CON0 0x071C
1074 +#define MT6397_AUDADC_CON0 0x071E
1075 +#define MT6397_AUDADC_CON1 0x0720
1076 +#define MT6397_AUDADC_CON2 0x0722
1077 +#define MT6397_AUDADC_CON3 0x0724
1078 +#define MT6397_AUDADC_CON4 0x0726
1079 +#define MT6397_AUDADC_CON5 0x0728
1080 +#define MT6397_AUDADC_CON6 0x072A
1081 +#define MT6397_AUDDIGMI_CON0 0x072C
1082 +#define MT6397_AUDLSBUF_CON0 0x072E
1083 +#define MT6397_AUDLSBUF_CON1 0x0730
1084 +#define MT6397_AUDENCSPARE_CON0 0x0732
1085 +#define MT6397_AUDENCCLKSQ_CON0 0x0734
1086 +#define MT6397_AUDPREAMPGAIN_CON0 0x0736
1087 +#define MT6397_ZCD_CON0 0x0738
1088 +#define MT6397_ZCD_CON1 0x073A
1089 +#define MT6397_ZCD_CON2 0x073C
1090 +#define MT6397_ZCD_CON3 0x073E
1091 +#define MT6397_ZCD_CON4 0x0740
1092 +#define MT6397_ZCD_CON5 0x0742
1093 +#define MT6397_NCP_CLKDIV_CON0 0x0744
1094 +#define MT6397_NCP_CLKDIV_CON1 0x0746
1095 +
1096 +#endif /* __MFD_MT6397_REGISTERS_H__ */
1097 --
1098 1.7.10.4
1099
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