a40c957fb3b609959904e37a5fbd2abcc44452b0
[openwrt/svn-archive/archive.git] / target / linux / mvebu / patches-3.18 / 021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch
1 From e5ee12817e9eac891c6b2a340f64d94d9abd355f Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
3 Date: Thu, 8 Jan 2015 18:38:09 +0100
4 Subject: [PATCH 4/4] ARM: mvebu: Add Armada 385 Access Point Development Board
5 support
6
7 The A385-AP is a board produced by Marvell that holds 3 mPCIe slot, a 16MB
8 SPI-NOR, 3 Gigabit Ethernet ports, USB3 and NAND flash storage.
9
10 [gregory.clement@free-electrons.com: switch the license to the dual
11 X11/GPL with the agreement of the author]
12
13 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
14 Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
15 Signed-off-by: Andrew Lunn <andrew@lunn.ch>
16 ---
17 arch/arm/boot/dts/Makefile | 1 +
18 arch/arm/boot/dts/armada-385-db-ap.dts | 178 +++++++++++++++++++++++++++++++++
19 2 files changed, 179 insertions(+)
20 create mode 100644 arch/arm/boot/dts/armada-385-db-ap.dts
21
22 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
23 index 6dc9c17f9ff5..d34837104949 100644
24 --- a/arch/arm/boot/dts/Makefile
25 +++ b/arch/arm/boot/dts/Makefile
26 @@ -536,6 +536,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \
27 armada-375-db.dtb
28 dtb-$(CONFIG_MACH_ARMADA_38X) += \
29 armada-385-db.dtb \
30 + armada-385-db-ap.dtb \
31 armada-385-rd.dtb
32 dtb-$(CONFIG_MACH_ARMADA_XP) += \
33 armada-xp-axpwifiap.dtb \
34 diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
35 new file mode 100644
36 index 000000000000..57b9119fb3e0
37 --- /dev/null
38 +++ b/arch/arm/boot/dts/armada-385-db-ap.dts
39 @@ -0,0 +1,178 @@
40 +/*
41 + * Device Tree file for Marvell Armada 385 Access Point Development board
42 + * (DB-88F6820-AP)
43 + *
44 + * Copyright (C) 2014 Marvell
45 + *
46 + * Nadav Haklai <nadavh@marvell.com>
47 + *
48 + * This file is dual-licensed: you can use it either under the terms
49 + * of the GPL or the X11 license, at your option. Note that this dual
50 + * licensing only applies to this file, and not this project as a
51 + * whole.
52 + *
53 + * a) This file is licensed under the terms of the GNU General Public
54 + * License version 2. This program is licensed "as is" without
55 + * any warranty of any kind, whether express or implied.
56 + *
57 + * Or, alternatively,
58 + *
59 + * b) Permission is hereby granted, free of charge, to any person
60 + * obtaining a copy of this software and associated documentation
61 + * files (the "Software"), to deal in the Software without
62 + * restriction, including without limitation the rights to use,
63 + * copy, modify, merge, publish, distribute, sublicense, and/or
64 + * sell copies of the Software, and to permit persons to whom the
65 + * Software is furnished to do so, subject to the following
66 + * conditions:
67 + *
68 + * The above copyright notice and this permission notice shall be
69 + * included in all copies or substantial portions of the Software.
70 + *
71 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
72 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
73 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
74 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
75 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
76 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
77 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
78 + * OTHER DEALINGS IN THE SOFTWARE.
79 + */
80 +
81 +/dts-v1/;
82 +#include "armada-385.dtsi"
83 +
84 +#include <dt-bindings/gpio/gpio.h>
85 +
86 +/ {
87 + model = "Marvell Armada 385 Access Point Development Board";
88 + compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
89 +
90 + chosen {
91 + bootargs = "console=ttyS0,115200";
92 + stdout-path = &uart1;
93 + };
94 +
95 + memory {
96 + device_type = "memory";
97 + reg = <0x00000000 0x80000000>; /* 2GB */
98 + };
99 +
100 + soc {
101 + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
102 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
103 +
104 + internal-regs {
105 + spi1: spi@10680 {
106 + pinctrl-names = "default";
107 + pinctrl-0 = <&spi1_pins>;
108 + status = "okay";
109 +
110 + spi-flash@0 {
111 + #address-cells = <1>;
112 + #size-cells = <1>;
113 + compatible = "st,m25p128";
114 + reg = <0>; /* Chip select 0 */
115 + spi-max-frequency = <54000000>;
116 + };
117 + };
118 +
119 + i2c0: i2c@11000 {
120 + pinctrl-names = "default";
121 + pinctrl-0 = <&i2c0_pins>;
122 + status = "okay";
123 +
124 + /*
125 + * This bus is wired to two EEPROM
126 + * sockets, one of which holding the
127 + * board ID used by the bootloader.
128 + * Erasing this EEPROM's content will
129 + * brick the board.
130 + * Use this bus with caution.
131 + */
132 + };
133 +
134 + mdio@72004 {
135 + pinctrl-names = "default";
136 + pinctrl-0 = <&mdio_pins>;
137 +
138 + phy0: ethernet-phy@1 {
139 + reg = <1>;
140 + };
141 +
142 + phy1: ethernet-phy@4 {
143 + reg = <4>;
144 + };
145 +
146 + phy2: ethernet-phy@6 {
147 + reg = <6>;
148 + };
149 + };
150 +
151 + /* UART0 is exposed through the JP8 connector */
152 + uart0: serial@12000 {
153 + pinctrl-names = "default";
154 + pinctrl-0 = <&uart0_pins>;
155 + status = "okay";
156 + };
157 +
158 + /*
159 + * UART1 is exposed through a FTDI chip
160 + * wired to the mini-USB connector
161 + */
162 + uart1: serial@12100 {
163 + pinctrl-names = "default";
164 + pinctrl-0 = <&uart1_pins>;
165 + status = "okay";
166 + };
167 +
168 + ethernet@30000 {
169 + status = "okay";
170 + phy = <&phy2>;
171 + phy-mode = "sgmii";
172 + };
173 +
174 + ethernet@34000 {
175 + status = "okay";
176 + phy = <&phy1>;
177 + phy-mode = "sgmii";
178 + };
179 +
180 + ethernet@70000 {
181 + pinctrl-names = "default";
182 +
183 + /*
184 + * The Reference Clock 0 is used to
185 + * provide a clock to the PHY
186 + */
187 + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
188 + status = "okay";
189 + phy = <&phy0>;
190 + phy-mode = "rgmii-id";
191 + };
192 + };
193 +
194 + pcie-controller {
195 + status = "okay";
196 +
197 + /*
198 + * The three PCIe units are accessible through
199 + * standard mini-PCIe slots on the board.
200 + */
201 + pcie@1,0 {
202 + /* Port 0, Lane 0 */
203 + status = "okay";
204 + };
205 +
206 + pcie@2,0 {
207 + /* Port 1, Lane 0 */
208 + status = "okay";
209 + };
210 +
211 + pcie@3,0 {
212 + /* Port 2, Lane 0 */
213 + status = "okay";
214 + };
215 + };
216 + };
217 +};
218 --
219 2.2.1
220