target/linux/mvebu/patches-3.18/198-gpio_mvebu_suspend.patch

   1 This commit adds the implementation of ->suspend() and ->resume()
   2 platform_driver hooks in order to save and restore the state of the
   3 GPIO configuration. In order to achieve that, additional fields are
   4 added to the mvebu_gpio_chip structure.
   5
   6 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   7 Acked-by: Alexandre Courbot <acourbot@nvidia.com>
   8 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
   9
  10 --- a/drivers/gpio/gpio-mvebu.c
  11 +++ b/drivers/gpio/gpio-mvebu.c
  12 @@ -83,6 +83,14 @@ struct mvebu_gpio_chip {
  13         int                irqbase;
  14         struct irq_domain *domain;
  15         int                soc_variant;
  16 +
  17 +       /* Used to preserve GPIO registers accross suspend/resume */
  18 +       u32                out_reg;
  19 +       u32                io_conf_reg;
  20 +       u32                blink_en_reg;
  21 +       u32                in_pol_reg;
  22 +       u32                edge_mask_regs[4];
  23 +       u32                level_mask_regs[4];
  24  };
  25
  26  /*
  27 @@ -554,6 +562,93 @@ static const struct of_device_id mvebu_g
  28  };
  29  MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
  30
  31 +static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
  32 +{
  33 +       struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
  34 +       int i;
  35 +
  36 +       mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip));
  37 +       mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip));
  38 +       mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip));
  39 +       mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip));
  40 +
  41 +       switch (mvchip->soc_variant) {
  42 +       case MVEBU_GPIO_SOC_VARIANT_ORION:
  43 +               mvchip->edge_mask_regs[0] =
  44 +                       readl(mvchip->membase + GPIO_EDGE_MASK_OFF);
  45 +               mvchip->level_mask_regs[0] =
  46 +                       readl(mvchip->membase + GPIO_LEVEL_MASK_OFF);
  47 +               break;
  48 +       case MVEBU_GPIO_SOC_VARIANT_MV78200:
  49 +               for (i = 0; i < 2; i++) {
  50 +                       mvchip->edge_mask_regs[i] =
  51 +                               readl(mvchip->membase +
  52 +                                     GPIO_EDGE_MASK_MV78200_OFF(i));
  53 +                       mvchip->level_mask_regs[i] =
  54 +                               readl(mvchip->membase +
  55 +                                     GPIO_LEVEL_MASK_MV78200_OFF(i));
  56 +               }
  57 +               break;
  58 +       case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
  59 +               for (i = 0; i < 4; i++) {
  60 +                       mvchip->edge_mask_regs[i] =
  61 +                               readl(mvchip->membase +
  62 +                                     GPIO_EDGE_MASK_ARMADAXP_OFF(i));
  63 +                       mvchip->level_mask_regs[i] =
  64 +                               readl(mvchip->membase +
  65 +                                     GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
  66 +               }
  67 +               break;
  68 +       default:
  69 +               BUG();
  70 +       }
  71 +
  72 +       return 0;
  73 +}
  74 +
  75 +static int mvebu_gpio_resume(struct platform_device *pdev)
  76 +{
  77 +       struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
  78 +       int i;
  79 +
  80 +       writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip));
  81 +       writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip));
  82 +       writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip));
  83 +       writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip));
  84 +
  85 +       switch (mvchip->soc_variant) {
  86 +       case MVEBU_GPIO_SOC_VARIANT_ORION:
  87 +               writel(mvchip->edge_mask_regs[0],
  88 +                      mvchip->membase + GPIO_EDGE_MASK_OFF);
  89 +               writel(mvchip->level_mask_regs[0],
  90 +                      mvchip->membase + GPIO_LEVEL_MASK_OFF);
  91 +               break;
  92 +       case MVEBU_GPIO_SOC_VARIANT_MV78200:
  93 +               for (i = 0; i < 2; i++) {
  94 +                       writel(mvchip->edge_mask_regs[i],
  95 +                              mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i));
  96 +                       writel(mvchip->level_mask_regs[i],
  97 +                              mvchip->membase +
  98 +                              GPIO_LEVEL_MASK_MV78200_OFF(i));
  99 +               }
 100 +               break;
 101 +       case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 102 +               for (i = 0; i < 4; i++) {
 103 +                       writel(mvchip->edge_mask_regs[i],
 104 +                              mvchip->membase +
 105 +                              GPIO_EDGE_MASK_ARMADAXP_OFF(i));
 106 +                       writel(mvchip->level_mask_regs[i],
 107 +                              mvchip->membase +
 108 +                              GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
 109 +               }
 110 +               break;
 111 +       default:
 112 +               BUG();
 113 +       }
 114 +
 115 +       return 0;
 116 +}
 117 +
 118  static int mvebu_gpio_probe(struct platform_device *pdev)
 119  {
 120         struct mvebu_gpio_chip *mvchip;
 121 @@ -577,6 +672,8 @@ static int mvebu_gpio_probe(struct platf
 122         if (!mvchip)
 123                 return -ENOMEM;
 124
 125 +       platform_set_drvdata(pdev, mvchip);
 126 +
 127         if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
 128                 dev_err(&pdev->dev, "Missing ngpios OF property\n");
 129                 return -ENODEV;
 130 @@ -735,5 +832,7 @@ static struct platform_driver mvebu_gpio
 131                 .of_match_table = mvebu_gpio_of_match,
 132         },
 133         .probe          = mvebu_gpio_probe,
 134 +       .suspend        = mvebu_gpio_suspend,
 135 +       .resume         = mvebu_gpio_resume,
 136  };
 137  module_platform_driver(mvebu_gpio_driver);