kernel: update 3.18 to 3.18.14
[openwrt/svn-archive/archive.git] / target / linux / mvebu / patches-3.18 / 200-gpio_mvebu_checkpatch_fixes.patch
1 Wrap some long lines.
2 Prefer seq_puts() over seq_printf().
3 space to tab conversions.
4 Spelling error fix.
5
6 Signed-off-by: Andrew Lunn <andrew@lunn.ch>
7 ---
8 drivers/gpio/gpio-mvebu.c | 77 ++++++++++++++++++++++++++---------------------
9 1 file changed, 42 insertions(+), 35 deletions(-)
10
11 --- a/drivers/gpio/gpio-mvebu.c
12 +++ b/drivers/gpio/gpio-mvebu.c
13 @@ -59,7 +59,7 @@
14 #define GPIO_LEVEL_MASK_OFF 0x001c
15
16 /* The MV78200 has per-CPU registers for edge mask and level mask */
17 -#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
18 +#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
19 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
20
21 /* The Armada XP has per-CPU registers for interrupt cause, interrupt
22 @@ -69,11 +69,11 @@
23 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
24 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
25
26 -#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
27 -#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
28 +#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
29 +#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
30 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
31
32 -#define MVEBU_MAX_GPIO_PER_BANK 32
33 +#define MVEBU_MAX_GPIO_PER_BANK 32
34
35 struct mvebu_gpio_chip {
36 struct gpio_chip chip;
37 @@ -82,9 +82,9 @@ struct mvebu_gpio_chip {
38 void __iomem *percpu_membase;
39 int irqbase;
40 struct irq_domain *domain;
41 - int soc_variant;
42 + int soc_variant;
43
44 - /* Used to preserve GPIO registers accross suspend/resume */
45 + /* Used to preserve GPIO registers across suspend/resume */
46 u32 out_reg;
47 u32 io_conf_reg;
48 u32 blink_en_reg;
49 @@ -107,7 +107,8 @@ static inline void __iomem *mvebu_gpiore
50 return mvchip->membase + GPIO_BLINK_EN_OFF;
51 }
52
53 -static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
54 +static inline void __iomem *
55 +mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
56 {
57 return mvchip->membase + GPIO_IO_CONF_OFF;
58 }
59 @@ -117,12 +118,14 @@ static inline void __iomem *mvebu_gpiore
60 return mvchip->membase + GPIO_IN_POL_OFF;
61 }
62
63 -static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
64 +static inline void __iomem *
65 +mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
66 {
67 return mvchip->membase + GPIO_DATA_IN_OFF;
68 }
69
70 -static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
71 +static inline void __iomem *
72 +mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
73 {
74 int cpu;
75
76 @@ -132,13 +135,15 @@ static inline void __iomem *mvebu_gpiore
77 return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
78 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
79 cpu = smp_processor_id();
80 - return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
81 + return mvchip->percpu_membase +
82 + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
83 default:
84 BUG();
85 }
86 }
87
88 -static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
89 +static inline void __iomem *
90 +mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
91 {
92 int cpu;
93
94 @@ -150,7 +155,8 @@ static inline void __iomem *mvebu_gpiore
95 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
96 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
97 cpu = smp_processor_id();
98 - return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
99 + return mvchip->percpu_membase +
100 + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
101 default:
102 BUG();
103 }
104 @@ -168,7 +174,8 @@ static void __iomem *mvebu_gpioreg_level
105 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
106 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
107 cpu = smp_processor_id();
108 - return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
109 + return mvchip->percpu_membase +
110 + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
111 default:
112 BUG();
113 }
114 @@ -372,22 +379,22 @@ static void mvebu_gpio_level_irq_unmask(
115 * value of the line or the opposite value.
116 *
117 * Level IRQ handlers: DATA_IN is used directly as cause register.
118 - * Interrupt are masked by LEVEL_MASK registers.
119 + * Interrupt are masked by LEVEL_MASK registers.
120 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
121 - * Interrupt are masked by EDGE_MASK registers.
122 + * Interrupt are masked by EDGE_MASK registers.
123 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
124 - * the polarity to catch the next line transaction.
125 - * This is a race condition that might not perfectly
126 - * work on some use cases.
127 + * the polarity to catch the next line transaction.
128 + * This is a race condition that might not perfectly
129 + * work on some use cases.
130 *
131 * Every eight GPIO lines are grouped (OR'ed) before going up to main
132 * cause register.
133 *
134 - * EDGE cause mask
135 - * data-in /--------| |-----| |----\
136 - * -----| |----- ---- to main cause reg
137 - * X \----------------| |----/
138 - * polarity LEVEL mask
139 + * EDGE cause mask
140 + * data-in /--------| |-----| |----\
141 + * -----| |----- ---- to main cause reg
142 + * X \----------------| |----/
143 + * polarity LEVEL mask
144 *
145 ****************************************************************************/
146
147 @@ -402,9 +409,8 @@ static int mvebu_gpio_irq_set_type(struc
148 pin = d->hwirq;
149
150 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
151 - if (!u) {
152 + if (!u)
153 return -EINVAL;
154 - }
155
156 type &= IRQ_TYPE_SENSE_MASK;
157 if (type == IRQ_TYPE_NONE)
158 @@ -537,13 +543,13 @@ static void mvebu_gpio_dbg_show(struct s
159 (data_in ^ in_pol) & msk ? "hi" : "lo",
160 in_pol & msk ? "lo" : "hi");
161 if (!((edg_msk | lvl_msk) & msk)) {
162 - seq_printf(s, " disabled\n");
163 + seq_puts(s, " disabled\n");
164 continue;
165 }
166 if (edg_msk & msk)
167 - seq_printf(s, " edge ");
168 + seq_puts(s, " edge ");
169 if (lvl_msk & msk)
170 - seq_printf(s, " level");
171 + seq_puts(s, " level");
172 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
173 }
174 }
175 @@ -554,15 +560,15 @@ static void mvebu_gpio_dbg_show(struct s
176 static const struct of_device_id mvebu_gpio_of_match[] = {
177 {
178 .compatible = "marvell,orion-gpio",
179 - .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
180 + .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
181 },
182 {
183 .compatible = "marvell,mv78200-gpio",
184 - .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
185 + .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
186 },
187 {
188 .compatible = "marvell,armadaxp-gpio",
189 - .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
190 + .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
191 },
192 {
193 /* sentinel */
194 @@ -676,7 +682,8 @@ static int mvebu_gpio_probe(struct platf
195 else
196 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
197
198 - mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
199 + mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
200 + GFP_KERNEL);
201 if (!mvchip)
202 return -ENOMEM;
203
204 @@ -775,8 +782,8 @@ static int mvebu_gpio_probe(struct platf
205 * interrupt handlers, with each handler dealing with 8 GPIO
206 * pins. */
207 for (i = 0; i < 4; i++) {
208 - int irq;
209 - irq = platform_get_irq(pdev, i);
210 + int irq = platform_get_irq(pdev, i);
211 +
212 if (irq < 0)
213 continue;
214 irq_set_handler_data(irq, mvchip);
215 @@ -835,7 +842,7 @@ static int mvebu_gpio_probe(struct platf
216
217 static struct platform_driver mvebu_gpio_driver = {
218 .driver = {
219 - .name = "mvebu-gpio",
220 + .name = "mvebu-gpio",
221 .of_match_table = mvebu_gpio_of_match,
222 },
223 .probe = mvebu_gpio_probe,