octeon: add gpio driver
[openwrt/svn-archive/archive.git] / target / linux / octeon / patches-3.10 / 130-gpio.patch
1 Index: linux-3.10.49/drivers/gpio/Kconfig
2 ===================================================================
3 --- linux-3.10.49.orig/drivers/gpio/Kconfig 2014-07-17 23:58:15.000000000 +0100
4 +++ linux-3.10.49/drivers/gpio/Kconfig 2014-07-27 05:55:40.312389198 +0100
5 @@ -171,6 +171,14 @@
6 Qualcomm MSM chips. Most of the pins on the MSM can be
7 selected for GPIO, and are controlled by this driver.
8
9 +config GPIO_OCTEON
10 + tristate "Cavium OCTEON GPIO"
11 + depends on GPIOLIB && CPU_CAVIUM_OCTEON
12 + default y
13 + help
14 + Say yes here to support the on-chip GPIO lines on the OCTEON
15 + family of SOCs.
16 +
17 config GPIO_MVEBU
18 def_bool y
19 depends on PLAT_ORION
20 Index: linux-3.10.49/drivers/gpio/Makefile
21 ===================================================================
22 --- linux-3.10.49.orig/drivers/gpio/Makefile 2014-07-17 23:58:15.000000000 +0100
23 +++ linux-3.10.49/drivers/gpio/Makefile 2014-07-27 05:55:40.312389198 +0100
24 @@ -10,6 +10,7 @@
25 # Device drivers. Generally keep list sorted alphabetically
26 obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o
27
28 +obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o
29 obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
30 obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
31 obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
32 Index: linux-3.10.49/drivers/gpio/gpio-octeon.c
33 ===================================================================
34 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
35 +++ linux-3.10.49/drivers/gpio/gpio-octeon.c 2014-07-27 05:55:40.312389198 +0100
36 @@ -0,0 +1,159 @@
37 +/*
38 + * This file is subject to the terms and conditions of the GNU General Public
39 + * License. See the file "COPYING" in the main directory of this archive
40 + * for more details.
41 + *
42 + * Copyright (C) 2011,2012 Cavium Inc.
43 + */
44 +
45 +#include <linux/platform_device.h>
46 +#include <linux/kernel.h>
47 +#include <linux/module.h>
48 +#include <linux/gpio.h>
49 +#include <linux/io.h>
50 +
51 +#include <asm/octeon/octeon.h>
52 +#include <asm/octeon/cvmx-gpio-defs.h>
53 +
54 +#define DRV_VERSION "1.0"
55 +#define DRV_DESCRIPTION "Cavium Inc. OCTEON GPIO Driver"
56 +
57 +#define RX_DAT 0x80
58 +#define TX_SET 0x88
59 +#define TX_CLEAR 0x90
60 +/*
61 + * The address offset of the GPIO configuration register for a given
62 + * line.
63 + */
64 +static unsigned int bit_cfg_reg(unsigned int gpio)
65 +{
66 + if (gpio < 16)
67 + return 8 * gpio;
68 + else
69 + return 8 * (gpio - 16) + 0x100;
70 +}
71 +
72 +struct octeon_gpio {
73 + struct gpio_chip chip;
74 + u64 register_base;
75 +};
76 +
77 +static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
78 +{
79 + struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
80 +
81 + cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
82 + return 0;
83 +}
84 +
85 +static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
86 +{
87 + struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
88 + u64 mask = 1ull << offset;
89 + u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
90 + cvmx_write_csr(reg, mask);
91 +}
92 +
93 +static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
94 + int value)
95 +{
96 + struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
97 + union cvmx_gpio_bit_cfgx cfgx;
98 +
99 +
100 + octeon_gpio_set(chip, offset, value);
101 +
102 + cfgx.u64 = 0;
103 + cfgx.s.tx_oe = 1;
104 +
105 + cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
106 + return 0;
107 +}
108 +
109 +static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
110 +{
111 + struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
112 + u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
113 +
114 + return ((1ull << offset) & read_bits) != 0;
115 +}
116 +
117 +static int octeon_gpio_probe(struct platform_device *pdev)
118 +{
119 + struct octeon_gpio *gpio;
120 + struct gpio_chip *chip;
121 + struct resource *res_mem;
122 + int err = 0;
123 +
124 + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
125 + if (!gpio)
126 + return -ENOMEM;
127 + chip = &gpio->chip;
128 +
129 + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
130 + if (res_mem == NULL) {
131 + dev_err(&pdev->dev, "found no memory resource\n");
132 + err = -ENXIO;
133 + goto out;
134 + }
135 + if (!devm_request_mem_region(&pdev->dev, res_mem->start,
136 + resource_size(res_mem),
137 + res_mem->name)) {
138 + dev_err(&pdev->dev, "request_mem_region failed\n");
139 + err = -ENXIO;
140 + goto out;
141 + }
142 + gpio->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
143 + resource_size(res_mem));
144 +
145 +
146 + pdev->dev.platform_data = chip;
147 + chip->label = "octeon-gpio";
148 + chip->dev = &pdev->dev;
149 + chip->owner = THIS_MODULE;
150 + chip->base = 0;
151 + chip->can_sleep = 0;
152 + chip->ngpio = 20;
153 + chip->direction_input = octeon_gpio_dir_in;
154 + chip->get = octeon_gpio_get;
155 + chip->direction_output = octeon_gpio_dir_out;
156 + chip->set = octeon_gpio_set;
157 + err = gpiochip_add(chip);
158 + if (err)
159 + goto out;
160 +
161 + dev_info(&pdev->dev, "version: " DRV_VERSION "\n");
162 +out:
163 + return err;
164 +}
165 +
166 +static int octeon_gpio_remove(struct platform_device *pdev)
167 +{
168 + struct gpio_chip *chip = pdev->dev.platform_data;
169 + return gpiochip_remove(chip);
170 +}
171 +
172 +static struct of_device_id octeon_gpio_match[] = {
173 + {
174 + .compatible = "cavium,octeon-3860-gpio",
175 + },
176 + {},
177 +};
178 +MODULE_DEVICE_TABLE(of, octeon_gpio_match);
179 +
180 +static struct platform_driver octeon_gpio_driver = {
181 + .probe = octeon_gpio_probe,
182 + .remove = octeon_gpio_remove,
183 + .driver = {
184 + .name = "octeon_gpio",
185 + .owner = THIS_MODULE,
186 + .of_match_table = octeon_gpio_match,
187 + },
188 +};
189 +
190 +module_platform_driver(octeon_gpio_driver);
191 +
192 +MODULE_DESCRIPTION(DRV_DESCRIPTION);
193 +MODULE_AUTHOR("David Daney");
194 +MODULE_LICENSE("GPL");
195 +MODULE_VERSION(DRV_VERSION);
196 Index: linux-3.10.49/arch/mips/Kconfig
197 ===================================================================
198 --- linux-3.10.49.orig/arch/mips/Kconfig 2014-07-27 05:55:38.620389229 +0100
199 +++ linux-3.10.49/arch/mips/Kconfig 2014-07-27 07:20:50.136294063 +0100
200 @@ -769,6 +769,7 @@
201 select USB_ARCH_HAS_OHCI
202 select USB_ARCH_HAS_EHCI
203 select HOLES_IN_ZONE
204 + select ARCH_REQUIRE_GPIOLIB
205 help
206 This option supports all of the Octeon reference boards from Cavium
207 Networks. It builds a kernel that dynamically determines the Octeon