octeon: Add MMC support for EdgeRouter ER8
[openwrt/svn-archive/archive.git] / target / linux / octeon / patches-3.18 / 140-MIPS-OCTEON-Update-octeon-model.h-code-for-new-SoCs.patch
1 diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
2 index e2c122c..35d7cbd 100644
3 --- a/arch/mips/include/asm/octeon/octeon-model.h
4 +++ b/arch/mips/include/asm/octeon/octeon-model.h
5 @@ -45,6 +45,7 @@
6 */
7
8 #define OCTEON_FAMILY_MASK 0x00ffff00
9 +#define OCTEON_PRID_MASK 0x00ffffff
10
11 /* Flag bits in top byte */
12 /* Ignores revision in model checks */
13 @@ -63,6 +64,46 @@
14 #define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000
15 /* Match all cnf7XXX Octeon models. */
16 #define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000
17 +/* Match all cn7XXX Octeon models. */
18 +#define OM_MATCH_7XXX_FAMILY_MODELS 0x10000000
19 +#define OM_MATCH_FAMILY_MODELS (OM_MATCH_5XXX_FAMILY_MODELS | \
20 + OM_MATCH_6XXX_FAMILY_MODELS | \
21 + OM_MATCH_F7XXX_FAMILY_MODELS | \
22 + OM_MATCH_7XXX_FAMILY_MODELS)
23 +/*
24 + * CN7XXX models with new revision encoding
25 + */
26 +
27 +#define OCTEON_CN73XX_PASS1_0 0x000d9700
28 +#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION)
29 +#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \
30 + OM_IGNORE_MINOR_REVISION)
31 +
32 +#define OCTEON_CN70XX_PASS1_0 0x000d9600
33 +#define OCTEON_CN70XX_PASS1_1 0x000d9601
34 +#define OCTEON_CN70XX_PASS1_2 0x000d9602
35 +
36 +#define OCTEON_CN70XX_PASS2_0 0x000d9608
37 +
38 +#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION)
39 +#define OCTEON_CN70XX_PASS1_X (OCTEON_CN70XX_PASS1_0 | \
40 + OM_IGNORE_MINOR_REVISION)
41 +#define OCTEON_CN70XX_PASS2_X (OCTEON_CN70XX_PASS2_0 | \
42 + OM_IGNORE_MINOR_REVISION)
43 +
44 +#define OCTEON_CN71XX OCTEON_CN70XX
45 +
46 +#define OCTEON_CN78XX_PASS1_0 0x000d9500
47 +#define OCTEON_CN78XX_PASS1_1 0x000d9501
48 +#define OCTEON_CN78XX_PASS2_0 0x000d9508
49 +
50 +#define OCTEON_CN78XX (OCTEON_CN78XX_PASS1_0 | OM_IGNORE_REVISION)
51 +#define OCTEON_CN78XX_PASS1_X (OCTEON_CN78XX_PASS1_0 | \
52 + OM_IGNORE_MINOR_REVISION)
53 +#define OCTEON_CN78XX_PASS2_X (OCTEON_CN78XX_PASS2_0 | \
54 + OM_IGNORE_MINOR_REVISION)
55 +
56 +#define OCTEON_CN76XX (0x000d9540 | OM_CHECK_SUBMODEL)
57
58 /*
59 * CNF7XXX models with new revision encoding
60 @@ -217,6 +258,10 @@
61 #define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
62 #define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
63 #define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
64 +#define OCTEON_CNF7XXX (OCTEON_CNF71XX_PASS1_0 | \
65 + OM_MATCH_F7XXX_FAMILY_MODELS)
66 +#define OCTEON_CN7XXX (OCTEON_CN78XX_PASS1_0 | \
67 + OM_MATCH_7XXX_FAMILY_MODELS)
68
69 /* These are used to cover entire families of OCTEON processors */
70 #define OCTEON_FAM_1 (OCTEON_CN3XXX)
71 @@ -288,9 +333,16 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
72 ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
73 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
74 ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
75 - && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
76 + && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN58XX_PASS1_0) \
77 + && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN63XX_PASS1_0)) || \
78 ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
79 - && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \
80 + && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN63XX_PASS1_0) \
81 + && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CNF71XX_PASS1_0)) || \
82 + ((((arg_model) & (OM_MATCH_F7XXX_FAMILY_MODELS)) == OM_MATCH_F7XXX_FAMILY_MODELS) \
83 + && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CNF71XX_PASS1_0) \
84 + && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN78XX_PASS1_0)) || \
85 + ((((arg_model) & (OM_MATCH_7XXX_FAMILY_MODELS)) == OM_MATCH_7XXX_FAMILY_MODELS) \
86 + && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN78XX_PASS1_0)) || \
87 ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
88 && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
89 )))
90 @@ -326,6 +378,15 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
91 #define OCTEON_IS_COMMON_BINARY() 1
92 #undef OCTEON_MODEL
93
94 +#define OCTEON_IS_OCTEON1() OCTEON_IS_MODEL(OCTEON_CN3XXX)
95 +#define OCTEON_IS_OCTEONPLUS() OCTEON_IS_MODEL(OCTEON_CN5XXX)
96 +#define OCTEON_IS_OCTEON2() \
97 + (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
98 +
99 +#define OCTEON_IS_OCTEON3() OCTEON_IS_MODEL(OCTEON_CN7XXX)
100 +
101 +#define OCTEON_IS_OCTEON1PLUS() (OCTEON_IS_OCTEON1() || OCTEON_IS_OCTEONPLUS())
102 +
103 const char *octeon_model_get_string(uint32_t chip_id);
104 const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
105