ralink: fix mt7621 i2c name
[openwrt/svn-archive/archive.git] / target / linux / ramips / dts / mt7621.dtsi
1 / {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "mediatek,mtk7621-soc";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips1004Kc";
9 };
10
11 cpu@1 {
12 compatible = "mips,mips1004Kc";
13 };
14 };
15
16 cpuintc: cpuintc@0 {
17 #address-cells = <0>;
18 #interrupt-cells = <1>;
19 interrupt-controller;
20 compatible = "mti,cpu-interrupt-controller";
21 };
22
23 palmbus@1E000000 {
24 compatible = "palmbus";
25 reg = <0x1E000000 0x100000>;
26 ranges = <0x0 0x1E000000 0x0FFFFF>;
27
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 sysc@0 {
32 compatible = "mtk,mt7621-sysc";
33 reg = <0x0 0x100>;
34 };
35
36 wdt@100 {
37 compatible = "mtk,mt7621-wdt";
38 reg = <0x100 0x100>;
39 };
40
41 gpio@600 {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 compatible = "mtk,mt7621-gpio";
46 reg = <0x600 0x100>;
47
48 gpio0: bank@0 {
49 reg = <0>;
50 compatible = "mtk,mt7621-gpio-bank";
51 gpio-controller;
52 #gpio-cells = <2>;
53 };
54
55 gpio1: bank@1 {
56 reg = <1>;
57 compatible = "mtk,mt7621-gpio-bank";
58 gpio-controller;
59 #gpio-cells = <2>;
60 };
61
62 gpio2: bank@2 {
63 reg = <2>;
64 compatible = "mtk,mt7621-gpio-bank";
65 gpio-controller;
66 #gpio-cells = <2>;
67 };
68 };
69
70 memc@5000 {
71 compatible = "mtk,mt7621-memc";
72 reg = <0x300 0x100>;
73 };
74
75 uartlite@c00 {
76 compatible = "ns16550a";
77 reg = <0xc00 0x100>;
78
79 interrupt-parent = <&gic>;
80 interrupts = <26>;
81
82 reg-shift = <2>;
83 reg-io-width = <4>;
84 no-loopback-test;
85 };
86
87 spi@b00 {
88 status = "okay";
89
90 compatible = "ralink,mt7621-spi";
91 reg = <0xb00 0x100>;
92
93 resets = <&rstctrl 18>;
94 reset-names = "spi";
95
96 #address-cells = <1>;
97 #size-cells = <1>;
98
99 pinctrl-names = "default";
100 pinctrl-0 = <&spi_pins>;
101
102 m25p80@0 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 reg = <0 0>;
106 spi-max-frequency = <10000000>;
107 m25p,chunked-io = <32>;
108 };
109 };
110 };
111
112 pinctrl {
113 compatible = "ralink,rt2880-pinmux";
114 pinctrl-names = "default";
115 pinctrl-0 = <&state_default>;
116 state_default: pinctrl0 {
117 };
118 spi_pins: spi {
119 spi {
120 ralink,group = "spi";
121 ralink,function = "spi";
122 };
123 };
124 i2c_pins: i2c {
125 i2c {
126 ralink,group = "i2c";
127 ralink,function = "i2c";
128 };
129 };
130 uart1_pins: uart1 {
131 uart1 {
132 ralink,group = "uart1";
133 ralink,function = "uart";
134 };
135 };
136 uart2_pins: uart2 {
137 uart2 {
138 ralink,group = "uart2";
139 ralink,function = "uart";
140 };
141 };
142 uart3_pins: uart3 {
143 uart3 {
144 ralink,group = "uart3";
145 ralink,function = "uart";
146 };
147 };
148 rgmii1_pins: rgmii1 {
149 rgmii1 {
150 ralink,group = "rgmii1";
151 ralink,function = "rgmii";
152 };
153 };
154 rgmii2_pins: rgmii2 {
155 rgmii2 {
156 ralink,group = "rgmii2";
157 ralink,function = "rgmii";
158 };
159 };
160 mdio_pins: mdio {
161 mdio {
162 ralink,group = "mdio";
163 ralink,function = "mdio";
164 };
165 };
166 pcie_pins: pcie {
167 pcie {
168 ralink,group = "pcie";
169 ralink,function = "pcie rst";
170 };
171 };
172 nand_pins: nand {
173 spi-nand {
174 ralink,group = "spi";
175 ralink,function = "nand";
176 };
177 sdhci-nand {
178 ralink,group = "sdhci";
179 ralink,function = "nand";
180 };
181 };
182 sdhci_pins: sdhci {
183 sdhci {
184 ralink,group = "sdhci";
185 ralink,function = "sdhci";
186 };
187 };
188 };
189
190 rstctrl: rstctrl {
191 compatible = "ralink,rt2880-reset";
192 #reset-cells = <1>;
193 };
194
195 sdhci@1E130000 {
196 compatible = "ralink,mt7620-sdhci";
197 reg = <0x1E130000 4000>;
198
199 interrupt-parent = <&gic>;
200 interrupts = <20>;
201 };
202
203 xhci@1E1C0000 {
204 status = "disabled";
205
206 compatible = "xhci-platform";
207 reg = <0x1E1C0000 4000>;
208
209 interrupt-parent = <&gic>;
210 interrupts = <22>;
211 };
212
213 gic: gic@1fbc0000 {
214 #address-cells = <0>;
215 #interrupt-cells = <1>;
216 interrupt-controller;
217 compatible = "ralink,mt7621-gic";
218 reg = < 0x1fbc0000 0x80 /* gic */
219 0x1fbf0000 0x8000 /* cpc */
220 0x1fbf8000 0x8000 /* gpmc */
221 >;
222 };
223
224 nand@1e003000 {
225 compatible = "mtk,mt7621-nand";
226 bank-width = <2>;
227 reg = <0x1e003000 0x800
228 0x1e003800 0x800>;
229 #address-cells = <1>;
230 #size-cells = <1>;
231
232 partition@0 {
233 label = "uboot";
234 reg = <0x00000 0x80000>; /* 64 KB */
235 };
236 partition@80000 {
237 label = "uboot_env";
238 reg = <0x80000 0x80000>; /* 64 KB */
239 };
240 partition@100000 {
241 label = "factory";
242 reg = <0x100000 0x40000>;
243 };
244 partition@140000 {
245 label = "rootfs";
246 reg = <0x140000 0xec0000>;
247 };
248 };
249
250 ethernet@1e100000 {
251 compatible = "ralink,mt7621-eth";
252 reg = <0x1e100000 10000>;
253
254 #address-cells = <1>;
255 #size-cells = <0>;
256
257 resets = <&rstctrl 6 &rstctrl 23>;
258 reset-names = "fe", "eth";
259
260 interrupt-parent = <&gic>;
261 interrupts = <3>;
262
263 mdio-bus {
264 #address-cells = <1>;
265 #size-cells = <0>;
266
267 phy1f: ethernet-phy@1f {
268 reg = <0x1f>;
269 phy-mode = "rgmii";
270 };
271 };
272 };
273
274 gsw@1e110000 {
275 compatible = "ralink,mt7620a-gsw";
276 reg = <0x1e110000 8000>;
277 interrupt-parent = <&gic>;
278 interrupts = <23>;
279 };
280
281 pcie@1e140000 {
282 compatible = "mediatek,mt7621-pci";
283 reg = <0x1e140000 0x100
284 0x1e142000 0x100>;
285
286 #address-cells = <3>;
287 #size-cells = <2>;
288
289 pinctrl-names = "default";
290 pinctrl-0 = <&pcie_pins>;
291
292 device_type = "pci";
293
294 bus-range = <0 255>;
295 ranges = <
296 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
297 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
298 >;
299
300 status = "okay";
301
302 pcie0 {
303 reg = <0x0000 0 0 0 0>;
304
305 #address-cells = <3>;
306 #size-cells = <2>;
307
308 device_type = "pci";
309 };
310
311 pcie1 {
312 reg = <0x0800 0 0 0 0>;
313
314 #address-cells = <3>;
315 #size-cells = <2>;
316
317 device_type = "pci";
318 };
319
320 pcie2 {
321 reg = <0x1000 0 0 0 0>;
322
323 #address-cells = <3>;
324 #size-cells = <2>;
325
326 device_type = "pci";
327 };
328 };
329 };