target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "mediatek,mtk7621-soc";
   7
   8         cpus {
   9                 cpu@0 {
  10                         compatible = "mips,mips1004Kc";
  11                 };
  12
  13                 cpu@1 {
  14                         compatible = "mips,mips1004Kc";
  15                 };
  16         };
  17
  18         cpuintc: cpuintc@0 {
  19                 #address-cells = <0>;
  20                 #interrupt-cells = <1>;
  21                 interrupt-controller;
  22                 compatible = "mti,cpu-interrupt-controller";
  23         };
  24
  25         palmbus@1E000000 {
  26                 compatible = "palmbus";
  27                 reg = <0x1E000000 0x100000>;
  28                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  29
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32
  33                 sysc@0 {
  34                         compatible = "mtk,mt7621-sysc";
  35                         reg = <0x0 0x100>;
  36                 };
  37
  38                 wdt@100 {
  39                         compatible = "mtk,mt7621-wdt";
  40                         reg = <0x100 0x100>;
  41                 };
  42
  43                 gpio@600 {
  44                         #address-cells = <1>;
  45                         #size-cells = <0>;
  46
  47                         compatible = "mtk,mt7621-gpio";
  48                         reg = <0x600 0x100>;
  49
  50                         gpio0: bank@0 {
  51                                 reg = <0>;
  52                                 compatible = "mtk,mt7621-gpio-bank";
  53                                 gpio-controller;
  54                                 #gpio-cells = <2>;
  55                         };
  56
  57                         gpio1: bank@1 {
  58                                 reg = <1>;
  59                                 compatible = "mtk,mt7621-gpio-bank";
  60                                 gpio-controller;
  61                                 #gpio-cells = <2>;
  62                         };
  63
  64                         gpio2: bank@2 {
  65                                 reg = <2>;
  66                                 compatible = "mtk,mt7621-gpio-bank";
  67                                 gpio-controller;
  68                                 #gpio-cells = <2>;
  69                         };
  70                 };
  71
  72                 memc@5000 {
  73                         compatible = "mtk,mt7621-memc";
  74                         reg = <0x300 0x100>;
  75                 };
  76
  77                 cpc@1fbf0000 {
  78                              compatible = "mtk,mt7621-cpc";
  79                              reg = <0x1fbf0000 0x8000>;
  80                 };
  81
  82                 mc@1fbf8000 {
  83                             compatible = "mtk,mt7621-mc";
  84                             reg = <0x1fbf8000 0x8000>;
  85                 };
  86
  87                 uartlite@c00 {
  88                         compatible = "ns16550a";
  89                         reg = <0xc00 0x100>;
  90
  91                         interrupt-parent = <&gic>;
  92                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
  93
  94                         reg-shift = <2>;
  95                         reg-io-width = <4>;
  96                         no-loopback-test;
  97                 };
  98
  99                 spi@b00 {
 100                         status = "okay";
 101
 102                         compatible = "ralink,mt7621-spi";
 103                         reg = <0xb00 0x100>;
 104
 105                         resets = <&rstctrl 18>;
 106                         reset-names = "spi";
 107
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110
 111                         pinctrl-names = "default";
 112                         pinctrl-0 = <&spi_pins>;
 113
 114                         m25p80@0 {
 115                                 #address-cells = <1>;
 116                                 #size-cells = <1>;
 117                                 reg = <0 0>;
 118                                 spi-max-frequency = <10000000>;
 119                                 m25p,chunked-io = <32>;
 120                         };
 121                 };
 122         };
 123
 124         pinctrl {
 125                 compatible = "ralink,rt2880-pinmux";
 126                 pinctrl-names = "default";
 127                 pinctrl-0 = <&state_default>;
 128
 129                 state_default: pinctrl0 {
 130                 };
 131
 132                 spi_pins: spi {
 133                         spi {
 134                                 ralink,group = "spi";
 135                                 ralink,function = "spi";
 136                         };
 137                 };
 138
 139                 i2c_pins: i2c {
 140                         i2c {
 141                                 ralink,group = "i2c";
 142                                 ralink,function = "i2c";
 143                         };
 144                 };
 145
 146                 uart1_pins: uart1 {
 147                         uart1 {
 148                                 ralink,group = "uart1";
 149                                 ralink,function = "uart1";
 150                         };
 151                 };
 152
 153                 uart2_pins: uart2 {
 154                         uart2 {
 155                                 ralink,group = "uart2";
 156                                 ralink,function = "uart2";
 157                         };
 158                 };
 159
 160                 uart3_pins: uart3 {
 161                         uart3 {
 162                                 ralink,group = "uart3";
 163                                 ralink,function = "uart3";
 164                         };
 165                 };
 166
 167                 rgmii1_pins: rgmii1 {
 168                         rgmii1 {
 169                                 ralink,group = "rgmii1";
 170                                 ralink,function = "rgmii1";
 171                         };
 172                 };
 173
 174                 rgmii2_pins: rgmii2 {
 175                         rgmii2 {
 176                                 ralink,group = "rgmii2";
 177                                 ralink,function = "rgmii2";
 178                         };
 179                 };
 180
 181                 mdio_pins: mdio {
 182                         mdio {
 183                                 ralink,group = "mdio";
 184                                 ralink,function = "mdio";
 185                         };
 186                 };
 187
 188                 pcie_pins: pcie {
 189                         pcie {
 190                                 ralink,group = "pcie";
 191                                 ralink,function = "pcie rst";
 192                         };
 193                 };
 194
 195                 nand_pins: nand {
 196                         spi-nand {
 197                                 ralink,group = "spi";
 198                                 ralink,function = "nand1";
 199                         };
 200
 201                         sdhci-nand {
 202                                 ralink,group = "sdhci";
 203                                 ralink,function = "nand2";
 204                         };
 205                 };
 206
 207                 sdhci_pins: sdhci {
 208                         sdhci {
 209                                 ralink,group = "sdhci";
 210                                 ralink,function = "sdhci";
 211                         };
 212                 };
 213         };
 214
 215         rstctrl: rstctrl {
 216                 compatible = "ralink,rt2880-reset";
 217                 #reset-cells = <1>;
 218         };
 219
 220         sdhci@1E130000 {
 221                 compatible = "ralink,mt7620-sdhci";
 222                 reg = <0x1E130000 4000>;
 223
 224                 interrupt-parent = <&gic>;
 225                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 226         };
 227
 228         xhci@1E1C0000 {
 229                 status = "okay";
 230
 231                 compatible = "xhci-platform";
 232                 reg = <0x1E1C0000 4000>;
 233
 234                 interrupt-parent = <&gic>;
 235                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 236         };
 237
 238         gic: interrupt-controller@1fbc0000 {
 239                 compatible = "mti,gic";
 240                 reg = <0x1fbc0000 0x80>;
 241
 242                 interrupt-controller;
 243                 #interrupt-cells = <3>;
 244
 245                 mti,reserved-cpu-vectors = <7>;
 246         };
 247
 248         nand@1e003000 {
 249                 compatible = "mtk,mt7621-nand";
 250                 bank-width = <2>;
 251                 reg = <0x1e003000 0x800
 252                         0x1e003800 0x800>;
 253                 #address-cells = <1>;
 254                 #size-cells = <1>;
 255
 256                 partition@0 {
 257                         label = "uboot";
 258                         reg = <0x00000 0x80000>; /* 64 KB */
 259                 };
 260
 261                 partition@80000 {
 262                         label = "uboot_env";
 263                         reg = <0x80000 0x80000>; /* 64 KB */
 264                 };
 265
 266                 partition@100000 {
 267                         label = "factory";
 268                         reg = <0x100000 0x40000>;
 269                 };
 270
 271                 partition@140000 {
 272                         label = "rootfs";
 273                         reg = <0x140000 0xec0000>;
 274                 };
 275         };
 276
 277         ethernet@1e100000 {
 278                 compatible = "ralink,mt7621-eth";
 279                 reg = <0x1e100000 10000>;
 280
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283
 284                 resets = <&rstctrl 6 &rstctrl 23>;
 285                 reset-names = "fe", "eth";
 286
 287                 interrupt-parent = <&gic>;
 288                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 289
 290                 mdio-bus {
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293
 294                         phy1f: ethernet-phy@1f {
 295                                 reg = <0x1f>;
 296                                 phy-mode = "rgmii";
 297                         };
 298                 };
 299         };
 300
 301         gsw@1e110000 {
 302                 compatible = "ralink,mt7620a-gsw";
 303                 reg = <0x1e110000 8000>;
 304                 interrupt-parent = <&gic>;
 305                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 306         };
 307
 308         pcie@1e140000 {
 309                 compatible = "mediatek,mt7621-pci";
 310                 reg = <0x1e140000 0x100
 311                         0x1e142000 0x100>;
 312
 313                 #address-cells = <3>;
 314                 #size-cells = <2>;
 315
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&pcie_pins>;
 318
 319                 device_type = "pci";
 320
 321                 bus-range = <0 255>;
 322                 ranges = <
 323                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 324                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 325                 >;
 326
 327                 interrupt-parent = <&gic>;
 328                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 329                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 330                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 331
 332                 status = "okay";
 333
 334                 pcie0 {
 335                         reg = <0x0000 0 0 0 0>;
 336
 337                         #address-cells = <3>;
 338                         #size-cells = <2>;
 339
 340                         device_type = "pci";
 341                 };
 342
 343                 pcie1 {
 344                         reg = <0x0800 0 0 0 0>;
 345
 346                         #address-cells = <3>;
 347                         #size-cells = <2>;
 348
 349                         device_type = "pci";
 350                 };
 351
 352                 pcie2 {
 353                         reg = <0x1000 0 0 0 0>;
 354
 355                         #address-cells = <3>;
 356                         #size-cells = <2>;
 357
 358                         device_type = "pci";
 359                 };
 360         };
 361 };