ramips: add watchdog device for RT288x
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / include / asm / mach-ralink / rt288x_regs.h
1 /*
2 * Ralink RT288x SoC register definitions
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #ifndef _RT288X_REGS_H_
13 #define _RT288X_REGS_H_
14
15 #include <linux/bitops.h>
16
17 #define RT2880_SYSC_BASE 0x00300000
18 #define RT2880_TIMER_BASE 0x00300100
19 #define RT2880_INTC_BASE 0x00300200
20 #define RT2880_MEMC_BASE 0x00300300
21 #define RT2880_UART0_BASE 0x00300500
22 #define RT2880_PIO_BASE 0x00300600
23 #define RT2880_I2C_BASE 0x00300900
24 #define RT2880_SPI_BASE 0x00300b00
25 #define RT2880_UART1_BASE 0x00300c00
26 #define RT2880_FE_BASE 0x00400000
27 #define RT2880_ROM_BASE 0x00410000
28 #define RT2880_PCM_BASE 0x00420000
29 #define RT2880_PCI_BASE 0x00440000
30 #define RT2880_WMAC_BASE 0x00480000
31 #define RT2880_FLASH1_BASE 0x01000000
32 #define RT2880_FLASH0_BASE 0x1fc00000
33 #define RT2880_SDRAM_BASE 0x08000000
34
35 #define RT2880_SYSC_SIZE 0x100
36 #define RT2880_TIMER_SIZE 0x100
37 #define RT2880_INTC_SIZE 0x100
38 #define RT2880_MEMC_SIZE 0x100
39 #define RT2880_UART0_SIZE 0x100
40 #define RT2880_UART1_SIZE 0x100
41 #define RT2880_FLASH1_SIZE (16 * 1024 * 1024)
42 #define RT2880_FLASH0_SIZE (4 * 1024 * 1024)
43
44 /* SYSC registers */
45 #define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */
46 #define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
47 #define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
48 #define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
49 #define SYSC_REG_CLKCFG 0x030
50 #define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
51 #define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
52 #define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
53 #define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
54 #define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
55
56 #define CHIP_ID_ID_MASK 0xff
57 #define CHIP_ID_ID_SHIFT 8
58 #define CHIP_ID_REV_MASK 0xff
59
60 #define SYSTEM_CONFIG_CPUCLK_SHIFT 20
61 #define SYSTEM_CONFIG_CPUCLK_MASK 0x3
62 #define SYSTEM_CONFIG_CPUCLK_250 0x0
63 #define SYSTEM_CONFIG_CPUCLK_266 0x1
64 #define SYSTEM_CONFIG_CPUCLK_280 0x2
65 #define SYSTEM_CONFIG_CPUCLK_300 0x3
66
67 #define CLKCFG_SRAM_CS_N_WDT BIT(9)
68
69 #define RT2880_RESET_SYSTEM BIT(0)
70 #define RT2880_RESET_TIMER BIT(1)
71 #define RT2880_RESET_INTC BIT(2)
72 #define RT2880_RESET_MEMC BIT(3)
73 #define RT2880_RESET_CPU BIT(4)
74 #define RT2880_RESET_UART0 BIT(5)
75 #define RT2880_RESET_PIO BIT(6)
76 #define RT2880_RESET_I2C BIT(9)
77 #define RT2880_RESET_SPI BIT(11)
78 #define RT2880_RESET_UART1 BIT(12)
79 #define RT2880_RESET_PCI BIT(16)
80 #define RT2880_RESET_WMAC BIT(17)
81 #define RT2880_RESET_FE BIT(18)
82 #define RT2880_RESET_PCM BIT(19)
83
84 #define RT2880_GPIO_MODE_I2C BIT(0)
85 #define RT2880_GPIO_MODE_UART0 BIT(1)
86 #define RT2880_GPIO_MODE_SPI BIT(2)
87 #define RT2880_GPIO_MODE_UART1 BIT(3)
88 #define RT2880_GPIO_MODE_JTAG BIT(4)
89 #define RT2880_GPIO_MODE_MDIO BIT(5)
90 #define RT2880_GPIO_MODE_SDRAM BIT(6)
91 #define RT2880_GPIO_MODE_PCI BIT(7)
92
93 #define RT2880_INTC_INT_TIMER0 BIT(0)
94 #define RT2880_INTC_INT_TIMER1 BIT(1)
95 #define RT2880_INTC_INT_UART0 BIT(2)
96 #define RT2880_INTC_INT_PIO BIT(3)
97 #define RT2880_INTC_INT_PCM BIT(4)
98 #define RT2880_INTC_INT_UART1 BIT(8)
99 #define RT2880_INTC_INT_IA BIT(23)
100 #define RT2880_INTC_INT_GLOBAL BIT(31)
101
102 /* MEMC registers */
103 #define MEMC_REG_SDRAM_CFG0 0x00
104 #define MEMC_REG_SDRAM_CFG1 0x04
105 #define MEMC_REG_FLASH_CFG0 0x08
106 #define MEMC_REG_FLASH_CFG1 0x0c
107 #define MEMC_REG_IA_ADDR 0x10
108 #define MEMC_REG_IA_TYPE 0x14
109
110 #define FLASH_CFG_WIDTH_SHIFT 26
111 #define FLASH_CFG_WIDTH_MASK 0x3
112 #define FLASH_CFG_WIDTH_8BIT 0x0
113 #define FLASH_CFG_WIDTH_16BIT 0x1
114 #define FLASH_CFG_WIDTH_32BIT 0x2
115
116 /* UART registers */
117 #define UART_REG_RX 0
118 #define UART_REG_TX 1
119 #define UART_REG_IER 2
120 #define UART_REG_IIR 3
121 #define UART_REG_FCR 4
122 #define UART_REG_LCR 5
123 #define UART_REG_MCR 6
124 #define UART_REG_LSR 7
125
126 #endif /* _RT288X_REGS_H_ */