target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h

   1 /*
   2  *  Ralink RT305 SoC register definitions
   3  *
   4  *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #ifndef _RT305X_REGS_H_
  12 #define _RT305X_REGS_H_
  13
  14 #include <linux/bitops.h>
  15
  16 #define RT305X_SDRAM_BASE       0x00000000
  17 #define RT305X_SYSC_BASE        0x10000000
  18 #define RT305X_TIMER_BASE       0x10000100
  19 #define RT305X_INTC_BASE        0x10000200
  20 #define RT305X_MEMC_BASE        0x10000300
  21 #define RT305X_PCM_BASE         0x10000400
  22 #define RT305X_UART0_BASE       0x10000500
  23 #define RT305X_GDMA_BASE        0x10000700
  24 #define RT305X_NANDC_BASE       0x10000800
  25 #define RT305X_I2C_BASE         0x10000900
  26 #define RT305X_I2S_BASE         0x10000a00
  27 #define RT305X_SPI_BASE         0x10000b00
  28 #define RT305X_UART1_BASE       0x10000c00
  29 #define RT305X_FE_BASE          0x10100000
  30 #define RT305X_SWITCH_BASE      0x10110000
  31 #define RT305X_WMAC_BASE        0x10180000
  32 #define RT305X_OTG_BASE         0x101c0000
  33 #define RT305X_ROM_BASE         0x00400000
  34 #define RT305X_FLASH1_BASE      0x1b000000
  35 #define RT305X_FLASH0_BASE      0x1f000000
  36
  37 #define RT305X_SYSC_SIZE        0x100
  38 #define RT305X_TIMER_SIZE       0x100
  39 #define RT305X_INTC_SIZE        0x100
  40 #define RT305X_MEMC_SIZE        0x100
  41 #define RT305X_UART0_SIZE       0x100
  42 #define RT305X_UART1_SIZE       0x100
  43 #define RT305X_FLASH1_SIZE      (16 * 1024 * 1024)
  44 #define RT305X_FLASH0_SIZE      (8 * 1024 * 1024)
  45
  46 /* SYSC registers */
  47 #define SYSC_REG_CHIP_NAME0     0x000   /* Chip Name 0 */
  48 #define SYSC_REG_CHIP_NAME1     0x004   /* Chip Name 1 */
  49 #define SYSC_REG_CHIP_ID        0x00c   /* Chip Identification */
  50 #define SYSC_REG_SYSTEM_CONFIG  0x010   /* System Configuration */
  51 #define SYSC_REG_RESET_CTRL     0x034   /* Reset Control*/
  52 #define SYSC_REG_RESET_STATUS   0x038   /* Reset Status*/
  53 #define SYSC_REG_GPIO_MODE      0x060   /* GPIO Purpose Select */
  54 #define SYSC_REG_IA_ADDRESS     0x310   /* Illegal Access Address */
  55 #define SYSC_REG_IA_TYPE        0x314   /* Illegal Access Type */
  56
  57 #define CHIP_ID_ID_MASK         0xff
  58 #define CHIP_ID_ID_SHIFT        8
  59 #define CHIP_ID_REV_MASK        0xff
  60
  61 #define SYSTEM_CONFIG_CPUCLK_SHIFT      18
  62 #define SYSTEM_CONFIG_CPUCLK_MASK       0x1
  63 #define SYSTEM_CONFIG_CPUCLK_320        0x0
  64 #define SYSTEM_CONFIG_CPUCLK_384        0x1
  65
  66 #define RT305X_GPIO_MODE_I2C            BIT(0)
  67 #define RT305X_GPIO_MODE_SPI            BIT(1)
  68 #define RT305X_GPIO_MODE_UART0_SHIFT    2
  69 #define RT305X_GPIO_MODE_UART0_MASK     0x7
  70 #define RT305X_GPIO_MODE_UART0(x)       ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
  71 #define RT305X_GPIO_MODE_UARTF          0x0
  72 #define RT305X_GPIO_MODE_PCM_UARTF      0x1
  73 #define RT305X_GPIO_MODE_PCM_I2S        0x2
  74 #define RT305X_GPIO_MODE_I2S_UARTF      0x3
  75 #define RT305X_GPIO_MODE_PCM_GPIO       0x4
  76 #define RT305X_GPIO_MODE_GPIO_UARTF     0x5
  77 #define RT305X_GPIO_MODE_GPIO_I2S       0x6
  78 #define RT305X_GPIO_MODE_GPIO           0x7
  79 #define RT305X_GPIO_MODE_UART1          BIT(5)
  80 #define RT305X_GPIO_MODE_JTAG           BIT(6)
  81 #define RT305X_GPIO_MODE_MDIO           BIT(7)
  82 #define RT305X_GPIO_MODE_SDRAM          BIT(8)
  83 #define RT305X_GPIO_MODE_RGMII          BIT(9)
  84
  85 #define RT305X_RESET_SYSTEM     BIT(0)
  86 #define RT305X_RESET_TIMER      BIT(8)
  87 #define RT305X_RESET_INTC       BIT(9)
  88 #define RT305X_RESET_MEMC       BIT(10)
  89 #define RT305X_RESET_PCM        BIT(11)
  90 #define RT305X_RESET_UART0      BIT(12)
  91 #define RT305X_RESET_PIO        BIT(13)
  92 #define RT305X_RESET_DMA        BIT(14)
  93 #define RT305X_RESET_I2C        BIT(16)
  94 #define RT305X_RESET_I2S        BIT(17)
  95 #define RT305X_RESET_SPI        BIT(18)
  96 #define RT305X_RESET_UART1      BIT(19)
  97 #define RT305X_RESET_WNIC       BIT(20)
  98 #define RT305X_RESET_FE         BIT(21)
  99 #define RT305X_RESET_OTG        BIT(22)
 100 #define RT305X_RESET_ESW        BIT(23)
 101
 102 #define RT305X_INTC_INT_SYSCTL  BIT(0)
 103 #define RT305X_INTC_INT_TIMER0  BIT(1)
 104 #define RT305X_INTC_INT_TIMER1  BIT(2)
 105 #define RT305X_INTC_INT_IA      BIT(3)
 106 #define RT305X_INTC_INT_PCM     BIT(4)
 107 #define RT305X_INTC_INT_UART0   BIT(5)
 108 #define RT305X_INTC_INT_PIO     BIT(6)
 109 #define RT305X_INTC_INT_DMA     BIT(7)
 110 #define RT305X_INTC_INT_NAND    BIT(8)
 111 #define RT305X_INTC_INT_PERFC   BIT(9)
 112 #define RT305X_INTC_INT_I2S     BIT(10)
 113 #define RT305X_INTC_INT_UART1   BIT(12)
 114 #define RT305X_INTC_INT_ESW     BIT(17)
 115 #define RT305X_INTC_INT_OTG     BIT(18)
 116 #define RT305X_INTC_INT_GLOBAL  BIT(31)
 117
 118 /* MEMC registers */
 119 #define MEMC_REG_SDRAM_CFG0     0x00
 120 #define MEMC_REG_SDRAM_CFG1     0x04
 121 #define MEMC_REG_FLASH_CFG0     0x08
 122 #define MEMC_REG_FLASH_CFG1     0x0c
 123 #define MEMC_REG_IA_ADDR        0x10
 124 #define MEMC_REG_IA_TYPE        0x14
 125
 126 #define FLASH_CFG_WIDTH_SHIFT   26
 127 #define FLASH_CFG_WIDTH_MASK    0x3
 128 #define FLASH_CFG_WIDTH_8BIT    0x0
 129 #define FLASH_CFG_WIDTH_16BIT   0x1
 130 #define FLASH_CFG_WIDTH_32BIT   0x2
 131
 132 /* UART registers */
 133 #define UART_REG_RX     0
 134 #define UART_REG_TX     1
 135 #define UART_REG_IER    2
 136 #define UART_REG_IIR    3
 137 #define UART_REG_FCR    4
 138 #define UART_REG_LCR    5
 139 #define UART_REG_MCR    6
 140 #define UART_REG_LSR    7
 141
 142 #endif /* _RT305X_REGS_H_ */