target/linux/ramips/files/arch/mips/pci/pci-rt288x.c

   1 /*
   2  *  Ralink RT288x SoC PCI register definitions
   3  *
   4  *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
   5  *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  *  Parts of this file are based on Ralink's 2.6.21 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16 #include <linux/io.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/mach-ralink/rt288x.h>
  20 #include <asm/mach-ralink/rt288x_regs.h>
  21
  22 #define RT2880_PCI_MEM_BASE     0x20000000
  23 #define RT2880_PCI_MEM_SIZE     0x10000000
  24 #define RT2880_PCI_IO_BASE      0x00460000
  25 #define RT2880_PCI_IO_SIZE      0x00010000
  26
  27 #define RT2880_PCI_REG_PCICFG_ADDR      0x00
  28 #define RT2880_PCI_REG_PCIMSK_ADDR      0x0c
  29 #define RT2880_PCI_REG_BAR0SETUP_ADDR   0x10
  30 #define RT2880_PCI_REG_IMBASEBAR0_ADDR  0x18
  31 #define RT2880_PCI_REG_CONFIG_ADDR      0x20
  32 #define RT2880_PCI_REG_CONFIG_DATA      0x24
  33 #define RT2880_PCI_REG_MEMBASE          0x28
  34 #define RT2880_PCI_REG_IOBASE           0x2c
  35 #define RT2880_PCI_REG_ID               0x30
  36 #define RT2880_PCI_REG_CLASS            0x34
  37 #define RT2880_PCI_REG_SUBID            0x38
  38 #define RT2880_PCI_REG_ARBCTL           0x80
  39
  40 #define PCI_ACCESS_READ  0
  41 #define PCI_ACCESS_WRITE 1
  42
  43 void __iomem *rt2880_pci_base;
  44
  45 static u32 rt2880_pci_reg_read(u32 reg)
  46 {
  47         return readl(rt2880_pci_base + reg);
  48 }
  49
  50 static void rt2880_pci_reg_write(u32 val, u32 reg)
  51 {
  52         writel(val, rt2880_pci_base + reg);
  53 }
  54
  55 static void config_access(unsigned char access_type, struct pci_bus *bus,
  56                           unsigned int devfn, unsigned char where, u32 *data)
  57 {
  58         unsigned int slot = PCI_SLOT(devfn);
  59         unsigned int address;
  60         u8 func = PCI_FUNC(devfn);
  61
  62         address = (bus->number << 16) | (slot << 11) | (func << 8) |
  63                   (where & 0xfc) | 0x80000000;
  64
  65         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
  66         if (access_type == PCI_ACCESS_WRITE)
  67                 rt2880_pci_reg_write(*data, RT2880_PCI_REG_CONFIG_DATA);
  68         else
  69                 *data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
  70 }
  71
  72 static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
  73                                   int where, int size, u32 *val)
  74 {
  75         u32 data = 0;
  76
  77         config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
  78
  79         if (size == 1)
  80                 *val = (data >> ((where & 3) << 3)) & 0xff;
  81         else if (size == 2)
  82                 *val = (data >> ((where & 3) << 3)) & 0xffff;
  83         else
  84                 *val = data;
  85
  86         return PCIBIOS_SUCCESSFUL;
  87 }
  88
  89 static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
  90                                    int where, int size, u32 val)
  91 {
  92         u32 data = 0;
  93
  94         if (size == 4) {
  95                 data = val;
  96         } else {
  97                 config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
  98                 if (size == 1)
  99                         data = (data & ~(0xff << ((where & 3) << 3))) |
 100                                (val << ((where & 3) << 3));
 101                 else if (size == 2)
 102                         data = (data & ~(0xffff << ((where & 3) << 3))) |
 103                                (val << ((where & 3) << 3));
 104         }
 105
 106         config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data);
 107
 108         return PCIBIOS_SUCCESSFUL;
 109 }
 110
 111 static struct pci_ops rt2880_pci_ops = {
 112         .read   = rt2880_pci_config_read,
 113         .write  = rt2880_pci_config_write,
 114 };
 115
 116 static struct resource rt2880_pci_io_resource = {
 117         .name   = "PCI MEM space",
 118         .start  = RT2880_PCI_MEM_BASE,
 119         .end    = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
 120         .flags  = IORESOURCE_MEM,
 121 };
 122
 123 static struct resource rt2880_pci_mem_resource = {
 124         .name   = "PCI IO space",
 125         .start  = RT2880_PCI_IO_BASE,
 126         .end    = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
 127         .flags  = IORESOURCE_IO,
 128 };
 129
 130 static struct pci_controller rt2880_pci_controller = {
 131         .pci_ops        = &rt2880_pci_ops,
 132         .mem_resource   = &rt2880_pci_io_resource,
 133         .io_resource    = &rt2880_pci_mem_resource,
 134 };
 135
 136 static inline void read_config(unsigned long bus, unsigned long dev,
 137                                unsigned long func, unsigned long reg,
 138                                unsigned long *val)
 139 {
 140         unsigned long address;
 141
 142         address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
 143                   0x80000000;
 144         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 145         *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 146 }
 147
 148 static inline void write_config(unsigned long bus, unsigned long dev,
 149                                 unsigned long func, unsigned long reg,
 150                                 unsigned long val)
 151 {
 152         unsigned long address;
 153
 154         address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
 155                   0x80000000;
 156         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 157         rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
 158 }
 159
 160 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 161 {
 162         u16 cmd;
 163         unsigned long val;
 164         int irq = -1;
 165
 166         if (dev->bus->number != 0)
 167                 return 0;
 168
 169         switch (PCI_SLOT(dev->devfn)) {
 170         case 0x00:
 171                 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 172                 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 173                 break;
 174         case 0x11:
 175                 irq = RT288X_CPU_IRQ_PCI;
 176                 break;
 177         default:
 178                 printk("%s:%s[%d] trying to alloc unknown pci irq\n",
 179                        __FILE__, __func__, __LINE__);
 180                 BUG();
 181                 break;
 182         }
 183
 184         pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
 185         pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
 186         pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
 187         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 188                PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
 189                PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
 190         pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
 191         pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
 192                               dev->irq);
 193         return irq;
 194 }
 195
 196 static int __init rt2880_pci_init(void)
 197 {
 198         unsigned long val = 0;
 199         int i;
 200
 201         rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
 202
 203         rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
 204         for(i = 0; i < 0xfffff; i++) {}
 205
 206         rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
 207         rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
 208         rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
 209         rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
 210         rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
 211         rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
 212         rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
 213         rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
 214         rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
 215         write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 216         read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 217
 218         register_pci_controller(&rt2880_pci_controller);
 219         return 0;
 220 }
 221
 222 int pcibios_plat_dev_init(struct pci_dev *dev)
 223 {
 224         return 0;
 225 }
 226
 227 struct pci_fixup pcibios_fixups[] = {
 228         {0}
 229 };
 230
 231 arch_initcall(rt2880_pci_init);