766d7876d548f1426e6af62ea69ff475cc13b8ad
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / ralink / common / gpio.c
1 /*
2 * Ralink SoC specific GPIO support
3 *
4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/io.h>
13 #include <linux/spinlock.h>
14 #include <linux/gpio.h>
15
16 #include <ralink_soc.h>
17
18 #define GPIO0_REG_INT 0x00
19 #define GPIO0_REG_EDGE 0x04
20 #define GPIO0_REG_RENA 0x08
21 #define GPIO0_REG_FENA 0x0c
22 #define GPIO0_REG_DATA 0x20
23 #define GPIO0_REG_DIR 0x24
24 #define GPIO0_REG_POL 0x28
25 #define GPIO0_REG_SET 0x2c
26 #define GPIO0_REG_RESET 0x30
27 #define GPIO0_REG_TOGGLE 0x34
28
29 #define GPIO1_REG_INT 0x38
30 #define GPIO1_REG_EDGE 0x3c
31 #define GPIO1_REG_RENA 0x40
32 #define GPIO1_REG_FENA 0x44
33 #define GPIO1_REG_DATA 0x48
34 #define GPIO1_REG_DIR 0x4c
35 #define GPIO1_REG_POL 0x50
36 #define GPIO1_REG_SET 0x54
37 #define GPIO1_REG_RESET 0x58
38 #define GPIO1_REG_TOGGLE 0x5c
39
40 #define GPIO2_REG_INT 0x60
41 #define GPIO2_REG_EDGE 0x64
42 #define GPIO2_REG_RENA 0x68
43 #define GPIO2_REG_FENA 0x6c
44 #define GPIO2_REG_DATA 0x70
45 #define GPIO2_REG_DIR 0x74
46 #define GPIO2_REG_POL 0x78
47 #define GPIO2_REG_SET 0x7c
48 #define GPIO2_REG_RESET 0x80
49 #define GPIO2_REG_TOGGLE 0x84
50
51 enum ramips_pio_reg {
52 RAMIPS_GPIO_REG_INT, /* Interrupt status */
53 RAMIPS_GPIO_REG_EDGE,
54 RAMIPS_GPIO_REG_RENA,
55 RAMIPS_GPIO_REG_FENA,
56 RAMIPS_GPIO_REG_DATA,
57 RAMIPS_GPIO_REG_DIR, /* Direction, 0:in, 1: out */
58 RAMIPS_GPIO_REG_POL, /* Polarity, 0: normal, 1: invert */
59 RAMIPS_GPIO_REG_SET,
60 RAMIPS_GPIO_REG_RESET,
61 RAMIPS_GPIO_REG_TOGGLE,
62 RAMIPS_GPIO_REG_MAX
63 };
64
65 struct ramips_gpio_chip {
66 struct gpio_chip chip;
67 u8 regs[RAMIPS_GPIO_REG_MAX];
68 unsigned long map_base;
69 unsigned long map_size;
70
71 spinlock_t lock;
72 void __iomem *regs_base;
73 };
74
75 static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip)
76 {
77 struct ramips_gpio_chip *rg;
78
79 rg = container_of(chip, struct ramips_gpio_chip, chip);
80 return rg;
81 }
82
83 static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val)
84 {
85 __raw_writel(val, rg->regs_base + rg->regs[reg]);
86 }
87
88 static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg)
89 {
90 return __raw_readl(rg->regs_base + rg->regs[reg]);
91 }
92
93 static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
94 {
95 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
96 unsigned long flags;
97 u32 t;
98
99 spin_lock_irqsave(&rg->lock, flags);
100 t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
101 t &= ~(1 << offset);
102 ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
103 spin_unlock_irqrestore(&rg->lock, flags);
104
105 return 0;
106 }
107
108 static int ramips_gpio_direction_output(struct gpio_chip *chip,
109 unsigned offset, int value)
110 {
111 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
112 unsigned long flags;
113 u32 reg;
114 u32 t;
115
116 reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
117
118 spin_lock_irqsave(&rg->lock, flags);
119 ramips_gpio_wr(rg, reg, 1 << offset);
120
121 t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
122 t |= 1 << offset;
123 ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
124 spin_unlock_irqrestore(&rg->lock, flags);
125
126 return 0;
127 }
128
129 static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
130 {
131 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
132 u32 reg;
133
134 reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
135 ramips_gpio_wr(rg, reg, 1 << offset);
136 }
137
138 static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset)
139 {
140 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
141 u32 t;
142
143 t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA);
144 return !!(t & (1 << offset));
145 }
146
147 static struct ramips_gpio_chip ramips_gpio_chip0 = {
148 .chip = {
149 .label = "ramips-gpio0",
150 .direction_input = ramips_gpio_direction_input,
151 .direction_output = ramips_gpio_direction_output,
152 .get = ramips_gpio_get,
153 .set = ramips_gpio_set,
154 .base = 0,
155 .ngpio = RALINK_SOC_GPIO0_COUNT,
156 },
157 .regs = {
158 [RAMIPS_GPIO_REG_INT] = GPIO0_REG_INT,
159 [RAMIPS_GPIO_REG_EDGE] = GPIO0_REG_EDGE,
160 [RAMIPS_GPIO_REG_RENA] = GPIO0_REG_RENA,
161 [RAMIPS_GPIO_REG_FENA] = GPIO0_REG_FENA,
162 [RAMIPS_GPIO_REG_DATA] = GPIO0_REG_DATA,
163 [RAMIPS_GPIO_REG_DIR] = GPIO0_REG_DIR,
164 [RAMIPS_GPIO_REG_POL] = GPIO0_REG_POL,
165 [RAMIPS_GPIO_REG_SET] = GPIO0_REG_SET,
166 [RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET,
167 [RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE,
168 },
169 .map_base = RALINK_SOC_GPIO_BASE,
170 .map_size = PAGE_SIZE,
171 };
172
173 static struct ramips_gpio_chip ramips_gpio_chip1 = {
174 .chip = {
175 .label = "ramips-gpio1",
176 .direction_input = ramips_gpio_direction_input,
177 .direction_output = ramips_gpio_direction_output,
178 .get = ramips_gpio_get,
179 .set = ramips_gpio_set,
180 .base = 32,
181 .ngpio = RALINK_SOC_GPIO1_COUNT,
182 },
183 .regs = {
184 [RAMIPS_GPIO_REG_INT] = GPIO1_REG_INT,
185 [RAMIPS_GPIO_REG_EDGE] = GPIO1_REG_EDGE,
186 [RAMIPS_GPIO_REG_RENA] = GPIO1_REG_RENA,
187 [RAMIPS_GPIO_REG_FENA] = GPIO1_REG_FENA,
188 [RAMIPS_GPIO_REG_DATA] = GPIO1_REG_DATA,
189 [RAMIPS_GPIO_REG_DIR] = GPIO1_REG_DIR,
190 [RAMIPS_GPIO_REG_POL] = GPIO1_REG_POL,
191 [RAMIPS_GPIO_REG_SET] = GPIO1_REG_SET,
192 [RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET,
193 [RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE,
194 },
195 .map_base = RALINK_SOC_GPIO_BASE,
196 .map_size = PAGE_SIZE,
197 };
198
199 static struct ramips_gpio_chip ramips_gpio_chip2 = {
200 .chip = {
201 .label = "ramips-gpio2",
202 .direction_input = ramips_gpio_direction_input,
203 .direction_output = ramips_gpio_direction_output,
204 .get = ramips_gpio_get,
205 .set = ramips_gpio_set,
206 .base = 64,
207 .ngpio = RALINK_SOC_GPIO2_COUNT,
208 },
209 .regs = {
210 [RAMIPS_GPIO_REG_INT] = GPIO2_REG_INT,
211 [RAMIPS_GPIO_REG_EDGE] = GPIO2_REG_EDGE,
212 [RAMIPS_GPIO_REG_RENA] = GPIO2_REG_RENA,
213 [RAMIPS_GPIO_REG_FENA] = GPIO2_REG_FENA,
214 [RAMIPS_GPIO_REG_DATA] = GPIO2_REG_DATA,
215 [RAMIPS_GPIO_REG_DIR] = GPIO2_REG_DIR,
216 [RAMIPS_GPIO_REG_POL] = GPIO2_REG_POL,
217 [RAMIPS_GPIO_REG_SET] = GPIO2_REG_SET,
218 [RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET,
219 [RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE,
220 },
221 .map_base = RALINK_SOC_GPIO_BASE,
222 .map_size = PAGE_SIZE,
223 };
224
225 static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg)
226 {
227 spin_lock_init(&rg->lock);
228
229 rg->regs_base = ioremap(rg->map_base, rg->map_size);
230
231 /* set polarity to low for all lines */
232 ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0);
233
234 gpiochip_add(&rg->chip);
235 }
236
237 __init int ramips_gpio_init(void)
238 {
239 ramips_gpio_chip_add(&ramips_gpio_chip0);
240 ramips_gpio_chip_add(&ramips_gpio_chip1);
241 ramips_gpio_chip_add(&ramips_gpio_chip2);
242
243 return 0;
244 }