ramips: merge 2.6.39 patches
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / ralink / common / intc.c
1 /*
2 * Ralink SoC Interrupt controller routines
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/io.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/bitops.h>
17
18 #include <asm/irq_cpu.h>
19 #include <asm/mipsregs.h>
20
21 #include <asm/mach-ralink/common.h>
22
23 /* INTC register offsets */
24 #define INTC_REG_STATUS0 0x00
25 #define INTC_REG_STATUS1 0x04
26 #define INTC_REG_TYPE 0x20
27 #define INTC_REG_RAW_STATUS 0x30
28 #define INTC_REG_ENABLE 0x34
29 #define INTC_REG_DISABLE 0x38
30
31 #define INTC_INT_GLOBAL BIT(31)
32 #define INTC_IRQ_COUNT 32
33
34 static unsigned int ramips_intc_irq_base;
35 static void __iomem *ramips_intc_base;
36
37 static inline void ramips_intc_wr(u32 val, unsigned reg)
38 {
39 __raw_writel(val, ramips_intc_base + reg);
40 }
41
42 static inline u32 ramips_intc_rr(unsigned reg)
43 {
44 return __raw_readl(ramips_intc_base + reg);
45 }
46
47 static void ramips_intc_irq_unmask(struct irq_data *d)
48 {
49 unsigned int irq = d->irq - ramips_intc_irq_base;
50
51 ramips_intc_wr((1 << irq), INTC_REG_ENABLE);
52 }
53
54 static void ramips_intc_irq_mask(struct irq_data *d)
55 {
56 unsigned int irq = d->irq - ramips_intc_irq_base;
57
58 ramips_intc_wr((1 << irq), INTC_REG_DISABLE);
59 }
60
61 static struct irq_chip ramips_intc_irq_chip = {
62 .name = "INTC",
63 .irq_unmask = ramips_intc_irq_unmask,
64 .irq_mask = ramips_intc_irq_mask,
65 .irq_mask_ack = ramips_intc_irq_mask,
66 };
67
68 static struct irqaction ramips_intc_irqaction = {
69 .handler = no_action,
70 .name = "cascade [INTC]",
71 };
72
73 void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
74 unsigned irq_base)
75 {
76 int i;
77
78 ramips_intc_base = ioremap_nocache(intc_base, PAGE_SIZE);
79 ramips_intc_irq_base = irq_base;
80
81 /* disable all interrupts */
82 ramips_intc_wr(~0, INTC_REG_DISABLE);
83
84 /* route all INTC interrupts to MIPS HW0 interrupt */
85 ramips_intc_wr(0, INTC_REG_TYPE);
86
87 for (i = ramips_intc_irq_base;
88 i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++)
89 irq_set_chip_and_handler(i, &ramips_intc_irq_chip,
90 handle_level_irq);
91
92 setup_irq(irq, &ramips_intc_irqaction);
93 ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE);
94 }
95
96 u32 ramips_intc_get_status(void)
97 {
98 return ramips_intc_rr(INTC_REG_STATUS0);
99 }