ramips: implement clock API for RT288x
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / ralink / rt288x / setup.c
1 /*
2 * Ralink RT288x SoC specific setup
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Ralink's 2.6.21 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19
20 #include <asm/mips_machine.h>
21 #include <asm/reboot.h>
22 #include <asm/time.h>
23
24 #include <asm/mach-ralink/common.h>
25 #include <asm/mach-ralink/rt288x.h>
26 #include <asm/mach-ralink/rt288x_regs.h>
27 #include "common.h"
28
29 static void rt288x_restart(char *command)
30 {
31 rt288x_sysc_wr(RT2880_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
32 while (1)
33 if (cpu_wait)
34 cpu_wait();
35 }
36
37 static void rt288x_halt(void)
38 {
39 while (1)
40 cpu_wait();
41 }
42
43 unsigned int __cpuinit get_c0_compare_irq(void)
44 {
45 return CP0_LEGACY_COMPARE_IRQ;
46 }
47
48 void __init ramips_soc_setup(void)
49 {
50 struct clk *clk;
51
52 rt288x_sysc_base = ioremap_nocache(RT2880_SYSC_BASE, RT2880_SYSC_SIZE);
53 rt288x_memc_base = ioremap_nocache(RT2880_MEMC_BASE, RT2880_MEMC_SIZE);
54
55 rt288x_detect_sys_type();
56 rt288x_clocks_init();
57
58 clk = clk_get(NULL, "cpu");
59 if (IS_ERR(clk))
60 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
61
62 printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
63 clk_get_rate(clk) / 1000000,
64 (clk_get_rate(clk) % 1000000) * 100 / 1000000);
65
66 _machine_restart = rt288x_restart;
67 _machine_halt = rt288x_halt;
68 pm_power_off = rt288x_halt;
69
70 clk = clk_get(NULL, "uart");
71 if (IS_ERR(clk))
72 panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
73
74 ramips_early_serial_setup(0, RT2880_UART0_BASE, clk_get_rate(clk),
75 RT2880_INTC_IRQ_UART0);
76 ramips_early_serial_setup(1, RT2880_UART1_BASE, clk_get_rate(clk),
77 RT2880_INTC_IRQ_UART1);
78 }
79
80 void __init plat_time_init(void)
81 {
82 struct clk *clk;
83
84 clk = clk_get(NULL, "cpu");
85 if (IS_ERR(clk))
86 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
87
88 mips_hpt_frequency = clk_get_rate(clk) / 2;
89 }