002aaebabd692fcde42dfaf2054b82e80e62067d
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / ralink / rt305x / rt305x.c
1 /*
2 * Ralink RT305x SoC specific setup
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Ralink's 2.6.21 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/gpio.h>
18
19 #include <asm/mach-ralink/common.h>
20 #include <asm/mach-ralink/rt305x.h>
21 #include <asm/mach-ralink/rt305x_regs.h>
22
23 unsigned long rt305x_cpu_freq;
24 EXPORT_SYMBOL_GPL(rt305x_cpu_freq);
25
26 unsigned long rt305x_sys_freq;
27 EXPORT_SYMBOL_GPL(rt305x_sys_freq);
28
29 void __iomem * rt305x_sysc_base;
30 void __iomem * rt305x_memc_base;
31
32 void __init rt305x_detect_sys_type(void)
33 {
34 u32 n0;
35 u32 n1;
36 u32 id;
37
38 n0 = rt305x_sysc_rr(SYSC_REG_CHIP_NAME0);
39 n1 = rt305x_sysc_rr(SYSC_REG_CHIP_NAME1);
40 id = rt305x_sysc_rr(SYSC_REG_CHIP_ID);
41
42 snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
43 "Ralink %c%c%c%c%c%c%c%c id:%u rev:%u",
44 (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
45 (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
46 (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
47 (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
48 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
49 (id & CHIP_ID_REV_MASK));
50 }
51
52 void __init rt305x_detect_sys_freq(void)
53 {
54 u32 t;
55
56 t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
57 t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
58
59 switch (t) {
60 case SYSTEM_CONFIG_CPUCLK_320:
61 rt305x_cpu_freq = 320000000;
62 break;
63 case SYSTEM_CONFIG_CPUCLK_384:
64 rt305x_cpu_freq = 384000000;
65 break;
66 }
67
68 rt305x_sys_freq = rt305x_cpu_freq / 3;
69 }
70
71 static void rt305x_gpio_reserve(int first, int last)
72 {
73 for (; first <= last; first++)
74 gpio_request(first, "reserved");
75 }
76
77 void __init rt305x_gpio_init(u32 mode)
78 {
79 u32 t;
80
81 rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
82
83 ramips_gpio_init();
84 if ((mode & RT305X_GPIO_MODE_I2C) == 0)
85 rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);
86
87 if ((mode & RT305X_GPIO_MODE_SPI) == 0)
88 rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK);
89
90 t = mode >> RT305X_GPIO_MODE_UART0_SHIFT;
91 t &= RT305X_GPIO_MODE_UART0_MASK;
92 switch (t) {
93 case RT305X_GPIO_MODE_UARTF:
94 case RT305X_GPIO_MODE_PCM_UARTF:
95 case RT305X_GPIO_MODE_PCM_I2S:
96 case RT305X_GPIO_MODE_I2S_UARTF:
97 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14);
98 break;
99 case RT305X_GPIO_MODE_PCM_GPIO:
100 rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14);
101 break;
102 case RT305X_GPIO_MODE_GPIO_UARTF:
103 case RT305X_GPIO_MODE_GPIO_I2S:
104 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10);
105 break;
106 }
107
108 if ((mode & RT305X_GPIO_MODE_UART1) == 0)
109 rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD,
110 RT305X_GPIO_UART1_RXD);
111
112 if ((mode & RT305X_GPIO_MODE_JTAG) == 0)
113 rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI);
114
115 if ((mode & RT305X_GPIO_MODE_MDIO) == 0)
116 rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC,
117 RT305X_GPIO_MDIO_MDIO);
118
119 if ((mode & RT305X_GPIO_MODE_SDRAM) == 0)
120 rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16,
121 RT305X_GPIO_SDRAM_MD31);
122
123 if ((mode & RT305X_GPIO_MODE_RGMII) == 0)
124 rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0,
125 RT305X_GPIO_GE0_RXCLK);
126 }