4af495b78b54bc60791ae3600d202acb5aca4ab1
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / ralink / rt305x / setup.c
1 /*
2 * Ralink RT305x SoC specific setup
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/serial_8250.h>
17
18 #include <asm/bootinfo.h>
19 #include <asm/mips_machine.h>
20 #include <asm/reboot.h>
21 #include <asm/time.h>
22
23 #include <asm/mach-ralink/rt305x.h>
24 #include <asm/mach-ralink/rt305x_regs.h>
25
26 #include "machine.h"
27
28 enum rt305x_mach_type rt305x_mach;
29
30 static void rt305x_restart(char *command)
31 {
32 rt305x_sysc_wr(RT305X_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
33 while (1)
34 if (cpu_wait)
35 cpu_wait();
36 }
37
38 static void rt305x_halt(void)
39 {
40 while (1)
41 if (cpu_wait)
42 cpu_wait();
43 }
44
45 static void __init rt305x_detect_mem_size(void)
46 {
47 unsigned long size;
48
49 for (size = RT305X_MEM_SIZE_MIN; size < RT305X_MEM_SIZE_MAX;
50 size <<= 1 ) {
51 if (!memcmp(rt305x_detect_mem_size,
52 rt305x_detect_mem_size + size, 1024))
53 break;
54 }
55
56 add_memory_region(RT305X_SDRAM_BASE, size, BOOT_MEM_RAM);
57 }
58
59 static void __init rt305x_early_serial_setup(void)
60 {
61 struct uart_port p;
62 int err;
63
64 memset(&p, 0, sizeof(p));
65 p.flags = UPF_SKIP_TEST;
66 p.iotype = UPIO_AU;
67 p.uartclk = rt305x_sys_freq;
68 p.regshift = 2;
69 p.type = PORT_16550A;
70
71 p.mapbase = RT305X_UART0_BASE;
72 p.membase = ioremap_nocache(p.mapbase, RT305X_UART0_SIZE);
73 p.line = 0;
74 p.irq = RT305X_INTC_IRQ_UART0;
75
76 err = early_serial_setup(&p);
77 if (err)
78 printk(KERN_ERR "RT305x: early UART0 registration failed %d\n",
79 err);
80
81 p.mapbase = RT305X_UART1_BASE;
82 p.membase = ioremap_nocache(p.mapbase, RT305X_UART1_SIZE);
83 p.line = 1;
84 p.irq = RT305X_INTC_IRQ_UART1;
85
86 err = early_serial_setup(&p);
87 if (err)
88 printk(KERN_ERR "RT305x: early UART1 registration failed %d\n",
89 err);
90 }
91
92 const char *get_system_type(void)
93 {
94 return rt305x_sys_type;
95 }
96
97 unsigned int __cpuinit get_c0_compare_irq(void)
98 {
99 return CP0_LEGACY_COMPARE_IRQ;
100 }
101
102 void __init plat_mem_setup(void)
103 {
104 set_io_port_base(KSEG1);
105
106 rt305x_intc_base = ioremap_nocache(RT305X_INTC_BASE, PAGE_SIZE);
107 rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE);
108 rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE);
109
110 rt305x_detect_mem_size();
111 rt305x_detect_sys_type();
112 rt305x_detect_sys_freq();
113
114 printk(KERN_INFO "%s running at %lu.%02lu MHz\n", get_system_type(),
115 rt305x_cpu_freq / 1000000,
116 (rt305x_cpu_freq % 1000000) * 100 / 1000000);
117
118 _machine_restart = rt305x_restart;
119 _machine_halt = rt305x_halt;
120 pm_power_off = rt305x_halt;
121
122 rt305x_early_serial_setup();
123 }
124
125 void __init plat_time_init(void)
126 {
127 mips_hpt_frequency = rt305x_cpu_freq / 2;
128 }
129
130 static int __init rt305x_machine_setup(void)
131 {
132 mips_machine_setup(rt305x_mach);
133
134 return 0;
135 }
136
137 arch_initcall(rt305x_machine_setup);