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ralink: use fe_reset to control all reset
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define MAX_RX_LENGTH 1536
44 #define FE_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
45 #define FE_RX_HLEN (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
46 ETH_FCS_LEN)
47 #define DMA_DUMMY_DESC 0xffffffff
48 #define FE_DEFAULT_MSG_ENABLE \
49 (NETIF_MSG_DRV | \
50 NETIF_MSG_PROBE | \
51 NETIF_MSG_LINK | \
52 NETIF_MSG_TIMER | \
53 NETIF_MSG_IFDOWN | \
54 NETIF_MSG_IFUP | \
55 NETIF_MSG_RX_ERR | \
56 NETIF_MSG_TX_ERR)
57
58 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
59 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
60 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
61 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
62
63 #define SYSC_REG_RSTCTRL 0x34
64
65 static int fe_msg_level = -1;
66 module_param_named(msg_level, fe_msg_level, int, 0);
67 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
68
69 static const u32 fe_reg_table_default[FE_REG_COUNT] = {
70 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
71 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
72 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
73 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
74 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
75 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
76 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
77 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
78 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
79 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
80 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
81 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
82 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
83 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
84 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
85 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
86 };
87
88 static const u32 *fe_reg_table = fe_reg_table_default;
89
90 struct fe_work_t {
91 int bitnr;
92 void (*action)(struct fe_priv *);
93 };
94
95 static void __iomem *fe_base = 0;
96
97 void fe_w32(u32 val, unsigned reg)
98 {
99 __raw_writel(val, fe_base + reg);
100 }
101
102 u32 fe_r32(unsigned reg)
103 {
104 return __raw_readl(fe_base + reg);
105 }
106
107 void fe_reg_w32(u32 val, enum fe_reg reg)
108 {
109 fe_w32(val, fe_reg_table[reg]);
110 }
111
112 u32 fe_reg_r32(enum fe_reg reg)
113 {
114 return fe_r32(fe_reg_table[reg]);
115 }
116
117 void fe_reset(u32 reset_bits)
118 {
119 u32 t;
120
121 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
122 t |= reset_bits;
123 rt_sysc_w32(t , SYSC_REG_RSTCTRL);
124 udelay(10);
125
126 t &= ~reset_bits;
127 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
128 udelay(10);
129 }
130
131 static inline void fe_int_disable(u32 mask)
132 {
133 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
134 FE_REG_FE_INT_ENABLE);
135 /* flush write */
136 fe_reg_r32(FE_REG_FE_INT_ENABLE);
137 }
138
139 static inline void fe_int_enable(u32 mask)
140 {
141 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
142 FE_REG_FE_INT_ENABLE);
143 /* flush write */
144 fe_reg_r32(FE_REG_FE_INT_ENABLE);
145 }
146
147 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
148 {
149 unsigned long flags;
150
151 spin_lock_irqsave(&priv->page_lock, flags);
152 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
153 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
154 FE_GDMA1_MAC_ADRL);
155 spin_unlock_irqrestore(&priv->page_lock, flags);
156 }
157
158 static int fe_set_mac_address(struct net_device *dev, void *p)
159 {
160 int ret = eth_mac_addr(dev, p);
161
162 if (!ret) {
163 struct fe_priv *priv = netdev_priv(dev);
164
165 if (priv->soc->set_mac)
166 priv->soc->set_mac(priv, dev->dev_addr);
167 else
168 fe_hw_set_macaddr(priv, p);
169 }
170
171 return ret;
172 }
173
174 static inline int fe_max_frag_size(int mtu)
175 {
176 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
177 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
178 }
179
180 static inline int fe_max_buf_size(int frag_size)
181 {
182 return frag_size - FE_RX_HLEN -
183 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
184 }
185
186 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
187 {
188 rxd->rxd1 = dma_rxd->rxd1;
189 rxd->rxd2 = dma_rxd->rxd2;
190 rxd->rxd3 = dma_rxd->rxd3;
191 rxd->rxd4 = dma_rxd->rxd4;
192 }
193
194 static inline void fe_get_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
195 {
196 txd->txd1 = dma_txd->txd1;
197 txd->txd2 = dma_txd->txd2;
198 txd->txd3 = dma_txd->txd3;
199 txd->txd4 = dma_txd->txd4;
200 }
201
202 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
203 {
204 dma_txd->txd1 = txd->txd1;
205 dma_txd->txd3 = txd->txd3;
206 dma_txd->txd4 = txd->txd4;
207 /* clean dma done flag last */
208 dma_txd->txd2 = txd->txd2;
209 }
210
211 static void fe_clean_rx(struct fe_priv *priv)
212 {
213 int i;
214
215 if (priv->rx_data) {
216 for (i = 0; i < NUM_DMA_DESC; i++)
217 if (priv->rx_data[i]) {
218 if (priv->rx_dma && priv->rx_dma[i].rxd1)
219 dma_unmap_single(&priv->netdev->dev,
220 priv->rx_dma[i].rxd1,
221 priv->rx_buf_size,
222 DMA_FROM_DEVICE);
223 put_page(virt_to_head_page(priv->rx_data[i]));
224 }
225
226 kfree(priv->rx_data);
227 priv->rx_data = NULL;
228 }
229
230 if (priv->rx_dma) {
231 dma_free_coherent(&priv->netdev->dev,
232 NUM_DMA_DESC * sizeof(*priv->rx_dma),
233 priv->rx_dma,
234 priv->rx_phys);
235 priv->rx_dma = NULL;
236 }
237 }
238
239 static int fe_alloc_rx(struct fe_priv *priv)
240 {
241 struct net_device *netdev = priv->netdev;
242 int i;
243
244 priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
245 GFP_KERNEL);
246 if (!priv->rx_data)
247 goto no_rx_mem;
248
249 for (i = 0; i < NUM_DMA_DESC; i++) {
250 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
251 if (!priv->rx_data[i])
252 goto no_rx_mem;
253 }
254
255 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
256 NUM_DMA_DESC * sizeof(*priv->rx_dma),
257 &priv->rx_phys,
258 GFP_ATOMIC | __GFP_ZERO);
259 if (!priv->rx_dma)
260 goto no_rx_mem;
261
262 for (i = 0; i < NUM_DMA_DESC; i++) {
263 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
264 priv->rx_data[i] + FE_RX_OFFSET,
265 priv->rx_buf_size,
266 DMA_FROM_DEVICE);
267 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
268 goto no_rx_mem;
269 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
270
271 if (priv->soc->rx_dma)
272 priv->soc->rx_dma(&priv->rx_dma[i], priv->rx_buf_size);
273 else
274 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
275 }
276 wmb();
277
278 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
279 fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
280 fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
281 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
282
283 return 0;
284
285 no_rx_mem:
286 return -ENOMEM;
287 }
288
289 static void fe_clean_tx(struct fe_priv *priv)
290 {
291 int i;
292
293 if (priv->tx_skb) {
294 for (i = 0; i < NUM_DMA_DESC; i++) {
295 if (priv->tx_skb[i])
296 dev_kfree_skb_any(priv->tx_skb[i]);
297 }
298 kfree(priv->tx_skb);
299 priv->tx_skb = NULL;
300 }
301
302 if (priv->tx_dma) {
303 dma_free_coherent(&priv->netdev->dev,
304 NUM_DMA_DESC * sizeof(*priv->tx_dma),
305 priv->tx_dma,
306 priv->tx_phys);
307 priv->tx_dma = NULL;
308 }
309 }
310
311 static int fe_alloc_tx(struct fe_priv *priv)
312 {
313 int i;
314
315 priv->tx_free_idx = 0;
316
317 priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
318 GFP_KERNEL);
319 if (!priv->tx_skb)
320 goto no_tx_mem;
321
322 priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
323 NUM_DMA_DESC * sizeof(*priv->tx_dma),
324 &priv->tx_phys,
325 GFP_ATOMIC | __GFP_ZERO);
326 if (!priv->tx_dma)
327 goto no_tx_mem;
328
329 for (i = 0; i < NUM_DMA_DESC; i++) {
330 if (priv->soc->tx_dma) {
331 priv->soc->tx_dma(&priv->tx_dma[i]);
332 continue;
333 }
334 priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
335 }
336 wmb();
337
338 fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
339 fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
340 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
341 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
342
343 return 0;
344
345 no_tx_mem:
346 return -ENOMEM;
347 }
348
349 static int fe_init_dma(struct fe_priv *priv)
350 {
351 int err;
352
353 err = fe_alloc_tx(priv);
354 if (err)
355 return err;
356
357 err = fe_alloc_rx(priv);
358 if (err)
359 return err;
360
361 return 0;
362 }
363
364 static void fe_free_dma(struct fe_priv *priv)
365 {
366 fe_clean_tx(priv);
367 fe_clean_rx(priv);
368
369 netdev_reset_queue(priv->netdev);
370 }
371
372 static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
373 {
374 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
375 dma_unmap_single(dev, txd->txd1,
376 TX_DMA_GET_PLEN0(txd->txd2),
377 DMA_TO_DEVICE);
378 }
379
380 static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
381 {
382 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
383 dma_unmap_page(dev, txd->txd1,
384 TX_DMA_GET_PLEN0(txd->txd2),
385 DMA_TO_DEVICE);
386 }
387
388 static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
389 {
390 if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
391 dma_unmap_page(dev, txd->txd3,
392 TX_DMA_GET_PLEN1(txd->txd2),
393 DMA_TO_DEVICE);
394 }
395
396 void fe_stats_update(struct fe_priv *priv)
397 {
398 struct fe_hw_stats *hwstats = priv->hw_stats;
399 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
400
401 u64_stats_update_begin(&hwstats->syncp);
402
403 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
404 hwstats->rx_bytes += fe_r32(base);
405 hwstats->rx_packets += fe_r32(base + 0x08);
406 hwstats->rx_overflow += fe_r32(base + 0x10);
407 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
408 hwstats->rx_short_errors += fe_r32(base + 0x18);
409 hwstats->rx_long_errors += fe_r32(base + 0x1c);
410 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
411 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
412 hwstats->tx_skip += fe_r32(base + 0x28);
413 hwstats->tx_collisions += fe_r32(base + 0x2c);
414 hwstats->tx_bytes += fe_r32(base + 0x30);
415 hwstats->tx_packets += fe_r32(base + 0x38);
416 } else {
417 hwstats->tx_bytes += fe_r32(base);
418 hwstats->tx_packets += fe_r32(base + 0x04);
419 hwstats->tx_skip += fe_r32(base + 0x08);
420 hwstats->tx_collisions += fe_r32(base + 0x0c);
421 hwstats->rx_bytes += fe_r32(base + 0x20);
422 hwstats->rx_packets += fe_r32(base + 0x24);
423 hwstats->rx_overflow += fe_r32(base + 0x28);
424 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
425 hwstats->rx_short_errors += fe_r32(base + 0x30);
426 hwstats->rx_long_errors += fe_r32(base + 0x34);
427 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
428 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
429 }
430
431 u64_stats_update_end(&hwstats->syncp);
432 }
433
434 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
435 struct rtnl_link_stats64 *storage)
436 {
437 struct fe_priv *priv = netdev_priv(dev);
438 struct fe_hw_stats *hwstats = priv->hw_stats;
439 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
440 unsigned int start;
441
442 if (!base) {
443 netdev_stats_to_stats64(storage, &dev->stats);
444 return storage;
445 }
446
447 if (netif_running(dev) && netif_device_present(dev)) {
448 if (spin_trylock(&hwstats->stats_lock)) {
449 fe_stats_update(priv);
450 spin_unlock(&hwstats->stats_lock);
451 }
452 }
453
454 do {
455 start = u64_stats_fetch_begin_bh(&hwstats->syncp);
456 storage->rx_packets = hwstats->rx_packets;
457 storage->tx_packets = hwstats->tx_packets;
458 storage->rx_bytes = hwstats->rx_bytes;
459 storage->tx_bytes = hwstats->tx_bytes;
460 storage->collisions = hwstats->tx_collisions;
461 storage->rx_length_errors = hwstats->rx_short_errors +
462 hwstats->rx_long_errors;
463 storage->rx_over_errors = hwstats->rx_overflow;
464 storage->rx_crc_errors = hwstats->rx_fcs_errors;
465 storage->rx_errors = hwstats->rx_checksum_errors;
466 storage->tx_aborted_errors = hwstats->tx_skip;
467 } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
468
469 storage->tx_errors = priv->netdev->stats.tx_errors;
470 storage->rx_dropped = priv->netdev->stats.rx_dropped;
471 storage->tx_dropped = priv->netdev->stats.tx_dropped;
472
473 return storage;
474 }
475
476 static int fe_vlan_rx_add_vid(struct net_device *dev,
477 __be16 proto, u16 vid)
478 {
479 struct fe_priv *priv = netdev_priv(dev);
480 u32 idx = (vid & 0xf);
481 u32 vlan_cfg;
482
483 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
484 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
485 return 0;
486
487 if (test_bit(idx, &priv->vlan_map)) {
488 netdev_warn(dev, "disable tx vlan offload\n");
489 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
490 netdev_update_features(dev);
491 } else {
492 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
493 ((idx >> 1) << 2));
494 if (idx & 0x1) {
495 vlan_cfg &= 0xffff;
496 vlan_cfg |= (vid << 16);
497 } else {
498 vlan_cfg &= 0xffff0000;
499 vlan_cfg |= vid;
500 }
501 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
502 ((idx >> 1) << 2));
503 set_bit(idx, &priv->vlan_map);
504 }
505
506 return 0;
507 }
508
509 static int fe_vlan_rx_kill_vid(struct net_device *dev,
510 __be16 proto, u16 vid)
511 {
512 struct fe_priv *priv = netdev_priv(dev);
513 u32 idx = (vid & 0xf);
514
515 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
516 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
517 return 0;
518
519 clear_bit(idx, &priv->vlan_map);
520
521 return 0;
522 }
523
524 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
525 int idx)
526 {
527 struct fe_priv *priv = netdev_priv(dev);
528 struct skb_frag_struct *frag;
529 struct fe_tx_dma txd, *ptxd;
530 dma_addr_t mapped_addr;
531 unsigned int nr_frags;
532 u32 def_txd4;
533 int i, j, unmap_idx, tx_num;
534
535 memset(&txd, 0, sizeof(txd));
536 nr_frags = skb_shinfo(skb)->nr_frags;
537 tx_num = 1 + (nr_frags >> 1);
538
539 /* init tx descriptor */
540 if (priv->soc->tx_dma)
541 priv->soc->tx_dma(&txd);
542 else
543 txd.txd4 = TX_DMA_DESP4_DEF;
544 def_txd4 = txd.txd4;
545
546 /* use dma_unmap_single to free it */
547 txd.txd4 |= priv->soc->tx_udf_bit;
548
549 /* TX Checksum offload */
550 if (skb->ip_summed == CHECKSUM_PARTIAL)
551 txd.txd4 |= TX_DMA_CHKSUM;
552
553 /* VLAN header offload */
554 if (vlan_tx_tag_present(skb)) {
555 if (IS_ENABLED(CONFIG_SOC_MT7621))
556 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
557 else
558 txd.txd4 |= TX_DMA_INS_VLAN |
559 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
560 (vlan_tx_tag_get(skb) & 0xF);
561 }
562
563 /* TSO: fill MSS info in tcp checksum field */
564 if (skb_is_gso(skb)) {
565 if (skb_cow_head(skb, 0)) {
566 netif_warn(priv, tx_err, dev,
567 "GSO expand head fail.\n");
568 goto err_out;
569 }
570 if (skb_shinfo(skb)->gso_type &
571 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
572 txd.txd4 |= TX_DMA_TSO;
573 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
574 }
575 }
576
577 mapped_addr = dma_map_single(&dev->dev, skb->data,
578 skb_headlen(skb), DMA_TO_DEVICE);
579 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
580 goto err_out;
581 txd.txd1 = mapped_addr;
582 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
583
584 /* TX SG offload */
585 j = idx;
586 for (i = 0; i < nr_frags; i++) {
587
588 frag = &skb_shinfo(skb)->frags[i];
589 mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
590 skb_frag_size(frag), DMA_TO_DEVICE);
591 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
592 goto err_dma;
593
594 if (i & 0x1) {
595 j = NEXT_TX_DESP_IDX(j);
596 txd.txd1 = mapped_addr;
597 txd.txd2 = TX_DMA_PLEN0(frag->size);
598 txd.txd4 = def_txd4;
599 } else {
600 txd.txd3 = mapped_addr;
601 txd.txd2 |= TX_DMA_PLEN1(frag->size);
602 if (i != (nr_frags -1)) {
603 fe_set_txd(&txd, &priv->tx_dma[j]);
604 memset(&txd, 0, sizeof(txd));
605 }
606 priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
607 }
608 }
609
610 /* set last segment */
611 if (nr_frags & 0x1)
612 txd.txd2 |= TX_DMA_LS1;
613 else
614 txd.txd2 |= TX_DMA_LS0;
615 fe_set_txd(&txd, &priv->tx_dma[j]);
616
617 /* store skb to cleanup */
618 priv->tx_skb[j] = skb;
619
620 netdev_sent_queue(dev, skb->len);
621 skb_tx_timestamp(skb);
622
623 wmb();
624 j = NEXT_TX_DESP_IDX(j);
625 fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
626
627 return 0;
628
629 err_dma:
630 /* unmap dma */
631 ptxd = &priv->tx_dma[idx];
632 txd_unmap_single(&dev->dev, ptxd);
633
634 j = idx;
635 unmap_idx = i;
636 for (i = 0; i < unmap_idx; i++) {
637 if (i & 0x1) {
638 j = NEXT_TX_DESP_IDX(j);
639 ptxd = &priv->tx_dma[j];
640 txd_unmap_page0(&dev->dev, ptxd);
641 } else {
642 txd_unmap_page1(&dev->dev, ptxd);
643 }
644 }
645
646 err_out:
647 /* reinit descriptors and skb */
648 j = idx;
649 for (i = 0; i < tx_num; i++) {
650 priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
651 priv->tx_skb[j] = NULL;
652 j = NEXT_TX_DESP_IDX(j);
653 }
654 wmb();
655
656 return -1;
657 }
658
659 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
660 unsigned int len;
661 int ret;
662
663 ret = 0;
664 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
665 if ((priv->flags & FE_FLAG_PADDING_64B) &&
666 !(priv->flags & FE_FLAG_PADDING_BUG))
667 return ret;
668
669 if (vlan_tx_tag_present(skb))
670 len = ETH_ZLEN;
671 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
672 len = VLAN_ETH_ZLEN;
673 else if(!(priv->flags & FE_FLAG_PADDING_64B))
674 len = ETH_ZLEN;
675 else
676 return ret;
677
678 if (skb->len < len) {
679 if ((ret = skb_pad(skb, len - skb->len)) < 0)
680 return ret;
681 skb->len = len;
682 skb_set_tail_pointer(skb, len);
683 }
684 }
685
686 return ret;
687 }
688
689 static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
690 {
691 return (u32)(NUM_DMA_DESC - ((tx_fill_idx - priv->tx_free_idx) &
692 (NUM_DMA_DESC - 1)));
693 }
694
695 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
696 {
697 struct fe_priv *priv = netdev_priv(dev);
698 struct net_device_stats *stats = &dev->stats;
699 u32 tx;
700 int tx_num;
701 int len = skb->len;
702
703 if (fe_skb_padto(skb, priv)) {
704 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
705 return NETDEV_TX_OK;
706 }
707
708 tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
709 tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
710 if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
711 {
712 netif_stop_queue(dev);
713 netif_err(priv, tx_queued,dev,
714 "Tx Ring full when queue awake!\n");
715 return NETDEV_TX_BUSY;
716 }
717
718 if (fe_tx_map_dma(skb, dev, tx) < 0) {
719 kfree_skb(skb);
720
721 stats->tx_dropped++;
722 } else {
723 stats->tx_packets++;
724 stats->tx_bytes += len;
725 }
726
727 return NETDEV_TX_OK;
728 }
729
730 static inline void fe_rx_vlan(struct sk_buff *skb)
731 {
732 struct ethhdr *ehdr;
733 u16 vlanid;
734
735 if (!__vlan_get_tag(skb, &vlanid)) {
736 /* pop the vlan tag */
737 ehdr = (struct ethhdr *)skb->data;
738 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
739 skb_pull(skb, VLAN_HLEN);
740 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
741 }
742 }
743
744 static int fe_poll_rx(struct napi_struct *napi, int budget,
745 struct fe_priv *priv)
746 {
747 struct net_device *netdev = priv->netdev;
748 struct net_device_stats *stats = &netdev->stats;
749 struct fe_soc_data *soc = priv->soc;
750 u32 checksum_bit;
751 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
752 struct sk_buff *skb;
753 u8 *data, *new_data;
754 struct fe_rx_dma *rxd, trxd;
755 int done = 0;
756 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
757
758 if (netdev->features & NETIF_F_RXCSUM)
759 checksum_bit = soc->checksum_bit;
760 else
761 checksum_bit = 0;
762
763 while (done < budget) {
764 unsigned int pktlen;
765 dma_addr_t dma_addr;
766 idx = NEXT_RX_DESP_IDX(idx);
767 rxd = &priv->rx_dma[idx];
768 data = priv->rx_data[idx];
769
770 fe_get_rxd(&trxd, rxd);
771 if (!(trxd.rxd2 & RX_DMA_DONE))
772 break;
773
774 /* alloc new buffer */
775 new_data = netdev_alloc_frag(priv->frag_size);
776 if (unlikely(!new_data)) {
777 stats->rx_dropped++;
778 goto release_desc;
779 }
780 dma_addr = dma_map_single(&netdev->dev,
781 new_data + FE_RX_OFFSET,
782 priv->rx_buf_size,
783 DMA_FROM_DEVICE);
784 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
785 put_page(virt_to_head_page(new_data));
786 goto release_desc;
787 }
788
789 /* receive data */
790 skb = build_skb(data, priv->frag_size);
791 if (unlikely(!skb)) {
792 put_page(virt_to_head_page(new_data));
793 goto release_desc;
794 }
795 skb_reserve(skb, FE_RX_OFFSET);
796
797 dma_unmap_single(&netdev->dev, trxd.rxd1,
798 priv->rx_buf_size, DMA_FROM_DEVICE);
799 pktlen = RX_DMA_PLEN0(trxd.rxd2);
800 skb->dev = netdev;
801 skb_put(skb, pktlen);
802 if (trxd.rxd4 & checksum_bit) {
803 skb->ip_summed = CHECKSUM_UNNECESSARY;
804 } else {
805 skb_checksum_none_assert(skb);
806 }
807 if (rx_vlan)
808 fe_rx_vlan(skb);
809 skb->protocol = eth_type_trans(skb, netdev);
810
811 stats->rx_packets++;
812 stats->rx_bytes += pktlen;
813
814 if (skb->ip_summed == CHECKSUM_NONE)
815 netif_receive_skb(skb);
816 else
817 napi_gro_receive(napi, skb);
818
819 priv->rx_data[idx] = new_data;
820 rxd->rxd1 = (unsigned int) dma_addr;
821
822 release_desc:
823 if (soc->rx_dma)
824 soc->rx_dma(rxd, priv->rx_buf_size);
825 else
826 rxd->rxd2 = RX_DMA_LSO;
827
828 wmb();
829 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
830 done++;
831 }
832
833 return done;
834 }
835
836 static int fe_poll_tx(struct fe_priv *priv, int budget)
837 {
838 struct net_device *netdev = priv->netdev;
839 struct device *dev = &netdev->dev;
840 unsigned int bytes_compl = 0;
841 struct sk_buff *skb;
842 struct fe_tx_dma txd;
843 int done = 0, idx;
844 u32 udf_bit = priv->soc->tx_udf_bit;
845
846 idx = priv->tx_free_idx;
847 while (done < budget) {
848 fe_get_txd(&txd, &priv->tx_dma[idx]);
849 skb = priv->tx_skb[idx];
850
851 if (!(txd.txd2 & TX_DMA_DONE) || !skb)
852 break;
853
854 txd_unmap_page1(dev, &txd);
855
856 if (txd.txd4 & udf_bit)
857 txd_unmap_single(dev, &txd);
858 else
859 txd_unmap_page0(dev, &txd);
860
861 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
862 bytes_compl += skb->len;
863 dev_kfree_skb_any(skb);
864 done++;
865 }
866 priv->tx_skb[idx] = NULL;
867 idx = NEXT_TX_DESP_IDX(idx);
868 }
869 priv->tx_free_idx = idx;
870
871 if (!done)
872 return 0;
873
874 netdev_completed_queue(netdev, done, bytes_compl);
875 if (unlikely(netif_queue_stopped(netdev) &&
876 netif_carrier_ok(netdev))) {
877 netif_wake_queue(netdev);
878 }
879
880 return done;
881 }
882
883 static int fe_poll(struct napi_struct *napi, int budget)
884 {
885 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
886 struct fe_hw_stats *hwstat = priv->hw_stats;
887 int tx_done, rx_done;
888 u32 status, mask;
889 u32 tx_intr, rx_intr;
890
891 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
892 tx_intr = priv->soc->tx_int;
893 rx_intr = priv->soc->rx_int;
894 tx_done = rx_done = 0;
895
896 poll_again:
897 if (status & tx_intr) {
898 tx_done += fe_poll_tx(priv, budget - tx_done);
899 if (tx_done < budget) {
900 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
901 }
902 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
903 }
904
905 if (status & rx_intr) {
906 rx_done += fe_poll_rx(napi, budget - rx_done, priv);
907 if (rx_done < budget) {
908 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
909 }
910 }
911
912 if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
913 if (spin_trylock(&hwstat->stats_lock)) {
914 fe_stats_update(priv);
915 spin_unlock(&hwstat->stats_lock);
916 }
917 fe_reg_w32(FE_CNT_GDM_AF, FE_REG_FE_INT_STATUS);
918 }
919
920 if (unlikely(netif_msg_intr(priv))) {
921 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
922 netdev_info(priv->netdev,
923 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
924 tx_done, rx_done, status, mask);
925 }
926
927 if ((tx_done < budget) && (rx_done < budget)) {
928 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
929 if (status & (tx_intr | rx_intr )) {
930 goto poll_again;
931 }
932 napi_complete(napi);
933 fe_int_enable(tx_intr | rx_intr);
934 }
935
936 return rx_done;
937 }
938
939 static void fe_tx_timeout(struct net_device *dev)
940 {
941 struct fe_priv *priv = netdev_priv(dev);
942
943 priv->netdev->stats.tx_errors++;
944 netif_err(priv, tx_err, dev,
945 "transmit timed out\n");
946 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
947 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
948 netif_info(priv, drv, dev, "tx_ring=%d, " \
949 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%d\n", 0,
950 fe_reg_r32(FE_REG_TX_BASE_PTR0),
951 fe_reg_r32(FE_REG_TX_MAX_CNT0),
952 fe_reg_r32(FE_REG_TX_CTX_IDX0),
953 fe_reg_r32(FE_REG_TX_DTX_IDX0),
954 priv->tx_free_idx
955 );
956 netif_info(priv, drv, dev, "rx_ring=%d, " \
957 "base=%08x, max=%u, calc=%u, drx=%u\n", 0,
958 fe_reg_r32(FE_REG_RX_BASE_PTR0),
959 fe_reg_r32(FE_REG_RX_MAX_CNT0),
960 fe_reg_r32(FE_REG_RX_CALC_IDX0),
961 fe_reg_r32(FE_REG_RX_DRX_IDX0)
962 );
963
964 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
965 schedule_work(&priv->pending_work);
966 }
967
968 static irqreturn_t fe_handle_irq(int irq, void *dev)
969 {
970 struct fe_priv *priv = netdev_priv(dev);
971 u32 status, int_mask;
972
973 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
974
975 if (unlikely(!status))
976 return IRQ_NONE;
977
978 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
979 if (likely(status & int_mask)) {
980 fe_int_disable(int_mask);
981 napi_schedule(&priv->rx_napi);
982 } else {
983 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
984 }
985
986 return IRQ_HANDLED;
987 }
988
989 #ifdef CONFIG_NET_POLL_CONTROLLER
990 static void fe_poll_controller(struct net_device *dev)
991 {
992 struct fe_priv *priv = netdev_priv(dev);
993 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
994
995 fe_int_disable(int_mask);
996 fe_handle_irq(dev->irq, dev);
997 fe_int_enable(int_mask);
998 }
999 #endif
1000
1001 int fe_set_clock_cycle(struct fe_priv *priv)
1002 {
1003 unsigned long sysclk = priv->sysclk;
1004
1005 if (!sysclk) {
1006 return -EINVAL;
1007 }
1008
1009 sysclk /= FE_US_CYC_CNT_DIVISOR;
1010 sysclk <<= FE_US_CYC_CNT_SHIFT;
1011
1012 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1013 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1014 sysclk,
1015 FE_FE_GLO_CFG);
1016 return 0;
1017 }
1018
1019 void fe_fwd_config(struct fe_priv *priv)
1020 {
1021 u32 fwd_cfg;
1022
1023 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1024
1025 /* disable jumbo frame */
1026 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1027 fwd_cfg &= ~FE_GDM1_JMB_EN;
1028
1029 /* set unicast/multicast/broadcast frame to cpu */
1030 fwd_cfg &= ~0xffff;
1031
1032 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1033 }
1034
1035 static void fe_rxcsum_config(bool enable)
1036 {
1037 if (enable)
1038 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1039 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1040 FE_GDMA1_FWD_CFG);
1041 else
1042 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1043 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1044 FE_GDMA1_FWD_CFG);
1045 }
1046
1047 static void fe_txcsum_config(bool enable)
1048 {
1049 if (enable)
1050 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1051 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1052 FE_CDMA_CSG_CFG);
1053 else
1054 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1055 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1056 FE_CDMA_CSG_CFG);
1057 }
1058
1059 void fe_csum_config(struct fe_priv *priv)
1060 {
1061 struct net_device *dev = priv_netdev(priv);
1062
1063 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1064 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1065 }
1066
1067 static int fe_hw_init(struct net_device *dev)
1068 {
1069 struct fe_priv *priv = netdev_priv(dev);
1070 int i, err;
1071
1072 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1073 dev_name(priv->device), dev);
1074 if (err)
1075 return err;
1076
1077 if (priv->soc->set_mac)
1078 priv->soc->set_mac(priv, dev->dev_addr);
1079 else
1080 fe_hw_set_macaddr(priv, dev->dev_addr);
1081
1082 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1083
1084 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1085 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1086 for (i = 0; i < 16; i += 2)
1087 fe_w32(((i + 1) << 16) + i,
1088 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1089 (i * 2));
1090
1091 BUG_ON(!priv->soc->fwd_config);
1092 if (priv->soc->fwd_config(priv))
1093 netdev_err(dev, "unable to get clock\n");
1094
1095 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1096 fe_reg_w32(1, FE_REG_FE_RST_GL);
1097 fe_reg_w32(0, FE_REG_FE_RST_GL);
1098 }
1099
1100 return 0;
1101 }
1102
1103 static int fe_open(struct net_device *dev)
1104 {
1105 struct fe_priv *priv = netdev_priv(dev);
1106 unsigned long flags;
1107 u32 val;
1108 int err;
1109
1110 err = fe_init_dma(priv);
1111 if (err)
1112 goto err_out;
1113
1114 spin_lock_irqsave(&priv->page_lock, flags);
1115 napi_enable(&priv->rx_napi);
1116
1117 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1118 val |= priv->soc->pdma_glo_cfg;
1119 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1120
1121 spin_unlock_irqrestore(&priv->page_lock, flags);
1122
1123 if (priv->phy)
1124 priv->phy->start(priv);
1125
1126 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1127 netif_carrier_on(dev);
1128
1129 netif_start_queue(dev);
1130 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1131
1132 return 0;
1133
1134 err_out:
1135 fe_free_dma(priv);
1136 return err;
1137 }
1138
1139 static int fe_stop(struct net_device *dev)
1140 {
1141 struct fe_priv *priv = netdev_priv(dev);
1142 unsigned long flags;
1143 int i;
1144
1145 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1146
1147 netif_tx_disable(dev);
1148
1149 if (priv->phy)
1150 priv->phy->stop(priv);
1151
1152 spin_lock_irqsave(&priv->page_lock, flags);
1153 napi_disable(&priv->rx_napi);
1154
1155 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1156 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1157 FE_REG_PDMA_GLO_CFG);
1158 spin_unlock_irqrestore(&priv->page_lock, flags);
1159
1160 /* wait dma stop */
1161 for (i = 0; i < 10; i++) {
1162 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1163 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1164 msleep(10);
1165 continue;
1166 }
1167 break;
1168 }
1169
1170 fe_free_dma(priv);
1171
1172 return 0;
1173 }
1174
1175 static int __init fe_init(struct net_device *dev)
1176 {
1177 struct fe_priv *priv = netdev_priv(dev);
1178 struct device_node *port;
1179 int err;
1180
1181 BUG_ON(!priv->soc->reset_fe);
1182 priv->soc->reset_fe();
1183
1184 if (priv->soc->switch_init)
1185 priv->soc->switch_init(priv);
1186
1187 memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
1188 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1189
1190 err = fe_mdio_init(priv);
1191 if (err)
1192 return err;
1193
1194 if (priv->soc->port_init)
1195 for_each_child_of_node(priv->device->of_node, port)
1196 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1197 priv->soc->port_init(priv, port);
1198
1199 if (priv->phy) {
1200 err = priv->phy->connect(priv);
1201 if (err)
1202 goto err_phy_disconnect;
1203 }
1204
1205 err = fe_hw_init(dev);
1206 if (err)
1207 goto err_phy_disconnect;
1208
1209 if (priv->soc->switch_config)
1210 priv->soc->switch_config(priv);
1211
1212 return 0;
1213
1214 err_phy_disconnect:
1215 if (priv->phy)
1216 priv->phy->disconnect(priv);
1217 fe_mdio_cleanup(priv);
1218
1219 return err;
1220 }
1221
1222 static void fe_uninit(struct net_device *dev)
1223 {
1224 struct fe_priv *priv = netdev_priv(dev);
1225
1226 if (priv->phy)
1227 priv->phy->disconnect(priv);
1228 fe_mdio_cleanup(priv);
1229
1230 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1231 free_irq(dev->irq, dev);
1232 }
1233
1234 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1235 {
1236 struct fe_priv *priv = netdev_priv(dev);
1237
1238 if (!priv->phy_dev)
1239 return -ENODEV;
1240
1241 switch (cmd) {
1242 case SIOCETHTOOL:
1243 return phy_ethtool_ioctl(priv->phy_dev,
1244 (void *) ifr->ifr_data);
1245 case SIOCGMIIPHY:
1246 case SIOCGMIIREG:
1247 case SIOCSMIIREG:
1248 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1249 default:
1250 break;
1251 }
1252
1253 return -EOPNOTSUPP;
1254 }
1255
1256 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1257 {
1258 struct fe_priv *priv = netdev_priv(dev);
1259 int frag_size, old_mtu;
1260 u32 fwd_cfg;
1261
1262 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1263 return eth_change_mtu(dev, new_mtu);
1264
1265 frag_size = fe_max_frag_size(new_mtu);
1266 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1267 return -EINVAL;
1268
1269 old_mtu = dev->mtu;
1270 dev->mtu = new_mtu;
1271
1272 /* return early if the buffer sizes will not change */
1273 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1274 return 0;
1275 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1276 return 0;
1277
1278 if (new_mtu <= ETH_DATA_LEN) {
1279 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1280 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1281 } else {
1282 priv->frag_size = PAGE_SIZE;
1283 priv->rx_buf_size = fe_max_buf_size(PAGE_SIZE);
1284 }
1285
1286 if (!netif_running(dev))
1287 return 0;
1288
1289 fe_stop(dev);
1290 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1291 if (new_mtu <= ETH_DATA_LEN)
1292 fwd_cfg &= ~FE_GDM1_JMB_EN;
1293 else {
1294 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1295 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1296 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1297 }
1298 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1299
1300 return fe_open(dev);
1301 }
1302
1303 static const struct net_device_ops fe_netdev_ops = {
1304 .ndo_init = fe_init,
1305 .ndo_uninit = fe_uninit,
1306 .ndo_open = fe_open,
1307 .ndo_stop = fe_stop,
1308 .ndo_start_xmit = fe_start_xmit,
1309 .ndo_set_mac_address = fe_set_mac_address,
1310 .ndo_validate_addr = eth_validate_addr,
1311 .ndo_do_ioctl = fe_do_ioctl,
1312 .ndo_change_mtu = fe_change_mtu,
1313 .ndo_tx_timeout = fe_tx_timeout,
1314 .ndo_get_stats64 = fe_get_stats64,
1315 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1316 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1317 #ifdef CONFIG_NET_POLL_CONTROLLER
1318 .ndo_poll_controller = fe_poll_controller,
1319 #endif
1320 };
1321
1322 static void fe_reset_pending(struct fe_priv *priv)
1323 {
1324 struct net_device *dev = priv->netdev;
1325 int err;
1326
1327 rtnl_lock();
1328 fe_stop(dev);
1329
1330 err = fe_open(dev);
1331 if (err)
1332 goto error;
1333 rtnl_unlock();
1334
1335 return;
1336 error:
1337 netif_alert(priv, ifup, dev,
1338 "Driver up/down cycle failed, closing device.\n");
1339 dev_close(dev);
1340 rtnl_unlock();
1341 }
1342
1343 static const struct fe_work_t fe_work[] = {
1344 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1345 };
1346
1347 static void fe_pending_work(struct work_struct *work)
1348 {
1349 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1350 int i;
1351 bool pending;
1352
1353 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1354 pending = test_and_clear_bit(fe_work[i].bitnr,
1355 priv->pending_flags);
1356 if (pending)
1357 fe_work[i].action(priv);
1358 }
1359 }
1360
1361 static int fe_probe(struct platform_device *pdev)
1362 {
1363 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1364 const struct of_device_id *match;
1365 struct fe_soc_data *soc;
1366 struct net_device *netdev;
1367 struct fe_priv *priv;
1368 struct clk *sysclk;
1369 int err;
1370
1371 device_reset(&pdev->dev);
1372
1373 match = of_match_device(of_fe_match, &pdev->dev);
1374 soc = (struct fe_soc_data *) match->data;
1375
1376 if (soc->reg_table)
1377 fe_reg_table = soc->reg_table;
1378 else
1379 soc->reg_table = fe_reg_table;
1380
1381 fe_base = devm_request_and_ioremap(&pdev->dev, res);
1382 if (!fe_base) {
1383 err = -EADDRNOTAVAIL;
1384 goto err_out;
1385 }
1386
1387 netdev = alloc_etherdev(sizeof(*priv));
1388 if (!netdev) {
1389 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1390 err = -ENOMEM;
1391 goto err_iounmap;
1392 }
1393
1394 SET_NETDEV_DEV(netdev, &pdev->dev);
1395 netdev->netdev_ops = &fe_netdev_ops;
1396 netdev->base_addr = (unsigned long) fe_base;
1397
1398 netdev->irq = platform_get_irq(pdev, 0);
1399 if (netdev->irq < 0) {
1400 dev_err(&pdev->dev, "no IRQ resource found\n");
1401 err = -ENXIO;
1402 goto err_free_dev;
1403 }
1404
1405 if (soc->init_data)
1406 soc->init_data(soc, netdev);
1407 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1408 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1409 netdev->vlan_features = netdev->hw_features &
1410 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1411 netdev->features |= netdev->hw_features;
1412
1413 /* fake rx vlan filter func. to support tx vlan offload func */
1414 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1415 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1416
1417 priv = netdev_priv(netdev);
1418 spin_lock_init(&priv->page_lock);
1419 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1420 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1421 if (!priv->hw_stats) {
1422 err = -ENOMEM;
1423 goto err_free_dev;
1424 }
1425 spin_lock_init(&priv->hw_stats->stats_lock);
1426 }
1427
1428 sysclk = devm_clk_get(&pdev->dev, NULL);
1429 if (!IS_ERR(sysclk))
1430 priv->sysclk = clk_get_rate(sysclk);
1431
1432 priv->netdev = netdev;
1433 priv->device = &pdev->dev;
1434 priv->soc = soc;
1435 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1436 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1437 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1438 if (priv->frag_size > PAGE_SIZE) {
1439 dev_err(&pdev->dev, "error frag size.\n");
1440 err = -EINVAL;
1441 goto err_free_dev;
1442 }
1443 INIT_WORK(&priv->pending_work, fe_pending_work);
1444
1445 netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
1446 fe_set_ethtool_ops(netdev);
1447
1448 err = register_netdev(netdev);
1449 if (err) {
1450 dev_err(&pdev->dev, "error bringing up device\n");
1451 goto err_free_dev;
1452 }
1453
1454 platform_set_drvdata(pdev, netdev);
1455
1456 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1457 netdev->base_addr, netdev->irq);
1458
1459 return 0;
1460
1461 err_free_dev:
1462 free_netdev(netdev);
1463 err_iounmap:
1464 devm_iounmap(&pdev->dev, fe_base);
1465 err_out:
1466 return err;
1467 }
1468
1469 static int fe_remove(struct platform_device *pdev)
1470 {
1471 struct net_device *dev = platform_get_drvdata(pdev);
1472 struct fe_priv *priv = netdev_priv(dev);
1473
1474 netif_napi_del(&priv->rx_napi);
1475 if (priv->hw_stats)
1476 kfree(priv->hw_stats);
1477
1478 cancel_work_sync(&priv->pending_work);
1479
1480 unregister_netdev(dev);
1481 free_netdev(dev);
1482 platform_set_drvdata(pdev, NULL);
1483
1484 return 0;
1485 }
1486
1487 static struct platform_driver fe_driver = {
1488 .probe = fe_probe,
1489 .remove = fe_remove,
1490 .driver = {
1491 .name = "ralink_soc_eth",
1492 .owner = THIS_MODULE,
1493 .of_match_table = of_fe_match,
1494 },
1495 };
1496
1497 static int __init init_rtfe(void)
1498 {
1499 int ret;
1500
1501 ret = rtesw_init();
1502 if (ret)
1503 return ret;
1504
1505 ret = platform_driver_register(&fe_driver);
1506 if (ret)
1507 rtesw_exit();
1508
1509 return ret;
1510 }
1511
1512 static void __exit exit_rtfe(void)
1513 {
1514 platform_driver_unregister(&fe_driver);
1515 rtesw_exit();
1516 }
1517
1518 module_init(init_rtfe);
1519 module_exit(exit_rtfe);
1520
1521 MODULE_LICENSE("GPL");
1522 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1523 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1524 MODULE_VERSION(FE_DRV_VERSION);
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