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8c204768b79c668699f4cfd460118ff26a649487
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.h
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * based on Ralink SDK3.3
16 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
17 */
18
19 #ifndef FE_ETH_H
20 #define FE_ETH_H
21
22 #include <linux/mii.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/phy.h>
27 #include <linux/ethtool.h>
28
29 enum fe_reg {
30 FE_REG_PDMA_GLO_CFG = 0,
31 FE_REG_PDMA_RST_CFG,
32 FE_REG_DLY_INT_CFG,
33 FE_REG_TX_BASE_PTR0,
34 FE_REG_TX_MAX_CNT0,
35 FE_REG_TX_CTX_IDX0,
36 FE_REG_TX_DTX_IDX0,
37 FE_REG_RX_BASE_PTR0,
38 FE_REG_RX_MAX_CNT0,
39 FE_REG_RX_CALC_IDX0,
40 FE_REG_RX_DRX_IDX0,
41 FE_REG_FE_INT_ENABLE,
42 FE_REG_FE_INT_STATUS,
43 FE_REG_FE_DMA_VID_BASE,
44 FE_REG_FE_COUNTER_BASE,
45 FE_REG_FE_RST_GL,
46 FE_REG_COUNT
47 };
48
49 enum fe_work_flag {
50 FE_FLAG_RESET_PENDING,
51 FE_FLAG_MAX
52 };
53
54 #define FE_DRV_VERSION "0.1.2"
55
56 /* power of 2 to let NEXT_TX_DESP_IDX work */
57 #ifdef CONFIG_SOC_MT7621
58 #define NUM_DMA_DESC (1 << 9)
59 #else
60 #define NUM_DMA_DESC (1 << 7)
61 #endif
62 #define MAX_DMA_DESC 0xfff
63
64 #define FE_DELAY_EN_INT 0x80
65 #define FE_DELAY_MAX_INT 0x04
66 #define FE_DELAY_MAX_TOUT 0x04
67 #define FE_DELAY_TIME 20
68 #define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
69 #define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
70 #define FE_PSE_FQFC_CFG_INIT 0x80504000
71 #define FE_PSE_FQFC_CFG_256Q 0xff908000
72
73 /* interrupt bits */
74 #define FE_CNT_PPE_AF BIT(31)
75 #define FE_CNT_GDM_AF BIT(29)
76 #define FE_PSE_P2_FC BIT(26)
77 #define FE_PSE_BUF_DROP BIT(24)
78 #define FE_GDM_OTHER_DROP BIT(23)
79 #define FE_PSE_P1_FC BIT(22)
80 #define FE_PSE_P0_FC BIT(21)
81 #define FE_PSE_FQ_EMPTY BIT(20)
82 #define FE_GE1_STA_CHG BIT(18)
83 #define FE_TX_COHERENT BIT(17)
84 #define FE_RX_COHERENT BIT(16)
85 #define FE_TX_DONE_INT3 BIT(11)
86 #define FE_TX_DONE_INT2 BIT(10)
87 #define FE_TX_DONE_INT1 BIT(9)
88 #define FE_TX_DONE_INT0 BIT(8)
89 #define FE_RX_DONE_INT0 BIT(2)
90 #define FE_TX_DLY_INT BIT(1)
91 #define FE_RX_DLY_INT BIT(0)
92
93 #define FE_RX_DONE_INT FE_RX_DONE_INT0
94 #define FE_TX_DONE_INT (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
95 FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
96
97 #define RT5350_RX_DLY_INT BIT(30)
98 #define RT5350_TX_DLY_INT BIT(28)
99 #define RT5350_RX_DONE_INT1 BIT(17)
100 #define RT5350_RX_DONE_INT0 BIT(16)
101 #define RT5350_TX_DONE_INT3 BIT(3)
102 #define RT5350_TX_DONE_INT2 BIT(2)
103 #define RT5350_TX_DONE_INT1 BIT(1)
104 #define RT5350_TX_DONE_INT0 BIT(0)
105
106 #define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
107 #define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
108 RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
109
110 /* registers */
111 #define FE_FE_OFFSET 0x0000
112 #define FE_GDMA_OFFSET 0x0020
113 #define FE_PSE_OFFSET 0x0040
114 #define FE_GDMA2_OFFSET 0x0060
115 #define FE_CDMA_OFFSET 0x0080
116 #define FE_DMA_VID0 0x00a8
117 #define FE_PDMA_OFFSET 0x0100
118 #define FE_PPE_OFFSET 0x0200
119 #define FE_CMTABLE_OFFSET 0x0400
120 #define FE_POLICYTABLE_OFFSET 0x1000
121
122 #define RT5350_PDMA_OFFSET 0x0800
123 #define RT5350_SDM_OFFSET 0x0c00
124
125 #define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
126 #define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
127 #define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
128 #define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
129 #define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
130 #define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
131 #define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
132 #define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
133
134 #define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
135 #define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
136 #define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
137 #define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
138 #define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
139
140 #define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
141 #define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
142 #define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
143 #define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
144 #define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
145
146 #define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
147 #define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
148 #define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
149 #define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
150
151 #define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
152 #define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
153
154 #ifdef CONFIG_SOC_MT7621
155 #define MT7620A_GDMA_OFFSET 0x0500
156 #else
157 #define MT7620A_GDMA_OFFSET 0x0600
158 #endif
159 #define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
160 #define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
161 #define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
162 #define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
163 #define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
164
165 #define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
166 #define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
167 #define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
168 #define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
169 #define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
170 #define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
171 #define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
172 #define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
173 #define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
174 #define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
175 #define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
176 #define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
177 #define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
178 #define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
179 #define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
180 #define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
181 #define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
182 #define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
183 #define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
184 #define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
185 #define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
186 #define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
187 #define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
188 #define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
189 #define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
190 #define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
191 #define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
192 #define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
193 #define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
194 #define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
195
196 #define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
197 #define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
198 #define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
199 #define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
200 #define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
201 #define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
202 #define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
203 #define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
204 #define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
205 #define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
206 #define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
207 #define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
208 #define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
209 #define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
210 #define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
211 #define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
212 #define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
213 #define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
214 #define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
215 #define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
216 #define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
217 #define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
218 #define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
219 #define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
220 #define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
221 #define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
222 #define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
223 #define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
224
225 #define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
226 #define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
227 #define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
228 #define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
229 #define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
230 #define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
231 #define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
232 #define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
233 #define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
234 #define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
235
236 #define RT5350_SDM_ICS_EN BIT(16)
237 #define RT5350_SDM_TCS_EN BIT(17)
238 #define RT5350_SDM_UCS_EN BIT(18)
239
240
241 /* MDIO_CFG register bits */
242 #define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
243 #define FE_MDIO_CFG_GP1_BP_EN BIT(16)
244 #define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
245 #define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
246 #define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
247 #define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
248 #define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
249 #define FE_MDIO_CFG_GP1_FC_TX BIT(11)
250 #define FE_MDIO_CFG_GP1_FC_RX BIT(10)
251 #define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
252 #define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
253 #define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
254 #define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
255 #define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
256 #define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
257 #define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
258 #define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
259 #define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
260 #define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
261 #define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
262 #define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
263 #define FE_MDIO_CFG_TX_CLK_SKEW_0 0
264 #define FE_MDIO_CFG_TX_CLK_SKEW_200 1
265 #define FE_MDIO_CFG_TX_CLK_SKEW_400 2
266 #define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
267
268 /* uni-cast port */
269 #define FE_GDM1_JMB_LEN_MASK 0xf
270 #define FE_GDM1_JMB_LEN_SHIFT 28
271 #define FE_GDM1_ICS_EN BIT(22)
272 #define FE_GDM1_TCS_EN BIT(21)
273 #define FE_GDM1_UCS_EN BIT(20)
274 #define FE_GDM1_JMB_EN BIT(19)
275 #define FE_GDM1_STRPCRC BIT(16)
276 #define FE_GDM1_UFRC_P_CPU (0 << 12)
277 #define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
278 #define FE_GDM1_UFRC_P_PPE (6 << 12)
279
280 /* checksums */
281 #define FE_ICS_GEN_EN BIT(2)
282 #define FE_UCS_GEN_EN BIT(1)
283 #define FE_TCS_GEN_EN BIT(0)
284
285 /* dma ring */
286 #define FE_PST_DRX_IDX0 BIT(16)
287 #define FE_PST_DTX_IDX3 BIT(3)
288 #define FE_PST_DTX_IDX2 BIT(2)
289 #define FE_PST_DTX_IDX1 BIT(1)
290 #define FE_PST_DTX_IDX0 BIT(0)
291
292 #define FE_RX_2B_OFFSET BIT(31)
293 #define FE_TX_WB_DDONE BIT(6)
294 #define FE_RX_DMA_BUSY BIT(3)
295 #define FE_TX_DMA_BUSY BIT(1)
296 #define FE_RX_DMA_EN BIT(2)
297 #define FE_TX_DMA_EN BIT(0)
298
299 #define FE_PDMA_SIZE_4DWORDS (0 << 4)
300 #define FE_PDMA_SIZE_8DWORDS (1 << 4)
301 #define FE_PDMA_SIZE_16DWORDS (2 << 4)
302
303 #define FE_US_CYC_CNT_MASK 0xff
304 #define FE_US_CYC_CNT_SHIFT 0x8
305 #define FE_US_CYC_CNT_DIVISOR 1000000
306
307 /* rxd2 */
308 #define RX_DMA_DONE BIT(31)
309 #define RX_DMA_LSO BIT(30)
310 #define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
311 #define RX_DMA_TAG BIT(15)
312 /* rxd3 */
313 #define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff)
314 #define RX_DMA_VID(_x) ((_x) & 0xffff)
315 /* rxd4 */
316 #define RX_DMA_L4VALID BIT(30)
317
318 struct fe_rx_dma {
319 unsigned int rxd1;
320 unsigned int rxd2;
321 unsigned int rxd3;
322 unsigned int rxd4;
323 } __packed __aligned(4);
324
325 #define TX_DMA_BUF_LEN 0x3fff
326 #define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16)
327 #define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16)
328 #define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
329 #define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & TX_DMA_BUF_LEN)
330 #define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
331 #define TX_DMA_LS1 BIT(14)
332 #define TX_DMA_LS0 BIT(30)
333 #define TX_DMA_DONE BIT(31)
334
335 #define TX_DMA_INS_VLAN_MT7621 BIT(16)
336 #define TX_DMA_INS_VLAN BIT(7)
337 #define TX_DMA_INS_PPPOE BIT(12)
338 #define TX_DMA_QN(_x) ((_x) << 16)
339 #define TX_DMA_PN(_x) ((_x) << 24)
340 #define TX_DMA_QN_MASK TX_DMA_QN(0x7)
341 #define TX_DMA_PN_MASK TX_DMA_PN(0x7)
342 #define TX_DMA_UDF BIT(20)
343 #define TX_DMA_CHKSUM (0x7 << 29)
344 #define TX_DMA_TSO BIT(28)
345
346 /* frame engine counters */
347 #define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
348 #define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
349 #define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
350
351 /* phy device flags */
352 #define FE_PHY_FLAG_PORT BIT(0)
353 #define FE_PHY_FLAG_ATTACH BIT(1)
354
355 struct fe_tx_dma {
356 unsigned int txd1;
357 unsigned int txd2;
358 unsigned int txd3;
359 unsigned int txd4;
360 } __packed __aligned(4);
361
362 struct fe_priv;
363
364 struct fe_phy {
365 struct phy_device *phy[8];
366 struct device_node *phy_node[8];
367 const __be32 *phy_fixed[8];
368 int duplex[8];
369 int speed[8];
370 int tx_fc[8];
371 int rx_fc[8];
372 spinlock_t lock;
373
374 int (*connect)(struct fe_priv *priv);
375 void (*disconnect)(struct fe_priv *priv);
376 void (*start)(struct fe_priv *priv);
377 void (*stop)(struct fe_priv *priv);
378 };
379
380 struct fe_soc_data
381 {
382 unsigned char mac[6];
383 const u32 *reg_table;
384
385 void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
386 void (*reset_fe)(void);
387 void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
388 int (*fwd_config)(struct fe_priv *priv);
389 void (*tx_dma)(struct fe_tx_dma *txd);
390 int (*switch_init)(struct fe_priv *priv);
391 int (*switch_config)(struct fe_priv *priv);
392 void (*port_init)(struct fe_priv *priv, struct device_node *port);
393 int (*has_carrier)(struct fe_priv *priv);
394 int (*mdio_init)(struct fe_priv *priv);
395 void (*mdio_cleanup)(struct fe_priv *priv);
396 int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
397 int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
398 void (*mdio_adjust_link)(struct fe_priv *priv, int port);
399
400 void *swpriv;
401 u32 pdma_glo_cfg;
402 u32 rx_int;
403 u32 tx_int;
404 u32 checksum_bit;
405 };
406
407 #define FE_FLAG_PADDING_64B BIT(0)
408 #define FE_FLAG_PADDING_BUG BIT(1)
409 #define FE_FLAG_JUMBO_FRAME BIT(2)
410 #define FE_FLAG_RX_2B_OFFSET BIT(3)
411 #define FE_FLAG_RX_SG_DMA BIT(4)
412 #define FE_FLAG_RX_VLAN_CTAG BIT(5)
413 #define FE_FLAG_NAPI_WEIGHT BIT(6)
414
415 #define FE_STAT_REG_DECLARE \
416 _FE(tx_bytes) \
417 _FE(tx_packets) \
418 _FE(tx_skip) \
419 _FE(tx_collisions) \
420 _FE(rx_bytes) \
421 _FE(rx_packets) \
422 _FE(rx_overflow) \
423 _FE(rx_fcs_errors) \
424 _FE(rx_short_errors) \
425 _FE(rx_long_errors) \
426 _FE(rx_checksum_errors) \
427 _FE(rx_flow_control_packets)
428
429 struct fe_hw_stats
430 {
431 spinlock_t stats_lock;
432 struct u64_stats_sync syncp;
433 #define _FE(x) u64 x;
434 FE_STAT_REG_DECLARE
435 #undef _FE
436 };
437
438 enum fe_tx_flags {
439 FE_TX_FLAGS_SINGLE0 = 0x01,
440 FE_TX_FLAGS_PAGE0 = 0x02,
441 FE_TX_FLAGS_PAGE1 = 0x04,
442 };
443
444 struct fe_tx_buf
445 {
446 struct sk_buff *skb;
447 u32 flags;
448 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
449 DEFINE_DMA_UNMAP_LEN(dma_len0);
450 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
451 DEFINE_DMA_UNMAP_LEN(dma_len1);
452 };
453
454 struct fe_priv
455 {
456 spinlock_t page_lock;
457
458 struct fe_soc_data *soc;
459 struct net_device *netdev;
460 u32 msg_enable;
461 u32 flags;
462
463 struct device *device;
464 unsigned long sysclk;
465
466 u16 frag_size;
467 u16 rx_buf_size;
468 struct fe_rx_dma *rx_dma;
469 u8 **rx_data;
470 dma_addr_t rx_phys;
471 struct napi_struct rx_napi;
472
473 struct fe_tx_dma *tx_dma;
474 struct fe_tx_buf *tx_buf;
475 dma_addr_t tx_phys;
476 unsigned int tx_free_idx;
477
478 struct fe_phy *phy;
479 struct mii_bus *mii_bus;
480 struct phy_device *phy_dev;
481 u32 phy_flags;
482
483 int link[8];
484
485 struct fe_hw_stats *hw_stats;
486 unsigned long vlan_map;
487 struct work_struct pending_work;
488 DECLARE_BITMAP(pending_flags, FE_FLAG_MAX);
489 };
490
491 extern const struct of_device_id of_fe_match[];
492
493 void fe_w32(u32 val, unsigned reg);
494 u32 fe_r32(unsigned reg);
495
496 int fe_set_clock_cycle(struct fe_priv *priv);
497 void fe_csum_config(struct fe_priv *priv);
498 void fe_stats_update(struct fe_priv *priv);
499 void fe_fwd_config(struct fe_priv *priv);
500 void fe_reg_w32(u32 val, enum fe_reg reg);
501 u32 fe_reg_r32(enum fe_reg reg);
502
503 void fe_reset(u32 reset_bits);
504
505 static inline void *priv_netdev(struct fe_priv *priv)
506 {
507 return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
508 }
509
510 #endif /* FE_ETH_H */
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