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ralink: fix hw status almost full not work on mt7620 and mt7621
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.h
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * based on Ralink SDK3.3
16 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
17 */
18
19 #ifndef FE_ETH_H
20 #define FE_ETH_H
21
22 #include <linux/mii.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/phy.h>
27 #include <linux/ethtool.h>
28 #include <linux/version.h>
29
30 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
31 #define u64_stats_fetch_retry_irq u64_stats_fetch_retry_bh
32 #define u64_stats_fetch_begin_irq u64_stats_fetch_begin_bh
33 #endif
34
35 enum fe_reg {
36 FE_REG_PDMA_GLO_CFG = 0,
37 FE_REG_PDMA_RST_CFG,
38 FE_REG_DLY_INT_CFG,
39 FE_REG_TX_BASE_PTR0,
40 FE_REG_TX_MAX_CNT0,
41 FE_REG_TX_CTX_IDX0,
42 FE_REG_TX_DTX_IDX0,
43 FE_REG_RX_BASE_PTR0,
44 FE_REG_RX_MAX_CNT0,
45 FE_REG_RX_CALC_IDX0,
46 FE_REG_RX_DRX_IDX0,
47 FE_REG_FE_INT_ENABLE,
48 FE_REG_FE_INT_STATUS,
49 FE_REG_FE_DMA_VID_BASE,
50 FE_REG_FE_COUNTER_BASE,
51 FE_REG_FE_RST_GL,
52 FE_REG_FE_INT_STATUS2,
53 FE_REG_COUNT
54 };
55
56 enum fe_work_flag {
57 FE_FLAG_RESET_PENDING,
58 FE_FLAG_MAX
59 };
60
61 #define FE_DRV_VERSION "0.1.2"
62
63 /* power of 2 to let NEXT_TX_DESP_IDX work */
64 #ifdef CONFIG_SOC_MT7621
65 #define NUM_DMA_DESC (1 << 9)
66 #else
67 #define NUM_DMA_DESC (1 << 7)
68 #endif
69 #define MAX_DMA_DESC 0xfff
70
71 #define FE_DELAY_EN_INT 0x80
72 #define FE_DELAY_MAX_INT 0x04
73 #define FE_DELAY_MAX_TOUT 0x04
74 #define FE_DELAY_TIME 20
75 #define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
76 #define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
77 #define FE_PSE_FQFC_CFG_INIT 0x80504000
78 #define FE_PSE_FQFC_CFG_256Q 0xff908000
79
80 /* interrupt bits */
81 #define FE_CNT_PPE_AF BIT(31)
82 #define FE_CNT_GDM_AF BIT(29)
83 #define FE_PSE_P2_FC BIT(26)
84 #define FE_PSE_BUF_DROP BIT(24)
85 #define FE_GDM_OTHER_DROP BIT(23)
86 #define FE_PSE_P1_FC BIT(22)
87 #define FE_PSE_P0_FC BIT(21)
88 #define FE_PSE_FQ_EMPTY BIT(20)
89 #define FE_GE1_STA_CHG BIT(18)
90 #define FE_TX_COHERENT BIT(17)
91 #define FE_RX_COHERENT BIT(16)
92 #define FE_TX_DONE_INT3 BIT(11)
93 #define FE_TX_DONE_INT2 BIT(10)
94 #define FE_TX_DONE_INT1 BIT(9)
95 #define FE_TX_DONE_INT0 BIT(8)
96 #define FE_RX_DONE_INT0 BIT(2)
97 #define FE_TX_DLY_INT BIT(1)
98 #define FE_RX_DLY_INT BIT(0)
99
100 #define FE_RX_DONE_INT FE_RX_DONE_INT0
101 #define FE_TX_DONE_INT (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
102 FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
103
104 #define RT5350_RX_DLY_INT BIT(30)
105 #define RT5350_TX_DLY_INT BIT(28)
106 #define RT5350_RX_DONE_INT1 BIT(17)
107 #define RT5350_RX_DONE_INT0 BIT(16)
108 #define RT5350_TX_DONE_INT3 BIT(3)
109 #define RT5350_TX_DONE_INT2 BIT(2)
110 #define RT5350_TX_DONE_INT1 BIT(1)
111 #define RT5350_TX_DONE_INT0 BIT(0)
112
113 #define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
114 #define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
115 RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
116
117 /* registers */
118 #define FE_FE_OFFSET 0x0000
119 #define FE_GDMA_OFFSET 0x0020
120 #define FE_PSE_OFFSET 0x0040
121 #define FE_GDMA2_OFFSET 0x0060
122 #define FE_CDMA_OFFSET 0x0080
123 #define FE_DMA_VID0 0x00a8
124 #define FE_PDMA_OFFSET 0x0100
125 #define FE_PPE_OFFSET 0x0200
126 #define FE_CMTABLE_OFFSET 0x0400
127 #define FE_POLICYTABLE_OFFSET 0x1000
128
129 #define RT5350_PDMA_OFFSET 0x0800
130 #define RT5350_SDM_OFFSET 0x0c00
131
132 #define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
133 #define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
134 #define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
135 #define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
136 #define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
137 #define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
138 #define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
139 #define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
140
141 #define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
142 #define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
143 #define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
144 #define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
145 #define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
146
147 #define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
148 #define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
149 #define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
150 #define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
151 #define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
152
153 #define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
154 #define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
155 #define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
156 #define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
157
158 #define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
159 #define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
160
161 #ifdef CONFIG_SOC_MT7621
162 #define MT7620A_GDMA_OFFSET 0x0500
163 #else
164 #define MT7620A_GDMA_OFFSET 0x0600
165 #endif
166 #define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
167 #define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
168 #define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
169 #define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
170 #define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
171
172 #define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
173 #define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
174 #define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
175 #define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
176 #define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
177 #define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
178 #define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
179 #define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
180 #define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
181 #define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
182 #define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
183 #define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
184 #define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
185 #define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
186 #define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
187 #define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
188 #define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
189 #define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
190 #define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
191 #define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
192 #define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
193 #define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
194 #define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
195 #define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
196 #define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
197 #define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
198 #define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
199 #define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
200 #define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
201 #define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
202
203 #define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
204 #define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
205 #define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
206 #define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
207 #define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
208 #define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
209 #define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
210 #define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
211 #define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
212 #define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
213 #define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
214 #define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
215 #define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
216 #define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
217 #define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
218 #define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
219 #define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
220 #define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
221 #define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
222 #define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
223 #define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
224 #define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
225 #define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
226 #define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
227 #define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
228 #define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
229 #define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
230 #define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
231
232 #define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
233 #define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
234 #define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
235 #define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
236 #define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
237 #define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
238 #define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
239 #define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
240 #define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
241 #define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
242
243 #define RT5350_SDM_ICS_EN BIT(16)
244 #define RT5350_SDM_TCS_EN BIT(17)
245 #define RT5350_SDM_UCS_EN BIT(18)
246
247
248 /* MDIO_CFG register bits */
249 #define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
250 #define FE_MDIO_CFG_GP1_BP_EN BIT(16)
251 #define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
252 #define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
253 #define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
254 #define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
255 #define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
256 #define FE_MDIO_CFG_GP1_FC_TX BIT(11)
257 #define FE_MDIO_CFG_GP1_FC_RX BIT(10)
258 #define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
259 #define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
260 #define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
261 #define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
262 #define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
263 #define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
264 #define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
265 #define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
266 #define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
267 #define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
268 #define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
269 #define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
270 #define FE_MDIO_CFG_TX_CLK_SKEW_0 0
271 #define FE_MDIO_CFG_TX_CLK_SKEW_200 1
272 #define FE_MDIO_CFG_TX_CLK_SKEW_400 2
273 #define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
274
275 /* uni-cast port */
276 #define FE_GDM1_JMB_LEN_MASK 0xf
277 #define FE_GDM1_JMB_LEN_SHIFT 28
278 #define FE_GDM1_ICS_EN BIT(22)
279 #define FE_GDM1_TCS_EN BIT(21)
280 #define FE_GDM1_UCS_EN BIT(20)
281 #define FE_GDM1_JMB_EN BIT(19)
282 #define FE_GDM1_STRPCRC BIT(16)
283 #define FE_GDM1_UFRC_P_CPU (0 << 12)
284 #define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
285 #define FE_GDM1_UFRC_P_PPE (6 << 12)
286
287 /* checksums */
288 #define FE_ICS_GEN_EN BIT(2)
289 #define FE_UCS_GEN_EN BIT(1)
290 #define FE_TCS_GEN_EN BIT(0)
291
292 /* dma ring */
293 #define FE_PST_DRX_IDX0 BIT(16)
294 #define FE_PST_DTX_IDX3 BIT(3)
295 #define FE_PST_DTX_IDX2 BIT(2)
296 #define FE_PST_DTX_IDX1 BIT(1)
297 #define FE_PST_DTX_IDX0 BIT(0)
298
299 #define FE_RX_2B_OFFSET BIT(31)
300 #define FE_TX_WB_DDONE BIT(6)
301 #define FE_RX_DMA_BUSY BIT(3)
302 #define FE_TX_DMA_BUSY BIT(1)
303 #define FE_RX_DMA_EN BIT(2)
304 #define FE_TX_DMA_EN BIT(0)
305
306 #define FE_PDMA_SIZE_4DWORDS (0 << 4)
307 #define FE_PDMA_SIZE_8DWORDS (1 << 4)
308 #define FE_PDMA_SIZE_16DWORDS (2 << 4)
309
310 #define FE_US_CYC_CNT_MASK 0xff
311 #define FE_US_CYC_CNT_SHIFT 0x8
312 #define FE_US_CYC_CNT_DIVISOR 1000000
313
314 /* rxd2 */
315 #define RX_DMA_DONE BIT(31)
316 #define RX_DMA_LSO BIT(30)
317 #define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
318 #define RX_DMA_TAG BIT(15)
319 /* rxd3 */
320 #define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff)
321 #define RX_DMA_VID(_x) ((_x) & 0xffff)
322 /* rxd4 */
323 #define RX_DMA_L4VALID BIT(30)
324
325 struct fe_rx_dma {
326 unsigned int rxd1;
327 unsigned int rxd2;
328 unsigned int rxd3;
329 unsigned int rxd4;
330 } __packed __aligned(4);
331
332 #define TX_DMA_BUF_LEN 0x3fff
333 #define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16)
334 #define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16)
335 #define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
336 #define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & TX_DMA_BUF_LEN)
337 #define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
338 #define TX_DMA_LS1 BIT(14)
339 #define TX_DMA_LS0 BIT(30)
340 #define TX_DMA_DONE BIT(31)
341
342 #define TX_DMA_INS_VLAN_MT7621 BIT(16)
343 #define TX_DMA_INS_VLAN BIT(7)
344 #define TX_DMA_INS_PPPOE BIT(12)
345 #define TX_DMA_QN(_x) ((_x) << 16)
346 #define TX_DMA_PN(_x) ((_x) << 24)
347 #define TX_DMA_QN_MASK TX_DMA_QN(0x7)
348 #define TX_DMA_PN_MASK TX_DMA_PN(0x7)
349 #define TX_DMA_UDF BIT(20)
350 #define TX_DMA_CHKSUM (0x7 << 29)
351 #define TX_DMA_TSO BIT(28)
352
353 /* frame engine counters */
354 #define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
355 #define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
356 #define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
357
358 /* phy device flags */
359 #define FE_PHY_FLAG_PORT BIT(0)
360 #define FE_PHY_FLAG_ATTACH BIT(1)
361
362 struct fe_tx_dma {
363 unsigned int txd1;
364 unsigned int txd2;
365 unsigned int txd3;
366 unsigned int txd4;
367 } __packed __aligned(4);
368
369 struct fe_priv;
370
371 struct fe_phy {
372 struct phy_device *phy[8];
373 struct device_node *phy_node[8];
374 const __be32 *phy_fixed[8];
375 int duplex[8];
376 int speed[8];
377 int tx_fc[8];
378 int rx_fc[8];
379 spinlock_t lock;
380
381 int (*connect)(struct fe_priv *priv);
382 void (*disconnect)(struct fe_priv *priv);
383 void (*start)(struct fe_priv *priv);
384 void (*stop)(struct fe_priv *priv);
385 };
386
387 struct fe_soc_data
388 {
389 unsigned char mac[6];
390 const u32 *reg_table;
391
392 void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
393 void (*reset_fe)(void);
394 void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
395 int (*fwd_config)(struct fe_priv *priv);
396 void (*tx_dma)(struct fe_tx_dma *txd);
397 int (*switch_init)(struct fe_priv *priv);
398 int (*switch_config)(struct fe_priv *priv);
399 void (*port_init)(struct fe_priv *priv, struct device_node *port);
400 int (*has_carrier)(struct fe_priv *priv);
401 int (*mdio_init)(struct fe_priv *priv);
402 void (*mdio_cleanup)(struct fe_priv *priv);
403 int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
404 int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
405 void (*mdio_adjust_link)(struct fe_priv *priv, int port);
406
407 void *swpriv;
408 u32 pdma_glo_cfg;
409 u32 rx_int;
410 u32 tx_int;
411 u32 status_int;
412 u32 checksum_bit;
413 };
414
415 #define FE_FLAG_PADDING_64B BIT(0)
416 #define FE_FLAG_PADDING_BUG BIT(1)
417 #define FE_FLAG_JUMBO_FRAME BIT(2)
418 #define FE_FLAG_RX_2B_OFFSET BIT(3)
419 #define FE_FLAG_RX_SG_DMA BIT(4)
420 #define FE_FLAG_RX_VLAN_CTAG BIT(5)
421 #define FE_FLAG_NAPI_WEIGHT BIT(6)
422
423 #define FE_STAT_REG_DECLARE \
424 _FE(tx_bytes) \
425 _FE(tx_packets) \
426 _FE(tx_skip) \
427 _FE(tx_collisions) \
428 _FE(rx_bytes) \
429 _FE(rx_packets) \
430 _FE(rx_overflow) \
431 _FE(rx_fcs_errors) \
432 _FE(rx_short_errors) \
433 _FE(rx_long_errors) \
434 _FE(rx_checksum_errors) \
435 _FE(rx_flow_control_packets)
436
437 struct fe_hw_stats
438 {
439 spinlock_t stats_lock;
440 struct u64_stats_sync syncp;
441 #define _FE(x) u64 x;
442 FE_STAT_REG_DECLARE
443 #undef _FE
444 };
445
446 enum fe_tx_flags {
447 FE_TX_FLAGS_SINGLE0 = 0x01,
448 FE_TX_FLAGS_PAGE0 = 0x02,
449 FE_TX_FLAGS_PAGE1 = 0x04,
450 };
451
452 struct fe_tx_buf
453 {
454 struct sk_buff *skb;
455 u32 flags;
456 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
457 DEFINE_DMA_UNMAP_LEN(dma_len0);
458 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
459 DEFINE_DMA_UNMAP_LEN(dma_len1);
460 };
461
462 struct fe_priv
463 {
464 spinlock_t page_lock;
465
466 struct fe_soc_data *soc;
467 struct net_device *netdev;
468 u32 msg_enable;
469 u32 flags;
470
471 struct device *device;
472 unsigned long sysclk;
473
474 u16 frag_size;
475 u16 rx_buf_size;
476 struct fe_rx_dma *rx_dma;
477 u8 **rx_data;
478 dma_addr_t rx_phys;
479 struct napi_struct rx_napi;
480
481 struct fe_tx_dma *tx_dma;
482 struct fe_tx_buf *tx_buf;
483 dma_addr_t tx_phys;
484 unsigned int tx_free_idx;
485
486 struct fe_phy *phy;
487 struct mii_bus *mii_bus;
488 struct phy_device *phy_dev;
489 u32 phy_flags;
490
491 int link[8];
492
493 struct fe_hw_stats *hw_stats;
494 unsigned long vlan_map;
495 struct work_struct pending_work;
496 DECLARE_BITMAP(pending_flags, FE_FLAG_MAX);
497 };
498
499 extern const struct of_device_id of_fe_match[];
500
501 void fe_w32(u32 val, unsigned reg);
502 u32 fe_r32(unsigned reg);
503
504 int fe_set_clock_cycle(struct fe_priv *priv);
505 void fe_csum_config(struct fe_priv *priv);
506 void fe_stats_update(struct fe_priv *priv);
507 void fe_fwd_config(struct fe_priv *priv);
508 void fe_reg_w32(u32 val, enum fe_reg reg);
509 u32 fe_reg_r32(enum fe_reg reg);
510
511 void fe_reset(u32 reset_bits);
512
513 static inline void *priv_netdev(struct fe_priv *priv)
514 {
515 return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
516 }
517
518 #endif /* FE_ETH_H */
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