ralink: reduce access to uncached tx/rx dma ring buffer
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.h
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * based on Ralink SDK3.3
16 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
17 */
18
19 #ifndef FE_ETH_H
20 #define FE_ETH_H
21
22 #include <linux/mii.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/phy.h>
27 #include <linux/ethtool.h>
28
29 enum fe_reg {
30 FE_REG_PDMA_GLO_CFG = 0,
31 FE_REG_PDMA_RST_CFG,
32 FE_REG_DLY_INT_CFG,
33 FE_REG_TX_BASE_PTR0,
34 FE_REG_TX_MAX_CNT0,
35 FE_REG_TX_CTX_IDX0,
36 FE_REG_RX_BASE_PTR0,
37 FE_REG_RX_MAX_CNT0,
38 FE_REG_RX_CALC_IDX0,
39 FE_REG_FE_INT_ENABLE,
40 FE_REG_FE_INT_STATUS,
41 FE_REG_FE_DMA_VID_BASE,
42 FE_REG_FE_COUNTER_BASE,
43 FE_REG_FE_RST_GL,
44 FE_REG_COUNT
45 };
46
47 #define FE_DRV_VERSION "0.1.0"
48
49 /* power of 2 to let NEXT_TX_DESP_IDX work */
50 #ifdef CONFIG_SOC_MT7621
51 #define NUM_DMA_DESC (1 << 9)
52 #else
53 #define NUM_DMA_DESC (1 << 7)
54 #endif
55 #define MAX_DMA_DESC 0xfff
56
57 #define FE_DELAY_EN_INT 0x80
58 #define FE_DELAY_MAX_INT 0x04
59 #define FE_DELAY_MAX_TOUT 0x04
60 #define FE_DELAY_TIME 20
61 #define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
62 #define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
63 #define FE_PSE_FQFC_CFG_INIT 0x80504000
64 #define FE_PSE_FQFC_CFG_256Q 0xff908000
65
66 /* interrupt bits */
67 #define FE_CNT_PPE_AF BIT(31)
68 #define FE_CNT_GDM_AF BIT(29)
69 #define FE_PSE_P2_FC BIT(26)
70 #define FE_PSE_BUF_DROP BIT(24)
71 #define FE_GDM_OTHER_DROP BIT(23)
72 #define FE_PSE_P1_FC BIT(22)
73 #define FE_PSE_P0_FC BIT(21)
74 #define FE_PSE_FQ_EMPTY BIT(20)
75 #define FE_GE1_STA_CHG BIT(18)
76 #define FE_TX_COHERENT BIT(17)
77 #define FE_RX_COHERENT BIT(16)
78 #define FE_TX_DONE_INT3 BIT(11)
79 #define FE_TX_DONE_INT2 BIT(10)
80 #define FE_TX_DONE_INT1 BIT(9)
81 #define FE_TX_DONE_INT0 BIT(8)
82 #define FE_RX_DONE_INT0 BIT(2)
83 #define FE_TX_DLY_INT BIT(1)
84 #define FE_RX_DLY_INT BIT(0)
85
86 #define FE_RX_DONE_INT FE_RX_DONE_INT0
87 #define FE_TX_DONE_INT (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
88 FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
89
90 #define RT5350_RX_DLY_INT BIT(30)
91 #define RT5350_TX_DLY_INT BIT(28)
92 #define RT5350_RX_DONE_INT1 BIT(17)
93 #define RT5350_RX_DONE_INT0 BIT(16)
94 #define RT5350_TX_DONE_INT3 BIT(3)
95 #define RT5350_TX_DONE_INT2 BIT(2)
96 #define RT5350_TX_DONE_INT1 BIT(1)
97 #define RT5350_TX_DONE_INT0 BIT(0)
98
99 #define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
100 #define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
101 RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
102
103 /* registers */
104 #define FE_FE_OFFSET 0x0000
105 #define FE_GDMA_OFFSET 0x0020
106 #define FE_PSE_OFFSET 0x0040
107 #define FE_GDMA2_OFFSET 0x0060
108 #define FE_CDMA_OFFSET 0x0080
109 #define FE_DMA_VID0 0x00a8
110 #define FE_PDMA_OFFSET 0x0100
111 #define FE_PPE_OFFSET 0x0200
112 #define FE_CMTABLE_OFFSET 0x0400
113 #define FE_POLICYTABLE_OFFSET 0x1000
114
115 #define RT5350_PDMA_OFFSET 0x0800
116 #define RT5350_SDM_OFFSET 0x0c00
117
118 #define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
119 #define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
120 #define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
121 #define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
122 #define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
123 #define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
124 #define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
125 #define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
126
127 #define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
128 #define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
129 #define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
130 #define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
131 #define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
132
133 #define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
134 #define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
135 #define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
136 #define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
137 #define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
138
139 #define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
140 #define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
141 #define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
142 #define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
143
144 #define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
145 #define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
146
147 #ifdef CONFIG_SOC_MT7621
148 #define MT7620A_GDMA_OFFSET 0x0500
149 #else
150 #define MT7620A_GDMA_OFFSET 0x0600
151 #endif
152 #define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
153 #define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
154 #define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
155 #define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
156 #define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
157
158 #define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
159 #define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
160 #define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
161 #define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
162 #define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
163 #define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
164 #define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
165 #define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
166 #define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
167 #define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
168 #define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
169 #define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
170 #define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
171 #define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
172 #define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
173 #define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
174 #define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
175 #define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
176 #define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
177 #define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
178 #define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
179 #define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
180 #define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
181 #define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
182 #define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
183 #define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
184 #define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
185 #define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
186 #define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
187 #define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
188
189 #define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
190 #define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
191 #define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
192 #define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
193 #define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
194 #define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
195 #define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
196 #define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
197 #define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
198 #define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
199 #define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
200 #define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
201 #define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
202 #define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
203 #define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
204 #define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
205 #define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
206 #define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
207 #define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
208 #define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
209 #define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
210 #define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
211 #define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
212 #define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
213 #define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
214 #define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
215 #define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
216 #define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
217
218 #define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
219 #define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
220 #define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
221 #define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
222 #define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
223 #define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
224 #define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
225 #define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
226 #define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
227 #define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
228
229 #define RT5350_SDM_ICS_EN BIT(16)
230 #define RT5350_SDM_TCS_EN BIT(17)
231 #define RT5350_SDM_UCS_EN BIT(18)
232
233
234 /* MDIO_CFG register bits */
235 #define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
236 #define FE_MDIO_CFG_GP1_BP_EN BIT(16)
237 #define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
238 #define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
239 #define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
240 #define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
241 #define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
242 #define FE_MDIO_CFG_GP1_FC_TX BIT(11)
243 #define FE_MDIO_CFG_GP1_FC_RX BIT(10)
244 #define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
245 #define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
246 #define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
247 #define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
248 #define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
249 #define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
250 #define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
251 #define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
252 #define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
253 #define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
254 #define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
255 #define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
256 #define FE_MDIO_CFG_TX_CLK_SKEW_0 0
257 #define FE_MDIO_CFG_TX_CLK_SKEW_200 1
258 #define FE_MDIO_CFG_TX_CLK_SKEW_400 2
259 #define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
260
261 /* uni-cast port */
262 #define FE_GDM1_JMB_LEN_MASK 0xf
263 #define FE_GDM1_JMB_LEN_SHIFT 28
264 #define FE_GDM1_ICS_EN BIT(22)
265 #define FE_GDM1_TCS_EN BIT(21)
266 #define FE_GDM1_UCS_EN BIT(20)
267 #define FE_GDM1_JMB_EN BIT(19)
268 #define FE_GDM1_STRPCRC BIT(16)
269 #define FE_GDM1_UFRC_P_CPU (0 << 12)
270 #define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
271 #define FE_GDM1_UFRC_P_PPE (6 << 12)
272
273 /* checksums */
274 #define FE_ICS_GEN_EN BIT(2)
275 #define FE_UCS_GEN_EN BIT(1)
276 #define FE_TCS_GEN_EN BIT(0)
277
278 /* dma ring */
279 #define FE_PST_DRX_IDX0 BIT(16)
280 #define FE_PST_DTX_IDX3 BIT(3)
281 #define FE_PST_DTX_IDX2 BIT(2)
282 #define FE_PST_DTX_IDX1 BIT(1)
283 #define FE_PST_DTX_IDX0 BIT(0)
284
285 #define FE_TX_WB_DDONE BIT(6)
286 #define FE_RX_DMA_BUSY BIT(3)
287 #define FE_TX_DMA_BUSY BIT(1)
288 #define FE_RX_DMA_EN BIT(2)
289 #define FE_TX_DMA_EN BIT(0)
290
291 #define FE_PDMA_SIZE_4DWORDS (0 << 4)
292 #define FE_PDMA_SIZE_8DWORDS (1 << 4)
293 #define FE_PDMA_SIZE_16DWORDS (2 << 4)
294
295 #define FE_US_CYC_CNT_MASK 0xff
296 #define FE_US_CYC_CNT_SHIFT 0x8
297 #define FE_US_CYC_CNT_DIVISOR 1000000
298
299 #define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
300 #define RX_DMA_LSO BIT(30)
301 #define RX_DMA_DONE BIT(31)
302 #define RX_DMA_L4VALID BIT(30)
303
304 struct fe_rx_dma {
305 unsigned int rxd1;
306 unsigned int rxd2;
307 unsigned int rxd3;
308 unsigned int rxd4;
309 } __packed __aligned(4);
310
311 #define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
312 #define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
313 #define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
314 #define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & 0x3fff)
315 #define TX_DMA_GET_PLEN1(_x) ((_x) & 0x3fff)
316 #define TX_DMA_LS1 BIT(14)
317 #define TX_DMA_LS0 BIT(30)
318 #define TX_DMA_DONE BIT(31)
319
320 #define TX_DMA_INS_VLAN_MT7621 BIT(16)
321 #define TX_DMA_INS_VLAN BIT(7)
322 #define TX_DMA_INS_PPPOE BIT(12)
323 #define TX_DMA_QN(_x) ((_x) << 16)
324 #define TX_DMA_PN(_x) ((_x) << 24)
325 #define TX_DMA_QN_MASK TX_DMA_QN(0x7)
326 #define TX_DMA_PN_MASK TX_DMA_PN(0x7)
327 #define TX_DMA_UDF BIT(20)
328 #define TX_DMA_CHKSUM (0x7 << 29)
329 #define TX_DMA_TSO BIT(28)
330
331 /* frame engine counters */
332 #define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
333 #define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
334 #define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
335
336 /* phy device flags */
337 #define FE_PHY_FLAG_PORT BIT(0)
338 #define FE_PHY_FLAG_ATTACH BIT(1)
339
340 struct fe_tx_dma {
341 unsigned int txd1;
342 unsigned int txd2;
343 unsigned int txd3;
344 unsigned int txd4;
345 } __packed __aligned(4);
346
347 struct fe_priv;
348
349 struct fe_phy {
350 struct phy_device *phy[8];
351 struct device_node *phy_node[8];
352 const __be32 *phy_fixed[8];
353 int duplex[8];
354 int speed[8];
355 int tx_fc[8];
356 int rx_fc[8];
357 spinlock_t lock;
358
359 int (*connect)(struct fe_priv *priv);
360 void (*disconnect)(struct fe_priv *priv);
361 void (*start)(struct fe_priv *priv);
362 void (*stop)(struct fe_priv *priv);
363 };
364
365 struct fe_soc_data
366 {
367 unsigned char mac[6];
368 const u32 *reg_table;
369
370 void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
371 void (*reset_fe)(void);
372 void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
373 int (*fwd_config)(struct fe_priv *priv);
374 void (*tx_dma)(struct fe_tx_dma *txd);
375 void (*rx_dma)(struct fe_rx_dma *rxd, u16 len);
376 int (*switch_init)(struct fe_priv *priv);
377 int (*switch_config)(struct fe_priv *priv);
378 void (*port_init)(struct fe_priv *priv, struct device_node *port);
379 int (*has_carrier)(struct fe_priv *priv);
380 int (*mdio_init)(struct fe_priv *priv);
381 void (*mdio_cleanup)(struct fe_priv *priv);
382 int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
383 int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
384 void (*mdio_adjust_link)(struct fe_priv *priv, int port);
385
386 void *swpriv;
387 u32 pdma_glo_cfg;
388 u32 rx_int;
389 u32 tx_int;
390 u32 checksum_bit;
391 u32 tx_udf_bit;
392 };
393
394 #define FE_FLAG_PADDING_64B BIT(0)
395 #define FE_FLAG_PADDING_BUG BIT(1)
396 #define FE_FLAG_JUMBO_FRAME BIT(2)
397
398 #define FE_STAT_REG_DECLARE \
399 _FE(tx_bytes) \
400 _FE(tx_packets) \
401 _FE(tx_skip) \
402 _FE(tx_collisions) \
403 _FE(rx_bytes) \
404 _FE(rx_packets) \
405 _FE(rx_overflow) \
406 _FE(rx_fcs_errors) \
407 _FE(rx_short_errors) \
408 _FE(rx_long_errors) \
409 _FE(rx_checksum_errors) \
410 _FE(rx_flow_control_packets)
411
412 struct fe_hw_stats
413 {
414 spinlock_t stats_lock;
415 struct u64_stats_sync syncp;
416 #define _FE(x) u64 x;
417 FE_STAT_REG_DECLARE
418 #undef _FE
419 };
420
421 struct fe_priv
422 {
423 spinlock_t page_lock;
424
425 struct fe_soc_data *soc;
426 struct net_device *netdev;
427 u32 msg_enable;
428 u32 flags;
429
430 struct device *device;
431 unsigned long sysclk;
432
433 u16 frag_size;
434 u16 rx_buf_size;
435 struct fe_rx_dma *rx_dma;
436 u8 **rx_data;
437 dma_addr_t rx_phys;
438 struct napi_struct rx_napi;
439
440 struct fe_tx_dma *tx_dma;
441 struct sk_buff **tx_skb;
442 dma_addr_t tx_phys;
443 unsigned int tx_free_idx;
444
445 struct fe_phy *phy;
446 struct mii_bus *mii_bus;
447 struct phy_device *phy_dev;
448 u32 phy_flags;
449
450 int link[8];
451
452 struct fe_hw_stats *hw_stats;
453 unsigned long vlan_map;
454 };
455
456 extern const struct of_device_id of_fe_match[];
457
458 void fe_w32(u32 val, unsigned reg);
459 u32 fe_r32(unsigned reg);
460
461 int fe_set_clock_cycle(struct fe_priv *priv);
462 void fe_csum_config(struct fe_priv *priv);
463 void fe_stats_update(struct fe_priv *priv);
464 void fe_fwd_config(struct fe_priv *priv);
465 void fe_reg_w32(u32 val, enum fe_reg reg);
466 u32 fe_reg_r32(enum fe_reg reg);
467
468 static inline void *priv_netdev(struct fe_priv *priv)
469 {
470 return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
471 }
472
473 #endif /* FE_ETH_H */