target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
  16  */
  17
  18 #include <linux/module.h>
  19
  20 #include <asm/mach-ralink/ralink_regs.h>
  21
  22 #include "ralink_soc_eth.h"
  23 #include "mdio_rt2880.h"
  24
  25 #define SYSC_REG_RESET_CTRL             0x034
  26 #define RT2880_RESET_FE                 BIT(18)
  27
  28 static void rt2880_init_data(struct fe_soc_data *data,
  29                 struct net_device *netdev)
  30 {
  31         struct fe_priv *priv = netdev_priv(netdev);
  32
  33         priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
  34                 FE_FLAG_JUMBO_FRAME;
  35         netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
  36         /* maybe have hardware bug. */
  37         //netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
  38 }
  39
  40 void rt2880_fe_reset(void)
  41 {
  42         rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
  43 }
  44
  45 static int rt2880_fwd_config(struct fe_priv *priv)
  46 {
  47         int ret;
  48
  49         ret = fe_set_clock_cycle(priv);
  50         if (ret)
  51                 return ret;
  52
  53         fe_fwd_config(priv);
  54         fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
  55         fe_csum_config(priv);
  56
  57         return ret;
  58 }
  59
  60 struct fe_soc_data rt2880_data = {
  61         .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
  62         .init_data = rt2880_init_data,
  63         .reset_fe = rt2880_fe_reset,
  64         .fwd_config = rt2880_fwd_config,
  65         .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
  66         .checksum_bit = RX_DMA_L4VALID,
  67         .tx_udf_bit = TX_DMA_UDF,
  68         .rx_dly_int = FE_RX_DLY_INT,
  69         .tx_dly_int = FE_TX_DLY_INT,
  70         .mdio_read = rt2880_mdio_read,
  71         .mdio_write = rt2880_mdio_write,
  72         .mdio_adjust_link = rt2880_mdio_link_adjust,
  73         .port_init = rt2880_port_init,
  74 };
  75
  76 const struct of_device_id of_fe_match[] = {
  77         { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
  78         {},
  79 };
  80
  81 MODULE_DEVICE_TABLE(of, of_fe_match);