ramips: Add missing andmask to ramips_esw register read for recv_good value.
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ramips / ramips_esw.c
1 #include <linux/ioport.h>
2 #include <linux/switch.h>
3 #include <linux/mii.h>
4
5 #include <rt305x_regs.h>
6 #include <rt305x_esw_platform.h>
7
8 /*
9 * HW limitations for this switch:
10 * - No large frame support (PKT_MAX_LEN at most 1536)
11 * - Can't have untagged vlan and tagged vlan on one port at the same time,
12 * though this might be possible using the undocumented PPE.
13 */
14
15 #define RT305X_ESW_REG_FCT0 0x08
16 #define RT305X_ESW_REG_PFC1 0x14
17 #define RT305X_ESW_REG_ATS 0x24
18 #define RT305X_ESW_REG_ATS0 0x28
19 #define RT305X_ESW_REG_ATS1 0x2c
20 #define RT305X_ESW_REG_ATS2 0x30
21 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
22 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
23 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
24 #define RT305X_ESW_REG_POA 0x80
25 #define RT305X_ESW_REG_FPA 0x84
26 #define RT305X_ESW_REG_SOCPC 0x8c
27 #define RT305X_ESW_REG_POC0 0x90
28 #define RT305X_ESW_REG_POC1 0x94
29 #define RT305X_ESW_REG_POC2 0x98
30 #define RT305X_ESW_REG_SGC 0x9c
31 #define RT305X_ESW_REG_STRT 0xa0
32 #define RT305X_ESW_REG_PCR0 0xc0
33 #define RT305X_ESW_REG_PCR1 0xc4
34 #define RT305X_ESW_REG_FPA2 0xc8
35 #define RT305X_ESW_REG_FCT2 0xcc
36 #define RT305X_ESW_REG_SGC2 0xe4
37 #define RT305X_ESW_REG_P0LED 0xa4
38 #define RT305X_ESW_REG_P1LED 0xa8
39 #define RT305X_ESW_REG_P2LED 0xac
40 #define RT305X_ESW_REG_P3LED 0xb0
41 #define RT305X_ESW_REG_P4LED 0xb4
42 #define RT305X_ESW_REG_P0PC 0xe8
43 #define RT305X_ESW_REG_P1PC 0xec
44 #define RT305X_ESW_REG_P2PC 0xf0
45 #define RT305X_ESW_REG_P3PC 0xf4
46 #define RT305X_ESW_REG_P4PC 0xf8
47 #define RT305X_ESW_REG_P5PC 0xfc
48
49 #define RT305X_ESW_LED_LINK 0
50 #define RT305X_ESW_LED_100M 1
51 #define RT305X_ESW_LED_DUPLEX 2
52 #define RT305X_ESW_LED_ACTIVITY 3
53 #define RT305X_ESW_LED_COLLISION 4
54 #define RT305X_ESW_LED_LINKACT 5
55 #define RT305X_ESW_LED_DUPLCOLL 6
56 #define RT305X_ESW_LED_10MACT 7
57 #define RT305X_ESW_LED_100MACT 8
58 /* Additional led states not in datasheet: */
59 #define RT305X_ESW_LED_BLINK 10
60 #define RT305X_ESW_LED_ON 12
61
62 #define RT305X_ESW_LINK_S 25
63 #define RT305X_ESW_DUPLEX_S 9
64 #define RT305X_ESW_SPD_S 0
65
66 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
67 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
68 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
69
70 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
71
72 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
73 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
74
75 #define RT305X_ESW_PVIDC_PVID_M 0xfff
76 #define RT305X_ESW_PVIDC_PVID_S 12
77
78 #define RT305X_ESW_VLANI_VID_M 0xfff
79 #define RT305X_ESW_VLANI_VID_S 12
80
81 #define RT305X_ESW_VMSC_MSC_M 0xff
82 #define RT305X_ESW_VMSC_MSC_S 8
83
84 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
85 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
86 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
87 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
88
89 #define RT305X_ESW_POC0_EN_BP_S 0
90 #define RT305X_ESW_POC0_EN_FC_S 8
91 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
92 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
93 #define RT305X_ESW_POC0_DIS_PORT_S 23
94
95 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
96 #define RT305X_ESW_POC2_UNTAG_EN_S 0
97 #define RT305X_ESW_POC2_ENAGING_S 8
98 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
99
100 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
101 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
102 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
103 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
104
105 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
106 #define RT305X_ESW_PFC1_EN_VLAN_S 16
107 #define RT305X_ESW_PFC1_EN_TOS_S 24
108
109 #define RT305X_ESW_VLAN_NONE 0xfff
110
111 #define RT305X_ESW_PORT0 0
112 #define RT305X_ESW_PORT1 1
113 #define RT305X_ESW_PORT2 2
114 #define RT305X_ESW_PORT3 3
115 #define RT305X_ESW_PORT4 4
116 #define RT305X_ESW_PORT5 5
117 #define RT305X_ESW_PORT6 6
118
119 #define RT305X_ESW_PORTS_NONE 0
120
121 #define RT305X_ESW_PMAP_LLLLLL 0x3f
122 #define RT305X_ESW_PMAP_LLLLWL 0x2f
123 #define RT305X_ESW_PMAP_WLLLLL 0x3e
124
125 #define RT305X_ESW_PORTS_INTERNAL \
126 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
127 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
128 BIT(RT305X_ESW_PORT4))
129
130 #define RT305X_ESW_PORTS_NOCPU \
131 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
132
133 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
134
135 #define RT305X_ESW_PORTS_ALL \
136 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
137
138 #define RT305X_ESW_NUM_VLANS 16
139 #define RT305X_ESW_NUM_VIDS 4096
140 #define RT305X_ESW_NUM_PORTS 7
141 #define RT305X_ESW_NUM_LANWAN 6
142 #define RT305X_ESW_NUM_LEDS 5
143
144 enum {
145 /* Global attributes. */
146 RT305X_ESW_ATTR_ENABLE_VLAN,
147 RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
148 /* Port attributes. */
149 RT305X_ESW_ATTR_PORT_DISABLE,
150 RT305X_ESW_ATTR_PORT_DOUBLETAG,
151 RT305X_ESW_ATTR_PORT_UNTAG,
152 RT305X_ESW_ATTR_PORT_LED,
153 RT305X_ESW_ATTR_PORT_LAN,
154 RT305X_ESW_ATTR_PORT_RECV_BAD,
155 RT305X_ESW_ATTR_PORT_RECV_GOOD,
156 };
157
158 struct rt305x_esw_port {
159 bool disable;
160 bool doubletag;
161 bool untag;
162 u8 led;
163 u16 pvid;
164 };
165
166 struct rt305x_esw_vlan {
167 u8 ports;
168 u16 vid;
169 };
170
171 struct rt305x_esw {
172 void __iomem *base;
173 struct rt305x_esw_platform_data *pdata;
174 /* Protects against concurrent register rmw operations. */
175 spinlock_t reg_rw_lock;
176
177 struct switch_dev swdev;
178 bool global_vlan_enable;
179 bool alt_vlan_disable;
180 struct rt305x_esw_vlan vlans[RT305X_ESW_NUM_VLANS];
181 struct rt305x_esw_port ports[RT305X_ESW_NUM_PORTS];
182
183 };
184
185 static inline void
186 rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
187 {
188 __raw_writel(val, esw->base + reg);
189 }
190
191 static inline u32
192 rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
193 {
194 return __raw_readl(esw->base + reg);
195 }
196
197 static inline void
198 rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
199 unsigned long val)
200 {
201 unsigned long t;
202
203 t = __raw_readl(esw->base + reg) & ~mask;
204 __raw_writel(t | val, esw->base + reg);
205 }
206
207 static void
208 rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
209 unsigned long val)
210 {
211 unsigned long flags;
212
213 spin_lock_irqsave(&esw->reg_rw_lock, flags);
214 rt305x_esw_rmw_raw(esw, reg, mask, val);
215 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
216 }
217
218 static u32
219 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
220 u32 write_data)
221 {
222 unsigned long t_start = jiffies;
223 int ret = 0;
224
225 while (1) {
226 if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
227 RT305X_ESW_PCR1_WT_DONE))
228 break;
229 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
230 ret = 1;
231 goto out;
232 }
233 }
234
235 write_data &= 0xffff;
236 rt305x_esw_wr(esw,
237 (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
238 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
239 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
240 RT305X_ESW_REG_PCR0);
241
242 t_start = jiffies;
243 while (1) {
244 if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
245 RT305X_ESW_PCR1_WT_DONE)
246 break;
247
248 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
249 ret = 1;
250 break;
251 }
252 }
253 out:
254 if (ret)
255 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
256 return ret;
257 }
258
259 static unsigned
260 rt305x_esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
261 {
262 unsigned s;
263 unsigned val;
264
265 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
266 val = rt305x_esw_rr(esw, RT305X_ESW_REG_VLANI(vlan / 2));
267 val = (val >> s) & RT305X_ESW_VLANI_VID_M;
268
269 return val;
270 }
271
272 static void
273 rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
274 {
275 unsigned s;
276
277 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
278 rt305x_esw_rmw(esw,
279 RT305X_ESW_REG_VLANI(vlan / 2),
280 RT305X_ESW_VLANI_VID_M << s,
281 (vid & RT305X_ESW_VLANI_VID_M) << s);
282 }
283
284 static unsigned
285 rt305x_esw_get_pvid(struct rt305x_esw *esw, unsigned port)
286 {
287 unsigned s, val;
288
289 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
290 val = rt305x_esw_rr(esw, RT305X_ESW_REG_PVIDC(port / 2));
291 return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
292 }
293
294 static void
295 rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
296 {
297 unsigned s;
298
299 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
300 rt305x_esw_rmw(esw,
301 RT305X_ESW_REG_PVIDC(port / 2),
302 RT305X_ESW_PVIDC_PVID_M << s,
303 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
304 }
305
306 static unsigned
307 rt305x_esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
308 {
309 unsigned s, val;
310
311 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
312 val = rt305x_esw_rr(esw, RT305X_ESW_REG_VMSC(vlan / 4));
313 val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
314
315 return val;
316 }
317
318 static void
319 rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
320 {
321 unsigned s;
322
323 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
324 rt305x_esw_rmw(esw,
325 RT305X_ESW_REG_VMSC(vlan / 4),
326 RT305X_ESW_VMSC_MSC_M << s,
327 (msc & RT305X_ESW_VMSC_MSC_M) << s);
328 }
329
330 static unsigned
331 rt305x_esw_get_port_disable(struct rt305x_esw *esw)
332 {
333 unsigned reg;
334 reg = rt305x_esw_rr(esw, RT305X_ESW_REG_POC0);
335 return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
336 RT305X_ESW_POC0_DIS_PORT_M;
337 }
338
339 static void
340 rt305x_esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
341 {
342 unsigned old_mask;
343 unsigned enable_mask;
344 unsigned changed;
345 int i;
346
347 old_mask = rt305x_esw_get_port_disable(esw);
348 changed = old_mask ^ disable_mask;
349 enable_mask = old_mask & disable_mask;
350
351 /* enable before writing to MII */
352 rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
353 (RT305X_ESW_POC0_DIS_PORT_M <<
354 RT305X_ESW_POC0_DIS_PORT_S),
355 enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
356
357 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
358 if (!(changed & (1 << i)))
359 continue;
360 if (disable_mask & (1 << i)) {
361 /* disable */
362 rt305x_mii_write(esw, i, MII_BMCR,
363 BMCR_PDOWN);
364 } else {
365 /* enable */
366 rt305x_mii_write(esw, i, MII_BMCR,
367 BMCR_FULLDPLX |
368 BMCR_ANENABLE |
369 BMCR_ANRESTART |
370 BMCR_SPEED100);
371 }
372 }
373
374 /* disable after writing to MII */
375 rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
376 (RT305X_ESW_POC0_DIS_PORT_M <<
377 RT305X_ESW_POC0_DIS_PORT_S),
378 disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
379 }
380
381 static int
382 rt305x_esw_apply_config(struct switch_dev *dev);
383
384 static void
385 rt305x_esw_hw_init(struct rt305x_esw *esw)
386 {
387 int i;
388 u8 port_disable = 0;
389 u8 port_map = RT305X_ESW_PMAP_LLLLLL;
390
391 /* vodoo from original driver */
392 rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
393 rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
394 /* Port priority 1 for all ports, vlan enabled. */
395 rt305x_esw_wr(esw, 0x00005555 |
396 (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
397 RT305X_ESW_REG_PFC1);
398
399 /* Enable Back Pressure, and Flow Control */
400 rt305x_esw_wr(esw,
401 ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
402 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
403 RT305X_ESW_REG_POC0);
404
405 /* Enable Aging, and VLAN TAG removal */
406 rt305x_esw_wr(esw,
407 ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
408 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
409 RT305X_ESW_REG_POC2);
410
411 rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
412
413 /*
414 * 300s aging timer, max packet len 1536, broadcast storm prevention
415 * disabled, disable collision abort, mac xor48 hash, 10 packet back
416 * pressure jam, GMII disable was_transmit, back pressure disabled,
417 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
418 * ports.
419 */
420 rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
421
422 /* Setup SoC Port control register */
423 rt305x_esw_wr(esw,
424 (RT305X_ESW_SOCPC_CRC_PADDING |
425 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
426 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
427 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
428 RT305X_ESW_REG_SOCPC);
429
430 rt305x_esw_wr(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
431 rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
432
433 /* Force Link/Activity on ports */
434 rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED);
435 rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED);
436 rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED);
437 rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED);
438 rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED);
439
440 /* Copy disabled port configuration from bootloader setup */
441 port_disable = rt305x_esw_get_port_disable(esw);
442 for (i = 0; i < 6; i++)
443 esw->ports[i].disable = (port_disable & (1 << i)) != 0;
444
445 rt305x_mii_write(esw, 0, 31, 0x8000);
446 for (i = 0; i < 5; i++) {
447 if (esw->ports[i].disable) {
448 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
449 } else {
450 rt305x_mii_write(esw, i, MII_BMCR,
451 BMCR_FULLDPLX |
452 BMCR_ANENABLE |
453 BMCR_SPEED100);
454 }
455 /* TX10 waveform coefficient */
456 rt305x_mii_write(esw, i, 26, 0x1601);
457 /* TX100/TX10 AD/DA current bias */
458 rt305x_mii_write(esw, i, 29, 0x7058);
459 /* TX100 slew rate control */
460 rt305x_mii_write(esw, i, 30, 0x0018);
461 }
462
463 /* PHY IOT */
464 /* select global register */
465 rt305x_mii_write(esw, 0, 31, 0x0);
466 /* tune TP_IDL tail and head waveform */
467 rt305x_mii_write(esw, 0, 22, 0x052f);
468 /* set TX10 signal amplitude threshold to minimum */
469 rt305x_mii_write(esw, 0, 17, 0x0fe0);
470 /* set squelch amplitude to higher threshold */
471 rt305x_mii_write(esw, 0, 18, 0x40ba);
472 /* longer TP_IDL tail length */
473 rt305x_mii_write(esw, 0, 14, 0x65);
474 /* select local register */
475 rt305x_mii_write(esw, 0, 31, 0x8000);
476
477 switch (esw->pdata->vlan_config) {
478 case RT305X_ESW_VLAN_CONFIG_NONE:
479 port_map = RT305X_ESW_PMAP_LLLLLL;
480 break;
481 case RT305X_ESW_VLAN_CONFIG_LLLLW:
482 port_map = RT305X_ESW_PMAP_LLLLWL;
483 break;
484 case RT305X_ESW_VLAN_CONFIG_WLLLL:
485 port_map = RT305X_ESW_PMAP_WLLLLL;
486 break;
487 default:
488 BUG();
489 }
490
491 /*
492 * Unused HW feature, but still nice to be consistent here...
493 * This is also exported to userspace ('lan' attribute) so it's
494 * conveniently usable to decide which ports go into the wan vlan by
495 * default.
496 */
497 rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
498 RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
499 port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
500
501 /* Apply the empty config. */
502 rt305x_esw_apply_config(&esw->swdev);
503 }
504
505 static int
506 rt305x_esw_apply_config(struct switch_dev *dev)
507 {
508 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
509 int i;
510 u8 disable = 0;
511 u8 doubletag = 0;
512 u8 en_vlan = 0;
513 u8 untag = 0;
514
515 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
516 u32 vid, vmsc;
517 if (esw->global_vlan_enable) {
518 vid = esw->vlans[i].vid;
519 vmsc = esw->vlans[i].ports;
520 } else {
521 vid = RT305X_ESW_VLAN_NONE;
522 vmsc = RT305X_ESW_PORTS_NONE;
523 }
524 rt305x_esw_set_vlan_id(esw, i, vid);
525 rt305x_esw_set_vmsc(esw, i, vmsc);
526 }
527
528 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
529 u32 pvid;
530 disable |= esw->ports[i].disable << i;
531 if (esw->global_vlan_enable) {
532 doubletag |= esw->ports[i].doubletag << i;
533 en_vlan |= 1 << i;
534 untag |= esw->ports[i].untag << i;
535 pvid = esw->ports[i].pvid;
536 } else {
537 int x = esw->alt_vlan_disable ? 0 : 1;
538 doubletag |= x << i;
539 en_vlan |= x << i;
540 untag |= x << i;
541 pvid = 0;
542 }
543 rt305x_esw_set_pvid(esw, i, pvid);
544 if (i < RT305X_ESW_NUM_LEDS)
545 rt305x_esw_wr(esw, esw->ports[i].led,
546 RT305X_ESW_REG_P0LED + 4*i);
547 }
548
549 rt305x_esw_set_port_disable(esw, disable);
550 rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
551 (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
552 RT305X_ESW_SGC2_DOUBLE_TAG_S),
553 doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
554 rt305x_esw_rmw(esw, RT305X_ESW_REG_PFC1,
555 RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
556 en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
557 rt305x_esw_rmw(esw, RT305X_ESW_REG_POC2,
558 RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
559 untag << RT305X_ESW_POC2_UNTAG_EN_S);
560
561 if (!esw->global_vlan_enable) {
562 /*
563 * Still need to put all ports into vlan 0 or they'll be
564 * isolated.
565 * NOTE: vlan 0 is special, no vlan tag is prepended
566 */
567 rt305x_esw_set_vlan_id(esw, 0, 0);
568 rt305x_esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
569 }
570
571 return 0;
572 }
573
574 static int
575 rt305x_esw_reset_switch(struct switch_dev *dev)
576 {
577 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
578 esw->global_vlan_enable = 0;
579 memset(esw->ports, 0, sizeof(esw->ports));
580 memset(esw->vlans, 0, sizeof(esw->vlans));
581 rt305x_esw_hw_init(esw);
582
583 return 0;
584 }
585
586 static int
587 rt305x_esw_get_vlan_enable(struct switch_dev *dev,
588 const struct switch_attr *attr,
589 struct switch_val *val)
590 {
591 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
592
593 val->value.i = esw->global_vlan_enable;
594
595 return 0;
596 }
597
598 static int
599 rt305x_esw_set_vlan_enable(struct switch_dev *dev,
600 const struct switch_attr *attr,
601 struct switch_val *val)
602 {
603 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
604
605 esw->global_vlan_enable = val->value.i != 0;
606
607 return 0;
608 }
609
610 static int
611 rt305x_esw_get_alt_vlan_disable(struct switch_dev *dev,
612 const struct switch_attr *attr,
613 struct switch_val *val)
614 {
615 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
616
617 val->value.i = esw->alt_vlan_disable;
618
619 return 0;
620 }
621
622 static int
623 rt305x_esw_set_alt_vlan_disable(struct switch_dev *dev,
624 const struct switch_attr *attr,
625 struct switch_val *val)
626 {
627 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
628
629 esw->alt_vlan_disable = val->value.i != 0;
630
631 return 0;
632 }
633
634 static int
635 rt305x_esw_get_port_link(struct switch_dev *dev,
636 int port,
637 struct switch_port_link *link)
638 {
639 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
640 u32 speed, poa;
641
642 if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
643 return -EINVAL;
644
645 poa = rt305x_esw_rr(esw, RT305X_ESW_REG_POA) >> port;
646
647 link->link = (poa >> RT305X_ESW_LINK_S) & 1;
648 link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
649 if (port < RT305X_ESW_NUM_LEDS) {
650 speed = (poa >> RT305X_ESW_SPD_S) & 1;
651 } else {
652 if (port == RT305X_ESW_NUM_PORTS - 1)
653 poa >>= 1;
654 speed = (poa >> RT305X_ESW_SPD_S) & 3;
655 }
656 switch (speed) {
657 case 0:
658 link->speed = SWITCH_PORT_SPEED_10;
659 break;
660 case 1:
661 link->speed = SWITCH_PORT_SPEED_100;
662 break;
663 case 2:
664 case 3: /* forced gige speed can be 2 or 3 */
665 link->speed = SWITCH_PORT_SPEED_1000;
666 break;
667 default:
668 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
669 break;
670 }
671
672 return 0;
673 }
674
675 static int
676 rt305x_esw_get_port_bool(struct switch_dev *dev,
677 const struct switch_attr *attr,
678 struct switch_val *val)
679 {
680 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
681 int idx = val->port_vlan;
682 u32 x, reg, shift;
683
684 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
685 return -EINVAL;
686
687 switch (attr->id) {
688 case RT305X_ESW_ATTR_PORT_DISABLE:
689 reg = RT305X_ESW_REG_POC0;
690 shift = RT305X_ESW_POC0_DIS_PORT_S;
691 break;
692 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
693 reg = RT305X_ESW_REG_SGC2;
694 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
695 break;
696 case RT305X_ESW_ATTR_PORT_UNTAG:
697 reg = RT305X_ESW_REG_POC2;
698 shift = RT305X_ESW_POC2_UNTAG_EN_S;
699 break;
700 case RT305X_ESW_ATTR_PORT_LAN:
701 reg = RT305X_ESW_REG_SGC2;
702 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
703 if (idx >= RT305X_ESW_NUM_LANWAN)
704 return -EINVAL;
705 break;
706 default:
707 return -EINVAL;
708 }
709
710 x = rt305x_esw_rr(esw, reg);
711 val->value.i = (x >> (idx + shift)) & 1;
712
713 return 0;
714 }
715
716 static int
717 rt305x_esw_set_port_bool(struct switch_dev *dev,
718 const struct switch_attr *attr,
719 struct switch_val *val)
720 {
721 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
722 int idx = val->port_vlan;
723
724 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
725 val->value.i < 0 || val->value.i > 1)
726 return -EINVAL;
727
728 switch (attr->id) {
729 case RT305X_ESW_ATTR_PORT_DISABLE:
730 esw->ports[idx].disable = val->value.i;
731 break;
732 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
733 esw->ports[idx].doubletag = val->value.i;
734 break;
735 case RT305X_ESW_ATTR_PORT_UNTAG:
736 esw->ports[idx].untag = val->value.i;
737 break;
738 default:
739 return -EINVAL;
740 }
741
742 return 0;
743 }
744
745 static int
746 rt305x_esw_get_port_recv_badgood(struct switch_dev *dev,
747 const struct switch_attr *attr,
748 struct switch_val *val)
749 {
750 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
751 int idx = val->port_vlan;
752 int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
753 u32 reg;
754
755 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
756 return -EINVAL;
757
758 reg = rt305x_esw_rr(esw, RT305X_ESW_REG_P0PC + 4*idx);
759 val->value.i = (reg >> shift) & 0xffff;
760
761 return 0;
762 }
763
764 static int
765 rt305x_esw_get_port_led(struct switch_dev *dev,
766 const struct switch_attr *attr,
767 struct switch_val *val)
768 {
769 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
770 int idx = val->port_vlan;
771
772 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
773 idx >= RT305X_ESW_NUM_LEDS)
774 return -EINVAL;
775
776 val->value.i = rt305x_esw_rr(esw, RT305X_ESW_REG_P0LED + 4*idx);
777
778 return 0;
779 }
780
781 static int
782 rt305x_esw_set_port_led(struct switch_dev *dev,
783 const struct switch_attr *attr,
784 struct switch_val *val)
785 {
786 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
787 int idx = val->port_vlan;
788
789 if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
790 return -EINVAL;
791
792 esw->ports[idx].led = val->value.i;
793
794 return 0;
795 }
796
797 static int
798 rt305x_esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
799 {
800 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
801
802 if (port >= RT305X_ESW_NUM_PORTS)
803 return -EINVAL;
804
805 *val = rt305x_esw_get_pvid(esw, port);
806
807 return 0;
808 }
809
810 static int
811 rt305x_esw_set_port_pvid(struct switch_dev *dev, int port, int val)
812 {
813 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
814
815 if (port >= RT305X_ESW_NUM_PORTS)
816 return -EINVAL;
817
818 esw->ports[port].pvid = val;
819
820 return 0;
821 }
822
823 static int
824 rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
825 {
826 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
827 u32 vmsc, poc2;
828 int vlan_idx = -1;
829 int i;
830
831 val->len = 0;
832
833 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
834 return -EINVAL;
835
836 /* valid vlan? */
837 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
838 if (rt305x_esw_get_vlan_id(esw, i) == val->port_vlan &&
839 rt305x_esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
840 vlan_idx = i;
841 break;
842 }
843 }
844
845 if (vlan_idx == -1)
846 return -EINVAL;
847
848 vmsc = rt305x_esw_get_vmsc(esw, vlan_idx);
849 poc2 = rt305x_esw_rr(esw, RT305X_ESW_REG_POC2);
850
851 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
852 struct switch_port *p;
853 int port_mask = 1 << i;
854
855 if (!(vmsc & port_mask))
856 continue;
857
858 p = &val->value.ports[val->len++];
859 p->id = i;
860 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
861 p->flags = 0;
862 else
863 p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
864 }
865
866 return 0;
867 }
868
869 static int
870 rt305x_esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
871 {
872 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
873 int ports;
874 int vlan_idx = -1;
875 int i;
876
877 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
878 val->len > RT305X_ESW_NUM_PORTS)
879 return -EINVAL;
880
881 /* one of the already defined vlans? */
882 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
883 if (esw->vlans[i].vid == val->port_vlan &&
884 esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
885 vlan_idx = i;
886 break;
887 }
888 }
889
890 /* select a free slot */
891 for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
892 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
893 vlan_idx = i;
894 }
895
896 /* bail if all slots are in use */
897 if (vlan_idx == -1)
898 return -EINVAL;
899
900 ports = RT305X_ESW_PORTS_NONE;
901 for (i = 0; i < val->len; i++) {
902 struct switch_port *p = &val->value.ports[i];
903 int port_mask = 1 << p->id;
904 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
905
906 if (p->id >= RT305X_ESW_NUM_PORTS)
907 return -EINVAL;
908
909 ports |= port_mask;
910 esw->ports[p->id].untag = untagged;
911 }
912 esw->vlans[vlan_idx].ports = ports;
913 if (ports == RT305X_ESW_PORTS_NONE)
914 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
915 else
916 esw->vlans[vlan_idx].vid = val->port_vlan;
917
918 return 0;
919 }
920
921 static const struct switch_attr rt305x_esw_global[] = {
922 {
923 .type = SWITCH_TYPE_INT,
924 .name = "enable_vlan",
925 .description = "VLAN mode (1:enabled)",
926 .max = 1,
927 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
928 .get = rt305x_esw_get_vlan_enable,
929 .set = rt305x_esw_set_vlan_enable,
930 },
931 {
932 .type = SWITCH_TYPE_INT,
933 .name = "alternate_vlan_disable",
934 .description = "Use en_vlan instead of doubletag to disable"
935 " VLAN mode",
936 .max = 1,
937 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
938 .get = rt305x_esw_get_alt_vlan_disable,
939 .set = rt305x_esw_set_alt_vlan_disable,
940 },
941 };
942
943 static const struct switch_attr rt305x_esw_port[] = {
944 {
945 .type = SWITCH_TYPE_INT,
946 .name = "disable",
947 .description = "Port state (1:disabled)",
948 .max = 1,
949 .id = RT305X_ESW_ATTR_PORT_DISABLE,
950 .get = rt305x_esw_get_port_bool,
951 .set = rt305x_esw_set_port_bool,
952 },
953 {
954 .type = SWITCH_TYPE_INT,
955 .name = "doubletag",
956 .description = "Double tagging for incoming vlan packets "
957 "(1:enabled)",
958 .max = 1,
959 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
960 .get = rt305x_esw_get_port_bool,
961 .set = rt305x_esw_set_port_bool,
962 },
963 {
964 .type = SWITCH_TYPE_INT,
965 .name = "untag",
966 .description = "Untag (1:strip outgoing vlan tag)",
967 .max = 1,
968 .id = RT305X_ESW_ATTR_PORT_UNTAG,
969 .get = rt305x_esw_get_port_bool,
970 .set = rt305x_esw_set_port_bool,
971 },
972 {
973 .type = SWITCH_TYPE_INT,
974 .name = "led",
975 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
976 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
977 " 8:100mact, 10:blink, 12:on)",
978 .max = 15,
979 .id = RT305X_ESW_ATTR_PORT_LED,
980 .get = rt305x_esw_get_port_led,
981 .set = rt305x_esw_set_port_led,
982 },
983 {
984 .type = SWITCH_TYPE_INT,
985 .name = "lan",
986 .description = "HW port group (0:wan, 1:lan)",
987 .max = 1,
988 .id = RT305X_ESW_ATTR_PORT_LAN,
989 .get = rt305x_esw_get_port_bool,
990 },
991 {
992 .type = SWITCH_TYPE_INT,
993 .name = "recv_bad",
994 .description = "Receive bad packet counter",
995 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
996 .get = rt305x_esw_get_port_recv_badgood,
997 },
998 {
999 .type = SWITCH_TYPE_INT,
1000 .name = "recv_good",
1001 .description = "Receive good packet counter",
1002 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1003 .get = rt305x_esw_get_port_recv_badgood,
1004 },
1005 };
1006
1007 static const struct switch_attr rt305x_esw_vlan[] = {
1008 };
1009
1010 static const struct switch_dev_ops rt305x_esw_ops = {
1011 .attr_global = {
1012 .attr = rt305x_esw_global,
1013 .n_attr = ARRAY_SIZE(rt305x_esw_global),
1014 },
1015 .attr_port = {
1016 .attr = rt305x_esw_port,
1017 .n_attr = ARRAY_SIZE(rt305x_esw_port),
1018 },
1019 .attr_vlan = {
1020 .attr = rt305x_esw_vlan,
1021 .n_attr = ARRAY_SIZE(rt305x_esw_vlan),
1022 },
1023 .get_vlan_ports = rt305x_esw_get_vlan_ports,
1024 .set_vlan_ports = rt305x_esw_set_vlan_ports,
1025 .get_port_pvid = rt305x_esw_get_port_pvid,
1026 .set_port_pvid = rt305x_esw_set_port_pvid,
1027 .get_port_link = rt305x_esw_get_port_link,
1028 .apply_config = rt305x_esw_apply_config,
1029 .reset_switch = rt305x_esw_reset_switch,
1030 };
1031
1032 static int
1033 rt305x_esw_probe(struct platform_device *pdev)
1034 {
1035 struct rt305x_esw_platform_data *pdata;
1036 struct rt305x_esw *esw;
1037 struct switch_dev *swdev;
1038 struct resource *res;
1039 int err;
1040
1041 pdata = pdev->dev.platform_data;
1042 if (!pdata)
1043 return -EINVAL;
1044
1045 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1046 if (!res) {
1047 dev_err(&pdev->dev, "no memory resource found\n");
1048 return -ENOMEM;
1049 }
1050
1051 esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1052 if (!esw) {
1053 dev_err(&pdev->dev, "no memory for private data\n");
1054 return -ENOMEM;
1055 }
1056
1057 esw->base = ioremap(res->start, resource_size(res));
1058 if (!esw->base) {
1059 dev_err(&pdev->dev, "ioremap failed\n");
1060 err = -ENOMEM;
1061 goto free_esw;
1062 }
1063
1064 swdev = &esw->swdev;
1065 swdev->name = "rt305x-esw";
1066 swdev->alias = "rt305x";
1067 swdev->cpu_port = RT305X_ESW_PORT6;
1068 swdev->ports = RT305X_ESW_NUM_PORTS;
1069 swdev->vlans = RT305X_ESW_NUM_VIDS;
1070 swdev->ops = &rt305x_esw_ops;
1071
1072 err = register_switch(swdev, NULL);
1073 if (err < 0) {
1074 dev_err(&pdev->dev, "register_switch failed\n");
1075 goto unmap_base;
1076 }
1077
1078 platform_set_drvdata(pdev, esw);
1079
1080 esw->pdata = pdata;
1081 spin_lock_init(&esw->reg_rw_lock);
1082 rt305x_esw_hw_init(esw);
1083
1084 return 0;
1085
1086 unmap_base:
1087 iounmap(esw->base);
1088 free_esw:
1089 kfree(esw);
1090 return err;
1091 }
1092
1093 static int
1094 rt305x_esw_remove(struct platform_device *pdev)
1095 {
1096 struct rt305x_esw *esw;
1097
1098 esw = platform_get_drvdata(pdev);
1099 if (esw) {
1100 unregister_switch(&esw->swdev);
1101 platform_set_drvdata(pdev, NULL);
1102 iounmap(esw->base);
1103 kfree(esw);
1104 }
1105
1106 return 0;
1107 }
1108
1109 static struct platform_driver rt305x_esw_driver = {
1110 .probe = rt305x_esw_probe,
1111 .remove = rt305x_esw_remove,
1112 .driver = {
1113 .name = "rt305x-esw",
1114 .owner = THIS_MODULE,
1115 },
1116 };
1117
1118 static int __init
1119 rt305x_esw_init(void)
1120 {
1121 return platform_driver_register(&rt305x_esw_driver);
1122 }
1123
1124 static void
1125 rt305x_esw_exit(void)
1126 {
1127 platform_driver_unregister(&rt305x_esw_driver);
1128 }