target/linux/ramips/files/drivers/net/ramips_esw.c

   1 #define GPIO_PRUPOSE           0x60
   2 #define GPIO_MDIO_BIT          (1<<7)
   3 #define RT305X_ESW_PHY_WRITE            (1 << 13)
   4 #define RT305X_ESW_PHY_TOUT                     (5 * HZ)
   5 #define RT305X_ESW_PHY_CONTROL_0        0xC0
   6 #define RT305X_ESW_PHY_CONTROL_1        0xC4
   7
   8 static void __iomem *ramips_esw_base = 0;
   9
  10 static inline void
  11 ramips_esw_wr(u32 val, unsigned reg)
  12 {
  13         __raw_writel(val, ramips_esw_base + reg);
  14 }
  15
  16 static inline u32
  17 ramips_esw_rr(unsigned reg)
  18 {
  19         return __raw_readl(ramips_esw_base + reg);
  20 }
  21
  22 static void
  23 ramips_enable_mdio(int s)
  24 {
  25         u32 gpio = rt305x_sysc_rr(GPIO_PRUPOSE);
  26         if(s)
  27                 gpio &= ~GPIO_MDIO_BIT;
  28         else
  29                 gpio |= GPIO_MDIO_BIT;
  30         rt305x_sysc_wr(gpio, GPIO_PRUPOSE);
  31 }
  32
  33 u32
  34 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
  35 {
  36         unsigned long volatile t_start = jiffies;
  37         int ret = 0;
  38
  39         ramips_enable_mdio(1);
  40         while(1)
  41         {
  42                 if(!(ramips_esw_rr(RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0)))
  43                         break;
  44                 if(time_after(jiffies, t_start + RT305X_ESW_PHY_TOUT))
  45                 {
  46                         ret = 1;
  47                         goto out;
  48                 }
  49         }
  50         ramips_esw_wr(((write_data & 0xFFFF) << 16) | (phy_register << 8) |
  51                 (phy_addr) | RT305X_ESW_PHY_WRITE, RT305X_ESW_PHY_CONTROL_0);
  52         t_start = jiffies;
  53         while(1)
  54         {
  55                 if(ramips_esw_rr(RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0))
  56                         break;
  57                 if(time_after(jiffies, t_start + RT305X_ESW_PHY_TOUT))
  58                 {
  59                         ret = 1;
  60                         break;
  61                 }
  62         }
  63 out:
  64         ramips_enable_mdio(0);
  65         if(ret)
  66                 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
  67         return ret;
  68 }
  69
  70 static int
  71 rt305x_esw_init(void)
  72 {
  73         int i;
  74
  75         ramips_esw_base = ioremap_nocache(RT305X_SWITCH_BASE, PAGE_SIZE);
  76         if(!ramips_esw_base)
  77                 return -ENOMEM;
  78
  79         /* vodoo from original driver */
  80         ramips_esw_wr(0xC8A07850, 0x08);
  81         ramips_esw_wr(0x00000000, 0xe4);
  82         ramips_esw_wr(0x00405555, 0x14);
  83         ramips_esw_wr(0x00002001, 0x50);
  84         ramips_esw_wr(0x00007f7f, 0x90);
  85         ramips_esw_wr(0x00007f3f, 0x98);
  86         ramips_esw_wr(0x00d6500c, 0xcc);
  87         ramips_esw_wr(0x0008a301, 0x9c);
  88         ramips_esw_wr(0x02404040, 0x8c);
  89         ramips_esw_wr(0x00001002, 0x48);
  90         ramips_esw_wr(0x3f502b28, 0xc8);
  91         ramips_esw_wr(0x00000000, 0x84);
  92
  93         mii_mgr_write(0, 31, 0x8000);
  94         for(i = 0; i < 5; i++)
  95         {
  96                 mii_mgr_write(i, 0, 0x3100);   //TX10 waveform coefficient
  97                 mii_mgr_write(i, 26, 0x1601);   //TX10 waveform coefficient
  98                 mii_mgr_write(i, 29, 0x7058);   //TX100/TX10 AD/DA current bias
  99                 mii_mgr_write(i, 30, 0x0018);   //TX100 slew rate control
 100         }
 101         /* PHY IOT */
 102         mii_mgr_write(0, 31, 0x0);      //select global register
 103         mii_mgr_write(0, 22, 0x052f);   //tune TP_IDL tail and head waveform
 104         mii_mgr_write(0, 17, 0x0fe0);   //set TX10 signal amplitude threshold to minimum
 105         mii_mgr_write(0, 18, 0x40ba);   //set squelch amplitude to higher threshold
 106         mii_mgr_write(0, 14, 0x65);     //longer TP_IDL tail length
 107         mii_mgr_write(0, 31, 0x8000);   //select local register
 108
 109         /* Port 5 Disabled */
 110         rt305x_sysc_wr(rt305x_sysc_rr(0x60) | (1 << 9), 0x60); //set RGMII to GPIO mode (GPIO41-GPIO50)
 111         rt305x_sysc_wr(0xfff, 0x674); //GPIO41-GPIO50 output mode
 112         rt305x_sysc_wr(0x0, 0x670); //GPIO41-GPIO50 output low
 113
 114         /* set default vlan */
 115         ramips_esw_wr(0x2001, 0x50);
 116         ramips_esw_wr(0x5041, 0x70);
 117
 118         return 0;
 119 }